Bug Summary

File:build/gcc/lra.c
Warning:line 849, column 15
Value stored to 'fmt' during its initialization is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-unknown-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name lra.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -resource-dir /usr/lib64/clang/13.0.0 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../include/c++/11 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../include/c++/11/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../include/c++/11/backward -internal-isystem /usr/lib64/clang/13.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../x86_64-suse-linux/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-error=format-diag -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir=/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2021-11-20-133755-20252-1/report-1H9XQl.plist -x c++ /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c
1/* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2021 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 3, or (at your option) any later
10version.
11
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING3. If not see
19<http://www.gnu.org/licenses/>. */
20
21
22/* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
26
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
30 as possible
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
33
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
37 generated;
38 o Some pseudos might be spilled to assign hard registers to
39 new reload pseudos;
40 o Recalculating spilled pseudo values (rematerialization);
41 o Changing spilled pseudos to stack memory or their equivalences;
42 o Allocation stack memory changes the address displacement and
43 new iteration is needed.
44
45 Here is block diagram of LRA passes:
46
47 ------------------------
48 --------------- | Undo inheritance for | ---------------
49 | Memory-memory | | spilled pseudos, | | New (and old) |
50 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
51 --------------- | the same hard regs, | | assignment |
52 Start | | and optional reloads | ---------------
53 | | ------------------------ ^
54 V | ---------------- |
55 ----------- V | Update virtual | |
56| Remove |----> ------------>| register | |
57| scratches | ^ | displacements | |
58 ----------- | ---------------- |
59 | | |
60 | V New |
61 | ------------ pseudos -------------------
62 | |Constraints:| or insns | Inheritance/split |
63 | | RTL |--------->| transformations |
64 | | transfor- | | in EBB scope |
65 | substi- | mations | -------------------
66 | tutions ------------
67 | | No change
68 ---------------- V
69 | Spilled pseudo | -------------------
70 | to memory |<----| Rematerialization |
71 | substitution | -------------------
72 ----------------
73 | No susbtitions
74 V
75 -------------------------
76 | Hard regs substitution, |
77 | devirtalization, and |------> Finish
78 | restoring scratches got |
79 | memory |
80 -------------------------
81
82 To speed up the process:
83 o We process only insns affected by changes on previous
84 iterations;
85 o We don't use DFA-infrastructure because it results in much slower
86 compiler speed than a special IR described below does;
87 o We use a special insn representation for quick access to insn
88 info which is always *synchronized* with the current RTL;
89 o Insn IR is minimized by memory. It is divided on three parts:
90 o one specific for each insn in RTL (only operand locations);
91 o one common for all insns in RTL with the same insn code
92 (different operand attributes from machine descriptions);
93 o one oriented for maintenance of live info (list of pseudos).
94 o Pseudo data:
95 o all insns where the pseudo is referenced;
96 o live info (conflicting hard regs, live ranges, # of
97 references etc);
98 o data used for assigning (preferred hard regs, costs etc).
99
100 This file contains LRA driver, LRA utility functions and data, and
101 code for dealing with scratches. */
102
103#include "config.h"
104#include "system.h"
105#include "coretypes.h"
106#include "backend.h"
107#include "target.h"
108#include "rtl.h"
109#include "tree.h"
110#include "predict.h"
111#include "df.h"
112#include "memmodel.h"
113#include "tm_p.h"
114#include "optabs.h"
115#include "regs.h"
116#include "ira.h"
117#include "recog.h"
118#include "expr.h"
119#include "cfgrtl.h"
120#include "cfgbuild.h"
121#include "lra.h"
122#include "lra-int.h"
123#include "print-rtl.h"
124#include "function-abi.h"
125
126/* Dump bitmap SET with TITLE and BB INDEX. */
127void
128lra_dump_bitmap_with_title (const char *title, bitmap set, int index)
129{
130 unsigned int i;
131 int count;
132 bitmap_iterator bi;
133 static const int max_nums_on_line = 10;
134
135 if (bitmap_empty_p (set))
136 return;
137 fprintf (lra_dump_file, " %s %d:", title, index);
138 fprintf (lra_dump_file, "\n");
139 count = max_nums_on_line + 1;
140 EXECUTE_IF_SET_IN_BITMAP (set, 0, i, bi)for (bmp_iter_set_init (&(bi), (set), (0), &(i)); bmp_iter_set
(&(bi), &(i)); bmp_iter_next (&(bi), &(i)))
141 {
142 if (count > max_nums_on_line)
143 {
144 fprintf (lra_dump_file, "\n ");
145 count = 0;
146 }
147 fprintf (lra_dump_file, " %4u", i);
148 count++;
149 }
150 fprintf (lra_dump_file, "\n");
151}
152
153/* Hard registers currently not available for allocation. It can
154 changed after some hard registers become not eliminable. */
155HARD_REG_SET lra_no_alloc_regs;
156
157static int get_new_reg_value (void);
158static void expand_reg_info (void);
159static void invalidate_insn_recog_data (int);
160static int get_insn_freq (rtx_insn *);
161static void invalidate_insn_data_regno_info (lra_insn_recog_data_t,
162 rtx_insn *, int);
163/* Expand all regno related info needed for LRA. */
164static void
165expand_reg_data (int old)
166{
167 resize_reg_info ();
168 expand_reg_info ();
169 ira_expand_reg_equiv ();
170 for (int i = (int) max_reg_num () - 1; i >= old; i--)
171 lra_change_class (i, ALL_REGS, " Set", true);
172}
173
174/* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
175 or of VOIDmode, use MD_MODE for the new reg. Initialize its
176 register class to RCLASS. Print message about assigning class
177 RCLASS containing new register name TITLE unless it is NULL. Use
178 attributes of ORIGINAL if it is a register. The created register
179 will have unique held value. */
180rtx
181lra_create_new_reg_with_unique_value (machine_mode md_mode, rtx original,
182 enum reg_class rclass, const char *title)
183{
184 machine_mode mode;
185 rtx new_reg;
186
187 if (original == NULL_RTX(rtx) 0 || (mode = GET_MODE (original)((machine_mode) (original)->mode)) == VOIDmode((void) 0, E_VOIDmode))
188 mode = md_mode;
189 lra_assert (mode != VOIDmode)((void)(!(mode != ((void) 0, E_VOIDmode)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 189, __FUNCTION__), 0 : 0))
;
190 new_reg = gen_reg_rtx (mode);
191 if (original == NULL_RTX(rtx) 0 || ! REG_P (original)(((enum rtx_code) (original)->code) == REG))
192 {
193 if (lra_dump_file != NULLnullptr)
194 fprintf (lra_dump_file, " Creating newreg=%i", REGNO (new_reg)(rhs_regno(new_reg)));
195 }
196 else
197 {
198 if (ORIGINAL_REGNO (original)(__extension__ ({ __typeof ((original)) const _rtx = ((original
)); if (((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
("ORIGINAL_REGNO", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 198, __FUNCTION__); _rtx; })->u2.original_regno)
>= FIRST_PSEUDO_REGISTER76)
199 ORIGINAL_REGNO (new_reg)(__extension__ ({ __typeof ((new_reg)) const _rtx = ((new_reg
)); if (((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
("ORIGINAL_REGNO", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 199, __FUNCTION__); _rtx; })->u2.original_regno)
= ORIGINAL_REGNO (original)(__extension__ ({ __typeof ((original)) const _rtx = ((original
)); if (((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
("ORIGINAL_REGNO", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 199, __FUNCTION__); _rtx; })->u2.original_regno)
;
200 REG_USERVAR_P (new_reg)(__extension__ ({ __typeof ((new_reg)) const _rtx = ((new_reg
)); if (((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
("REG_USERVAR_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 200, __FUNCTION__); _rtx; })->volatil)
= REG_USERVAR_P (original)(__extension__ ({ __typeof ((original)) const _rtx = ((original
)); if (((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
("REG_USERVAR_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 200, __FUNCTION__); _rtx; })->volatil)
;
201 REG_POINTER (new_reg)(__extension__ ({ __typeof ((new_reg)) const _rtx = ((new_reg
)); if (((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
("REG_POINTER", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 201, __FUNCTION__); _rtx; })->frame_related)
= REG_POINTER (original)(__extension__ ({ __typeof ((original)) const _rtx = ((original
)); if (((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
("REG_POINTER", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 201, __FUNCTION__); _rtx; })->frame_related)
;
202 REG_ATTRS (new_reg)((&(new_reg)->u.reg)->attrs) = REG_ATTRS (original)((&(original)->u.reg)->attrs);
203 if (lra_dump_file != NULLnullptr)
204 fprintf (lra_dump_file, " Creating newreg=%i from oldreg=%i",
205 REGNO (new_reg)(rhs_regno(new_reg)), REGNO (original)(rhs_regno(original)));
206 }
207 if (lra_dump_file != NULLnullptr)
208 {
209 if (title != NULLnullptr)
210 fprintf (lra_dump_file, ", assigning class %s to%s%s r%d",
211 reg_class_names[rclass], *title == '\0' ? "" : " ",
212 title, REGNO (new_reg)(rhs_regno(new_reg)));
213 fprintf (lra_dump_file, "\n");
214 }
215 expand_reg_data (max_reg_num ());
216 setup_reg_classes (REGNO (new_reg)(rhs_regno(new_reg)), rclass, NO_REGS, rclass);
217 return new_reg;
218}
219
220/* Analogous to the previous function but also inherits value of
221 ORIGINAL. */
222rtx
223lra_create_new_reg (machine_mode md_mode, rtx original,
224 enum reg_class rclass, const char *title)
225{
226 rtx new_reg;
227
228 new_reg
229 = lra_create_new_reg_with_unique_value (md_mode, original, rclass, title);
230 if (original != NULL_RTX(rtx) 0 && REG_P (original)(((enum rtx_code) (original)->code) == REG))
231 lra_assign_reg_val (REGNO (original)(rhs_regno(original)), REGNO (new_reg)(rhs_regno(new_reg)));
232 return new_reg;
233}
234
235/* Set up for REGNO unique hold value. */
236void
237lra_set_regno_unique_value (int regno)
238{
239 lra_reg_info[regno].val = get_new_reg_value ();
240}
241
242/* Invalidate INSN related info used by LRA. The info should never be
243 used after that. */
244void
245lra_invalidate_insn_data (rtx_insn *insn)
246{
247 lra_invalidate_insn_regno_info (insn);
248 invalidate_insn_recog_data (INSN_UID (insn));
249}
250
251/* Mark INSN deleted and invalidate the insn related info used by
252 LRA. */
253void
254lra_set_insn_deleted (rtx_insn *insn)
255{
256 lra_invalidate_insn_data (insn);
257 SET_INSN_DELETED (insn)set_insn_deleted (insn);;
258}
259
260/* Delete an unneeded INSN and any previous insns who sole purpose is
261 loading data that is dead in INSN. */
262void
263lra_delete_dead_insn (rtx_insn *insn)
264{
265 rtx_insn *prev = prev_real_insn (insn);
266 rtx prev_dest;
267
268 /* If the previous insn sets a register that dies in our insn,
269 delete it too. */
270 if (prev && GET_CODE (PATTERN (prev))((enum rtx_code) (PATTERN (prev))->code) == SET
271 && (prev_dest = SET_DEST (PATTERN (prev))(((PATTERN (prev))->u.fld[0]).rt_rtx), REG_P (prev_dest)(((enum rtx_code) (prev_dest)->code) == REG))
272 && reg_mentioned_p (prev_dest, PATTERN (insn))
273 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)(rhs_regno(prev_dest)))
274 && ! side_effects_p (SET_SRC (PATTERN (prev))(((PATTERN (prev))->u.fld[1]).rt_rtx)))
275 lra_delete_dead_insn (prev);
276
277 lra_set_insn_deleted (insn);
278}
279
280/* Emit insn x = y + z. Return NULL if we failed to do it.
281 Otherwise, return the insn. We don't use gen_add3_insn as it might
282 clobber CC. */
283static rtx_insn *
284emit_add3_insn (rtx x, rtx y, rtx z)
285{
286 rtx_insn *last;
287
288 last = get_last_insn ();
289
290 if (have_addptr3_insn (x, y, z))
291 {
292 rtx_insn *insn = gen_addptr3_insn (x, y, z);
293
294 /* If the target provides an "addptr" pattern it hopefully does
295 for a reason. So falling back to the normal add would be
296 a bug. */
297 lra_assert (insn != NULL_RTX)((void)(!(insn != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 297, __FUNCTION__), 0 : 0))
;
298 emit_insn (insn);
299 return insn;
300 }
301
302 rtx_insn *insn = emit_insn (gen_rtx_SET (x, gen_rtx_PLUS (GET_MODE (y),gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((x)), (
(gen_rtx_fmt_ee_stat ((PLUS), ((((machine_mode) (y)->mode)
)), ((y)), ((z)) ))) )
303 y, z))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((x)), (
(gen_rtx_fmt_ee_stat ((PLUS), ((((machine_mode) (y)->mode)
)), ((y)), ((z)) ))) )
);
304 if (recog_memoized (insn) < 0)
305 {
306 delete_insns_since (last);
307 insn = NULLnullptr;
308 }
309 return insn;
310}
311
312/* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
313 last resort. */
314static rtx_insn *
315emit_add2_insn (rtx x, rtx y)
316{
317 rtx_insn *insn = emit_add3_insn (x, x, y);
318 if (insn == NULL_RTX(rtx) 0)
319 {
320 insn = gen_add2_insn (x, y);
321 if (insn != NULL_RTX(rtx) 0)
322 emit_insn (insn);
323 }
324 return insn;
325}
326
327/* Target checks operands through operand predicates to recognize an
328 insn. We should have a special precaution to generate add insns
329 which are frequent results of elimination.
330
331 Emit insns for x = y + z. X can be used to store intermediate
332 values and should be not in Y and Z when we use X to store an
333 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
334 + disp] where base and index are registers, disp and scale are
335 constants. Y should contain base if it is present, Z should
336 contain disp if any. index[*scale] can be part of Y or Z. */
337void
338lra_emit_add (rtx x, rtx y, rtx z)
339{
340 int old;
341 rtx_insn *last;
342 rtx a1, a2, base, index, disp, scale, index_scale;
343 bool ok_p;
344
345 rtx_insn *add3_insn = emit_add3_insn (x, y, z);
346 old = max_reg_num ();
347 if (add3_insn != NULLnullptr)
348 ;
349 else
350 {
351 disp = a2 = NULL_RTX(rtx) 0;
352 if (GET_CODE (y)((enum rtx_code) (y)->code) == PLUS)
353 {
354 a1 = XEXP (y, 0)(((y)->u.fld[0]).rt_rtx);
355 a2 = XEXP (y, 1)(((y)->u.fld[1]).rt_rtx);
356 disp = z;
357 }
358 else
359 {
360 a1 = y;
361 if (CONSTANT_P (z)((rtx_class[(int) (((enum rtx_code) (z)->code))]) == RTX_CONST_OBJ
)
)
362 disp = z;
363 else
364 a2 = z;
365 }
366 index_scale = scale = NULL_RTX(rtx) 0;
367 if (GET_CODE (a1)((enum rtx_code) (a1)->code) == MULT)
368 {
369 index_scale = a1;
370 index = XEXP (a1, 0)(((a1)->u.fld[0]).rt_rtx);
371 scale = XEXP (a1, 1)(((a1)->u.fld[1]).rt_rtx);
372 base = a2;
373 }
374 else if (a2 != NULL_RTX(rtx) 0 && GET_CODE (a2)((enum rtx_code) (a2)->code) == MULT)
375 {
376 index_scale = a2;
377 index = XEXP (a2, 0)(((a2)->u.fld[0]).rt_rtx);
378 scale = XEXP (a2, 1)(((a2)->u.fld[1]).rt_rtx);
379 base = a1;
380 }
381 else
382 {
383 base = a1;
384 index = a2;
385 }
386 if ((base != NULL_RTX(rtx) 0 && ! (REG_P (base)(((enum rtx_code) (base)->code) == REG) || GET_CODE (base)((enum rtx_code) (base)->code) == SUBREG))
387 || (index != NULL_RTX(rtx) 0
388 && ! (REG_P (index)(((enum rtx_code) (index)->code) == REG) || GET_CODE (index)((enum rtx_code) (index)->code) == SUBREG))
389 || (disp != NULL_RTX(rtx) 0 && ! CONSTANT_P (disp)((rtx_class[(int) (((enum rtx_code) (disp)->code))]) == RTX_CONST_OBJ
)
)
390 || (scale != NULL_RTX(rtx) 0 && ! CONSTANT_P (scale)((rtx_class[(int) (((enum rtx_code) (scale)->code))]) == RTX_CONST_OBJ
)
))
391 {
392 /* Probably we have no 3 op add. Last chance is to use 2-op
393 add insn. To succeed, don't move Z to X as an address
394 segment always comes in Y. Otherwise, we might fail when
395 adding the address segment to register. */
396 lra_assert (x != y && x != z)((void)(!(x != y && x != z) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 396, __FUNCTION__), 0 : 0))
;
397 emit_move_insn (x, y);
398 rtx_insn *insn = emit_add2_insn (x, z);
399 lra_assert (insn != NULL_RTX)((void)(!(insn != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 399, __FUNCTION__), 0 : 0))
;
400 }
401 else
402 {
403 if (index_scale == NULL_RTX(rtx) 0)
404 index_scale = index;
405 if (disp == NULL_RTX(rtx) 0)
406 {
407 /* Generate x = index_scale; x = x + base. */
408 lra_assert (index_scale != NULL_RTX && base != NULL_RTX)((void)(!(index_scale != (rtx) 0 && base != (rtx) 0) ?
fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 408, __FUNCTION__), 0 : 0))
;
409 emit_move_insn (x, index_scale);
410 rtx_insn *insn = emit_add2_insn (x, base);
411 lra_assert (insn != NULL_RTX)((void)(!(insn != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 411, __FUNCTION__), 0 : 0))
;
412 }
413 else if (scale == NULL_RTX(rtx) 0)
414 {
415 /* Try x = base + disp. */
416 lra_assert (base != NULL_RTX)((void)(!(base != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 416, __FUNCTION__), 0 : 0))
;
417 last = get_last_insn ();
418 rtx_insn *move_insn =
419 emit_move_insn (x, gen_rtx_PLUS (GET_MODE (base), base, disp)gen_rtx_fmt_ee_stat ((PLUS), ((((machine_mode) (base)->mode
))), ((base)), ((disp)) )
);
420 if (recog_memoized (move_insn) < 0)
421 {
422 delete_insns_since (last);
423 /* Generate x = disp; x = x + base. */
424 emit_move_insn (x, disp);
425 rtx_insn *add2_insn = emit_add2_insn (x, base);
426 lra_assert (add2_insn != NULL_RTX)((void)(!(add2_insn != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 426, __FUNCTION__), 0 : 0))
;
427 }
428 /* Generate x = x + index. */
429 if (index != NULL_RTX(rtx) 0)
430 {
431 rtx_insn *insn = emit_add2_insn (x, index);
432 lra_assert (insn != NULL_RTX)((void)(!(insn != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 432, __FUNCTION__), 0 : 0))
;
433 }
434 }
435 else
436 {
437 /* Try x = index_scale; x = x + disp; x = x + base. */
438 last = get_last_insn ();
439 rtx_insn *move_insn = emit_move_insn (x, index_scale);
440 ok_p = false;
441 if (recog_memoized (move_insn) >= 0)
442 {
443 rtx_insn *insn = emit_add2_insn (x, disp);
444 if (insn != NULL_RTX(rtx) 0)
445 {
446 if (base == NULL_RTX(rtx) 0)
447 ok_p = true;
448 else
449 {
450 insn = emit_add2_insn (x, base);
451 if (insn != NULL_RTX(rtx) 0)
452 ok_p = true;
453 }
454 }
455 }
456 if (! ok_p)
457 {
458 rtx_insn *insn;
459
460 delete_insns_since (last);
461 /* Generate x = disp; x = x + base; x = x + index_scale. */
462 emit_move_insn (x, disp);
463 if (base != NULL_RTX(rtx) 0)
464 {
465 insn = emit_add2_insn (x, base);
466 lra_assert (insn != NULL_RTX)((void)(!(insn != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 466, __FUNCTION__), 0 : 0))
;
467 }
468 insn = emit_add2_insn (x, index_scale);
469 lra_assert (insn != NULL_RTX)((void)(!(insn != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 469, __FUNCTION__), 0 : 0))
;
470 }
471 }
472 }
473 }
474 /* Functions emit_... can create pseudos -- so expand the pseudo
475 data. */
476 if (old != max_reg_num ())
477 expand_reg_data (old);
478}
479
480/* The number of emitted reload insns so far. */
481int lra_curr_reload_num;
482
483static void remove_insn_scratches (rtx_insn *insn);
484
485/* Emit x := y, processing special case when y = u + v or y = u + v *
486 scale + w through emit_add (Y can be an address which is base +
487 index reg * scale + displacement in general case). X may be used
488 as intermediate result therefore it should be not in Y. */
489void
490lra_emit_move (rtx x, rtx y)
491{
492 int old;
493 rtx_insn *insn;
494
495 if (GET_CODE (y)((enum rtx_code) (y)->code) != PLUS)
496 {
497 if (rtx_equal_p (x, y))
498 return;
499 old = max_reg_num ();
500
501 insn = (GET_CODE (x)((enum rtx_code) (x)->code) != STRICT_LOW_PART
502 ? emit_move_insn (x, y) : emit_insn (gen_rtx_SET (x, y)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((x)), (
(y)) )
));
503 /* The move pattern may require scratch registers, so convert them
504 into real registers now. */
505 if (insn != NULL_RTX(rtx) 0)
506 remove_insn_scratches (insn);
507 if (REG_P (x)(((enum rtx_code) (x)->code) == REG))
508 lra_reg_info[ORIGINAL_REGNO (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag ("ORIGINAL_REGNO"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 508, __FUNCTION__); _rtx; })->u2.original_regno)
].last_reload = ++lra_curr_reload_num;
509 /* Function emit_move can create pseudos -- so expand the pseudo
510 data. */
511 if (old != max_reg_num ())
512 expand_reg_data (old);
513 return;
514 }
515 lra_emit_add (x, XEXP (y, 0)(((y)->u.fld[0]).rt_rtx), XEXP (y, 1)(((y)->u.fld[1]).rt_rtx));
516}
517
518/* Update insn operands which are duplication of operands whose
519 numbers are in array of NOPS (with end marker -1). The insn is
520 represented by its LRA internal representation ID. */
521void
522lra_update_dups (lra_insn_recog_data_t id, signed char *nops)
523{
524 int i, j, nop;
525 struct lra_static_insn_data *static_id = id->insn_static_data;
526
527 for (i = 0; i < static_id->n_dups; i++)
528 for (j = 0; (nop = nops[j]) >= 0; j++)
529 if (static_id->dup_num[i] == nop)
530 *id->dup_loc[i] = *id->operand_loc[nop];
531}
532
533
534
535/* This page contains code dealing with info about registers in the
536 insns. */
537
538/* Pools for insn reg info. */
539object_allocator<lra_insn_reg> lra_insn_reg_pool ("insn regs");
540
541/* Create LRA insn related info about a reference to REGNO in INSN
542 with TYPE (in/out/inout), biggest reference mode MODE, flag that it
543 is reference through subreg (SUBREG_P), and reference to the next
544 insn reg info (NEXT). If REGNO can be early clobbered,
545 alternatives in which it can be early clobbered are given by
546 EARLY_CLOBBER_ALTS. */
547static struct lra_insn_reg *
548new_insn_reg (rtx_insn *insn, int regno, enum op_type type,
549 machine_mode mode, bool subreg_p,
550 alternative_mask early_clobber_alts,
551 struct lra_insn_reg *next)
552{
553 lra_insn_reg *ir = lra_insn_reg_pool.allocate ();
554 ir->type = type;
555 ir->biggest_mode = mode;
556 if (NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN))
557 && partial_subreg_p (lra_reg_info[regno].biggest_mode, mode))
558 lra_reg_info[regno].biggest_mode = mode;
559 ir->subreg_p = subreg_p;
560 ir->early_clobber_alts = early_clobber_alts;
561 ir->regno = regno;
562 ir->next = next;
563 return ir;
564}
565
566/* Free insn reg info list IR. */
567static void
568free_insn_regs (struct lra_insn_reg *ir)
569{
570 struct lra_insn_reg *next_ir;
571
572 for (; ir != NULLnullptr; ir = next_ir)
573 {
574 next_ir = ir->next;
575 lra_insn_reg_pool.remove (ir);
576 }
577}
578
579/* Finish pool for insn reg info. */
580static void
581finish_insn_regs (void)
582{
583 lra_insn_reg_pool.release ();
584}
585
586
587
588/* This page contains code dealing LRA insn info (or in other words
589 LRA internal insn representation). */
590
591/* Map INSN_CODE -> the static insn data. This info is valid during
592 all translation unit. */
593struct lra_static_insn_data *insn_code_data[NUM_INSN_CODES];
594
595/* Debug insns are represented as a special insn with one input
596 operand which is RTL expression in var_location. */
597
598/* The following data are used as static insn operand data for all
599 debug insns. If structure lra_operand_data is changed, the
600 initializer should be changed too. */
601static struct lra_operand_data debug_operand_data =
602 {
603 NULLnullptr, /* alternative */
604 0, /* early_clobber_alts */
605 E_VOIDmode, /* We are not interesting in the operand mode. */
606 OP_IN,
607 0, 0, 0
608 };
609
610/* The following data are used as static insn data for all debug
611 bind insns. If structure lra_static_insn_data is changed, the
612 initializer should be changed too. */
613static struct lra_static_insn_data debug_bind_static_data =
614 {
615 &debug_operand_data,
616 0, /* Duplication operands #. */
617 -1, /* Commutative operand #. */
618 1, /* Operands #. There is only one operand which is debug RTL
619 expression. */
620 0, /* Duplications #. */
621 0, /* Alternatives #. We are not interesting in alternatives
622 because we does not proceed debug_insns for reloads. */
623 NULLnullptr, /* Hard registers referenced in machine description. */
624 NULLnullptr /* Descriptions of operands in alternatives. */
625 };
626
627/* The following data are used as static insn data for all debug
628 marker insns. If structure lra_static_insn_data is changed, the
629 initializer should be changed too. */
630static struct lra_static_insn_data debug_marker_static_data =
631 {
632 &debug_operand_data,
633 0, /* Duplication operands #. */
634 -1, /* Commutative operand #. */
635 0, /* Operands #. There isn't any operand. */
636 0, /* Duplications #. */
637 0, /* Alternatives #. We are not interesting in alternatives
638 because we does not proceed debug_insns for reloads. */
639 NULLnullptr, /* Hard registers referenced in machine description. */
640 NULLnullptr /* Descriptions of operands in alternatives. */
641 };
642
643/* Called once per compiler work to initialize some LRA data related
644 to insns. */
645static void
646init_insn_code_data_once (void)
647{
648 memset (insn_code_data, 0, sizeof (insn_code_data));
649}
650
651/* Called once per compiler work to finalize some LRA data related to
652 insns. */
653static void
654finish_insn_code_data_once (void)
655{
656 for (unsigned int i = 0; i < NUM_INSN_CODES; i++)
657 {
658 if (insn_code_data[i] != NULLnullptr)
659 {
660 free (insn_code_data[i]);
661 insn_code_data[i] = NULLnullptr;
662 }
663 }
664}
665
666/* Return static insn data, allocate and setup if necessary. Although
667 dup_num is static data (it depends only on icode), to set it up we
668 need to extract insn first. So recog_data should be valid for
669 normal insn (ICODE >= 0) before the call. */
670static struct lra_static_insn_data *
671get_static_insn_data (int icode, int nop, int ndup, int nalt)
672{
673 struct lra_static_insn_data *data;
674 size_t n_bytes;
675
676 lra_assert (icode < (int) NUM_INSN_CODES)((void)(!(icode < (int) NUM_INSN_CODES) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 676, __FUNCTION__), 0 : 0))
;
677 if (icode >= 0 && (data = insn_code_data[icode]) != NULLnullptr)
678 return data;
679 lra_assert (nop >= 0 && ndup >= 0 && nalt >= 0)((void)(!(nop >= 0 && ndup >= 0 && nalt
>= 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 679, __FUNCTION__), 0 : 0))
;
680 n_bytes = sizeof (struct lra_static_insn_data)
681 + sizeof (struct lra_operand_data) * nop
682 + sizeof (int) * ndup;
683 data = XNEWVAR (struct lra_static_insn_data, n_bytes)((struct lra_static_insn_data *) xmalloc ((n_bytes)));
684 data->operand_alternative = NULLnullptr;
685 data->n_operands = nop;
686 data->n_dups = ndup;
687 data->n_alternatives = nalt;
688 data->operand = ((struct lra_operand_data *)
689 ((char *) data + sizeof (struct lra_static_insn_data)));
690 data->dup_num = ((int *) ((char *) data->operand
691 + sizeof (struct lra_operand_data) * nop));
692 if (icode >= 0)
693 {
694 int i;
695
696 insn_code_data[icode] = data;
697 for (i = 0; i < nop; i++)
698 {
699 data->operand[i].constraint
700 = insn_data[icode].operand[i].constraint;
701 data->operand[i].mode = insn_data[icode].operand[i].mode;
702 data->operand[i].strict_low = insn_data[icode].operand[i].strict_low;
703 data->operand[i].is_operator
704 = insn_data[icode].operand[i].is_operator;
705 data->operand[i].type
706 = (data->operand[i].constraint[0] == '=' ? OP_OUT
707 : data->operand[i].constraint[0] == '+' ? OP_INOUT
708 : OP_IN);
709 data->operand[i].is_address = false;
710 }
711 for (i = 0; i < ndup; i++)
712 data->dup_num[i] = recog_data.dup_num[i];
713 }
714 return data;
715}
716
717/* The current length of the following array. */
718int lra_insn_recog_data_len;
719
720/* Map INSN_UID -> the insn recog data (NULL if unknown). */
721lra_insn_recog_data_t *lra_insn_recog_data;
722
723/* Alloc pool we allocate entries for lra_insn_recog_data from. */
724static object_allocator<class lra_insn_recog_data>
725 lra_insn_recog_data_pool ("insn recog data pool");
726
727/* Initialize LRA data about insns. */
728static void
729init_insn_recog_data (void)
730{
731 lra_insn_recog_data_len = 0;
732 lra_insn_recog_data = NULLnullptr;
733}
734
735/* Expand, if necessary, LRA data about insns. */
736static void
737check_and_expand_insn_recog_data (int index)
738{
739 int i, old;
740
741 if (lra_insn_recog_data_len > index)
742 return;
743 old = lra_insn_recog_data_len;
744 lra_insn_recog_data_len = index * 3 / 2 + 1;
745 lra_insn_recog_data = XRESIZEVEC (lra_insn_recog_data_t,((lra_insn_recog_data_t *) xrealloc ((void *) (lra_insn_recog_data
), sizeof (lra_insn_recog_data_t) * (lra_insn_recog_data_len)
))
746 lra_insn_recog_data,((lra_insn_recog_data_t *) xrealloc ((void *) (lra_insn_recog_data
), sizeof (lra_insn_recog_data_t) * (lra_insn_recog_data_len)
))
747 lra_insn_recog_data_len)((lra_insn_recog_data_t *) xrealloc ((void *) (lra_insn_recog_data
), sizeof (lra_insn_recog_data_t) * (lra_insn_recog_data_len)
))
;
748 for (i = old; i < lra_insn_recog_data_len; i++)
749 lra_insn_recog_data[i] = NULLnullptr;
750}
751
752/* Finish LRA DATA about insn. */
753static void
754free_insn_recog_data (lra_insn_recog_data_t data)
755{
756 if (data->operand_loc != NULLnullptr)
757 free (data->operand_loc);
758 if (data->dup_loc != NULLnullptr)
759 free (data->dup_loc);
760 if (data->arg_hard_regs != NULLnullptr)
761 free (data->arg_hard_regs);
762 if (data->icode < 0 && NONDEBUG_INSN_P (data->insn)((((enum rtx_code) (data->insn)->code) == INSN) || (((enum
rtx_code) (data->insn)->code) == JUMP_INSN) || (((enum
rtx_code) (data->insn)->code) == CALL_INSN))
)
763 {
764 if (data->insn_static_data->operand_alternative != NULLnullptr)
765 free (const_cast <operand_alternative *>
766 (data->insn_static_data->operand_alternative));
767 free_insn_regs (data->insn_static_data->hard_regs);
768 free (data->insn_static_data);
769 }
770 free_insn_regs (data->regs);
771 data->regs = NULLnullptr;
772 lra_insn_recog_data_pool.remove (data);
773}
774
775/* Pools for copies. */
776static object_allocator<lra_copy> lra_copy_pool ("lra copies");
777
778/* Finish LRA data about all insns. */
779static void
780finish_insn_recog_data (void)
781{
782 int i;
783 lra_insn_recog_data_t data;
784
785 for (i = 0; i < lra_insn_recog_data_len; i++)
786 if ((data = lra_insn_recog_data[i]) != NULLnullptr)
787 free_insn_recog_data (data);
788 finish_insn_regs ();
789 lra_copy_pool.release ();
790 lra_insn_reg_pool.release ();
791 lra_insn_recog_data_pool.release ();
792 free (lra_insn_recog_data);
793}
794
795/* Setup info about operands in alternatives of LRA DATA of insn. */
796static void
797setup_operand_alternative (lra_insn_recog_data_t data,
798 const operand_alternative *op_alt)
799{
800 int i, j, nop, nalt;
801 int icode = data->icode;
802 struct lra_static_insn_data *static_data = data->insn_static_data;
803
804 static_data->commutative = -1;
805 nop = static_data->n_operands;
806 nalt = static_data->n_alternatives;
807 static_data->operand_alternative = op_alt;
808 for (i = 0; i < nop; i++)
809 {
810 static_data->operand[i].early_clobber_alts = 0;
811 static_data->operand[i].is_address = false;
812 if (static_data->operand[i].constraint[0] == '%')
813 {
814 /* We currently only support one commutative pair of operands. */
815 if (static_data->commutative < 0)
816 static_data->commutative = i;
817 else
818 lra_assert (icode < 0)((void)(!(icode < 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 818, __FUNCTION__), 0 : 0))
; /* Asm */
819 /* The last operand should not be marked commutative. */
820 lra_assert (i != nop - 1)((void)(!(i != nop - 1) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 820, __FUNCTION__), 0 : 0))
;
821 }
822 }
823 for (j = 0; j < nalt; j++)
824 for (i = 0; i < nop; i++, op_alt++)
825 {
826 if (op_alt->earlyclobber)
827 static_data->operand[i].early_clobber_alts |= (alternative_mask) 1 << j;
828 static_data->operand[i].is_address |= op_alt->is_address;
829 }
830}
831
832/* Recursively process X and collect info about registers, which are
833 not the insn operands, in X with TYPE (in/out/inout) and flag that
834 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
835 to LIST. X is a part of insn given by DATA. Return the result
836 list. */
837static struct lra_insn_reg *
838collect_non_operand_hard_regs (rtx_insn *insn, rtx *x,
839 lra_insn_recog_data_t data,
840 struct lra_insn_reg *list,
841 enum op_type type, bool early_clobber)
842{
843 int i, j, regno, last;
844 bool subreg_p;
845 machine_mode mode;
846 struct lra_insn_reg *curr;
847 rtx op = *x;
848 enum rtx_code code = GET_CODE (op)((enum rtx_code) (op)->code);
849 const char *fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
Value stored to 'fmt' during its initialization is never read
850
851 for (i = 0; i < data->insn_static_data->n_operands; i++)
852 if (! data->insn_static_data->operand[i].is_operator
853 && x == data->operand_loc[i])
854 /* It is an operand loc. Stop here. */
855 return list;
856 for (i = 0; i < data->insn_static_data->n_dups; i++)
857 if (x == data->dup_loc[i])
858 /* It is a dup loc. Stop here. */
859 return list;
860 mode = GET_MODE (op)((machine_mode) (op)->mode);
861 subreg_p = false;
862 if (code == SUBREG)
863 {
864 mode = wider_subreg_mode (op);
865 if (read_modify_subreg_p (op))
866 subreg_p = true;
867 op = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);
868 code = GET_CODE (op)((enum rtx_code) (op)->code);
869 }
870 if (REG_P (op)(((enum rtx_code) (op)->code) == REG))
871 {
872 if ((regno = REGNO (op)(rhs_regno(op))) >= FIRST_PSEUDO_REGISTER76)
873 return list;
874 /* Process all regs even unallocatable ones as we need info
875 about all regs for rematerialization pass. */
876 for (last = end_hard_regno (mode, regno); regno < last; regno++)
877 {
878 for (curr = list; curr != NULLnullptr; curr = curr->next)
879 if (curr->regno == regno && curr->subreg_p == subreg_p
880 && curr->biggest_mode == mode)
881 {
882 if (curr->type != type)
883 curr->type = OP_INOUT;
884 if (early_clobber)
885 curr->early_clobber_alts = ALL_ALTERNATIVES((alternative_mask) -1);
886 break;
887 }
888 if (curr == NULLnullptr)
889 {
890 /* This is a new hard regno or the info cannot be
891 integrated into the found structure. */
892#ifdef STACK_REGS
893 early_clobber
894 = (early_clobber
895 /* This clobber is to inform popping floating
896 point stack only. */
897 && ! (FIRST_STACK_REG8 <= regno
898 && regno <= LAST_STACK_REG15));
899#endif
900 list = new_insn_reg (data->insn, regno, type, mode, subreg_p,
901 early_clobber ? ALL_ALTERNATIVES((alternative_mask) -1) : 0, list);
902 }
903 }
904 return list;
905 }
906 switch (code)
907 {
908 case SET:
909 list = collect_non_operand_hard_regs (insn, &SET_DEST (op)(((op)->u.fld[0]).rt_rtx), data,
910 list, OP_OUT, false);
911 list = collect_non_operand_hard_regs (insn, &SET_SRC (op)(((op)->u.fld[1]).rt_rtx), data,
912 list, OP_IN, false);
913 break;
914 case CLOBBER:
915 /* We treat clobber of non-operand hard registers as early clobber. */
916 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0)(((op)->u.fld[0]).rt_rtx), data,
917 list, OP_OUT, true);
918 break;
919 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
920 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0)(((op)->u.fld[0]).rt_rtx), data,
921 list, OP_INOUT, false);
922 break;
923 case PRE_MODIFY: case POST_MODIFY:
924 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0)(((op)->u.fld[0]).rt_rtx), data,
925 list, OP_INOUT, false);
926 list = collect_non_operand_hard_regs (insn, &XEXP (op, 1)(((op)->u.fld[1]).rt_rtx), data,
927 list, OP_IN, false);
928 break;
929 default:
930 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
931 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
932 {
933 if (fmt[i] == 'e')
934 list = collect_non_operand_hard_regs (insn, &XEXP (op, i)(((op)->u.fld[i]).rt_rtx), data,
935 list, OP_IN, false);
936 else if (fmt[i] == 'E')
937 for (j = XVECLEN (op, i)(((((op)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
938 list = collect_non_operand_hard_regs (insn, &XVECEXP (op, i, j)(((((op)->u.fld[i]).rt_rtvec))->elem[j]),
939 data, list, OP_IN, false);
940 }
941 }
942 return list;
943}
944
945/* Set up and return info about INSN. Set up the info if it is not set up
946 yet. */
947lra_insn_recog_data_t
948lra_set_insn_recog_data (rtx_insn *insn)
949{
950 lra_insn_recog_data_t data;
951 int i, n, icode;
952 rtx **locs;
953 unsigned int uid = INSN_UID (insn);
954 struct lra_static_insn_data *insn_static_data;
955
956 check_and_expand_insn_recog_data (uid);
957 if (DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN))
958 icode = -1;
959 else
960 {
961 icode = INSN_CODE (insn)(((insn)->u.fld[5]).rt_int);
962 if (icode < 0)
963 /* It might be a new simple insn which is not recognized yet. */
964 INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) = icode = recog_memoized (insn);
965 }
966 data = lra_insn_recog_data_pool.allocate ();
967 lra_insn_recog_data[uid] = data;
968 data->insn = insn;
969 data->used_insn_alternative = LRA_UNKNOWN_ALT-1;
970 data->icode = icode;
971 data->regs = NULLnullptr;
972 if (DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN))
973 {
974 data->dup_loc = NULLnullptr;
975 data->arg_hard_regs = NULLnullptr;
976 data->preferred_alternatives = ALL_ALTERNATIVES((alternative_mask) -1);
977 if (DEBUG_BIND_INSN_P (insn)((((enum rtx_code) (insn)->code) == DEBUG_INSN) &&
(((enum rtx_code) (PATTERN (insn))->code) == VAR_LOCATION
))
)
978 {
979 data->insn_static_data = &debug_bind_static_data;
980 data->operand_loc = XNEWVEC (rtx *, 1)((rtx * *) xmalloc (sizeof (rtx *) * (1)));
981 data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn)((((((__extension__ ({ __typeof (PATTERN (insn)) const _rtx =
(PATTERN (insn)); if (((enum rtx_code) (_rtx)->code) != VAR_LOCATION
) rtl_check_failed_flag ("INSN_VAR_LOCATION", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 981, __FUNCTION__); _rtx; }))))->u.fld[1]).rt_rtx))
;
982 }
983 else if (DEBUG_MARKER_INSN_P (insn)((((enum rtx_code) (insn)->code) == DEBUG_INSN) &&
(((enum rtx_code) (PATTERN (insn))->code) != VAR_LOCATION
))
)
984 {
985 data->insn_static_data = &debug_marker_static_data;
986 data->operand_loc = NULLnullptr;
987 }
988 return data;
989 }
990 if (icode < 0)
991 {
992 int nop, nalt;
993 machine_mode operand_mode[MAX_RECOG_OPERANDS30];
994 const char *constraints[MAX_RECOG_OPERANDS30];
995
996 nop = asm_noperands (PATTERN (insn));
997 data->operand_loc = data->dup_loc = NULLnullptr;
998 nalt = 1;
999 if (nop < 0)
1000 {
1001 /* It is a special insn like USE or CLOBBER. We should
1002 recognize any regular insn otherwise LRA can do nothing
1003 with this insn. */
1004 gcc_assert (GET_CODE (PATTERN (insn)) == USE((void)(!(((enum rtx_code) (PATTERN (insn))->code) == USE ||
((enum rtx_code) (PATTERN (insn))->code) == CLOBBER || ((
enum rtx_code) (PATTERN (insn))->code) == ASM_INPUT) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1006, __FUNCTION__), 0 : 0))
1005 || GET_CODE (PATTERN (insn)) == CLOBBER((void)(!(((enum rtx_code) (PATTERN (insn))->code) == USE ||
((enum rtx_code) (PATTERN (insn))->code) == CLOBBER || ((
enum rtx_code) (PATTERN (insn))->code) == ASM_INPUT) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1006, __FUNCTION__), 0 : 0))
1006 || GET_CODE (PATTERN (insn)) == ASM_INPUT)((void)(!(((enum rtx_code) (PATTERN (insn))->code) == USE ||
((enum rtx_code) (PATTERN (insn))->code) == CLOBBER || ((
enum rtx_code) (PATTERN (insn))->code) == ASM_INPUT) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1006, __FUNCTION__), 0 : 0))
;
1007 data->insn_static_data = insn_static_data
1008 = get_static_insn_data (-1, 0, 0, nalt);
1009 }
1010 else
1011 {
1012 /* expand_asm_operands makes sure there aren't too many
1013 operands. */
1014 lra_assert (nop <= MAX_RECOG_OPERANDS)((void)(!(nop <= 30) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1014, __FUNCTION__), 0 : 0))
;
1015 if (nop != 0)
1016 data->operand_loc = XNEWVEC (rtx *, nop)((rtx * *) xmalloc (sizeof (rtx *) * (nop)));
1017 /* Now get the operand values and constraints out of the
1018 insn. */
1019 decode_asm_operands (PATTERN (insn), NULLnullptr,
1020 data->operand_loc,
1021 constraints, operand_mode, NULLnullptr);
1022 if (nop > 0)
1023 for (const char *p =constraints[0]; *p; p++)
1024 nalt += *p == ',';
1025 data->insn_static_data = insn_static_data
1026 = get_static_insn_data (-1, nop, 0, nalt);
1027 for (i = 0; i < nop; i++)
1028 {
1029 insn_static_data->operand[i].mode = operand_mode[i];
1030 insn_static_data->operand[i].constraint = constraints[i];
1031 insn_static_data->operand[i].strict_low = false;
1032 insn_static_data->operand[i].is_operator = false;
1033 insn_static_data->operand[i].is_address = false;
1034 }
1035 }
1036 for (i = 0; i < insn_static_data->n_operands; i++)
1037 insn_static_data->operand[i].type
1038 = (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT
1039 : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT
1040 : OP_IN);
1041 data->preferred_alternatives = ALL_ALTERNATIVES((alternative_mask) -1);
1042 if (nop > 0)
1043 {
1044 operand_alternative *op_alt = XCNEWVEC (operand_alternative,((operand_alternative *) xcalloc ((nalt * nop), sizeof (operand_alternative
)))
1045 nalt * nop)((operand_alternative *) xcalloc ((nalt * nop), sizeof (operand_alternative
)))
;
1046 preprocess_constraints (nop, nalt, constraints, op_alt,
1047 data->operand_loc);
1048 setup_operand_alternative (data, op_alt);
1049 }
1050 }
1051 else
1052 {
1053 insn_extract (insn);
1054 data->insn_static_data = insn_static_data
1055 = get_static_insn_data (icode, insn_data[icode].n_operands,
1056 insn_data[icode].n_dups,
1057 insn_data[icode].n_alternatives);
1058 n = insn_static_data->n_operands;
1059 if (n == 0)
1060 locs = NULLnullptr;
1061 else
1062 {
1063 locs = XNEWVEC (rtx *, n)((rtx * *) xmalloc (sizeof (rtx *) * (n)));
1064 memcpy (locs, recog_data.operand_loc, n * sizeof (rtx *));
1065 }
1066 data->operand_loc = locs;
1067 n = insn_static_data->n_dups;
1068 if (n == 0)
1069 locs = NULLnullptr;
1070 else
1071 {
1072 locs = XNEWVEC (rtx *, n)((rtx * *) xmalloc (sizeof (rtx *) * (n)));
1073 memcpy (locs, recog_data.dup_loc, n * sizeof (rtx *));
1074 }
1075 data->dup_loc = locs;
1076 data->preferred_alternatives = get_preferred_alternatives (insn);
1077 const operand_alternative *op_alt = preprocess_insn_constraints (icode);
1078 if (!insn_static_data->operand_alternative)
1079 setup_operand_alternative (data, op_alt);
1080 else if (op_alt != insn_static_data->operand_alternative)
1081 insn_static_data->operand_alternative = op_alt;
1082 }
1083 if (GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == CLOBBER || GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == USE)
1084 insn_static_data->hard_regs = NULLnullptr;
1085 else
1086 insn_static_data->hard_regs
1087 = collect_non_operand_hard_regs (insn, &PATTERN (insn), data,
1088 NULLnullptr, OP_IN, false);
1089 data->arg_hard_regs = NULLnullptr;
1090 if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
1091 {
1092 bool use_p;
1093 rtx link;
1094 int n_hard_regs, regno, arg_hard_regs[FIRST_PSEUDO_REGISTER76];
1095
1096 n_hard_regs = 0;
1097 /* Finding implicit hard register usage. We believe it will be
1098 not changed whatever transformations are used. Call insns
1099 are such example. */
1100 for (link = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx);
1101 link != NULL_RTX(rtx) 0;
1102 link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
1103 if (((use_p = GET_CODE (XEXP (link, 0))((enum rtx_code) ((((link)->u.fld[0]).rt_rtx))->code) == USE)
1104 || GET_CODE (XEXP (link, 0))((enum rtx_code) ((((link)->u.fld[0]).rt_rtx))->code) == CLOBBER)
1105 && REG_P (XEXP (XEXP (link, 0), 0))(((enum rtx_code) (((((((link)->u.fld[0]).rt_rtx))->u.fld
[0]).rt_rtx))->code) == REG)
)
1106 {
1107 regno = REGNO (XEXP (XEXP (link, 0), 0))(rhs_regno(((((((link)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx
)))
;
1108 lra_assert (regno < FIRST_PSEUDO_REGISTER)((void)(!(regno < 76) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1108, __FUNCTION__), 0 : 0))
;
1109 /* It is an argument register. */
1110 for (i = REG_NREGS (XEXP (XEXP (link, 0), 0))((&(((((((link)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx
))->u.reg)->nregs)
- 1; i >= 0; i--)
1111 arg_hard_regs[n_hard_regs++]
1112 = regno + i + (use_p ? 0 : FIRST_PSEUDO_REGISTER76);
1113 }
1114
1115 if (n_hard_regs != 0)
1116 {
1117 arg_hard_regs[n_hard_regs++] = -1;
1118 data->arg_hard_regs = XNEWVEC (int, n_hard_regs)((int *) xmalloc (sizeof (int) * (n_hard_regs)));
1119 memcpy (data->arg_hard_regs, arg_hard_regs,
1120 sizeof (int) * n_hard_regs);
1121 }
1122 }
1123 /* Some output operand can be recognized only from the context not
1124 from the constraints which are empty in this case. Call insn may
1125 contain a hard register in set destination with empty constraint
1126 and extract_insn treats them as an input. */
1127 for (i = 0; i < insn_static_data->n_operands; i++)
1128 {
1129 int j;
1130 rtx pat, set;
1131 struct lra_operand_data *operand = &insn_static_data->operand[i];
1132
1133 /* ??? Should we treat 'X' the same way. It looks to me that
1134 'X' means anything and empty constraint means we do not
1135 care. */
1136 if (operand->type != OP_IN || *operand->constraint != '\0'
1137 || operand->is_operator)
1138 continue;
1139 pat = PATTERN (insn);
1140 if (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET)
1141 {
1142 if (data->operand_loc[i] != &SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx))
1143 continue;
1144 }
1145 else if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
1146 {
1147 for (j = XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
1148 {
1149 set = XVECEXP (PATTERN (insn), 0, j)(((((PATTERN (insn))->u.fld[0]).rt_rtvec))->elem[j]);
1150 if (GET_CODE (set)((enum rtx_code) (set)->code) == SET
1151 && &SET_DEST (set)(((set)->u.fld[0]).rt_rtx) == data->operand_loc[i])
1152 break;
1153 }
1154 if (j < 0)
1155 continue;
1156 }
1157 else
1158 continue;
1159 operand->type = OP_OUT;
1160 }
1161 return data;
1162}
1163
1164/* Return info about insn give by UID. The info should be already set
1165 up. */
1166static lra_insn_recog_data_t
1167get_insn_recog_data_by_uid (int uid)
1168{
1169 lra_insn_recog_data_t data;
1170
1171 data = lra_insn_recog_data[uid];
1172 lra_assert (data != NULL)((void)(!(data != nullptr) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1172, __FUNCTION__), 0 : 0))
;
1173 return data;
1174}
1175
1176/* Invalidate all info about insn given by its UID. */
1177static void
1178invalidate_insn_recog_data (int uid)
1179{
1180 lra_insn_recog_data_t data;
1181
1182 data = lra_insn_recog_data[uid];
1183 lra_assert (data != NULL)((void)(!(data != nullptr) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1183, __FUNCTION__), 0 : 0))
;
1184 free_insn_recog_data (data);
1185 lra_insn_recog_data[uid] = NULLnullptr;
1186}
1187
1188/* Update all the insn info about INSN. It is usually called when
1189 something in the insn was changed. Return the updated info. */
1190lra_insn_recog_data_t
1191lra_update_insn_recog_data (rtx_insn *insn)
1192{
1193 lra_insn_recog_data_t data;
1194 int n;
1195 unsigned int uid = INSN_UID (insn);
1196 struct lra_static_insn_data *insn_static_data;
1197 poly_int64 sp_offset = 0;
1198
1199 check_and_expand_insn_recog_data (uid);
1200 if ((data = lra_insn_recog_data[uid]) != NULLnullptr
1201 && data->icode != INSN_CODE (insn)(((insn)->u.fld[5]).rt_int))
1202 {
1203 sp_offset = data->sp_offset;
1204 invalidate_insn_data_regno_info (data, insn, get_insn_freq (insn));
1205 invalidate_insn_recog_data (uid);
1206 data = NULLnullptr;
1207 }
1208 if (data == NULLnullptr)
1209 {
1210 data = lra_get_insn_recog_data (insn);
1211 /* Initiate or restore SP offset. */
1212 data->sp_offset = sp_offset;
1213 return data;
1214 }
1215 insn_static_data = data->insn_static_data;
1216 data->used_insn_alternative = LRA_UNKNOWN_ALT-1;
1217 if (DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN))
1218 return data;
1219 if (data->icode < 0)
1220 {
1221 int nop;
1222 machine_mode operand_mode[MAX_RECOG_OPERANDS30];
1223 const char *constraints[MAX_RECOG_OPERANDS30];
1224
1225 nop = asm_noperands (PATTERN (insn));
1226 if (nop >= 0)
1227 {
1228 lra_assert (nop == data->insn_static_data->n_operands)((void)(!(nop == data->insn_static_data->n_operands) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1228, __FUNCTION__), 0 : 0))
;
1229 /* Now get the operand values and constraints out of the
1230 insn. */
1231 decode_asm_operands (PATTERN (insn), NULLnullptr,
1232 data->operand_loc,
1233 constraints, operand_mode, NULLnullptr);
1234
1235 if (flag_checkingglobal_options.x_flag_checking)
1236 for (int i = 0; i < nop; i++)
1237 lra_assert((void)(!(insn_static_data->operand[i].mode == operand_mode
[i] && insn_static_data->operand[i].constraint == constraints
[i] && ! insn_static_data->operand[i].is_operator)
? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1240, __FUNCTION__), 0 : 0))
1238 (insn_static_data->operand[i].mode == operand_mode[i]((void)(!(insn_static_data->operand[i].mode == operand_mode
[i] && insn_static_data->operand[i].constraint == constraints
[i] && ! insn_static_data->operand[i].is_operator)
? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1240, __FUNCTION__), 0 : 0))
1239 && insn_static_data->operand[i].constraint == constraints[i]((void)(!(insn_static_data->operand[i].mode == operand_mode
[i] && insn_static_data->operand[i].constraint == constraints
[i] && ! insn_static_data->operand[i].is_operator)
? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1240, __FUNCTION__), 0 : 0))
1240 && ! insn_static_data->operand[i].is_operator)((void)(!(insn_static_data->operand[i].mode == operand_mode
[i] && insn_static_data->operand[i].constraint == constraints
[i] && ! insn_static_data->operand[i].is_operator)
? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1240, __FUNCTION__), 0 : 0))
;
1241 }
1242
1243 if (flag_checkingglobal_options.x_flag_checking)
1244 for (int i = 0; i < insn_static_data->n_operands; i++)
1245 lra_assert((void)(!(insn_static_data->operand[i].type == (insn_static_data
->operand[i].constraint[0] == '=' ? OP_OUT : insn_static_data
->operand[i].constraint[0] == '+' ? OP_INOUT : OP_IN)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1249, __FUNCTION__), 0 : 0))
1246 (insn_static_data->operand[i].type((void)(!(insn_static_data->operand[i].type == (insn_static_data
->operand[i].constraint[0] == '=' ? OP_OUT : insn_static_data
->operand[i].constraint[0] == '+' ? OP_INOUT : OP_IN)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1249, __FUNCTION__), 0 : 0))
1247 == (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT((void)(!(insn_static_data->operand[i].type == (insn_static_data
->operand[i].constraint[0] == '=' ? OP_OUT : insn_static_data
->operand[i].constraint[0] == '+' ? OP_INOUT : OP_IN)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1249, __FUNCTION__), 0 : 0))
1248 : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT((void)(!(insn_static_data->operand[i].type == (insn_static_data
->operand[i].constraint[0] == '=' ? OP_OUT : insn_static_data
->operand[i].constraint[0] == '+' ? OP_INOUT : OP_IN)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1249, __FUNCTION__), 0 : 0))
1249 : OP_IN))((void)(!(insn_static_data->operand[i].type == (insn_static_data
->operand[i].constraint[0] == '=' ? OP_OUT : insn_static_data
->operand[i].constraint[0] == '+' ? OP_INOUT : OP_IN)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1249, __FUNCTION__), 0 : 0))
;
1250 }
1251 else
1252 {
1253 insn_extract (insn);
1254 n = insn_static_data->n_operands;
1255 if (n != 0)
1256 memcpy (data->operand_loc, recog_data.operand_loc, n * sizeof (rtx *));
1257 n = insn_static_data->n_dups;
1258 if (n != 0)
1259 memcpy (data->dup_loc, recog_data.dup_loc, n * sizeof (rtx *));
1260 lra_assert (check_bool_attrs (insn))((void)(!(check_bool_attrs (insn)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1260, __FUNCTION__), 0 : 0))
;
1261 }
1262 return data;
1263}
1264
1265/* Set up that INSN is using alternative ALT now. */
1266void
1267lra_set_used_insn_alternative (rtx_insn *insn, int alt)
1268{
1269 lra_insn_recog_data_t data;
1270
1271 data = lra_get_insn_recog_data (insn);
1272 data->used_insn_alternative = alt;
1273}
1274
1275/* Set up that insn with UID is using alternative ALT now. The insn
1276 info should be already set up. */
1277void
1278lra_set_used_insn_alternative_by_uid (int uid, int alt)
1279{
1280 lra_insn_recog_data_t data;
1281
1282 check_and_expand_insn_recog_data (uid);
1283 data = lra_insn_recog_data[uid];
1284 lra_assert (data != NULL)((void)(!(data != nullptr) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1284, __FUNCTION__), 0 : 0))
;
1285 data->used_insn_alternative = alt;
1286}
1287
1288
1289
1290/* This page contains code dealing with common register info and
1291 pseudo copies. */
1292
1293/* The size of the following array. */
1294static int reg_info_size;
1295/* Common info about each register. */
1296class lra_reg *lra_reg_info;
1297
1298HARD_REG_SET hard_regs_spilled_into;
1299
1300/* Last register value. */
1301static int last_reg_value;
1302
1303/* Return new register value. */
1304static int
1305get_new_reg_value (void)
1306{
1307 return ++last_reg_value;
1308}
1309
1310/* Vec referring to pseudo copies. */
1311static vec<lra_copy_t> copy_vec;
1312
1313/* Initialize I-th element of lra_reg_info. */
1314static inline void
1315initialize_lra_reg_info_element (int i)
1316{
1317 bitmap_initialize (&lra_reg_info[i].insn_bitmap, &reg_obstack);
1318#ifdef STACK_REGS
1319 lra_reg_info[i].no_stack_p = false;
1320#endif
1321 CLEAR_HARD_REG_SET (lra_reg_info[i].conflict_hard_regs);
1322 lra_reg_info[i].preferred_hard_regno1 = -1;
1323 lra_reg_info[i].preferred_hard_regno2 = -1;
1324 lra_reg_info[i].preferred_hard_regno_profit1 = 0;
1325 lra_reg_info[i].preferred_hard_regno_profit2 = 0;
1326 lra_reg_info[i].biggest_mode = VOIDmode((void) 0, E_VOIDmode);
1327 lra_reg_info[i].live_ranges = NULLnullptr;
1328 lra_reg_info[i].nrefs = lra_reg_info[i].freq = 0;
1329 lra_reg_info[i].last_reload = 0;
1330 lra_reg_info[i].restore_rtx = NULL_RTX(rtx) 0;
1331 lra_reg_info[i].val = get_new_reg_value ();
1332 lra_reg_info[i].offset = 0;
1333 lra_reg_info[i].copies = NULLnullptr;
1334}
1335
1336/* Initialize common reg info and copies. */
1337static void
1338init_reg_info (void)
1339{
1340 int i;
1341
1342 last_reg_value = 0;
1343 reg_info_size = max_reg_num () * 3 / 2 + 1;
1344 lra_reg_info = XNEWVEC (class lra_reg, reg_info_size)((class lra_reg *) xmalloc (sizeof (class lra_reg) * (reg_info_size
)))
;
1345 for (i = 0; i < reg_info_size; i++)
1346 initialize_lra_reg_info_element (i);
1347 copy_vec.truncate (0);
1348 CLEAR_HARD_REG_SET (hard_regs_spilled_into);
1349}
1350
1351
1352/* Finish common reg info and copies. */
1353static void
1354finish_reg_info (void)
1355{
1356 int i;
1357
1358 for (i = 0; i < reg_info_size; i++)
1359 bitmap_clear (&lra_reg_info[i].insn_bitmap);
1360 free (lra_reg_info);
1361 reg_info_size = 0;
1362}
1363
1364/* Expand common reg info if it is necessary. */
1365static void
1366expand_reg_info (void)
1367{
1368 int i, old = reg_info_size;
1369
1370 if (reg_info_size > max_reg_num ())
1371 return;
1372 reg_info_size = max_reg_num () * 3 / 2 + 1;
1373 lra_reg_info = XRESIZEVEC (class lra_reg, lra_reg_info, reg_info_size)((class lra_reg *) xrealloc ((void *) (lra_reg_info), sizeof (
class lra_reg) * (reg_info_size)))
;
1374 for (i = old; i < reg_info_size; i++)
1375 initialize_lra_reg_info_element (i);
1376}
1377
1378/* Free all copies. */
1379void
1380lra_free_copies (void)
1381{
1382 lra_copy_t cp;
1383
1384 while (copy_vec.length () != 0)
1385 {
1386 cp = copy_vec.pop ();
1387 lra_reg_info[cp->regno1].copies = lra_reg_info[cp->regno2].copies = NULLnullptr;
1388 lra_copy_pool.remove (cp);
1389 }
1390}
1391
1392/* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1393 frequency is FREQ. */
1394void
1395lra_create_copy (int regno1, int regno2, int freq)
1396{
1397 bool regno1_dest_p;
1398 lra_copy_t cp;
1399
1400 lra_assert (regno1 != regno2)((void)(!(regno1 != regno2) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1400, __FUNCTION__), 0 : 0))
;
1401 regno1_dest_p = true;
1402 if (regno1 > regno2)
1403 {
1404 std::swap (regno1, regno2);
1405 regno1_dest_p = false;
1406 }
1407 cp = lra_copy_pool.allocate ();
1408 copy_vec.safe_push (cp);
1409 cp->regno1_dest_p = regno1_dest_p;
1410 cp->freq = freq;
1411 cp->regno1 = regno1;
1412 cp->regno2 = regno2;
1413 cp->regno1_next = lra_reg_info[regno1].copies;
1414 lra_reg_info[regno1].copies = cp;
1415 cp->regno2_next = lra_reg_info[regno2].copies;
1416 lra_reg_info[regno2].copies = cp;
1417 if (lra_dump_file != NULLnullptr)
1418 fprintf (lra_dump_file, " Creating copy r%d%sr%d@%d\n",
1419 regno1, regno1_dest_p ? "<-" : "->", regno2, freq);
1420}
1421
1422/* Return N-th (0, 1, ...) copy. If there is no copy, return
1423 NULL. */
1424lra_copy_t
1425lra_get_copy (int n)
1426{
1427 if (n >= (int) copy_vec.length ())
1428 return NULLnullptr;
1429 return copy_vec[n];
1430}
1431
1432
1433
1434/* This page contains code dealing with info about registers in
1435 insns. */
1436
1437/* Process X of INSN recursively and add info (operand type is given
1438 by TYPE) about registers in X to the insn DATA. If X can be early
1439 clobbered, alternatives in which it can be early clobbered are given
1440 by EARLY_CLOBBER_ALTS. */
1441static void
1442add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x,
1443 rtx_insn *insn, enum op_type type,
1444 alternative_mask early_clobber_alts)
1445{
1446 int i, j, regno;
1447 bool subreg_p;
1448 machine_mode mode;
1449 const char *fmt;
1450 enum rtx_code code;
1451 struct lra_insn_reg *curr;
1452
1453 code = GET_CODE (x)((enum rtx_code) (x)->code);
1454 mode = GET_MODE (x)((machine_mode) (x)->mode);
1455 subreg_p = false;
1456 if (GET_CODE (x)((enum rtx_code) (x)->code) == SUBREG)
1457 {
1458 mode = wider_subreg_mode (x);
1459 if (read_modify_subreg_p (x))
1460 subreg_p = true;
1461 x = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
1462 code = GET_CODE (x)((enum rtx_code) (x)->code);
1463 }
1464 if (REG_P (x)(((enum rtx_code) (x)->code) == REG))
1465 {
1466 regno = REGNO (x)(rhs_regno(x));
1467 /* Process all regs even unallocatable ones as we need info about
1468 all regs for rematerialization pass. */
1469 expand_reg_info ();
1470 if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, INSN_UID (insn)))
1471 {
1472 data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p,
1473 early_clobber_alts, data->regs);
1474 return;
1475 }
1476 else
1477 {
1478 for (curr = data->regs; curr != NULLnullptr; curr = curr->next)
1479 if (curr->regno == regno)
1480 {
1481 if (curr->subreg_p != subreg_p || curr->biggest_mode != mode)
1482 /* The info cannot be integrated into the found
1483 structure. */
1484 data->regs = new_insn_reg (data->insn, regno, type, mode,
1485 subreg_p, early_clobber_alts,
1486 data->regs);
1487 else
1488 {
1489 if (curr->type != type)
1490 curr->type = OP_INOUT;
1491 curr->early_clobber_alts |= early_clobber_alts;
1492 }
1493 return;
1494 }
1495 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1495, __FUNCTION__))
;
1496 }
1497 }
1498
1499 switch (code)
1500 {
1501 case SET:
1502 add_regs_to_insn_regno_info (data, SET_DEST (x)(((x)->u.fld[0]).rt_rtx), insn, OP_OUT, 0);
1503 add_regs_to_insn_regno_info (data, SET_SRC (x)(((x)->u.fld[1]).rt_rtx), insn, OP_IN, 0);
1504 break;
1505 case CLOBBER:
1506 /* We treat clobber of non-operand hard registers as early
1507 clobber. */
1508 add_regs_to_insn_regno_info (data, XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), insn, OP_OUT,
1509 ALL_ALTERNATIVES((alternative_mask) -1));
1510 break;
1511 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
1512 add_regs_to_insn_regno_info (data, XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), insn, OP_INOUT, 0);
1513 break;
1514 case PRE_MODIFY: case POST_MODIFY:
1515 add_regs_to_insn_regno_info (data, XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), insn, OP_INOUT, 0);
1516 add_regs_to_insn_regno_info (data, XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), insn, OP_IN, 0);
1517 break;
1518 default:
1519 if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT)
1520 /* Some targets place small structures in registers for return
1521 values of functions, and those registers are wrapped in
1522 PARALLEL that we may see as the destination of a SET. Here
1523 is an example:
1524
1525 (call_insn 13 12 14 2 (set (parallel:BLK [
1526 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1527 (const_int 0 [0]))
1528 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1529 (const_int 8 [0x8]))
1530 ])
1531 (call (mem:QI (symbol_ref:DI (... */
1532 type = OP_IN;
1533 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
1534 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
1535 {
1536 if (fmt[i] == 'e')
1537 add_regs_to_insn_regno_info (data, XEXP (x, i)(((x)->u.fld[i]).rt_rtx), insn, type, 0);
1538 else if (fmt[i] == 'E')
1539 {
1540 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
1541 add_regs_to_insn_regno_info (data, XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), insn,
1542 type, 0);
1543 }
1544 }
1545 }
1546}
1547
1548/* Return execution frequency of INSN. */
1549static int
1550get_insn_freq (rtx_insn *insn)
1551{
1552 basic_block bb = BLOCK_FOR_INSN (insn);
1553
1554 gcc_checking_assert (bb != NULL)((void)(!(bb != nullptr) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1554, __FUNCTION__), 0 : 0))
;
1555 return REG_FREQ_FROM_BB (bb)((optimize_function_for_size_p ((cfun + 0)) || !(cfun + 0)->
cfg->count_max.initialized_p ()) ? 1000 : ((bb)->count.
to_frequency ((cfun + 0)) * 1000 / 10000) ? ((bb)->count.to_frequency
((cfun + 0)) * 1000 / 10000) : 1)
;
1556}
1557
1558/* Invalidate all reg info of INSN with DATA and execution frequency
1559 FREQ. Update common info about the invalidated registers. */
1560static void
1561invalidate_insn_data_regno_info (lra_insn_recog_data_t data, rtx_insn *insn,
1562 int freq)
1563{
1564 int uid;
1565 bool debug_p;
1566 unsigned int i;
1567 struct lra_insn_reg *ir, *next_ir;
1568
1569 uid = INSN_UID (insn);
1570 debug_p = DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN);
1571 for (ir = data->regs; ir != NULLnullptr; ir = next_ir)
1572 {
1573 i = ir->regno;
1574 next_ir = ir->next;
1575 lra_insn_reg_pool.remove (ir);
1576 bitmap_clear_bit (&lra_reg_info[i].insn_bitmap, uid);
1577 if (i >= FIRST_PSEUDO_REGISTER76 && ! debug_p)
1578 {
1579 lra_reg_info[i].nrefs--;
1580 lra_reg_info[i].freq -= freq;
1581 lra_assert (lra_reg_info[i].nrefs >= 0 && lra_reg_info[i].freq >= 0)((void)(!(lra_reg_info[i].nrefs >= 0 && lra_reg_info
[i].freq >= 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1581, __FUNCTION__), 0 : 0))
;
1582 }
1583 }
1584 data->regs = NULLnullptr;
1585}
1586
1587/* Invalidate all reg info of INSN. Update common info about the
1588 invalidated registers. */
1589void
1590lra_invalidate_insn_regno_info (rtx_insn *insn)
1591{
1592 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn), insn,
1593 get_insn_freq (insn));
1594}
1595
1596/* Update common reg info from reg info of insn given by its DATA and
1597 execution frequency FREQ. */
1598static void
1599setup_insn_reg_info (lra_insn_recog_data_t data, int freq)
1600{
1601 unsigned int i;
1602 struct lra_insn_reg *ir;
1603
1604 for (ir = data->regs; ir != NULLnullptr; ir = ir->next)
1605 if ((i = ir->regno) >= FIRST_PSEUDO_REGISTER76)
1606 {
1607 lra_reg_info[i].nrefs++;
1608 lra_reg_info[i].freq += freq;
1609 }
1610}
1611
1612/* Set up insn reg info of INSN. Update common reg info from reg info
1613 of INSN. */
1614void
1615lra_update_insn_regno_info (rtx_insn *insn)
1616{
1617 int i, freq;
1618 lra_insn_recog_data_t data;
1619 struct lra_static_insn_data *static_data;
1620 enum rtx_code code;
1621 rtx link;
1622
1623 if (! INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
)
1624 return;
1625 data = lra_get_insn_recog_data (insn);
1626 static_data = data->insn_static_data;
1627 freq = NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN))
? get_insn_freq (insn) : 0;
1628 invalidate_insn_data_regno_info (data, insn, freq);
1629 for (i = static_data->n_operands - 1; i >= 0; i--)
1630 add_regs_to_insn_regno_info (data, *data->operand_loc[i], insn,
1631 static_data->operand[i].type,
1632 static_data->operand[i].early_clobber_alts);
1633 if ((code = GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code)) == CLOBBER || code == USE)
1634 add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0)(((PATTERN (insn))->u.fld[0]).rt_rtx), insn,
1635 code == USE ? OP_IN : OP_OUT, 0);
1636 if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
1637 /* On some targets call insns can refer to pseudos in memory in
1638 CALL_INSN_FUNCTION_USAGE list. Process them in order to
1639 consider their occurrences in calls for different
1640 transformations (e.g. inheritance) with given pseudos. */
1641 for (link = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx);
1642 link != NULL_RTX(rtx) 0;
1643 link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
1644 {
1645 code = GET_CODE (XEXP (link, 0))((enum rtx_code) ((((link)->u.fld[0]).rt_rtx))->code);
1646 if ((code == USE || code == CLOBBER)
1647 && MEM_P (XEXP (XEXP (link, 0), 0))(((enum rtx_code) (((((((link)->u.fld[0]).rt_rtx))->u.fld
[0]).rt_rtx))->code) == MEM)
)
1648 add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0)((((((link)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx), insn,
1649 code == USE ? OP_IN : OP_OUT, 0);
1650 }
1651 if (NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN))
)
1652 setup_insn_reg_info (data, freq);
1653}
1654
1655/* Return reg info of insn given by it UID. */
1656struct lra_insn_reg *
1657lra_get_insn_regs (int uid)
1658{
1659 lra_insn_recog_data_t data;
1660
1661 data = get_insn_recog_data_by_uid (uid);
1662 return data->regs;
1663}
1664
1665
1666
1667/* Recursive hash function for RTL X. */
1668hashval_t
1669lra_rtx_hash (rtx x)
1670{
1671 int i, j;
1672 enum rtx_code code;
1673 const char *fmt;
1674 hashval_t val = 0;
1675
1676 if (x == 0)
1677 return val;
1678
1679 code = GET_CODE (x)((enum rtx_code) (x)->code);
1680 val += (int) code + 4095;
1681
1682 /* Some RTL can be compared nonrecursively. */
1683 switch (code)
1684 {
1685 case REG:
1686 return val + REGNO (x)(rhs_regno(x));
1687
1688 case LABEL_REF:
1689 return iterative_hash_object (XEXP (x, 0), val)iterative_hash (&(((x)->u.fld[0]).rt_rtx), sizeof ((((
x)->u.fld[0]).rt_rtx)), val)
;
1690
1691 case SYMBOL_REF:
1692 return iterative_hash_object (XSTR (x, 0), val)iterative_hash (&(((x)->u.fld[0]).rt_str), sizeof ((((
x)->u.fld[0]).rt_str)), val)
;
1693
1694 case SCRATCH:
1695 case CONST_DOUBLE:
1696 case CONST_VECTOR:
1697 return val;
1698
1699 case CONST_INT:
1700 return val + UINTVAL (x)((unsigned long) ((x)->u.hwint[0]));
1701
1702 default:
1703 break;
1704 }
1705
1706 /* Hash the elements. */
1707 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
1708 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
1709 {
1710 switch (fmt[i])
1711 {
1712 case 'w':
1713 val += XWINT (x, i)((x)->u.hwint[i]);
1714 break;
1715
1716 case 'n':
1717 case 'i':
1718 val += XINT (x, i)(((x)->u.fld[i]).rt_int);
1719 break;
1720
1721 case 'V':
1722 case 'E':
1723 val += XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem);
1724
1725 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
1726 val += lra_rtx_hash (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]));
1727 break;
1728
1729 case 'e':
1730 val += lra_rtx_hash (XEXP (x, i)(((x)->u.fld[i]).rt_rtx));
1731 break;
1732
1733 case 'S':
1734 case 's':
1735 val += htab_hash_string (XSTR (x, i)(((x)->u.fld[i]).rt_str));
1736 break;
1737
1738 case 'u':
1739 case '0':
1740 case 't':
1741 break;
1742
1743 /* It is believed that rtx's at this level will never
1744 contain anything but integers and other rtx's, except for
1745 within LABEL_REFs and SYMBOL_REFs. */
1746 default:
1747 abort ()fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1747, __FUNCTION__)
;
1748 }
1749 }
1750 return val;
1751}
1752
1753
1754
1755/* This page contains code dealing with stack of the insns which
1756 should be processed by the next constraint pass. */
1757
1758/* Bitmap used to put an insn on the stack only in one exemplar. */
1759static sbitmap lra_constraint_insn_stack_bitmap;
1760
1761/* The stack itself. */
1762vec<rtx_insn *> lra_constraint_insn_stack;
1763
1764/* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1765 info for INSN, otherwise only update it if INSN is not already on the
1766 stack. */
1767static inline void
1768lra_push_insn_1 (rtx_insn *insn, bool always_update)
1769{
1770 unsigned int uid = INSN_UID (insn);
1771 if (always_update)
1772 lra_update_insn_regno_info (insn);
1773 if (uid >= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap)((lra_constraint_insn_stack_bitmap)->n_bits))
1774 lra_constraint_insn_stack_bitmap =
1775 sbitmap_resize (lra_constraint_insn_stack_bitmap, 3 * uid / 2, 0);
1776 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap, uid))
1777 return;
1778 bitmap_set_bit (lra_constraint_insn_stack_bitmap, uid);
1779 if (! always_update)
1780 lra_update_insn_regno_info (insn);
1781 lra_constraint_insn_stack.safe_push (insn);
1782}
1783
1784/* Put INSN on the stack. */
1785void
1786lra_push_insn (rtx_insn *insn)
1787{
1788 lra_push_insn_1 (insn, false);
1789}
1790
1791/* Put INSN on the stack and update its reg info. */
1792void
1793lra_push_insn_and_update_insn_regno_info (rtx_insn *insn)
1794{
1795 lra_push_insn_1 (insn, true);
1796}
1797
1798/* Put insn with UID on the stack. */
1799void
1800lra_push_insn_by_uid (unsigned int uid)
1801{
1802 lra_push_insn (lra_insn_recog_data[uid]->insn);
1803}
1804
1805/* Take the last-inserted insns off the stack and return it. */
1806rtx_insn *
1807lra_pop_insn (void)
1808{
1809 rtx_insn *insn = lra_constraint_insn_stack.pop ();
1810 bitmap_clear_bit (lra_constraint_insn_stack_bitmap, INSN_UID (insn));
1811 return insn;
1812}
1813
1814/* Return the current size of the insn stack. */
1815unsigned int
1816lra_insn_stack_length (void)
1817{
1818 return lra_constraint_insn_stack.length ();
1819}
1820
1821/* Push insns FROM to TO (excluding it) going in reverse order. */
1822static void
1823push_insns (rtx_insn *from, rtx_insn *to)
1824{
1825 rtx_insn *insn;
1826
1827 if (from == NULL_RTX(rtx) 0)
1828 return;
1829 for (insn = from; insn != to; insn = PREV_INSN (insn))
1830 if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
)
1831 lra_push_insn (insn);
1832}
1833
1834/* Set up sp offset for insn in range [FROM, LAST]. The offset is
1835 taken from the next BB insn after LAST or zero if there in such
1836 insn. */
1837static void
1838setup_sp_offset (rtx_insn *from, rtx_insn *last)
1839{
1840 rtx_insn *before = next_nonnote_nondebug_insn_bb (last);
1841 poly_int64 offset = (before == NULL_RTX(rtx) 0 || ! INSN_P (before)(((((enum rtx_code) (before)->code) == INSN) || (((enum rtx_code
) (before)->code) == JUMP_INSN) || (((enum rtx_code) (before
)->code) == CALL_INSN)) || (((enum rtx_code) (before)->
code) == DEBUG_INSN))
1842 ? 0 : lra_get_insn_recog_data (before)->sp_offset);
1843
1844 for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
1845 lra_get_insn_recog_data (insn)->sp_offset = offset;
1846}
1847
1848/* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1849 insns onto the stack. Print about emitting the insns with
1850 TITLE. */
1851void
1852lra_process_new_insns (rtx_insn *insn, rtx_insn *before, rtx_insn *after,
1853 const char *title)
1854{
1855 if (before == NULL_RTX(rtx) 0 && after == NULL_RTX(rtx) 0)
1856 return;
1857 if (lra_dump_file != NULLnullptr)
1858 {
1859 dump_insn_slim (lra_dump_file, insn);
1860 if (before != NULL_RTX(rtx) 0)
1861 {
1862 fprintf (lra_dump_file," %s before:\n", title);
1863 dump_rtl_slim (lra_dump_file, before, NULLnullptr, -1, 0);
1864 }
1865 }
1866 if (before != NULL_RTX(rtx) 0)
1867 {
1868 if (cfun(cfun + 0)->can_throw_non_call_exceptions)
1869 copy_reg_eh_region_note_forward (insn, before, NULLnullptr);
1870 emit_insn_before (before, insn);
1871 push_insns (PREV_INSN (insn), PREV_INSN (before));
1872 setup_sp_offset (before, PREV_INSN (insn));
1873 }
1874 if (after != NULL_RTX(rtx) 0)
1875 {
1876 if (cfun(cfun + 0)->can_throw_non_call_exceptions)
1877 copy_reg_eh_region_note_forward (insn, after, NULLnullptr);
1878 if (! JUMP_P (insn)(((enum rtx_code) (insn)->code) == JUMP_INSN))
1879 {
1880 rtx_insn *last;
1881
1882 if (lra_dump_file != NULLnullptr)
1883 {
1884 fprintf (lra_dump_file, " %s after:\n", title);
1885 dump_rtl_slim (lra_dump_file, after, NULLnullptr, -1, 0);
1886 }
1887 for (last = after;
1888 NEXT_INSN (last) != NULL_RTX(rtx) 0;
1889 last = NEXT_INSN (last))
1890 ;
1891 emit_insn_after (after, insn);
1892 push_insns (last, insn);
1893 setup_sp_offset (after, last);
1894 }
1895 else
1896 {
1897 /* Put output reload insns on successor BBs: */
1898 edge_iterator ei;
1899 edge e;
1900
1901 FOR_EACH_EDGE (e, ei, BLOCK_FOR_INSN (insn)->succs)for ((ei) = ei_start_1 (&((BLOCK_FOR_INSN (insn)->succs
))); ei_cond ((ei), &(e)); ei_next (&(ei)))
1902 if (e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_exit_block_ptr))
1903 {
1904 /* We already made the edge no-critical in ira.c::ira */
1905 lra_assert (!EDGE_CRITICAL_P (e))((void)(!(!(vec_safe_length ((e)->src->succs) >= 2 &&
vec_safe_length ((e)->dest->preds) >= 2)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 1905, __FUNCTION__), 0 : 0))
;
1906 rtx_insn *curr, *tmp = BB_HEAD (e->dest)(e->dest)->il.x.head_;
1907 if (LABEL_P (tmp)(((enum rtx_code) (tmp)->code) == CODE_LABEL))
1908 tmp = NEXT_INSN (tmp);
1909 if (NOTE_INSN_BASIC_BLOCK_P (tmp)((((enum rtx_code) (tmp)->code) == NOTE) && (((tmp
)->u.fld[4]).rt_int) == NOTE_INSN_BASIC_BLOCK)
)
1910 tmp = NEXT_INSN (tmp);
1911 /* Do not put reload insns if it is the last BB
1912 without actual insns. */
1913 if (tmp == NULLnullptr)
1914 continue;
1915 start_sequence ();
1916 for (curr = after; curr != NULL_RTX(rtx) 0; curr = NEXT_INSN (curr))
1917 emit_insn (copy_insn (PATTERN (curr)));
1918 rtx_insn *copy = get_insns (), *last = get_last_insn ();
1919 end_sequence ();
1920 if (lra_dump_file != NULLnullptr)
1921 {
1922 fprintf (lra_dump_file, " %s after in bb%d:\n", title,
1923 e->dest->index);
1924 dump_rtl_slim (lra_dump_file, copy, NULLnullptr, -1, 0);
1925 }
1926 /* Use the right emit func for setting up BB_END/BB_HEAD: */
1927 if (BB_END (e->dest)(e->dest)->il.x.rtl->end_ == PREV_INSN (tmp))
1928 emit_insn_after_noloc (copy, PREV_INSN (tmp), e->dest);
1929 else
1930 emit_insn_before_noloc (copy, tmp, e->dest);
1931 push_insns (last, PREV_INSN (copy));
1932 setup_sp_offset (copy, last);
1933 /* We can ignore BB live info here as it and reg notes
1934 will be updated before the next assignment
1935 sub-pass. */
1936 }
1937 }
1938 }
1939 if (lra_dump_file != NULLnullptr)
1940 fprintf (lra_dump_file, "\n");
1941 if (cfun(cfun + 0)->can_throw_non_call_exceptions)
1942 {
1943 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX(rtx) 0);
1944 if (note && !insn_could_throw_p (insn))
1945 remove_note (insn, note);
1946 }
1947}
1948
1949
1950/* Replace all references to register OLD_REGNO in *LOC with pseudo
1951 register NEW_REG. Try to simplify subreg of constant if SUBREG_P.
1952 DEBUG_P is if LOC is within a DEBUG_INSN. Return true if any
1953 change was made. */
1954bool
1955lra_substitute_pseudo (rtx *loc, int old_regno, rtx new_reg, bool subreg_p,
1956 bool debug_p)
1957{
1958 rtx x = *loc;
1959 bool result = false;
1960 enum rtx_code code;
1961 const char *fmt;
1962 int i, j;
1963
1964 if (x == NULL_RTX(rtx) 0)
1965 return false;
1966
1967 code = GET_CODE (x)((enum rtx_code) (x)->code);
1968 if (code == SUBREG && subreg_p)
1969 {
1970 rtx subst, inner = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
1971 /* Transform subreg of constant while we still have inner mode
1972 of the subreg. The subreg internal should not be an insn
1973 operand. */
1974 if (REG_P (inner)(((enum rtx_code) (inner)->code) == REG) && (int) REGNO (inner)(rhs_regno(inner)) == old_regno
1975 && CONSTANT_P (new_reg)((rtx_class[(int) (((enum rtx_code) (new_reg)->code))]) ==
RTX_CONST_OBJ)
1976 && (subst = simplify_subreg (GET_MODE (x)((machine_mode) (x)->mode), new_reg, GET_MODE (inner)((machine_mode) (inner)->mode),
1977 SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg))) != NULL_RTX(rtx) 0)
1978 {
1979 *loc = subst;
1980 return true;
1981 }
1982
1983 }
1984 else if (code == REG && (int) REGNO (x)(rhs_regno(x)) == old_regno)
1985 {
1986 machine_mode mode = GET_MODE (x)((machine_mode) (x)->mode);
1987 machine_mode inner_mode = GET_MODE (new_reg)((machine_mode) (new_reg)->mode);
1988
1989 if (mode != inner_mode
1990 && ! (CONST_SCALAR_INT_P (new_reg)((((enum rtx_code) (new_reg)->code) == CONST_INT) || (((enum
rtx_code) (new_reg)->code) == CONST_WIDE_INT))
&& SCALAR_INT_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_INT || ((enum mode_class
) mode_class[mode]) == MODE_PARTIAL_INT)
))
1991 {
1992 poly_uint64 offset = 0;
1993 if (partial_subreg_p (mode, inner_mode)
1994 && SCALAR_INT_MODE_P (inner_mode)(((enum mode_class) mode_class[inner_mode]) == MODE_INT || ((
enum mode_class) mode_class[inner_mode]) == MODE_PARTIAL_INT)
)
1995 offset = subreg_lowpart_offset (mode, inner_mode);
1996 if (debug_p)
1997 new_reg = gen_rtx_raw_SUBREG (mode, new_reg, offset)gen_rtx_fmt_ep_stat ((SUBREG), ((mode)), ((new_reg)), ((offset
)) )
;
1998 else
1999 new_reg = gen_rtx_SUBREG (mode, new_reg, offset);
2000 }
2001 *loc = new_reg;
2002 return true;
2003 }
2004
2005 /* Scan all the operand sub-expressions. */
2006 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
2007 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
2008 {
2009 if (fmt[i] == 'e')
2010 {
2011 if (lra_substitute_pseudo (&XEXP (x, i)(((x)->u.fld[i]).rt_rtx), old_regno,
2012 new_reg, subreg_p, debug_p))
2013 result = true;
2014 }
2015 else if (fmt[i] == 'E')
2016 {
2017 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
2018 if (lra_substitute_pseudo (&XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), old_regno,
2019 new_reg, subreg_p, debug_p))
2020 result = true;
2021 }
2022 }
2023 return result;
2024}
2025
2026/* Call lra_substitute_pseudo within an insn. Try to simplify subreg
2027 of constant if SUBREG_P. This won't update the insn ptr, just the
2028 contents of the insn. */
2029bool
2030lra_substitute_pseudo_within_insn (rtx_insn *insn, int old_regno,
2031 rtx new_reg, bool subreg_p)
2032{
2033 rtx loc = insn;
2034 return lra_substitute_pseudo (&loc, old_regno, new_reg, subreg_p,
2035 DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN));
2036}
2037
2038
2039
2040/* Return new register of the same mode as ORIGINAL of class ALL_REGS.
2041 Used in ira_remove_scratches. */
2042static rtx
2043get_scratch_reg (rtx original)
2044{
2045 return lra_create_new_reg (GET_MODE (original)((machine_mode) (original)->mode), original, ALL_REGS, NULLnullptr);
2046}
2047
2048/* Remove all insn scratches in INSN. */
2049static void
2050remove_insn_scratches (rtx_insn *insn)
2051{
2052 if (ira_remove_insn_scratches (insn, true, lra_dump_file, get_scratch_reg))
2053 df_insn_rescan (insn);
2054}
2055
2056/* Remove all insn scratches in the current function. */
2057static void
2058remove_scratches (void)
2059{
2060 basic_block bb;
2061 rtx_insn *insn;
2062
2063 FOR_EACH_BB_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_entry_block_ptr->next_bb
; bb != ((cfun + 0))->cfg->x_exit_block_ptr; bb = bb->
next_bb)
2064 FOR_BB_INSNS (bb, insn)for ((insn) = (bb)->il.x.head_; (insn) && (insn) !=
NEXT_INSN ((bb)->il.x.rtl->end_); (insn) = NEXT_INSN (
insn))
2065 if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
)
2066 remove_insn_scratches (insn);
2067}
2068
2069/* Function checks RTL for correctness. If FINAL_P is true, it is
2070 done at the end of LRA and the check is more rigorous. */
2071static void
2072check_rtl (bool final_p)
2073{
2074 basic_block bb;
2075 rtx_insn *insn;
2076
2077 lra_assert (! final_p || reload_completed)((void)(!(! final_p || reload_completed) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 2077, __FUNCTION__), 0 : 0))
;
2078 FOR_EACH_BB_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_entry_block_ptr->next_bb
; bb != ((cfun + 0))->cfg->x_exit_block_ptr; bb = bb->
next_bb)
2079 FOR_BB_INSNS (bb, insn)for ((insn) = (bb)->il.x.head_; (insn) && (insn) !=
NEXT_INSN ((bb)->il.x.rtl->end_); (insn) = NEXT_INSN (
insn))
2080 if (NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN))
2081 && GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) != USE
2082 && GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) != CLOBBER
2083 && GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) != ASM_INPUT)
2084 {
2085 if (final_p)
2086 {
2087 extract_constrain_insn (insn);
2088 continue;
2089 }
2090 /* LRA code is based on assumption that all addresses can be
2091 correctly decomposed. LRA can generate reloads for
2092 decomposable addresses. The decomposition code checks the
2093 correctness of the addresses. So we don't need to check
2094 the addresses here. Don't call insn_invalid_p here, it can
2095 change the code at this stage. */
2096 if (recog_memoized (insn) < 0 && asm_noperands (PATTERN (insn)) < 0)
2097 fatal_insn_not_found (insn)_fatal_insn_not_found (insn, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra.c"
, 2097, __FUNCTION__)
;
2098 }
2099}
2100
2101/* Determine if the current function has an exception receiver block
2102 that reaches the exit block via non-exceptional edges */
2103static bool
2104has_nonexceptional_receiver (void)
2105{
2106 edge e;
2107 edge_iterator ei;
2108 basic_block *tos, *worklist, bb;
2109
2110 /* If we're not optimizing, then just err on the safe side. */
2111 if (!optimizeglobal_options.x_optimize)
2112 return true;
2113
2114 /* First determine which blocks can reach exit via normal paths. */
2115 tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1)((basic_block *) xmalloc (sizeof (basic_block) * ((((cfun + 0
))->cfg->x_n_basic_blocks) + 1)))
;
2116
2117 FOR_EACH_BB_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_entry_block_ptr->next_bb
; bb != ((cfun + 0))->cfg->x_exit_block_ptr; bb = bb->
next_bb)
2118 bb->flags &= ~BB_REACHABLE;
2119
2120 /* Place the exit block on our worklist. */
2121 EXIT_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_exit_block_ptr)->flags |= BB_REACHABLE;
2122 *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_exit_block_ptr);
2123
2124 /* Iterate: find everything reachable from what we've already seen. */
2125 while (tos != worklist)
2126 {
2127 bb = *--tos;
2128
2129 FOR_EACH_EDGE (e, ei, bb->preds)for ((ei) = ei_start_1 (&((bb->preds))); ei_cond ((ei)
, &(e)); ei_next (&(ei)))
2130 if (e->flags & EDGE_ABNORMAL)
2131 {
2132 free (worklist);
2133 return true;
2134 }
2135 else
2136 {
2137 basic_block src = e->src;
2138
2139 if (!(src->flags & BB_REACHABLE))
2140 {
2141 src->flags |= BB_REACHABLE;
2142 *tos++ = src;
2143 }
2144 }
2145 }
2146 free (worklist);
2147 /* No exceptional block reached exit unexceptionally. */
2148 return false;
2149}
2150
2151/* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2152 We change pseudos by hard registers without notification of DF and
2153 that can make the notes obsolete. DF-infrastructure does not deal
2154 with REG_INC notes -- so we should regenerate them here. */
2155static void
2156update_inc_notes (void)
2157{
2158 rtx *pnote;
2159 basic_block bb;
2160 rtx_insn *insn;
2161
2162 FOR_EACH_BB_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_entry_block_ptr->next_bb
; bb != ((cfun + 0))->cfg->x_exit_block_ptr; bb = bb->
next_bb)
2163 FOR_BB_INSNS (bb, insn)for ((insn) = (bb)->il.x.head_; (insn) && (insn) !=
NEXT_INSN ((bb)->il.x.rtl->end_); (insn) = NEXT_INSN (
insn))
2164 if (NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN))
)
2165 {
2166 pnote = &REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx);
2167 while (*pnote != 0)
2168 {
2169 if (REG_NOTE_KIND (*pnote)((enum reg_note) ((machine_mode) (*pnote)->mode)) == REG_DEAD
2170 || REG_NOTE_KIND (*pnote)((enum reg_note) ((machine_mode) (*pnote)->mode)) == REG_UNUSED
2171 || REG_NOTE_KIND (*pnote)((enum reg_note) ((machine_mode) (*pnote)->mode)) == REG_INC)
2172 *pnote = XEXP (*pnote, 1)(((*pnote)->u.fld[1]).rt_rtx);
2173 else
2174 pnote = &XEXP (*pnote, 1)(((*pnote)->u.fld[1]).rt_rtx);
2175 }
2176
2177 if (AUTO_INC_DEC0)
2178 add_auto_inc_notes (insn, PATTERN (insn));
2179 }
2180}
2181
2182/* Set to 1 while in lra. */
2183int lra_in_progress;
2184
2185/* Start of pseudo regnos before the LRA. */
2186int lra_new_regno_start;
2187
2188/* Start of reload pseudo regnos before the new spill pass. */
2189int lra_constraint_new_regno_start;
2190
2191/* Avoid spilling pseudos with regno more than the following value if
2192 it is possible. */
2193int lra_bad_spill_regno_start;
2194
2195/* A pseudo of Pmode. */
2196rtx lra_pmode_pseudo;
2197
2198/* Inheritance pseudo regnos before the new spill pass. */
2199bitmap_head lra_inheritance_pseudos;
2200
2201/* Split regnos before the new spill pass. */
2202bitmap_head lra_split_regs;
2203
2204/* Reload pseudo regnos before the new assignment pass which still can
2205 be spilled after the assignment pass as memory is also accepted in
2206 insns for the reload pseudos. */
2207bitmap_head lra_optional_reload_pseudos;
2208
2209/* Pseudo regnos used for subreg reloads before the new assignment
2210 pass. Such pseudos still can be spilled after the assignment
2211 pass. */
2212bitmap_head lra_subreg_reload_pseudos;
2213
2214/* File used for output of LRA debug information. */
2215FILE *lra_dump_file;
2216
2217/* True if we split hard reg after the last constraint sub-pass. */
2218bool lra_hard_reg_split_p;
2219
2220/* True if we found an asm error. */
2221bool lra_asm_error_p;
2222
2223/* True if we should try spill into registers of different classes
2224 instead of memory. */
2225bool lra_reg_spill_p;
2226
2227/* Set up value LRA_REG_SPILL_P. */
2228static void
2229setup_reg_spill_flag (void)
2230{
2231 int cl, mode;
2232
2233 if (targetm.spill_class != NULLnullptr)
2234 for (cl = 0; cl < (int) LIM_REG_CLASSES; cl++)
2235 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
2236 if (targetm.spill_class ((enum reg_class) cl,
2237 (machine_mode) mode) != NO_REGS)
2238 {
2239 lra_reg_spill_p = true;
2240 return;
2241 }
2242 lra_reg_spill_p = false;
2243}
2244
2245/* True if the current function is too big to use regular algorithms
2246 in LRA. In other words, we should use simpler and faster algorithms
2247 in LRA. It also means we should not worry about generation code
2248 for caller saves. The value is set up in IRA. */
2249bool lra_simple_p;
2250
2251/* Major LRA entry function. F is a file should be used to dump LRA
2252 debug info. */
2253void
2254lra (FILE *f)
2255{
2256 int i;
2257 bool live_p, inserted_p;
2258
2259 lra_dump_file = f;
2260 lra_asm_error_p = false;
2261 lra_pmode_pseudo = gen_reg_rtx (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
);
2262
2263 timevar_push (TV_LRA);
2264
2265 /* Make sure that the last insn is a note. Some subsequent passes
2266 need it. */
2267 emit_note (NOTE_INSN_DELETED);
2268
2269 lra_no_alloc_regs = ira_no_alloc_regs(this_target_ira->x_ira_no_alloc_regs);
2270
2271 init_reg_info ();
2272 expand_reg_info ();
2273
2274 init_insn_recog_data ();
2275
2276 /* Some quick check on RTL generated by previous passes. */
2277 if (flag_checkingglobal_options.x_flag_checking)
2278 check_rtl (false);
2279
2280 lra_in_progress = 1;
2281
2282 lra_live_range_iter = lra_coalesce_iter = lra_constraint_iter = 0;
2283 lra_assignment_iter = lra_assignment_iter_after_spill = 0;
2284 lra_inheritance_iter = lra_undo_inheritance_iter = 0;
2285 lra_rematerialization_iter = 0;
2286
2287 setup_reg_spill_flag ();
2288
2289 /* Function remove_scratches can creates new pseudos for clobbers --
2290 so set up lra_constraint_new_regno_start before its call to
2291 permit changing reg classes for pseudos created by this
2292 simplification. */
2293 lra_constraint_new_regno_start = lra_new_regno_start = max_reg_num ();
2294 lra_bad_spill_regno_start = INT_MAX2147483647;
2295 remove_scratches ();
2296
2297 /* A function that has a non-local label that can reach the exit
2298 block via non-exceptional paths must save all call-saved
2299 registers. */
2300 if (cfun(cfun + 0)->has_nonlocal_label && has_nonexceptional_receiver ())
2301 crtl(&x_rtl)->saves_all_registers = 1;
2302
2303 if (crtl(&x_rtl)->saves_all_registers)
2304 for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
2305 if (!crtl(&x_rtl)->abi->clobbers_full_reg_p (i)
2306 && !fixed_regs(this_target_hard_regs->x_fixed_regs)[i]
2307 && !LOCAL_REGNO (i)0)
2308 df_set_regs_ever_live (i, true);
2309
2310 /* We don't DF from now and avoid its using because it is to
2311 expensive when a lot of RTL changes are made. */
2312 df_set_flags (DF_NO_INSN_RESCAN);
2313 lra_constraint_insn_stack.create (get_max_uid ());
2314 lra_constraint_insn_stack_bitmap = sbitmap_alloc (get_max_uid ());
2315 bitmap_clear (lra_constraint_insn_stack_bitmap);
2316 lra_live_ranges_init ();
2317 lra_constraints_init ();
2318 lra_curr_reload_num = 0;
2319 push_insns (get_last_insn (), NULLnullptr);
2320 /* It is needed for the 1st coalescing. */
2321 bitmap_initialize (&lra_inheritance_pseudos, &reg_obstack);
2322 bitmap_initialize (&lra_split_regs, &reg_obstack);
2323 bitmap_initialize (&lra_optional_reload_pseudos, &reg_obstack);
2324 bitmap_initialize (&lra_subreg_reload_pseudos, &reg_obstack);
2325 live_p = false;
2326 if (maybe_ne (get_frame_size (), 0) && crtl(&x_rtl)->stack_alignment_needed)
2327 /* If we have a stack frame, we must align it now. The stack size
2328 may be a part of the offset computation for register
2329 elimination. */
2330 assign_stack_local (BLKmode((void) 0, E_BLKmode), 0, crtl(&x_rtl)->stack_alignment_needed);
2331 lra_init_equiv ();
2332 for (;;)
2333 {
2334 for (;;)
2335 {
2336 bool reloads_p = lra_constraints (lra_constraint_iter == 0);
2337 /* Constraint transformations may result in that eliminable
2338 hard regs become uneliminable and pseudos which use them
2339 should be spilled. It is better to do it before pseudo
2340 assignments.
2341
2342 For example, rs6000 can make
2343 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2344 to use a constant pool. */
2345 lra_eliminate (false, false);
2346 /* We should try to assign hard registers to scratches even
2347 if there were no RTL transformations in lra_constraints.
2348 Also we should check IRA assignments on the first
2349 iteration as they can be wrong because of early clobbers
2350 operands which are ignored in IRA. */
2351 if (! reloads_p && lra_constraint_iter > 1)
2352 {
2353 /* Stack is not empty here only when there are changes
2354 during the elimination sub-pass. */
2355 if (bitmap_empty_p (lra_constraint_insn_stack_bitmap))
2356 break;
2357 else
2358 /* If there are no reloads but changing due
2359 elimination, restart the constraint sub-pass
2360 first. */
2361 continue;
2362 }
2363 /* Do inheritance only for regular algorithms. */
2364 if (! lra_simple_p)
2365 lra_inheritance ();
2366 if (live_p)
2367 lra_clear_live_ranges ();
2368 bool fails_p;
2369 lra_hard_reg_split_p = false;
2370 do
2371 {
2372 /* We need live ranges for lra_assign -- so build them.
2373 But don't remove dead insns or change global live
2374 info as we can undo inheritance transformations after
2375 inheritance pseudo assigning. */
2376 lra_create_live_ranges (true, !lra_simple_p);
2377 live_p = true;
2378 /* If we don't spill non-reload and non-inheritance
2379 pseudos, there is no sense to run memory-memory move
2380 coalescing. If inheritance pseudos were spilled, the
2381 memory-memory moves involving them will be removed by
2382 pass undoing inheritance. */
2383 if (lra_simple_p)
2384 lra_assign (fails_p);
2385 else
2386 {
2387 bool spill_p = !lra_assign (fails_p);
2388
2389 if (lra_undo_inheritance ())
2390 live_p = false;
2391 if (spill_p && ! fails_p)
2392 {
2393 if (! live_p)
2394 {
2395 lra_create_live_ranges (true, true);
2396 live_p = true;
2397 }
2398 if (lra_coalesce ())
2399 live_p = false;
2400 }
2401 if (! live_p)
2402 lra_clear_live_ranges ();
2403 }
2404 if (fails_p)
2405 {
2406 /* It is a very rare case. It is the last hope to
2407 split a hard regno live range for a reload
2408 pseudo. */
2409 if (live_p)
2410 lra_clear_live_ranges ();
2411 live_p = false;
2412 if (! lra_split_hard_reg_for ())
2413 break;
2414 lra_hard_reg_split_p = true;
2415 }
2416 }
2417 while (fails_p);
2418 if (! live_p) {
2419 /* We need the correct reg notes for work of constraint sub-pass. */
2420 lra_create_live_ranges (true, true);
2421 live_p = true;
2422 }
2423 }
2424 /* Don't clear optional reloads bitmap until all constraints are
2425 satisfied as we need to differ them from regular reloads. */
2426 bitmap_clear (&lra_optional_reload_pseudos);
2427 bitmap_clear (&lra_subreg_reload_pseudos);
2428 bitmap_clear (&lra_inheritance_pseudos);
2429 bitmap_clear (&lra_split_regs);
2430 if (! live_p)
2431 {
2432 /* We need full live info for spilling pseudos into
2433 registers instead of memory. */
2434 lra_create_live_ranges (lra_reg_spill_p, true);
2435 live_p = true;
2436 }
2437 /* We should check necessity for spilling here as the above live
2438 range pass can remove spilled pseudos. */
2439 if (! lra_need_for_spills_p ())
2440 break;
2441 /* Now we know what pseudos should be spilled. Try to
2442 rematerialize them first. */
2443 if (lra_remat ())
2444 {
2445 /* We need full live info -- see the comment above. */
2446 lra_create_live_ranges (lra_reg_spill_p, true);
2447 live_p = true;
2448 if (! lra_need_for_spills_p ())
2449 {
2450 if (lra_need_for_scratch_reg_p ())
2451 continue;
2452 break;
2453 }
2454 }
2455 lra_spill ();
2456 /* Assignment of stack slots changes elimination offsets for
2457 some eliminations. So update the offsets here. */
2458 lra_eliminate (false, false);
2459 lra_constraint_new_regno_start = max_reg_num ();
2460 if (lra_bad_spill_regno_start == INT_MAX2147483647
2461 && lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES2
2462 && lra_rematerialization_iter > LRA_MAX_REMATERIALIZATION_PASSES2)
2463 /* After switching off inheritance and rematerialization
2464 passes, avoid spilling reload pseudos will be created to
2465 prevent LRA cycling in some complicated cases. */
2466 lra_bad_spill_regno_start = lra_constraint_new_regno_start;
2467 lra_assignment_iter_after_spill = 0;
2468 }
2469 ira_restore_scratches (lra_dump_file);
2470 lra_eliminate (true, false);
2471 lra_final_code_change ();
2472 lra_in_progress = 0;
2473 if (live_p)
2474 lra_clear_live_ranges ();
2475 lra_live_ranges_finish ();
2476 lra_constraints_finish ();
2477 finish_reg_info ();
2478 sbitmap_free (lra_constraint_insn_stack_bitmap);
2479 lra_constraint_insn_stack.release ();
2480 finish_insn_recog_data ();
2481 regstat_free_n_sets_and_refs ();
2482 regstat_free_ri ();
2483 reload_completed = 1;
2484 update_inc_notes ();
2485
2486 inserted_p = fixup_abnormal_edges ();
2487
2488 /* We've possibly turned single trapping insn into multiple ones. */
2489 if (cfun(cfun + 0)->can_throw_non_call_exceptions)
2490 {
2491 auto_sbitmap blocks (last_basic_block_for_fn (cfun)(((cfun + 0))->cfg->x_last_basic_block));
2492 bitmap_ones (blocks);
2493 find_many_sub_basic_blocks (blocks);
2494 }
2495
2496 if (inserted_p)
2497 commit_edge_insertions ();
2498
2499 /* Replacing pseudos with their memory equivalents might have
2500 created shared rtx. Subsequent passes would get confused
2501 by this, so unshare everything here. */
2502 unshare_all_rtl_again (get_insns ());
2503
2504 if (flag_checkingglobal_options.x_flag_checking)
2505 check_rtl (true);
2506
2507 timevar_pop (TV_LRA);
2508}
2509
2510/* Called once per compiler to initialize LRA data once. */
2511void
2512lra_init_once (void)
2513{
2514 init_insn_code_data_once ();
2515}
2516
2517/* Called once per compiler to finish LRA data which are initialize
2518 once. */
2519void
2520lra_finish_once (void)
2521{
2522 finish_insn_code_data_once ();
2523}