/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc

Bug Summary

File:	build/gcc/combine.cc
Warning:	line 4505, column 9 Branch condition evaluates to a garbage value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-suse-linux -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name combine.cc -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -resource-dir /usr/lib64/clang/15.0.7 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/backward -internal-isystem /usr/lib64/clang/15.0.7/include -internal-isystem /usr/local/include -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../x86_64-suse-linux/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2023-03-27-141847-20772-1/report-PNXTni.plist -x c++ /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc

1/* Optimize by combining instructions for GNU compiler.
 Copyright (C) 1987-2023 Free Software Foundation, Inc.

4This file is part of GCC.

6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8Software Foundation; either version 3, or (at your option) any later
9version.

11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14for more details.

16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3.  If not see
18<http://www.gnu.org/licenses/>.  */

20/* This module is essentially the "combiner" phase of the U. of Arizona
 Portable Optimizer, but redone to work on our list-structured
 representation for RTL instead of their string representation.

 The LOG_LINKS of each insn identify the most recent assignment
 to each REG used in the insn.  It is a list of previous insns,
 each of which contains a SET for a REG that is used in this insn
 and not used or set in between.  LOG_LINKs never cross basic blocks.
 They were set up by the preceding pass (lifetime analysis).

 We try to combine each pair of insns joined by a logical link.
 We also try to combine triplets of insns A, B and C when C has
 a link back to B and B has a link back to A.  Likewise for a
 small number of quadruplets of insns A, B, C and D for which
 there's high likelihood of success.

 We check (with modified_between_p) to avoid combining in such a way
 as to move a computation to a place where its value would be different.

 Combination is done by mathematically substituting the previous
 insn(s) values for the regs they set into the expressions in
 the later insns that refer to these regs.  If the result is a valid insn
 for our target machine, according to the machine description,
 we install it, delete the earlier insns, and update the data flow
 information (LOG_LINKS and REG_NOTES) for what we did.

 There are a few exceptions where the dataflow information isn't
 completely updated (however this is only a local issue since it is
 regenerated before the next pass that uses it):

 - reg_live_length is not updated
 - reg_n_refs is not adjusted in the rare case when a register is
   no longer required in a computation
 - there are extremely rare cases (see distribute_notes) when a
   REG_DEAD note is lost
 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
   removed because there is no way to know which register it was
   linking

 To simplify substitution, we combine only when the earlier insn(s)
 consist of only a single assignment.  To simplify updating afterward,
 we never combine when a subroutine call appears in the middle.  */

63#include "config.h"
64#include "system.h"
65#include "coretypes.h"
66#include "backend.h"
67#include "target.h"
68#include "rtl.h"
69#include "tree.h"
70#include "cfghooks.h"
71#include "predict.h"
72#include "df.h"
73#include "memmodel.h"
74#include "tm_p.h"
75#include "optabs.h"
76#include "regs.h"
77#include "emit-rtl.h"
78#include "recog.h"
79#include "cgraph.h"
80#include "stor-layout.h"
81#include "cfgrtl.h"
82#include "cfgcleanup.h"
83/* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
84#include "explow.h"
85#include "insn-attr.h"
86#include "rtlhooks-def.h"
87#include "expr.h"
88#include "tree-pass.h"
89#include "valtrack.h"
90#include "rtl-iter.h"
91#include "print-rtl.h"
92#include "function-abi.h"
93#include "rtlanal.h"

95/* Number of attempts to combine instructions in this function.  */

97static int combine_attempts;

99/* Number of attempts that got as far as substitution in this function.  */

101static int combine_merges;

103/* Number of instructions combined with added SETs in this function.  */

105static int combine_extras;

107/* Number of instructions combined in this function.  */

109static int combine_successes;

111/* Totals over entire compilation.  */

113static int total_attempts, total_merges, total_extras, total_successes;

115/* combine_instructions may try to replace the right hand side of the
 second instruction with the value of an associated REG_EQUAL note
 before throwing it at try_combine.  That is problematic when there
 is a REG_DEAD note for a register used in the old right hand side
 and can cause distribute_notes to do wrong things.  This is the
 second instruction if it has been so modified, null otherwise.  */

122static rtx_insn *i2mod;

124/* When I2MOD is nonnull, this is a copy of the old right hand side.  */

126static rtx i2mod_old_rhs;

128/* When I2MOD is nonnull, this is a copy of the new right hand side.  */

130static rtx i2mod_new_rhs;
131
132struct reg_stat_type {
/* Record last point of death of (hard or pseudo) register n.  */
rtx_insn			*last_death;

/* Record last point of modification of (hard or pseudo) register n.  */
rtx_insn			*last_set;

/* The next group of fields allows the recording of the last value assigned
   to (hard or pseudo) register n.  We use this information to see if an
   operation being processed is redundant given a prior operation performed
   on the register.  For example, an `and' with a constant is redundant if
   all the zero bits are already known to be turned off.

   We use an approach similar to that used by cse, but change it in the
   following ways:

   (1) We do not want to reinitialize at each label.
   (2) It is useful, but not critical, to know the actual value assigned
to a register.  Often just its form is helpful.

   Therefore, we maintain the following fields:

   last_set_value		the last value assigned
   last_set_label		records the value of label_tick when the
		register was assigned
   last_set_table_tick	records the value of label_tick when a
		value using the register is assigned
   last_set_invalid		set to nonzero when it is not valid
		to use the value of this register in some
		register's value

   To understand the usage of these tables, it is important to understand
   the distinction between the value in last_set_value being valid and
   the register being validly contained in some other expression in the
   table.

   (The next two parameters are out of date).

   reg_stat[i].last_set_value is valid if it is nonzero, and either
   reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.

   Register I may validly appear in any expression returned for the value
   of another register if reg_n_sets[i] is 1.  It may also appear in the
   value for register J if reg_stat[j].last_set_invalid is zero, or
   reg_stat[i].last_set_label < reg_stat[j].last_set_label.

   If an expression is found in the table containing a register which may
   not validly appear in an expression, the register is replaced by
   something that won't match, (clobber (const_int 0)).  */

/* Record last value assigned to (hard or pseudo) register n.  */

rtx				last_set_value;

/* Record the value of label_tick when an expression involving register n
   is placed in last_set_value.  */

int				last_set_table_tick;

/* Record the value of label_tick when the value for register n is placed in
   last_set_value.  */

int				last_set_label;

/* These fields are maintained in parallel with last_set_value and are
   used to store the mode in which the register was last set, the bits
   that were known to be zero when it was last set, and the number of
   sign bits copies it was known to have when it was last set.  */

unsigned HOST_WIDE_INTlong	last_set_nonzero_bits;
char				last_set_sign_bit_copies;
ENUM_BITFIELD(machine_mode)enum machine_mode	last_set_mode : 8;

/* Set nonzero if references to register n in expressions should not be
   used.  last_set_invalid is set nonzero when this register is being
   assigned to and last_set_table_tick == label_tick.  */

char				last_set_invalid;

/* Some registers that are set more than once and used in more than one
   basic block are nevertheless always set in similar ways.  For example,
   a QImode register may be loaded from memory in two places on a machine
   where byte loads zero extend.

   We record in the following fields if a register has some leading bits
   that are always equal to the sign bit, and what we know about the
   nonzero bits of a register, specifically which bits are known to be
   zero.

   If an entry is zero, it means that we don't know anything special.  */

unsigned char			sign_bit_copies;

unsigned HOST_WIDE_INTlong	nonzero_bits;

/* Record the value of the label_tick when the last truncation
   happened.  The field truncated_to_mode is only valid if
   truncation_label == label_tick.  */

int				truncation_label;

/* Record the last truncation seen for this register.  If truncation
   is not a nop to this mode we might be able to save an explicit
   truncation if we know that value already contains a truncated
   value.  */

ENUM_BITFIELD(machine_mode)enum machine_mode	truncated_to_mode : 8;
239};


242static vec<reg_stat_type> reg_stat;

244/* One plus the highest pseudo for which we track REG_N_SETS.
 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
 but during combine_split_insns new pseudos can be created.  As we don't have
 updated DF information in that case, it is hard to initialize the array
 after growing.  The combiner only cares about REG_N_SETS (regno) == 1,
 so instead of growing the arrays, just assume all newly created pseudos
 during combine might be set multiple times.  */

252static unsigned int reg_n_sets_max;

254/* Record the luid of the last insn that invalidated memory
 (anything that writes memory, and subroutine calls, but not pushes).  */

257static int mem_last_set;

259/* Record the luid of the last CALL_INSN
 so we can tell whether a potential combination crosses any calls.  */

262static int last_call_luid;

264/* When `subst' is called, this is the insn that is being modified
 (by combining in a previous insn).  The PATTERN of this insn
 is still the old pattern partially modified and it should not be
 looked at, but this may be used to examine the successors of the insn
 to judge whether a simplification is valid.  */

270static rtx_insn *subst_insn;

272/* This is the lowest LUID that `subst' is currently dealing with.
 get_last_value will not return a value if the register was set at or
 after this LUID.  If not for this mechanism, we could get confused if
 I2 or I1 in try_combine were an insn that used the old value of a register
 to obtain a new value.  In that case, we might erroneously get the
 new value of the register when we wanted the old one.  */

279static int subst_low_luid;

281/* This contains any hard registers that are used in newpat; reg_dead_at_p
 must consider all these registers to be always live.  */

284static HARD_REG_SET newpat_used_regs;

286/* This is an insn to which a LOG_LINKS entry has been added.  If this
 insn is the earlier than I2 or I3, combine should rescan starting at
 that location.  */

290static rtx_insn *added_links_insn;

292/* And similarly, for notes.  */

294static rtx_insn *added_notes_insn;

296/* Basic block in which we are performing combines.  */
297static basic_block this_basic_block;
298static bool optimize_this_for_speed_p;

300
301/* Length of the currently allocated uid_insn_cost array.  */

303static int max_uid_known;

305/* The following array records the insn_cost for every insn
 in the instruction stream.  */

308static int *uid_insn_cost;

310/* The following array records the LOG_LINKS for every insn in the
 instruction stream as struct insn_link pointers.  */

313struct insn_link {
rtx_insn *insn;
unsigned int regno;
struct insn_link *next;
317};

319static struct insn_link **uid_log_links;

321static inline int
322insn_uid_check (const_rtx insn)
323{
int uid = INSN_UID (insn);
gcc_checking_assert (uid <= max_uid_known)((void)(!(uid <= max_uid_known) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 325, __FUNCTION__), 0 : 0));
return uid;
327}

329#define INSN_COST(INSN)(uid_insn_cost[insn_uid_check (INSN)])		(uid_insn_cost[insn_uid_check (INSN)])
330#define LOG_LINKS(INSN)(uid_log_links[insn_uid_check (INSN)])		(uid_log_links[insn_uid_check (INSN)])

332#define FOR_EACH_LOG_LINK(L, INSN)for ((L) = (uid_log_links[insn_uid_check (INSN)]); (L); (L) =
 (L)->next)				\
for ((L) = LOG_LINKS (INSN)(uid_log_links[insn_uid_check (INSN)]); (L); (L) = (L)->next)

335/* Links for LOG_LINKS are allocated from this obstack.  */

337static struct obstack insn_link_obstack;

339/* Allocate a link.  */

341static inline struct insn_link *
342alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next)
343{
struct insn_link *l
  = (struct insn_link *) obstack_alloc (&insn_link_obstack,__extension__ ({ struct obstack *__h = (&insn_link_obstack
); __extension__ ({ struct obstack *__o = (__h); size_t __len
 = ((sizeof (struct insn_link))); if (__extension__ ({ struct
 obstack const *__o1 = (__o); (size_t) (__o1->chunk_limit -
 __o1->next_free); }) < __len) _obstack_newchunk (__o, __len
); ((void) ((__o)->next_free += (__len))); }); __extension__
 ({ struct obstack *__o1 = (__h); void *__value = (void *) __o1
->object_base; if (__o1->next_free == __value) __o1->
maybe_empty_object = 1; __o1->next_free = (sizeof (ptrdiff_t
) < sizeof (void *) ? ((__o1->object_base) + (((__o1->
next_free) - (__o1->object_base) + (__o1->alignment_mask
)) & ~(__o1->alignment_mask))) : (char *) (((ptrdiff_t
) (__o1->next_free) + (__o1->alignment_mask)) & ~(__o1
->alignment_mask))); if ((size_t) (__o1->next_free - (char
 *) __o1->chunk) > (size_t) (__o1->chunk_limit - (char
 *) __o1->chunk)) __o1->next_free = __o1->chunk_limit
; __o1->object_base = __o1->next_free; __value; }); })
			  sizeof (struct insn_link))__extension__ ({ struct obstack *__h = (&insn_link_obstack
); __extension__ ({ struct obstack *__o = (__h); size_t __len
 = ((sizeof (struct insn_link))); if (__extension__ ({ struct
 obstack const *__o1 = (__o); (size_t) (__o1->chunk_limit -
 __o1->next_free); }) < __len) _obstack_newchunk (__o, __len
); ((void) ((__o)->next_free += (__len))); }); __extension__
 ({ struct obstack *__o1 = (__h); void *__value = (void *) __o1
->object_base; if (__o1->next_free == __value) __o1->
maybe_empty_object = 1; __o1->next_free = (sizeof (ptrdiff_t
) < sizeof (void *) ? ((__o1->object_base) + (((__o1->
next_free) - (__o1->object_base) + (__o1->alignment_mask
)) & ~(__o1->alignment_mask))) : (char *) (((ptrdiff_t
) (__o1->next_free) + (__o1->alignment_mask)) & ~(__o1
->alignment_mask))); if ((size_t) (__o1->next_free - (char
 *) __o1->chunk) > (size_t) (__o1->chunk_limit - (char
 *) __o1->chunk)) __o1->next_free = __o1->chunk_limit
; __o1->object_base = __o1->next_free; __value; }); });
l->insn = insn;
l->regno = regno;
l->next = next;
return l;
351}

353/* Incremented for each basic block.  */

355static int label_tick;

357/* Reset to label_tick for each extended basic block in scanning order.  */

359static int label_tick_ebb_start;

361/* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */

364static scalar_int_mode nonzero_bits_mode;

366/* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 be safely used.  It is zero while computing them and after combine has
 completed.  This former test prevents propagating values based on
 previously set values, which can be incorrect if a variable is modified
 in a loop.  */

372static int nonzero_sign_valid;

374
375/* Record one modification to rtl structure
 to be undone by storing old_contents into *where.  */

378enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };

380struct undo
381{
struct undo *next;
enum undo_kind kind;
union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
union { rtx *r; int *i; int regno; struct insn_link **l; } where;
386};

388/* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 num_undo says how many are currently recorded.

 other_insn is nonzero if we have modified some other insn in the process
 of working on subst_insn.  It must be verified too.  */

394struct undobuf
395{
struct undo *undos;
struct undo *frees;
rtx_insn *other_insn;
399};

401static struct undobuf undobuf;

403/* Number of times the pseudo being substituted for
 was found and replaced.  */

406static int n_occurrences;

408static rtx reg_nonzero_bits_for_combine (const_rtx, scalar_int_mode,
			 scalar_int_mode,
			 unsigned HOST_WIDE_INTlong *);
411static rtx reg_num_sign_bit_copies_for_combine (const_rtx, scalar_int_mode,
				scalar_int_mode,
				unsigned int *);
414static void do_SUBST (rtx *, rtx);
415static void do_SUBST_INT (int *, int);
416static void init_reg_last (void);
417static void setup_incoming_promotions (rtx_insn *);
418static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
419static int cant_combine_insn_p (rtx_insn *);
420static int can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
	  rtx_insn *, rtx_insn *, rtx *, rtx *);
422static int combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx, int, int, rtx *);
423static int contains_muldiv (rtx);
424static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
	      int *, rtx_insn *);
426static void undo_all (void);
427static void undo_commit (void);
428static rtx *find_split_point (rtx *, rtx_insn *, bool);
429static rtx subst (rtx, rtx, rtx, int, int, int);
430static rtx combine_simplify_rtx (rtx, machine_mode, int, int);
431static rtx simplify_if_then_else (rtx);
432static rtx simplify_set (rtx);
433static rtx simplify_logical (rtx);
434static rtx expand_compound_operation (rtx);
435static const_rtx expand_field_assignment (const_rtx);
436static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INTlong,
	    rtx, unsigned HOST_WIDE_INTlong, int, int, int);
438static int get_pos_from_mask (unsigned HOST_WIDE_INTlong,
	      unsigned HOST_WIDE_INTlong *);
440static rtx canon_reg_for_combine (rtx, rtx);
441static rtx force_int_to_mode (rtx, scalar_int_mode, scalar_int_mode,
	      scalar_int_mode, unsigned HOST_WIDE_INTlong, int);
443static rtx force_to_mode (rtx, machine_mode,
	  unsigned HOST_WIDE_INTlong, int);
445static rtx if_then_else_cond (rtx, rtx *, rtx *);
446static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
447static int rtx_equal_for_field_assignment_p (rtx, rtx, bool = false);
448static rtx make_field_assignment (rtx);
449static rtx apply_distributive_law (rtx);
450static rtx distribute_and_simplify_rtx (rtx, int);
451static rtx simplify_and_const_int_1 (scalar_int_mode, rtx,
		     unsigned HOST_WIDE_INTlong);
453static rtx simplify_and_const_int (rtx, scalar_int_mode, rtx,
		   unsigned HOST_WIDE_INTlong);
455static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INTlong *, enum rtx_code,
	    HOST_WIDE_INTlong, machine_mode, int *);
457static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
458static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
		 int);
460static int recog_for_combine (rtx *, rtx_insn *, rtx *);
461static rtx gen_lowpart_for_combine (machine_mode, rtx);
462static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
			     rtx, rtx *);
464static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
465static void update_table_tick (rtx);
466static void record_value_for_reg (rtx, rtx_insn *, rtx);
467static void check_promoted_subreg (rtx_insn *, rtx);
468static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
469static void record_dead_and_set_regs (rtx_insn *);
470static int get_last_value_validate (rtx *, rtx_insn *, int, int);
471static rtx get_last_value (const_rtx);
472static void reg_dead_at_p_1 (rtx, const_rtx, void *);
473static int reg_dead_at_p (rtx, rtx_insn *);
474static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
475static int reg_bitfield_target_p (rtx, rtx);
476static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *, rtx, rtx, rtx);
477static void distribute_links (struct insn_link *);
478static void mark_used_regs_combine (rtx);
479static void record_promoted_value (rtx_insn *, rtx);
480static bool unmentioned_reg_p (rtx, rtx);
481static void record_truncated_values (rtx *, void *);
482static bool reg_truncated_to_mode (machine_mode, const_rtx);
483static rtx gen_lowpart_or_truncate (machine_mode, rtx);
484

486/* It is not safe to use ordinary gen_lowpart in combine.
 See comments in gen_lowpart_for_combine.  */
488#undef RTL_HOOKS_GEN_LOWPARTgen_lowpart_for_combine
489#define RTL_HOOKS_GEN_LOWPARTgen_lowpart_for_combine              gen_lowpart_for_combine

491/* Our implementation of gen_lowpart never emits a new pseudo.  */
492#undef RTL_HOOKS_GEN_LOWPART_NO_EMITgen_lowpart_for_combine
493#define RTL_HOOKS_GEN_LOWPART_NO_EMITgen_lowpart_for_combine      gen_lowpart_for_combine

495#undef RTL_HOOKS_REG_NONZERO_REG_BITSreg_nonzero_bits_for_combine
496#define RTL_HOOKS_REG_NONZERO_REG_BITSreg_nonzero_bits_for_combine     reg_nonzero_bits_for_combine

498#undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIESreg_num_sign_bit_copies_for_combine
499#define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIESreg_num_sign_bit_copies_for_combine  reg_num_sign_bit_copies_for_combine

501#undef RTL_HOOKS_REG_TRUNCATED_TO_MODEreg_truncated_to_mode
502#define RTL_HOOKS_REG_TRUNCATED_TO_MODEreg_truncated_to_mode    reg_truncated_to_mode

504static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER{ gen_lowpart_for_combine, gen_lowpart_for_combine, reg_nonzero_bits_for_combine
, reg_num_sign_bit_copies_for_combine, reg_truncated_to_mode };

506
507/* Convenience wrapper for the canonicalize_comparison target hook.
 Target hooks cannot use enum rtx_code.  */
509static inline void
510target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
		bool op0_preserve_value)
512{
int code_int = (int)*code;
targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
*code = (enum rtx_code)code_int;
516}

518/* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 PATTERN cannot be split.  Otherwise, it returns an insn sequence.
 This is a wrapper around split_insns which ensures that the
 reg_stat vector is made larger if the splitter creates a new
 register.  */

524static rtx_insn *
525combine_split_insns (rtx pattern, rtx_insn *insn)
526{
rtx_insn *ret;
unsigned int nregs;

ret = split_insns (pattern, insn);
nregs = max_reg_num ();
if (nregs > reg_stat.length ())
  reg_stat.safe_grow_cleared (nregs, true);
return ret;
535}

537/* This is used by find_single_use to locate an rtx in LOC that
 contains exactly one use of DEST, which is typically a REG.
 It returns a pointer to the innermost rtx expression
 containing DEST.  Appearances of DEST that are being used to
 totally replace it are not counted.  */

543static rtx *
544find_single_use_1 (rtx dest, rtx *loc)
545{
rtx x = *loc;
enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
rtx *result = NULLnullptr;
rtx *this_result;
int i;
const char *fmt;

switch (code)
  {
  case CONST:
  case LABEL_REF:
  case SYMBOL_REF:
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case CLOBBER:
    return 0;

  case SET:
    /* If the destination is anything other than PC, a REG or a SUBREG
of a REG that occupies all of the REG, the insn uses DEST if
it is mentioned in the destination or the source.  Otherwise, we
need just check the source.  */
    if (GET_CODE (SET_DEST (x))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) != PC
 && !REG_P (SET_DEST (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
 && ! (GET_CODE (SET_DEST (x))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == SUBREG
&& REG_P (SUBREG_REG (SET_DEST (x)))(((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[
0]).rt_rtx))->code) == REG)
&& !read_modify_subreg_p (SET_DEST (x)(((x)->u.fld[0]).rt_rtx))))
break;

    return find_single_use_1 (dest, &SET_SRC (x)(((x)->u.fld[1]).rt_rtx));

  case MEM:
  case SUBREG:
    return find_single_use_1 (dest, &XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));

  default:
    break;
  }

/* If it wasn't one of the common cases above, check each expression and
   vector of this code.  Look for a unique usage of DEST.  */

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'e')
{
 if (dest == XEXP (x, i)(((x)->u.fld[i]).rt_rtx)
     || (REG_P (dest)(((enum rtx_code) (dest)->code) == REG) && REG_P (XEXP (x, i))(((enum rtx_code) ((((x)->u.fld[i]).rt_rtx))->code) == REG
)
  && REGNO (dest)(rhs_regno(dest)) == REGNO (XEXP (x, i))(rhs_regno((((x)->u.fld[i]).rt_rtx)))))
   this_result = loc;
 else
   this_result = find_single_use_1 (dest, &XEXP (x, i)(((x)->u.fld[i]).rt_rtx));

 if (result == NULLnullptr)
   result = this_result;
 else if (this_result)
   /* Duplicate usage.  */
   return NULLnullptr;
}
    else if (fmt[i] == 'E')
{
 int j;

 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
   {
     if (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]) == dest
  || (REG_P (dest)(((enum rtx_code) (dest)->code) == REG)
      && REG_P (XVECEXP (x, i, j))(((enum rtx_code) ((((((x)->u.fld[i]).rt_rtvec))->elem[
j]))->code) == REG)
      && REGNO (XVECEXP (x, i, j))(rhs_regno((((((x)->u.fld[i]).rt_rtvec))->elem[j]))) == REGNO (dest)(rhs_regno(dest))))
this_result = loc;
     else
this_result = find_single_use_1 (dest, &XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]));

     if (result == NULLnullptr)
result = this_result;
     else if (this_result)
return NULLnullptr;
   }
}
  }

return result;
628}


631/* See if DEST, produced in INSN, is used only a single time in the
 sequel.  If so, return a pointer to the innermost rtx expression in which
 it is used.

 If PLOC is nonzero, *PLOC is set to the insn containing the single use.

 Otherwise, we find the single use by finding an insn that has a
 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 only referenced once in that insn, we know that it must be the first
 and last insn referencing DEST.  */

642static rtx *
643find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
644{
basic_block bb;
rtx_insn *next;
rtx *result;
struct insn_link *link;

if (!REG_P (dest)(((enum rtx_code) (dest)->code) == REG))
  return 0;

bb = BLOCK_FOR_INSN (insn);
for (next = NEXT_INSN (insn);
     next && BLOCK_FOR_INSN (next) == bb;
     next = NEXT_INSN (next))
  if (NONDEBUG_INSN_P (next)((((enum rtx_code) (next)->code) == INSN) || (((enum rtx_code
) (next)->code) == JUMP_INSN) || (((enum rtx_code) (next)->
code) == CALL_INSN)) && dead_or_set_p (next, dest))
    {
FOR_EACH_LOG_LINK (link, next)for ((link) = (uid_log_links[insn_uid_check (next)]); (link);
 (link) = (link)->next)
 if (link->insn == insn && link->regno == REGNO (dest)(rhs_regno(dest)))
   break;

if (link)
 {
   result = find_single_use_1 (dest, &PATTERN (next));
   if (ploc)
     *ploc = next;
   return result;
 }
    }

return 0;
673}
674
675/* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 insn.  The substitution can be undone by undo_all.  If INTO is already
 set to NEWVAL, do not record this change.  Because computing NEWVAL might
 also call SUBST, we have to compute it before we put anything into
 the undo table.  */

681static void
682do_SUBST (rtx *into, rtx newval)
683{
struct undo *buf;
rtx oldval = *into;

if (oldval == newval)
  return;

/* We'd like to catch as many invalid transformations here as
   possible.  Unfortunately, there are way too many mode changes
   that are perfectly valid, so we'd waste too much effort for
   little gain doing the checks here.  Focus on catching invalid
   transformations involving integer constants.  */
if (GET_MODE_CLASS (GET_MODE (oldval))((enum mode_class) mode_class[((machine_mode) (oldval)->mode
)]) == MODE_INT
    && CONST_INT_P (newval)(((enum rtx_code) (newval)->code) == CONST_INT))
  {
    /* Sanity check that we're replacing oldval with a CONST_INT
that is a valid sign-extension for the original mode.  */
    gcc_assert (INTVAL (newval)((void)(!(((newval)->u.hwint[0]) == trunc_int_for_mode (((
newval)->u.hwint[0]), ((machine_mode) (oldval)->mode)))
 ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 701, __FUNCTION__), 0 : 0))
  == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)))((void)(!(((newval)->u.hwint[0]) == trunc_int_for_mode (((
newval)->u.hwint[0]), ((machine_mode) (oldval)->mode)))
 ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 701, __FUNCTION__), 0 : 0));

    /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
CONST_INT is not valid, because after the replacement, the
original mode would be gone.  Unfortunately, we can't tell
when do_SUBST is called to replace the operand thereof, so we
perform this test on oldval instead, checking whether an
invalid replacement took place before we got here.  */
    gcc_assert (!(GET_CODE (oldval) == SUBREG((void)(!(!(((enum rtx_code) (oldval)->code) == SUBREG &&
 (((enum rtx_code) ((((oldval)->u.fld[0]).rt_rtx))->code
) == CONST_INT))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 710, __FUNCTION__), 0 : 0))
    && CONST_INT_P (SUBREG_REG (oldval))))((void)(!(!(((enum rtx_code) (oldval)->code) == SUBREG &&
 (((enum rtx_code) ((((oldval)->u.fld[0]).rt_rtx))->code
) == CONST_INT))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 710, __FUNCTION__), 0 : 0));
    gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND((void)(!(!(((enum rtx_code) (oldval)->code) == ZERO_EXTEND
 && (((enum rtx_code) ((((oldval)->u.fld[0]).rt_rtx
))->code) == CONST_INT))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 712, __FUNCTION__), 0 : 0))
    && CONST_INT_P (XEXP (oldval, 0))))((void)(!(!(((enum rtx_code) (oldval)->code) == ZERO_EXTEND
 && (((enum rtx_code) ((((oldval)->u.fld[0]).rt_rtx
))->code) == CONST_INT))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 712, __FUNCTION__), 0 : 0));
  }

if (undobuf.frees)
  buf = undobuf.frees, undobuf.frees = buf->next;
else
  buf = XNEW (struct undo)((struct undo *) xmalloc (sizeof (struct undo)));

buf->kind = UNDO_RTX;
buf->where.r = into;
buf->old_contents.r = oldval;
*into = newval;

buf->next = undobuf.undos, undobuf.undos = buf;
726}

728#define SUBST(INTO, NEWVAL)do_SUBST (&(INTO), (NEWVAL))	do_SUBST (&(INTO), (NEWVAL))

730/* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 for the value of a HOST_WIDE_INT value (including CONST_INT) is
 not safe.  */

734static void
735do_SUBST_INT (int *into, int newval)
736{
struct undo *buf;
int oldval = *into;

if (oldval == newval)
  return;

if (undobuf.frees)
  buf = undobuf.frees, undobuf.frees = buf->next;
else
  buf = XNEW (struct undo)((struct undo *) xmalloc (sizeof (struct undo)));

buf->kind = UNDO_INT;
buf->where.i = into;
buf->old_contents.i = oldval;
*into = newval;

buf->next = undobuf.undos, undobuf.undos = buf;
754}

756#define SUBST_INT(INTO, NEWVAL)do_SUBST_INT (&(INTO), (NEWVAL))  do_SUBST_INT (&(INTO), (NEWVAL))

758/* Similar to SUBST, but just substitute the mode.  This is used when
 changing the mode of a pseudo-register, so that any other
 references to the entry in the regno_reg_rtx array will change as
 well.  */

763static void
764subst_mode (int regno, machine_mode newval)
765{
struct undo *buf;
rtx reg = regno_reg_rtx[regno];
machine_mode oldval = GET_MODE (reg)((machine_mode) (reg)->mode);

if (oldval == newval)
  return;

if (undobuf.frees)
  buf = undobuf.frees, undobuf.frees = buf->next;
else
  buf = XNEW (struct undo)((struct undo *) xmalloc (sizeof (struct undo)));

buf->kind = UNDO_MODE;
buf->where.regno = regno;
buf->old_contents.m = oldval;
adjust_reg_mode (reg, newval);

buf->next = undobuf.undos, undobuf.undos = buf;
784}

786/* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */

788static void
789do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
790{
struct undo *buf;
struct insn_link * oldval = *into;

if (oldval == newval)
  return;

if (undobuf.frees)
  buf = undobuf.frees, undobuf.frees = buf->next;
else
  buf = XNEW (struct undo)((struct undo *) xmalloc (sizeof (struct undo)));

buf->kind = UNDO_LINKS;
buf->where.l = into;
buf->old_contents.l = oldval;
*into = newval;

buf->next = undobuf.undos, undobuf.undos = buf;
808}

810#define SUBST_LINK(oldval, newval)do_SUBST_LINK (&oldval, newval) do_SUBST_LINK (&oldval, newval)
811
812/* Subroutine of try_combine.  Determine whether the replacement patterns
 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
 than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 of all the instructions can be estimated and the replacements are more
 expensive than the original sequence.  */

820static bool
821combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
       rtx newpat, rtx newi2pat, rtx newotherpat)
823{
int i0_cost, i1_cost, i2_cost, i3_cost;
int new_i2_cost, new_i3_cost;
int old_cost, new_cost;

/* Lookup the original insn_costs.  */
i2_cost = INSN_COST (i2)(uid_insn_cost[insn_uid_check (i2)]);
i3_cost = INSN_COST (i3)(uid_insn_cost[insn_uid_check (i3)]);

if (i159.1
'i1' is null
)
  {
    i1_cost = INSN_COST (i1)(uid_insn_cost[insn_uid_check (i1)]);
    if (i0)
{
 i0_cost = INSN_COST (i0)(uid_insn_cost[insn_uid_check (i0)]);
 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
      ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
}
    else
{
 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
      ? i1_cost + i2_cost + i3_cost : 0);
 i0_cost = 0;
}
  }
else
  {
    old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
60
←
Assuming 'i2_cost' is <= 0→
    i1_cost = i0_cost = 0;
  }

/* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
   correct that.  */
if (old_cost60.1
'old_cost' is 0
 && i1 && INSN_UID (i1) == INSN_UID (i2))
  old_cost -= i1_cost;


/* Calculate the replacement insn_costs.  */
rtx tmp = PATTERN (i3);
PATTERN (i3) = newpat;
int tmpi = INSN_CODE (i3)(((i3)->u.fld[5]).rt_int);
INSN_CODE (i3)(((i3)->u.fld[5]).rt_int) = -1;
new_i3_cost = insn_cost (i3, optimize_this_for_speed_p);
61
←
Value assigned to 'global_options.x_flag_var_tracking_assignments', which participates in a condition later→
PATTERN (i3) = tmp;
INSN_CODE (i3)(((i3)->u.fld[5]).rt_int) = tmpi;
if (newi2pat61.1
'newi2pat' is null
)
62
←
Taking false branch→
  {
    tmp = PATTERN (i2);
    PATTERN (i2) = newi2pat;
    tmpi = INSN_CODE (i2)(((i2)->u.fld[5]).rt_int);
    INSN_CODE (i2)(((i2)->u.fld[5]).rt_int) = -1;
    new_i2_cost = insn_cost (i2, optimize_this_for_speed_p);
    PATTERN (i2) = tmp;
    INSN_CODE (i2)(((i2)->u.fld[5]).rt_int) = tmpi;
    new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 ? new_i2_cost + new_i3_cost : 0;
  }
else
  {
    new_cost = new_i3_cost;
    new_i2_cost = 0;
  }

if (undobuf.other_insn)
63
←
Assuming field 'other_insn' is null→
  {
    int old_other_cost, new_other_cost;

    old_other_cost = INSN_COST (undobuf.other_insn)(uid_insn_cost[insn_uid_check (undobuf.other_insn)]);
    tmp = PATTERN (undobuf.other_insn);
    PATTERN (undobuf.other_insn) = newotherpat;
    tmpi = INSN_CODE (undobuf.other_insn)(((undobuf.other_insn)->u.fld[5]).rt_int);
    INSN_CODE (undobuf.other_insn)(((undobuf.other_insn)->u.fld[5]).rt_int) = -1;
    new_other_cost = insn_cost (undobuf.other_insn,
		  optimize_this_for_speed_p);
    PATTERN (undobuf.other_insn) = tmp;
    INSN_CODE (undobuf.other_insn)(((undobuf.other_insn)->u.fld[5]).rt_int) = tmpi;
    if (old_other_cost > 0 && new_other_cost > 0)
{
 old_cost += old_other_cost;
 new_cost += new_other_cost;
}
    else
old_cost = 0;
  }

/* Disallow this combination if both new_cost and old_cost are greater than
   zero, and new_cost is greater than old cost.  */
int reject = old_cost63.1
'old_cost' is <= 0
 > 0 && new_cost > old_cost;

if (dump_file)
64
←
Assuming 'dump_file' is null→
65
←
Taking false branch→
  {
    fprintf (dump_file, "%s combination of insns ",
      reject ? "rejecting" : "allowing");
    if (i0)
fprintf (dump_file, "%d, ", INSN_UID (i0));
    if (i1 && INSN_UID (i1) != INSN_UID (i2))
fprintf (dump_file, "%d, ", INSN_UID (i1));
    fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3));

    fprintf (dump_file, "original costs ");
    if (i0)
fprintf (dump_file, "%d + ", i0_cost);
    if (i1 && INSN_UID (i1) != INSN_UID (i2))
fprintf (dump_file, "%d + ", i1_cost);
    fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost);

    if (newi2pat)
fprintf (dump_file, "replacement costs %d + %d = %d\n",
 new_i2_cost, new_i3_cost, new_cost);
    else
fprintf (dump_file, "replacement cost %d\n", new_cost);
  }

if (reject65.1
'reject' is 0
)
66
←
Taking false branch→
  return false;

/* Update the uid_insn_cost array with the replacement costs.  */
INSN_COST (i2)(uid_insn_cost[insn_uid_check (i2)]) = new_i2_cost;
INSN_COST (i3)(uid_insn_cost[insn_uid_check (i3)]) = new_i3_cost;
if (i166.1
'i1' is null
)
67
←
Taking false branch→
  {
    INSN_COST (i1)(uid_insn_cost[insn_uid_check (i1)]) = 0;
    if (i0)
INSN_COST (i0)(uid_insn_cost[insn_uid_check (i0)]) = 0;
  }

return true;
950}


953/* Delete any insns that copy a register to itself.
 Return true if the CFG was changed.  */

956static bool
957delete_noop_moves (void)
958{
rtx_insn *insn, *next;
basic_block bb;

bool edges_deleted = false;

FOR_EACH_BB_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_entry_block_ptr->next_bb
; bb != ((cfun + 0))->cfg->x_exit_block_ptr; bb = bb->
next_bb)
  {
    for (insn = BB_HEAD (bb)(bb)->il.x.head_; insn != NEXT_INSN (BB_END (bb)(bb)->il.x.rtl->end_); insn = next)
{
 next = NEXT_INSN (insn);
 if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)) && noop_move_p (insn))
   {
     if (dump_file)
fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));

     edges_deleted |= delete_insn_and_edges (insn);
   }
}
  }

return edges_deleted;
980}

982
983/* Return false if we do not want to (or cannot) combine DEF.  */
984static bool
985can_combine_def_p (df_ref def)
986{
/* Do not consider if it is pre/post modification in MEM.  */
if (DF_REF_FLAGS (def)((def)->base.flags) & DF_REF_PRE_POST_MODIFY)
  return false;

unsigned int regno = DF_REF_REGNO (def)((def)->base.regno);

/* Do not combine frame pointer adjustments.  */
if ((regno == FRAME_POINTER_REGNUM19
     && (!reload_completed || frame_pointer_needed((&x_rtl)->frame_pointer_needed)))
    || (!HARD_FRAME_POINTER_IS_FRAME_POINTER(6 == 19)
 && regno == HARD_FRAME_POINTER_REGNUM6
 && (!reload_completed || frame_pointer_needed((&x_rtl)->frame_pointer_needed)))
    || (FRAME_POINTER_REGNUM19 != ARG_POINTER_REGNUM16
 && regno == ARG_POINTER_REGNUM16 && fixed_regs(this_target_hard_regs->x_fixed_regs)[regno]))
  return false;

return true;
1004}

1006/* Return false if we do not want to (or cannot) combine USE.  */
1007static bool
1008can_combine_use_p (df_ref use)
1009{
/* Do not consider the usage of the stack pointer by function call.  */
if (DF_REF_FLAGS (use)((use)->base.flags) & DF_REF_CALL_STACK_USAGE)
  return false;

return true;
1015}

1017/* Fill in log links field for all insns.  */

1019static void
1020create_log_links (void)
1021{
basic_block bb;
rtx_insn **next_use;
rtx_insn *insn;
df_ref def, use;

next_use = XCNEWVEC (rtx_insn *, max_reg_num ())((rtx_insn * *) xcalloc ((max_reg_num ()), sizeof (rtx_insn *
)));

/* Pass through each block from the end, recording the uses of each
   register and establishing log links when def is encountered.
   Note that we do not clear next_use array in order to save time,
   so we have to test whether the use is in the same basic block as def.

   There are a few cases below when we do not consider the definition or
   usage -- these are taken from original flow.c did. Don't ask me why it is
   done this way; I don't know and if it works, I don't want to know.  */

FOR_EACH_BB_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_entry_block_ptr->next_bb
; bb != ((cfun + 0))->cfg->x_exit_block_ptr; bb = bb->
next_bb)
  {
    FOR_BB_INSNS_REVERSE (bb, insn)for ((insn) = (bb)->il.x.rtl->end_; (insn) && (
insn) != PREV_INSN ((bb)->il.x.head_); (insn) = PREV_INSN (
insn))
      {
        if (!NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)))
          continue;

 /* Log links are created only once.  */
 gcc_assert (!LOG_LINKS (insn))((void)(!(!(uid_log_links[insn_uid_check (insn)])) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1046, __FUNCTION__), 0 : 0));

 FOR_EACH_INSN_DEF (def, insn)for (def = (((df->insns[(INSN_UID (insn))]))->defs); def
; def = ((def)->base.next_loc))
          {
            unsigned int regno = DF_REF_REGNO (def)((def)->base.regno);
            rtx_insn *use_insn;

            if (!next_use[regno])
              continue;

     if (!can_combine_def_p (def))
continue;

     use_insn = next_use[regno];
     next_use[regno] = NULLnullptr;

     if (BLOCK_FOR_INSN (use_insn) != bb)
continue;

     /* flow.c claimed:

 We don't build a LOG_LINK for hard registers contained
 in ASM_OPERANDs.  If these registers get replaced,
 we might wind up changing the semantics of the insn,
 even if reload can make what appear to be valid
 assignments later.  */
     if (regno < FIRST_PSEUDO_REGISTER76
  && asm_noperands (PATTERN (use_insn)) >= 0)
continue;

     /* Don't add duplicate links between instructions.  */
     struct insn_link *links;
     FOR_EACH_LOG_LINK (links, use_insn)for ((links) = (uid_log_links[insn_uid_check (use_insn)]); (links
); (links) = (links)->next)
       if (insn == links->insn && regno == links->regno)
  break;

     if (!links)
LOG_LINKS (use_insn)(uid_log_links[insn_uid_check (use_insn)])
  = alloc_insn_link (insn, regno, LOG_LINKS (use_insn)(uid_log_links[insn_uid_check (use_insn)]));
          }

 FOR_EACH_INSN_USE (use, insn)for (use = (((df->insns[(INSN_UID (insn))]))->uses); use
; use = ((use)->base.next_loc))
   if (can_combine_use_p (use))
     next_use[DF_REF_REGNO (use)((use)->base.regno)] = insn;
      }
  }

free (next_use);
1094}

1096/* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
 true if we found a LOG_LINK that proves that A feeds B.  This only works
 if there are no instructions between A and B which could have a link
 depending on A, since in that case we would not record a link for B.  */

1101static bool
1102insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1103{
struct insn_link *links;
FOR_EACH_LOG_LINK (links, b)for ((links) = (uid_log_links[insn_uid_check (b)]); (links); (
links) = (links)->next)
  if (links->insn == a)
    return true;
return false;
1109}
1110
1111/* Main entry point for combiner.  F is the first insn of the function.
 NREGS is the first unused pseudo-reg number.

 Return nonzero if the CFG was changed (e.g. if the combiner has
 turned an indirect jump instruction into a direct jump).  */
1116static int
1117combine_instructions (rtx_insn *f, unsigned int nregs)
1118{
rtx_insn *insn, *next;
struct insn_link *links, *nextlinks;
rtx_insn *first;
basic_block last_bb;

int new_direct_jump_p = 0;

for (first = f; first && !NONDEBUG_INSN_P (first)((((enum rtx_code) (first)->code) == INSN) || (((enum rtx_code
) (first)->code) == JUMP_INSN) || (((enum rtx_code) (first
)->code) == CALL_INSN)); )
  first = NEXT_INSN (first);
if (!first)
  return 0;

combine_attempts = 0;
combine_merges = 0;
combine_extras = 0;
combine_successes = 0;

rtl_hooks = combine_rtl_hooks;

reg_stat.safe_grow_cleared (nregs, true);

init_recog_no_volatile ();

/* Allocate array for insn info.  */
max_uid_known = get_max_uid ();
uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1)((struct insn_link * *) xcalloc ((max_uid_known + 1), sizeof (
struct insn_link *)));
uid_insn_cost = XCNEWVEC (int, max_uid_known + 1)((int *) xcalloc ((max_uid_known + 1), sizeof (int)));
gcc_obstack_init (&insn_link_obstack)_obstack_begin (((&insn_link_obstack)), (memory_block_pool
::block_size), (0), (mempool_obstack_chunk_alloc), (mempool_obstack_chunk_free
));

nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT64, 0).require ();

/* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
   problems when, for example, we have j <<= 1 in a loop.  */

nonzero_sign_valid = 0;
label_tick = label_tick_ebb_start = 1;

/* Scan all SETs and see if we can deduce anything about what
   bits are known to be zero for some registers and how many copies
   of the sign bit are known to exist for those registers.

   Also set any known values so that we can use it while searching
   for what bits are known to be set.  */

setup_incoming_promotions (first);
/* Allow the entry block and the first block to fall into the same EBB.
   Conceptually the incoming promotions are assigned to the entry block.  */
last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_entry_block_ptr);

create_log_links ();
FOR_EACH_BB_FN (this_basic_block, cfun)for (this_basic_block = ((cfun + 0))->cfg->x_entry_block_ptr
->next_bb; this_basic_block != ((cfun + 0))->cfg->x_exit_block_ptr
; this_basic_block = this_basic_block->next_bb)
  {
    optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
    last_call_luid = 0;
    mem_last_set = -1;

    label_tick++;
    if (!single_pred_p (this_basic_block)
 || single_pred (this_basic_block) != last_bb)
label_tick_ebb_start = label_tick;
    last_bb = this_basic_block;

    FOR_BB_INSNS (this_basic_block, insn)for ((insn) = (this_basic_block)->il.x.head_; (insn) &&
 (insn) != NEXT_INSN ((this_basic_block)->il.x.rtl->end_
); (insn) = NEXT_INSN (insn))
      if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)) && BLOCK_FOR_INSN (insn))
 {
          rtx links;

          subst_low_luid = DF_INSN_LUID (insn)((((df->insns[(INSN_UID (insn))]))->luid));
          subst_insn = insn;

   note_stores (insn, set_nonzero_bits_and_sign_copies, insn);
   record_dead_and_set_regs (insn);

   if (AUTO_INC_DEC0)
     for (links = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); links; links = XEXP (links, 1)(((links)->u.fld[1]).rt_rtx))
if (REG_NOTE_KIND (links)((enum reg_note) ((machine_mode) (links)->mode)) == REG_INC)
  set_nonzero_bits_and_sign_copies (XEXP (links, 0)(((links)->u.fld[0]).rt_rtx), NULL_RTX(rtx) 0,
				    insn);

   /* Record the current insn_cost of this instruction.  */
   INSN_COST (insn)(uid_insn_cost[insn_uid_check (insn)]) = insn_cost (insn, optimize_this_for_speed_p);
   if (dump_file)
     {
fprintf (dump_file, "insn_cost %d for ", INSN_COST (insn)(uid_insn_cost[insn_uid_check (insn)]));
dump_insn_slim (dump_file, insn);
     }
 }
  }

nonzero_sign_valid = 1;

/* Now scan all the insns in forward order.  */
label_tick = label_tick_ebb_start = 1;
init_reg_last ();
setup_incoming_promotions (first);
last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_entry_block_ptr);
int max_combine = param_max_combine_insnsglobal_options.x_param_max_combine_insns;

FOR_EACH_BB_FN (this_basic_block, cfun)for (this_basic_block = ((cfun + 0))->cfg->x_entry_block_ptr
->next_bb; this_basic_block != ((cfun + 0))->cfg->x_exit_block_ptr
; this_basic_block = this_basic_block->next_bb)
  {
    rtx_insn *last_combined_insn = NULLnullptr;

    /* Ignore instruction combination in basic blocks that are going to
be removed as unreachable anyway.  See PR82386.  */
    if (EDGE_COUNT (this_basic_block->preds)vec_safe_length (this_basic_block->preds) == 0)
continue;

    optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
    last_call_luid = 0;
    mem_last_set = -1;

    label_tick++;
    if (!single_pred_p (this_basic_block)
 || single_pred (this_basic_block) != last_bb)
label_tick_ebb_start = label_tick;
    last_bb = this_basic_block;

    rtl_profile_for_bb (this_basic_block);
    for (insn = BB_HEAD (this_basic_block)(this_basic_block)->il.x.head_;
  insn != NEXT_INSN (BB_END (this_basic_block)(this_basic_block)->il.x.rtl->end_);
  insn = next ? next : NEXT_INSN (insn))
{
 next = 0;
 if (!NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)))
   continue;

 while (last_combined_insn
 && (!NONDEBUG_INSN_P (last_combined_insn)((((enum rtx_code) (last_combined_insn)->code) == INSN) ||
 (((enum rtx_code) (last_combined_insn)->code) == JUMP_INSN
) || (((enum rtx_code) (last_combined_insn)->code) == CALL_INSN
))
     || last_combined_insn->deleted ()))
   last_combined_insn = PREV_INSN (last_combined_insn);
 if (last_combined_insn == NULL_RTX(rtx) 0
     || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
     || DF_INSN_LUID (last_combined_insn)((((df->insns[(INSN_UID (last_combined_insn))]))->luid)
) <= DF_INSN_LUID (insn)((((df->insns[(INSN_UID (insn))]))->luid)))
   last_combined_insn = insn;

 /* See if we know about function return values before this
    insn based upon SUBREG flags.  */
 check_promoted_subreg (insn, PATTERN (insn));

 /* See if we can find hardregs and subreg of pseudos in
    narrower modes.  This could help turning TRUNCATEs
    into SUBREGs.  */
 note_uses (&PATTERN (insn), record_truncated_values, NULLnullptr);

 /* Try this insn with each insn it links back to.  */

 FOR_EACH_LOG_LINK (links, insn)for ((links) = (uid_log_links[insn_uid_check (insn)]); (links
); (links) = (links)->next)
   if ((next = try_combine (insn, links->insn, NULLnullptr,
		     NULLnullptr, &new_direct_jump_p,
		     last_combined_insn)) != 0)
     {
statistics_counter_event (cfun(cfun + 0), "two-insn combine", 1);
goto retry;
     }

 /* Try each sequence of three linked insns ending with this one.  */

 if (max_combine >= 3)
   FOR_EACH_LOG_LINK (links, insn)for ((links) = (uid_log_links[insn_uid_check (insn)]); (links
); (links) = (links)->next)
     {
rtx_insn *link = links->insn;

/* If the linked insn has been replaced by a note, then there
   is no point in pursuing this chain any further.  */
if (NOTE_P (link)(((enum rtx_code) (link)->code) == NOTE))
  continue;

FOR_EACH_LOG_LINK (nextlinks, link)for ((nextlinks) = (uid_log_links[insn_uid_check (link)]); (nextlinks
); (nextlinks) = (nextlinks)->next)
  if ((next = try_combine (insn, link, nextlinks->insn,
			   NULLnullptr, &new_direct_jump_p,
			   last_combined_insn)) != 0)
    {
      statistics_counter_event (cfun(cfun + 0), "three-insn combine", 1);
      goto retry;
    }
     }

 /* Try combining an insn with two different insns whose results it
    uses.  */
 if (max_combine >= 3)
   FOR_EACH_LOG_LINK (links, insn)for ((links) = (uid_log_links[insn_uid_check (insn)]); (links
); (links) = (links)->next)
     for (nextlinks = links->next; nextlinks;
   nextlinks = nextlinks->next)
if ((next = try_combine (insn, links->insn,
			 nextlinks->insn, NULLnullptr,
			 &new_direct_jump_p,
			 last_combined_insn)) != 0)

  {
    statistics_counter_event (cfun(cfun + 0), "three-insn combine", 1);
    goto retry;
  }

 /* Try four-instruction combinations.  */
 if (max_combine >= 4)
   FOR_EACH_LOG_LINK (links, insn)for ((links) = (uid_log_links[insn_uid_check (insn)]); (links
); (links) = (links)->next)
     {
struct insn_link *next1;
rtx_insn *link = links->insn;

/* If the linked insn has been replaced by a note, then there
   is no point in pursuing this chain any further.  */
if (NOTE_P (link)(((enum rtx_code) (link)->code) == NOTE))
  continue;

FOR_EACH_LOG_LINK (next1, link)for ((next1) = (uid_log_links[insn_uid_check (link)]); (next1
); (next1) = (next1)->next)
  {
    rtx_insn *link1 = next1->insn;
    if (NOTE_P (link1)(((enum rtx_code) (link1)->code) == NOTE))
      continue;
    /* I0 -> I1 -> I2 -> I3.  */
    FOR_EACH_LOG_LINK (nextlinks, link1)for ((nextlinks) = (uid_log_links[insn_uid_check (link1)]); (
nextlinks); (nextlinks) = (nextlinks)->next)
      if ((next = try_combine (insn, link, link1,
			       nextlinks->insn,
			       &new_direct_jump_p,
			       last_combined_insn)) != 0)
	{
	  statistics_counter_event (cfun(cfun + 0), "four-insn combine", 1);
	  goto retry;
	}
    /* I0, I1 -> I2, I2 -> I3.  */
    for (nextlinks = next1->next; nextlinks;
	 nextlinks = nextlinks->next)
      if ((next = try_combine (insn, link, link1,
			       nextlinks->insn,
			       &new_direct_jump_p,
			       last_combined_insn)) != 0)
	{
	  statistics_counter_event (cfun(cfun + 0), "four-insn combine", 1);
	  goto retry;
	}
  }

for (next1 = links->next; next1; next1 = next1->next)
  {
    rtx_insn *link1 = next1->insn;
    if (NOTE_P (link1)(((enum rtx_code) (link1)->code) == NOTE))
      continue;
    /* I0 -> I2; I1, I2 -> I3.  */
    FOR_EACH_LOG_LINK (nextlinks, link)for ((nextlinks) = (uid_log_links[insn_uid_check (link)]); (nextlinks
); (nextlinks) = (nextlinks)->next)
      if ((next = try_combine (insn, link, link1,
			       nextlinks->insn,
			       &new_direct_jump_p,
			       last_combined_insn)) != 0)
	{
	  statistics_counter_event (cfun(cfun + 0), "four-insn combine", 1);
	  goto retry;
	}
    /* I0 -> I1; I1, I2 -> I3.  */
    FOR_EACH_LOG_LINK (nextlinks, link1)for ((nextlinks) = (uid_log_links[insn_uid_check (link1)]); (
nextlinks); (nextlinks) = (nextlinks)->next)
      if ((next = try_combine (insn, link, link1,
			       nextlinks->insn,
			       &new_direct_jump_p,
			       last_combined_insn)) != 0)
	{
	  statistics_counter_event (cfun(cfun + 0), "four-insn combine", 1);
	  goto retry;
	}
  }
     }

 /* Try this insn with each REG_EQUAL note it links back to.  */
 FOR_EACH_LOG_LINK (links, insn)for ((links) = (uid_log_links[insn_uid_check (insn)]); (links
); (links) = (links)->next)
   {
     rtx set, note;
     rtx_insn *temp = links->insn;
     if ((set = single_set (temp)) != 0
  && (note = find_reg_equal_equiv_note (temp)) != 0
  && (note = XEXP (note, 0)(((note)->u.fld[0]).rt_rtx), GET_CODE (note)((enum rtx_code) (note)->code)) != EXPR_LIST
  && ! side_effects_p (SET_SRC (set)(((set)->u.fld[1]).rt_rtx))
  /* Avoid using a register that may already been marked
     dead by an earlier instruction.  */
  && ! unmentioned_reg_p (note, SET_SRC (set)(((set)->u.fld[1]).rt_rtx))
  && (GET_MODE (note)((machine_mode) (note)->mode) == VOIDmode((void) 0, E_VOIDmode)
      ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))(((enum mode_class) mode_class[((machine_mode) ((((set)->u
.fld[0]).rt_rtx))->mode)]) == MODE_INT || ((enum mode_class
) mode_class[((machine_mode) ((((set)->u.fld[0]).rt_rtx))->
mode)]) == MODE_PARTIAL_INT)
      : (GET_MODE (SET_DEST (set))((machine_mode) ((((set)->u.fld[0]).rt_rtx))->mode) == GET_MODE (note)((machine_mode) (note)->mode)
	 && (GET_CODE (SET_DEST (set))((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) != ZERO_EXTRACT
	     || (GET_MODE (XEXP (SET_DEST (set), 0))((machine_mode) (((((((set)->u.fld[0]).rt_rtx))->u.fld[
0]).rt_rtx))->mode)
		 == GET_MODE (note)((machine_mode) (note)->mode))))))
{
  /* Temporarily replace the set's source with the
     contents of the REG_EQUAL note.  The insn will
     be deleted or recognized by try_combine.  */
  rtx orig_src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
  rtx orig_dest = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);
  if (GET_CODE (SET_DEST (set))((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) == ZERO_EXTRACT)
    SET_DEST (set)(((set)->u.fld[0]).rt_rtx) = XEXP (SET_DEST (set), 0)((((((set)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx);
  SET_SRC (set)(((set)->u.fld[1]).rt_rtx) = note;
  i2mod = temp;
  i2mod_old_rhs = copy_rtx (orig_src);
  i2mod_new_rhs = copy_rtx (note);
  next = try_combine (insn, i2mod, NULLnullptr, NULLnullptr,
		      &new_direct_jump_p,
		      last_combined_insn);
  i2mod = NULLnullptr;
  if (next)
    {
      statistics_counter_event (cfun(cfun + 0), "insn-with-note combine", 1);
      goto retry;
    }
  SET_SRC (set)(((set)->u.fld[1]).rt_rtx) = orig_src;
  SET_DEST (set)(((set)->u.fld[0]).rt_rtx) = orig_dest;
}
   }

 if (!NOTE_P (insn)(((enum rtx_code) (insn)->code) == NOTE))
   record_dead_and_set_regs (insn);

1427retry:
 ;
}
  }

default_rtl_profile ();
clear_bb_flags ();
new_direct_jump_p |= purge_all_dead_edges ();
new_direct_jump_p |= delete_noop_moves ();

/* Clean up.  */
obstack_free (&insn_link_obstack, NULL)__extension__ ({ struct obstack *__o = (&insn_link_obstack
); void *__obj = (void *) (nullptr); if (__obj > (void *) __o
->chunk && __obj < (void *) __o->chunk_limit
) __o->next_free = __o->object_base = (char *) __obj; else
 _obstack_free (__o, __obj); });
free (uid_log_links);
free (uid_insn_cost);
reg_stat.release ();

{
  struct undo *undo, *next;
  for (undo = undobuf.frees; undo; undo = next)
    {
next = undo->next;
free (undo);
    }
  undobuf.frees = 0;
}

total_attempts += combine_attempts;
total_merges += combine_merges;
total_extras += combine_extras;
total_successes += combine_successes;

nonzero_sign_valid = 0;
rtl_hooks = general_rtl_hooks;

/* Make recognizer allow volatile MEMs again.  */
init_recog ();

return new_direct_jump_p;
1465}

1467/* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */

1469static void
1470init_reg_last (void)
1471{
unsigned int i;
reg_stat_type *p;

FOR_EACH_VEC_ELT (reg_stat, i, p)for (i = 0; (reg_stat).iterate ((i), &(p)); ++(i))
  memset (p, 0, offsetof (reg_stat_type, sign_bit_copies)__builtin_offsetof(reg_stat_type, sign_bit_copies));
1477}
1478
1479/* Set up any promoted values for incoming argument registers.  */

1481static void
1482setup_incoming_promotions (rtx_insn *first)
1483{
tree arg;
bool strictly_local = false;

for (arg = DECL_ARGUMENTS (current_function_decl)((tree_check ((current_function_decl), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1487, __FUNCTION__, (FUNCTION_DECL)))->function_decl.arguments
); arg;
     arg = DECL_CHAIN (arg)(((contains_struct_check (((contains_struct_check ((arg), (TS_DECL_MINIMAL
), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1488, __FUNCTION__))), (TS_COMMON), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1488, __FUNCTION__))->common.chain)))
  {
    rtx x, reg = DECL_INCOMING_RTL (arg)((tree_check ((arg), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1490, __FUNCTION__, (PARM_DECL)))->parm_decl.incoming_rtl
);
    int uns1, uns3;
    machine_mode mode1, mode2, mode3, mode4;

    /* Only continue if the incoming argument is in a register.  */
    if (!REG_P (reg)(((enum rtx_code) (reg)->code) == REG))
continue;

    /* Determine, if possible, whether all call sites of the current
       function lie within the current compilation unit.  (This does
take into account the exporting of a function via taking its
address, and so forth.)  */
    strictly_local
= cgraph_node::local_info_node (current_function_decl)->local;

    /* The mode and signedness of the argument before any promotions happen
       (equal to the mode of the pseudo holding it at that stage).  */
    mode1 = TYPE_MODE (TREE_TYPE (arg))((((enum tree_code) ((tree_class_check ((((contains_struct_check
 ((arg), (TS_TYPED), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1507, __FUNCTION__))->typed.type)), (tcc_type), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1507, __FUNCTION__)))->base.code) == VECTOR_TYPE) ? vector_type_mode
 (((contains_struct_check ((arg), (TS_TYPED), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1507, __FUNCTION__))->typed.type)) : (((contains_struct_check
 ((arg), (TS_TYPED), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1507, __FUNCTION__))->typed.type))->type_common.mode);
    uns1 = TYPE_UNSIGNED (TREE_TYPE (arg))((tree_class_check ((((contains_struct_check ((arg), (TS_TYPED
), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1508, __FUNCTION__))->typed.type)), (tcc_type), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1508, __FUNCTION__))->base.u.bits.unsigned_flag);

    /* The mode and signedness of the argument after any source language and
       TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
    mode2 = TYPE_MODE (DECL_ARG_TYPE (arg))((((enum tree_code) ((tree_class_check ((((tree_check ((arg),
 "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1512, __FUNCTION__, (PARM_DECL)))->decl_common.initial))
, (tcc_type), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1512, __FUNCTION__)))->base.code) == VECTOR_TYPE) ? vector_type_mode
 (((tree_check ((arg), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1512, __FUNCTION__, (PARM_DECL)))->decl_common.initial))
 : (((tree_check ((arg), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1512, __FUNCTION__, (PARM_DECL)))->decl_common.initial))
->type_common.mode);
    uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg))((tree_class_check ((((tree_check ((arg), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1513, __FUNCTION__, (PARM_DECL)))->decl_common.initial))
, (tcc_type), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1513, __FUNCTION__))->base.u.bits.unsigned_flag);

    /* The mode and signedness of the argument as it is actually passed,
       see assign_parm_setup_reg in function.cc.  */
    mode3 = promote_function_mode (TREE_TYPE (arg)((contains_struct_check ((arg), (TS_TYPED), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1517, __FUNCTION__))->typed.type), mode1, &uns3,
		     TREE_TYPE (cfun->decl)((contains_struct_check (((cfun + 0)->decl), (TS_TYPED), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1518, __FUNCTION__))->typed.type), 0);

    /* The mode of the register in which the argument is being passed.  */
    mode4 = GET_MODE (reg)((machine_mode) (reg)->mode);

    /* Eliminate sign extensions in the callee when:
(a) A mode promotion has occurred;  */
    if (mode1 == mode3)
continue;
    /* (b) The mode of the register is the same as the mode of
    the argument as it is passed; */
    if (mode3 != mode4)
continue;
    /* (c) There's no language level extension;  */
    if (mode1 == mode2)
;
    /* (c.1) All callers are from the current compilation unit.  If that's
the case we don't have to rely on an ABI, we only have to know
what we're generating right now, and we know that we will do the
mode1 to mode2 promotion with the given sign.  */
    else if (!strictly_local)
continue;
    /* (c.2) The combination of the two promotions is useful.  This is
true when the signs match, or if the first promotion is unsigned.
In the later case, (sign_extend (zero_extend x)) is the same as
(zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
    else if (uns1)
uns3 = true;
    else if (uns3)
continue;

    /* Record that the value was promoted from mode1 to mode3,
so that any sign extension at the head of the current
function may be eliminated.  */
    x = gen_rtx_CLOBBER (mode1, const0_rtx)gen_rtx_fmt_e_stat ((CLOBBER), ((mode1)), (((const_int_rtx[64
]))) );
    x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x)gen_rtx_fmt_e_stat (((uns3 ? ZERO_EXTEND : SIGN_EXTEND)), (mode3
), (x) );
    record_value_for_reg (reg, first, x);
  }
1556}

1558/* If MODE has a precision lower than PREC and SRC is a non-negative constant
 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
 because some machines (maybe most) will actually do the sign-extension and
 this is the conservative approach.

 ??? For 2.5, try to tighten up the MD files in this regard instead of this
 kludge.  */

1566static rtx
1567sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
1568{
scalar_int_mode int_mode;
if (CONST_INT_P (src)(((enum rtx_code) (src)->code) == CONST_INT)
    && is_a <scalar_int_mode> (mode, &int_mode)
    && GET_MODE_PRECISION (int_mode) < prec
    && INTVAL (src)((src)->u.hwint[0]) > 0
    && val_signbit_known_set_p (int_mode, INTVAL (src)((src)->u.hwint[0])))
  src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode))gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (((src)->u.hwint
[0]) | ~mode_mask_array[int_mode]));

return src;
1578}

1580/* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
 and SET.  */

1583static void
1584update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
	   rtx x)
1586{
rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX(rtx) 0;
unsigned HOST_WIDE_INTlong bits = 0;
rtx reg_equal = NULLnullptr, src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
unsigned int num = 0;

if (reg_equal_note)
  reg_equal = XEXP (reg_equal_note, 0)(((reg_equal_note)->u.fld[0]).rt_rtx);

if (SHORT_IMMEDIATES_SIGN_EXTEND0)
  {
    src = sign_extend_short_imm (src, GET_MODE (x)((machine_mode) (x)->mode), BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
 1)) != 0) ? 8 : 4)));
    if (reg_equal)
reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x)((machine_mode) (x)->mode), BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
 1)) != 0) ? 8 : 4)));
  }

/* Don't call nonzero_bits if it cannot change anything.  */
if (rsp->nonzero_bits != HOST_WIDE_INT_M1U-1UL)
  {
    machine_mode mode = GET_MODE (x)((machine_mode) (x)->mode);
    if (GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) == MODE_INT
 && HWI_COMPUTABLE_MODE_P (mode))
mode = nonzero_bits_mode;
    bits = nonzero_bits (src, mode);
    if (reg_equal && bits)
bits &= nonzero_bits (reg_equal, mode);
    rsp->nonzero_bits |= bits;
  }

/* Don't call num_sign_bit_copies if it cannot change anything.  */
if (rsp->sign_bit_copies != 1)
  {
    num = num_sign_bit_copies (SET_SRC (set)(((set)->u.fld[1]).rt_rtx), GET_MODE (x)((machine_mode) (x)->mode));
    if (reg_equal && maybe_ne (num, GET_MODE_PRECISION (GET_MODE (x)((machine_mode) (x)->mode))))
{
 unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x)((machine_mode) (x)->mode));
 if (num == 0 || numeq > num)
   num = numeq;
}
    if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies)
rsp->sign_bit_copies = num;
  }
1628}

1630/* Called via note_stores.  If X is a pseudo that is narrower than
 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.

 If we are setting only a portion of X and we can't figure out what
 portion, assume all bits will be used since we don't know what will
 be happening.

 Similarly, set how many bits of X are known to be copies of the sign bit
 at all locations in the function.  This is the smallest number implied
 by any set of X.  */

1641static void
1642set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1643{
rtx_insn *insn = (rtx_insn *) data;
scalar_int_mode mode;

if (REG_P (x)(((enum rtx_code) (x)->code) == REG)
    && REGNO (x)(rhs_regno(x)) >= FIRST_PSEUDO_REGISTER76
    /* If this register is undefined at the start of the file, we can't
say what its contents were.  */
    && ! REGNO_REG_SET_Pbitmap_bit_p ((&(df_lr_get_bb_info (((((cfun + 0))->cfg
->x_entry_block_ptr)->next_bb)->index))->in), (rhs_regno
(x)))
  (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))bitmap_bit_p ((&(df_lr_get_bb_info (((((cfun + 0))->cfg
->x_entry_block_ptr)->next_bb)->index))->in), (rhs_regno
(x)))
    && is_a <scalar_int_mode> (GET_MODE (x)((machine_mode) (x)->mode), &mode)
    && HWI_COMPUTABLE_MODE_P (mode))
  {
    reg_stat_type *rsp = &reg_stat[REGNO (x)(rhs_regno(x))];

    if (set == 0 || GET_CODE (set)((enum rtx_code) (set)->code) == CLOBBER)
{
 rsp->nonzero_bits = GET_MODE_MASK (mode)mode_mask_array[mode];
 rsp->sign_bit_copies = 1;
 return;
}

    /* If this register is being initialized using itself, and the
register is uninitialized in this basic block, and there are
no LOG_LINKS which set the register, then part of the
register is uninitialized.  In that case we can't assume
anything about the number of nonzero bits.

??? We could do better if we checked this in
reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
could avoid making assumptions about the insn which initially
sets the register, while still using the information in other
insns.  We would have to be careful to check every insn
involved in the combination.  */

    if (insn
 && reg_referenced_p (x, PATTERN (insn))
 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),bitmap_bit_p ((&(df_lr_get_bb_info ((BLOCK_FOR_INSN (insn
))->index))->in), (rhs_regno(x)))
	       REGNO (x))bitmap_bit_p ((&(df_lr_get_bb_info ((BLOCK_FOR_INSN (insn
))->index))->in), (rhs_regno(x))))
{
 struct insn_link *link;

 FOR_EACH_LOG_LINK (link, insn)for ((link) = (uid_log_links[insn_uid_check (insn)]); (link);
 (link) = (link)->next)
   if (dead_or_set_p (link->insn, x))
     break;
 if (!link)
   {
     rsp->nonzero_bits = GET_MODE_MASK (mode)mode_mask_array[mode];
     rsp->sign_bit_copies = 1;
     return;
   }
}

    /* If this is a complex assignment, see if we can convert it into a
simple assignment.  */
    set = expand_field_assignment (set);

    /* If this is a simple assignment, or we have a paradoxical SUBREG,
set what we know about X.  */

    if (SET_DEST (set)(((set)->u.fld[0]).rt_rtx) == x
 || (paradoxical_subreg_p (SET_DEST (set)(((set)->u.fld[0]).rt_rtx))
     && SUBREG_REG (SET_DEST (set))((((((set)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx) == x))
update_rsp_from_reg_equal (rsp, insn, set, x);
    else
{
 rsp->nonzero_bits = GET_MODE_MASK (mode)mode_mask_array[mode];
 rsp->sign_bit_copies = 1;
}
  }
1713}
1714
1715/* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
 optionally insns that were previously combined into I3 or that will be
 combined into the merger of INSN and I3.  The order is PRED, PRED2,
 INSN, SUCC, SUCC2, I3.

 Return 0 if the combination is not allowed for any reason.

 If the combination is allowed, *PDEST will be set to the single
 destination of INSN and *PSRC to the single source, and this function
 will return 1.  */

1726static int
1727can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED__attribute__ ((__unused__)),
      rtx_insn *pred2 ATTRIBUTE_UNUSED__attribute__ ((__unused__)), rtx_insn *succ, rtx_insn *succ2,
      rtx *pdest, rtx *psrc)
1730{
int i;
const_rtx set = 0;
rtx src, dest;
rtx_insn *p;
rtx link;
bool all_adjacent = true;
int (*is_volatile_p) (const_rtx);

if (succ)
  {
    if (succ2)
{
 if (next_active_insn (succ2) != i3)
   all_adjacent = false;
 if (next_active_insn (succ) != succ2)
   all_adjacent = false;
}
    else if (next_active_insn (succ) != i3)
all_adjacent = false;
    if (next_active_insn (insn) != succ)
all_adjacent = false;
  }
else if (next_active_insn (insn) != i3)
  all_adjacent = false;
  
/* Can combine only if previous insn is a SET of a REG or a SUBREG,
   or a PARALLEL consisting of such a SET and CLOBBERs.

   If INSN has CLOBBER parallel parts, ignore them for our processing.
   By definition, these happen during the execution of the insn.  When it
   is merged with another insn, all bets are off.  If they are, in fact,
   needed and aren't also supplied in I3, they may be added by
   recog_for_combine.  Otherwise, it won't match.

   We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
   note.

   Get the source and destination of INSN.  If more than one, can't
   combine.  */

if (GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == SET)
  set = PATTERN (insn);
else if (GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == PARALLEL
  && GET_CODE (XVECEXP (PATTERN (insn), 0, 0))((enum rtx_code) ((((((PATTERN (insn))->u.fld[0]).rt_rtvec
))->elem[0]))->code) == SET)
  {
    for (i = 0; i < XVECLEN (PATTERN (insn), 0)(((((PATTERN (insn))->u.fld[0]).rt_rtvec))->num_elem); i++)
{
 rtx elt = XVECEXP (PATTERN (insn), 0, i)(((((PATTERN (insn))->u.fld[0]).rt_rtvec))->elem[i]);

 switch (GET_CODE (elt)((enum rtx_code) (elt)->code))
   {
   /* This is important to combine floating point insns
      for the SH4 port.  */
   case USE:
     /* Combining an isolated USE doesn't make sense.
 We depend here on combinable_i3pat to reject them.  */
     /* The code below this loop only verifies that the inputs of
 the SET in INSN do not change.  We call reg_set_between_p
 to verify that the REG in the USE does not change between
 I3 and INSN.
 If the USE in INSN was for a pseudo register, the matching
 insn pattern will likely match any register; combining this
 with any other USE would only be safe if we knew that the
 used registers have identical values, or if there was
 something to tell them apart, e.g. different modes.  For
 now, we forgo such complicated tests and simply disallow
 combining of USES of pseudo registers with any other USE.  */
     if (REG_P (XEXP (elt, 0))(((enum rtx_code) ((((elt)->u.fld[0]).rt_rtx))->code) ==
 REG)
  && GET_CODE (PATTERN (i3))((enum rtx_code) (PATTERN (i3))->code) == PARALLEL)
{
  rtx i3pat = PATTERN (i3);
  int i = XVECLEN (i3pat, 0)(((((i3pat)->u.fld[0]).rt_rtvec))->num_elem) - 1;
  unsigned int regno = REGNO (XEXP (elt, 0))(rhs_regno((((elt)->u.fld[0]).rt_rtx)));

  do
    {
      rtx i3elt = XVECEXP (i3pat, 0, i)(((((i3pat)->u.fld[0]).rt_rtvec))->elem[i]);

      if (GET_CODE (i3elt)((enum rtx_code) (i3elt)->code) == USE
	  && REG_P (XEXP (i3elt, 0))(((enum rtx_code) ((((i3elt)->u.fld[0]).rt_rtx))->code)
 == REG)
	  && (REGNO (XEXP (i3elt, 0))(rhs_regno((((i3elt)->u.fld[0]).rt_rtx))) == regno
	      ? reg_set_between_p (XEXP (elt, 0)(((elt)->u.fld[0]).rt_rtx),
				   PREV_INSN (insn), i3)
	      : regno >= FIRST_PSEUDO_REGISTER76))
	return 0;
    }
  while (--i >= 0);
}
     break;

     /* We can ignore CLOBBERs.  */
   case CLOBBER:
     break;

   case SET:
     /* Ignore SETs whose result isn't used but not those that
 have side-effects.  */
     if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)(((elt)->u.fld[0]).rt_rtx))
  && insn_nothrow_p (insn)
  && !side_effects_p (elt))
break;

     /* If we have already found a SET, this is a second one and
 so we cannot combine with this insn.  */
     if (set)
return 0;

     set = elt;
     break;

   default:
     /* Anything else means we can't combine.  */
     return 0;
   }
}

    if (set == 0
 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
    so don't do anything with it.  */
 || GET_CODE (SET_SRC (set))((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) == ASM_OPERANDS)
return 0;
  }
else
  return 0;

if (set == 0)
  return 0;

/* The simplification in expand_field_assignment may call back to
   get_last_value, so set safe guard here.  */
subst_low_luid = DF_INSN_LUID (insn)((((df->insns[(INSN_UID (insn))]))->luid));

set = expand_field_assignment (set);
src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx), dest = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);

/* Do not eliminate user-specified register if it is in an
   asm input because we may break the register asm usage defined
   in GCC manual if allow to do so.
   Be aware that this may cover more cases than we expect but this
   should be harmless.  */
if (REG_P (dest)(((enum rtx_code) (dest)->code) == REG) && REG_USERVAR_P (dest)(__extension__ ({ __typeof ((dest)) const _rtx = ((dest)); if
 (((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
 ("REG_USERVAR_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1871, __FUNCTION__); _rtx; })->volatil) && HARD_REGISTER_P (dest)((((rhs_regno(dest))) < 76))
    && extract_asm_operands (PATTERN (i3)))
  return 0;

/* Don't eliminate a store in the stack pointer.  */
if (dest == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
    /* Don't combine with an insn that sets a register to itself if it has
a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
    || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX(rtx) 0))
    /* Can't merge an ASM_OPERANDS.  */
    || GET_CODE (src)((enum rtx_code) (src)->code) == ASM_OPERANDS
    /* Can't merge a function call.  */
    || GET_CODE (src)((enum rtx_code) (src)->code) == CALL
    /* Don't eliminate a function call argument.  */
    || (CALL_P (i3)(((enum rtx_code) (i3)->code) == CALL_INSN)
 && (find_reg_fusage (i3, USE, dest)
     || (REG_P (dest)(((enum rtx_code) (dest)->code) == REG)
  && REGNO (dest)(rhs_regno(dest)) < FIRST_PSEUDO_REGISTER76
  && global_regs[REGNO (dest)(rhs_regno(dest))])))
    /* Don't substitute into an incremented register.  */
    || FIND_REG_INC_NOTE (i3, dest)0
    || (succ && FIND_REG_INC_NOTE (succ, dest)0)
    || (succ2 && FIND_REG_INC_NOTE (succ2, dest)0)
    /* Don't substitute into a non-local goto, this confuses CFG.  */
    || (JUMP_P (i3)(((enum rtx_code) (i3)->code) == JUMP_INSN) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX(rtx) 0))
    /* Make sure that DEST is not used after INSN but before SUCC, or
after SUCC and before SUCC2, or after SUCC2 but before I3.  */
    || (!all_adjacent
 && ((succ2
      && (reg_used_between_p (dest, succ2, i3)
   || reg_used_between_p (dest, succ, succ2)))
     || (!succ2 && succ && reg_used_between_p (dest, succ, i3))
     || (!succ2 && !succ && reg_used_between_p (dest, insn, i3))
     || (succ
  /* SUCC and SUCC2 can be split halves from a PARALLEL; in
     that case SUCC is not in the insn stream, so use SUCC2
     instead for this test.  */
  && reg_used_between_p (dest, insn,
			 succ2
			 && INSN_UID (succ) == INSN_UID (succ2)
			 ? succ2 : succ))))
    /* Make sure that the value that is to be substituted for the register
does not use any registers whose values alter in between.  However,
If the insns are adjacent, a use can't cross a set even though we
think it might (this can happen for a sequence of insns each setting
the same destination; last_set of that register might point to
a NOTE).  If INSN has a REG_EQUIV note, the register is always
equivalent to the memory so the substitution is valid even if there
are intervening stores.  Also, don't move a volatile asm or
UNSPEC_VOLATILE across any other insns.  */
    || (! all_adjacent
 && (((!MEM_P (src)(((enum rtx_code) (src)->code) == MEM)
|| ! find_reg_note (insn, REG_EQUIV, src))
      && modified_between_p (src, insn, i3))
     || (GET_CODE (src)((enum rtx_code) (src)->code) == ASM_OPERANDS && MEM_VOLATILE_P (src)(__extension__ ({ __typeof ((src)) const _rtx = ((src)); if (
((enum rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 1925, __FUNCTION__); _rtx; })->volatil))
     || GET_CODE (src)((enum rtx_code) (src)->code) == UNSPEC_VOLATILE))
    /* Don't combine across a CALL_INSN, because that would possibly
change whether the life span of some REGs crosses calls or not,
and it is a pain to update that information.
Exception: if source is a constant, moving it later can't hurt.
Accept that as a special case.  */
    || (DF_INSN_LUID (insn)((((df->insns[(INSN_UID (insn))]))->luid)) < last_call_luid && ! CONSTANT_P (src)((rtx_class[(int) (((enum rtx_code) (src)->code))]) == RTX_CONST_OBJ
)))
  return 0;

/* DEST must be a REG.  */
if (REG_P (dest)(((enum rtx_code) (dest)->code) == REG))
  {
    /* If register alignment is being enforced for multi-word items in all
cases except for parameters, it is possible to have a register copy
insn referencing a hard register that is not allowed to contain the
mode being copied and which would not be valid as an operand of most
insns.  Eliminate this problem by not combining with such an insn.

Also, on some machines we don't want to extend the life of a hard
register.  */

    if (REG_P (src)(((enum rtx_code) (src)->code) == REG)
 && ((REGNO (dest)(rhs_regno(dest)) < FIRST_PSEUDO_REGISTER76
      && !targetm.hard_regno_mode_ok (REGNO (dest)(rhs_regno(dest)), GET_MODE (dest)((machine_mode) (dest)->mode)))
     /* Don't extend the life of a hard register unless it is
 user variable (if we have few registers) or it can't
 fit into the desired register (meaning something special
 is going on).
 Also avoid substituting a return register into I3, because
 reload can't handle a conflict with constraints of other
 inputs.  */
     || (REGNO (src)(rhs_regno(src)) < FIRST_PSEUDO_REGISTER76
  && !targetm.hard_regno_mode_ok (REGNO (src)(rhs_regno(src)),
				  GET_MODE (src)((machine_mode) (src)->mode)))))
return 0;
  }
else
  return 0;


if (GET_CODE (PATTERN (i3))((enum rtx_code) (PATTERN (i3))->code) == PARALLEL)
  for (i = XVECLEN (PATTERN (i3), 0)(((((PATTERN (i3))->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
    if (GET_CODE (XVECEXP (PATTERN (i3), 0, i))((enum rtx_code) ((((((PATTERN (i3))->u.fld[0]).rt_rtvec))
->elem[i]))->code) == CLOBBER)
{
 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0)((((((((PATTERN (i3))->u.fld[0]).rt_rtvec))->elem[i]))->
u.fld[0]).rt_rtx);

 /* If the clobber represents an earlyclobber operand, we must not
    substitute an expression containing the clobbered register.
    As we do not analyze the constraint strings here, we have to
    make the conservative assumption.  However, if the register is
    a fixed hard reg, the clobber cannot represent any operand;
    we leave it up to the machine description to either accept or
    reject use-and-clobber patterns.  */
 if (!REG_P (reg)(((enum rtx_code) (reg)->code) == REG)
     || REGNO (reg)(rhs_regno(reg)) >= FIRST_PSEUDO_REGISTER76
     || !fixed_regs(this_target_hard_regs->x_fixed_regs)[REGNO (reg)(rhs_regno(reg))])
   if (reg_overlap_mentioned_p (reg, src))
     return 0;
}

/* If INSN contains anything volatile, or is an `asm' (whether volatile
   or not), reject, unless nothing volatile comes between it and I3 */

if (GET_CODE (src)((enum rtx_code) (src)->code) == ASM_OPERANDS || volatile_refs_p (src))
  {
    /* Make sure neither succ nor succ2 contains a volatile reference.  */
    if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
return 0;
    if (succ != 0 && volatile_refs_p (PATTERN (succ)))
return 0;
    /* We'll check insns between INSN and I3 below.  */
  }

/* If INSN is an asm, and DEST is a hard register, reject, since it has
   to be an explicit register variable, and was chosen for a reason.  */

if (GET_CODE (src)((enum rtx_code) (src)->code) == ASM_OPERANDS
    && REG_P (dest)(((enum rtx_code) (dest)->code) == REG) && REGNO (dest)(rhs_regno(dest)) < FIRST_PSEUDO_REGISTER76)
  return 0;

/* If INSN contains volatile references (specifically volatile MEMs),
   we cannot combine across any other volatile references.
   Even if INSN doesn't contain volatile references, any intervening
   volatile insn might affect machine state.  */

is_volatile_p = volatile_refs_p (PATTERN (insn))
  ? volatile_refs_p
  : volatile_insn_p;

for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
  if (INSN_P (p)(((((enum rtx_code) (p)->code) == INSN) || (((enum rtx_code
) (p)->code) == JUMP_INSN) || (((enum rtx_code) (p)->code
) == CALL_INSN)) || (((enum rtx_code) (p)->code) == DEBUG_INSN
)) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
    return 0;

/* If INSN contains an autoincrement or autodecrement, make sure that
   register is not used between there and I3, and not already used in
   I3 either.  Neither must it be used in PRED or SUCC, if they exist.
   Also insist that I3 not be a jump if using LRA; if it were one
   and the incremented register were spilled, we would lose.
   Reload handles this correctly.  */

if (AUTO_INC_DEC0)
  for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
    if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == REG_INC
 && ((JUMP_P (i3)(((enum rtx_code) (i3)->code) == JUMP_INSN) && targetm.lra_p ())
     || reg_used_between_p (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), insn, i3)
     || (pred != NULL_RTX(rtx) 0
  && reg_overlap_mentioned_p (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), PATTERN (pred)))
     || (pred2 != NULL_RTX(rtx) 0
  && reg_overlap_mentioned_p (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), PATTERN (pred2)))
     || (succ != NULL_RTX(rtx) 0
  && reg_overlap_mentioned_p (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), PATTERN (succ)))
     || (succ2 != NULL_RTX(rtx) 0
  && reg_overlap_mentioned_p (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), PATTERN (succ2)))
     || reg_overlap_mentioned_p (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), PATTERN (i3))))
return 0;

/* If we get here, we have passed all the tests and the combination is
   to be allowed.  */

*pdest = dest;
*psrc = src;

return 1;
2049}
2050
2051/* LOC is the location within I3 that contains its pattern or the component
 of a PARALLEL of the pattern.  We validate that it is valid for combining.

 One problem is if I3 modifies its output, as opposed to replacing it
 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
 doing so would produce an insn that is not equivalent to the original insns.

 Consider:

(set (reg:DI 101) (reg:DI 100))
(set (subreg:SI (reg:DI 101) 0) <foo>)

 This is NOT equivalent to:

(parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
    (set (reg:DI 101) (reg:DI 100))])

 Not only does this modify 100 (in which case it might still be valid
 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.

 We can also run into a problem if I2 sets a register that I1
 uses and I1 gets directly substituted into I3 (not via I2).  In that
 case, we would be getting the wrong value of I2DEST into I3, so we
 must reject the combination.  This case occurs when I2 and I1 both
 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
 of a SET must prevent combination from occurring.  The same situation
 can occur for I0, in which case I0_NOT_IN_SRC is set.

 Before doing the above check, we first try to expand a field assignment
 into a set of logical operations.

 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
 we place a register that is both set and used within I3.  If more than one
 such register is detected, we fail.

 Return 1 if the combination is valid, zero otherwise.  */

2089static int
2090combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
  int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2092{
rtx x = *loc;

if (GET_CODE (x)((enum rtx_code) (x)->code) == SET)
  {
    rtx set = x ;
    rtx dest = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);
    rtx src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
    rtx inner_dest = dest;
    rtx subdest;

    while (GET_CODE (inner_dest)((enum rtx_code) (inner_dest)->code) == STRICT_LOW_PART
    || GET_CODE (inner_dest)((enum rtx_code) (inner_dest)->code) == SUBREG
    || GET_CODE (inner_dest)((enum rtx_code) (inner_dest)->code) == ZERO_EXTRACT)
inner_dest = XEXP (inner_dest, 0)(((inner_dest)->u.fld[0]).rt_rtx);

    /* Check for the case where I3 modifies its output, as discussed
above.  We don't want to prevent pseudos from being combined
into the address of a MEM, so only prevent the combination if
i1 or i2 set the same MEM.  */
    if ((inner_dest != dest &&
  (!MEM_P (inner_dest)(((enum rtx_code) (inner_dest)->code) == MEM)
   || rtx_equal_p (i2dest, inner_dest)
   || (i1dest && rtx_equal_p (i1dest, inner_dest))
   || (i0dest && rtx_equal_p (i0dest, inner_dest)))
  && (reg_overlap_mentioned_p (i2dest, inner_dest)
      || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
      || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))

 /* This is the same test done in can_combine_p except we can't test
    all_adjacent; we don't have to, since this instruction will stay
    in place, thus we are not considering increasing the lifetime of
    INNER_DEST.

    Also, if this insn sets a function argument, combining it with
    something that might need a spill could clobber a previous
    function argument; the all_adjacent test in can_combine_p also
    checks this; here, we do a more specific test for this case.  */

 || (REG_P (inner_dest)(((enum rtx_code) (inner_dest)->code) == REG)
     && REGNO (inner_dest)(rhs_regno(inner_dest)) < FIRST_PSEUDO_REGISTER76
     && !targetm.hard_regno_mode_ok (REGNO (inner_dest)(rhs_regno(inner_dest)),
			      GET_MODE (inner_dest)((machine_mode) (inner_dest)->mode)))
 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
return 0;

    /* If DEST is used in I3, it is being killed in this insn, so
record that for later.  We have to consider paradoxical
subregs here, since they kill the whole register, but we
ignore partial subregs, STRICT_LOW_PART, etc.
Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
STACK_POINTER_REGNUM, since these are always considered to be
live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
    subdest = dest;
    if (GET_CODE (subdest)((enum rtx_code) (subdest)->code) == SUBREG && !partial_subreg_p (subdest))
subdest = SUBREG_REG (subdest)(((subdest)->u.fld[0]).rt_rtx);
    if (pi3dest_killed
 && REG_P (subdest)(((enum rtx_code) (subdest)->code) == REG)
 && reg_referenced_p (subdest, PATTERN (i3))
 && REGNO (subdest)(rhs_regno(subdest)) != FRAME_POINTER_REGNUM19
 && (HARD_FRAME_POINTER_IS_FRAME_POINTER(6 == 19)
     || REGNO (subdest)(rhs_regno(subdest)) != HARD_FRAME_POINTER_REGNUM6)
 && (FRAME_POINTER_REGNUM19 == ARG_POINTER_REGNUM16
     || (REGNO (subdest)(rhs_regno(subdest)) != ARG_POINTER_REGNUM16
  || ! fixed_regs(this_target_hard_regs->x_fixed_regs) [REGNO (subdest)(rhs_regno(subdest))]))
 && REGNO (subdest)(rhs_regno(subdest)) != STACK_POINTER_REGNUM7)
{
 if (*pi3dest_killed)
   return 0;

 *pi3dest_killed = subdest;
}
  }

else if (GET_CODE (x)((enum rtx_code) (x)->code) == PARALLEL)
  {
    int i;

    for (i = 0; i < XVECLEN (x, 0)(((((x)->u.fld[0]).rt_rtvec))->num_elem); i++)
if (! combinable_i3pat (i3, &XVECEXP (x, 0, i)(((((x)->u.fld[0]).rt_rtvec))->elem[i]), i2dest, i1dest, i0dest,
		i1_not_in_src, i0_not_in_src, pi3dest_killed))
 return 0;
  }

return 1;
2178}
2179
2180/* Return 1 if X is an arithmetic expression that contains a multiplication
 and division.  We don't count multiplications by powers of two here.  */

2183static int
2184contains_muldiv (rtx x)
2185{
switch (GET_CODE (x)((enum rtx_code) (x)->code))
  {
  case MOD:  case DIV:  case UMOD:  case UDIV:
    return 1;

  case MULT:
    return ! (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
&& pow2p_hwi (UINTVAL (XEXP (x, 1))((unsigned long) (((((x)->u.fld[1]).rt_rtx))->u.hwint[0
]))));
  default:
    if (BINARY_P (x)(((rtx_class[(int) (((enum rtx_code) (x)->code))]) & (
~3)) == (RTX_COMPARE & (~3))))
return contains_muldiv (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
   || contains_muldiv (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));

    if (UNARY_P (x)((rtx_class[(int) (((enum rtx_code) (x)->code))]) == RTX_UNARY
))
return contains_muldiv (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));

    return 0;
  }
2204}
2205
2206/* Determine whether INSN can be used in a combination.  Return nonzero if
 not.  This is used in try_combine to detect early some cases where we
 can't perform combinations.  */

2210static int
2211cant_combine_insn_p (rtx_insn *insn)
2212{
rtx set;
rtx src, dest;

/* If this isn't really an insn, we can't do anything.
   This can occur when flow deletes an insn that it has merged into an
   auto-increment address.  */
if (!NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)))
  return 1;

/* Never combine loads and stores involving hard regs that are likely
   to be spilled.  The register allocator can usually handle such
   reg-reg moves by tying.  If we allow the combiner to make
   substitutions of likely-spilled regs, reload might die.
   As an exception, we allow combinations involving fixed regs; these are
   not available to the register allocator so there's no risk involved.  */

set = single_set (insn);
if (! set)
  return 0;
src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
dest = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);
if (GET_CODE (src)((enum rtx_code) (src)->code) == SUBREG)
  src = SUBREG_REG (src)(((src)->u.fld[0]).rt_rtx);
if (GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG)
  dest = SUBREG_REG (dest)(((dest)->u.fld[0]).rt_rtx);
if (REG_P (src)(((enum rtx_code) (src)->code) == REG) && REG_P (dest)(((enum rtx_code) (dest)->code) == REG)
    && ((HARD_REGISTER_P (src)((((rhs_regno(src))) < 76))
  && ! TEST_HARD_REG_BIT (fixed_reg_set(this_target_hard_regs->x_fixed_reg_set), REGNO (src)(rhs_regno(src)))
2241#ifdef LEAF_REGISTERS
  && ! LEAF_REGISTERS [REGNO (src)(rhs_regno(src))])
2243#else
  )
2245#endif
 || (HARD_REGISTER_P (dest)((((rhs_regno(dest))) < 76))
     && ! TEST_HARD_REG_BIT (fixed_reg_set(this_target_hard_regs->x_fixed_reg_set), REGNO (dest)(rhs_regno(dest)))
     && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))(regclass_map[((rhs_regno(dest)))])))))
  return 1;

return 0;
2252}

2254struct likely_spilled_retval_info
2255{
unsigned regno, nregs;
unsigned mask;
2258};

2260/* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
 hard registers that are known to be written to / clobbered in full.  */
2262static void
2263likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2264{
struct likely_spilled_retval_info *const info =
  (struct likely_spilled_retval_info *) data;
unsigned regno, nregs;
unsigned new_mask;

if (!REG_P (XEXP (set, 0))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 REG))
  return;
regno = REGNO (x)(rhs_regno(x));
if (regno >= info->regno + info->nregs)
  return;
nregs = REG_NREGS (x)((&(x)->u.reg)->nregs);
if (regno + nregs <= info->regno)
  return;
new_mask = (2U << (nregs - 1)) - 1;
if (regno < info->regno)
  new_mask >>= info->regno - regno;
else
  new_mask <<= regno - info->regno;
info->mask &= ~new_mask;
2284}

2286/* Return nonzero iff part of the return value is live during INSN, and
 it is likely spilled.  This can happen when more than one insn is needed
 to copy the return value, e.g. when we consider to combine into the
 second copy insn for a complex value.  */

2291static int
2292likely_spilled_retval_p (rtx_insn *insn)
2293{
rtx_insn *use = BB_END (this_basic_block)(this_basic_block)->il.x.rtl->end_;
rtx reg;
rtx_insn *p;
unsigned regno, nregs;
/* We assume here that no machine mode needs more than
   32 hard registers when the value overlaps with a register
   for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
unsigned mask;
struct likely_spilled_retval_info info;

if (!NONJUMP_INSN_P (use)(((enum rtx_code) (use)->code) == INSN) || GET_CODE (PATTERN (use))((enum rtx_code) (PATTERN (use))->code) != USE || insn == use)
  return 0;
reg = XEXP (PATTERN (use), 0)(((PATTERN (use))->u.fld[0]).rt_rtx);
if (!REG_P (reg)(((enum rtx_code) (reg)->code) == REG) || !targetm.calls.function_value_regno_p (REGNO (reg)(rhs_regno(reg))))
  return 0;
regno = REGNO (reg)(rhs_regno(reg));
nregs = REG_NREGS (reg)((&(reg)->u.reg)->nregs);
if (nregs == 1)
  return 0;
mask = (2U << (nregs - 1)) - 1;

/* Disregard parts of the return value that are set later.  */
info.regno = regno;
info.nregs = nregs;
info.mask = mask;
for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
  if (INSN_P (p)(((((enum rtx_code) (p)->code) == INSN) || (((enum rtx_code
) (p)->code) == JUMP_INSN) || (((enum rtx_code) (p)->code
) == CALL_INSN)) || (((enum rtx_code) (p)->code) == DEBUG_INSN
)))
    note_stores (p, likely_spilled_retval_1, &info);
mask = info.mask;

/* Check if any of the (probably) live return value registers is
   likely spilled.  */
nregs --;
do
  {
    if ((mask & 1 << nregs)
 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)(regclass_map[(regno + nregs)])))
return 1;
  } while (nregs--);
return 0;
2334}

2336/* Adjust INSN after we made a change to its destination.

 Changing the destination can invalidate notes that say something about
 the results of the insn and a LOG_LINK pointing to the insn.  */

2341static void
2342adjust_for_new_dest (rtx_insn *insn)
2343{
/* For notes, be conservative and simply remove them.  */
remove_reg_equal_equiv_notes (insn, true);

/* The new insn will have a destination that was previously the destination
   of an insn just above it.  Call distribute_links to make a LOG_LINK from
   the next use of that destination.  */

rtx set = single_set (insn);
gcc_assert (set)((void)(!(set) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 2352, __FUNCTION__), 0 : 0));

rtx reg = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);

while (GET_CODE (reg)((enum rtx_code) (reg)->code) == ZERO_EXTRACT
|| GET_CODE (reg)((enum rtx_code) (reg)->code) == STRICT_LOW_PART
|| GET_CODE (reg)((enum rtx_code) (reg)->code) == SUBREG)
  reg = XEXP (reg, 0)(((reg)->u.fld[0]).rt_rtx);
gcc_assert (REG_P (reg))((void)(!((((enum rtx_code) (reg)->code) == REG)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 2360, __FUNCTION__), 0 : 0));

distribute_links (alloc_insn_link (insn, REGNO (reg)(rhs_regno(reg)), NULLnullptr));

df_insn_rescan (insn);
2365}

2367/* Return TRUE if combine can reuse reg X in mode MODE.
 ADDED_SETS is nonzero if the original set is still required.  */
2369static bool
2370can_change_dest_mode (rtx x, int added_sets, machine_mode mode)
2371{
unsigned int regno;

if (!REG_P (x)(((enum rtx_code) (x)->code) == REG))
  return false;

/* Don't change between modes with different underlying register sizes,
   since this could lead to invalid subregs.  */
if (maybe_ne (REGMODE_NATURAL_SIZE (mode)ix86_regmode_natural_size (mode),
REGMODE_NATURAL_SIZE (GET_MODE (x))ix86_regmode_natural_size (((machine_mode) (x)->mode))))
  return false;

regno = REGNO (x)(rhs_regno(x));
/* Allow hard registers if the new mode is legal, and occupies no more
   registers than the old mode.  */
if (regno < FIRST_PSEUDO_REGISTER76)
  return (targetm.hard_regno_mode_ok (regno, mode)
   && REG_NREGS (x)((&(x)->u.reg)->nregs) >= hard_regno_nregs (regno, mode));

/* Or a pseudo that is only used once.  */
return (regno < reg_n_sets_max
 && REG_N_SETS (regno) == 1
 && !added_sets
 && !REG_USERVAR_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag ("REG_USERVAR_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 2394, __FUNCTION__); _rtx; })->volatil));
2395}


2398/* Check whether X, the destination of a set, refers to part of
 the register specified by REG.  */

2401static bool
2402reg_subword_p (rtx x, rtx reg)
2403{
/* Check that reg is an integer mode register.  */
if (!REG_P (reg)(((enum rtx_code) (reg)->code) == REG) || GET_MODE_CLASS (GET_MODE (reg))((enum mode_class) mode_class[((machine_mode) (reg)->mode)
]) != MODE_INT)
  return false;

if (GET_CODE (x)((enum rtx_code) (x)->code) == STRICT_LOW_PART
    || GET_CODE (x)((enum rtx_code) (x)->code) == ZERO_EXTRACT)
  x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);

return GET_CODE (x)((enum rtx_code) (x)->code) == SUBREG
&& !paradoxical_subreg_p (x)
&& SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx) == reg
&& GET_MODE_CLASS (GET_MODE (x))((enum mode_class) mode_class[((machine_mode) (x)->mode)]) == MODE_INT;
2416}

2418/* Return whether PAT is a PARALLEL of exactly N register SETs followed
 by an arbitrary number of CLOBBERs.  */
2420static bool
2421is_parallel_of_n_reg_sets (rtx pat, int n)
2422{
if (GET_CODE (pat)((enum rtx_code) (pat)->code) != PARALLEL)
  return false;

int len = XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem);
if (len < n)
  return false;

int i;
for (i = 0; i < n; i++)
  if (GET_CODE (XVECEXP (pat, 0, i))((enum rtx_code) ((((((pat)->u.fld[0]).rt_rtvec))->elem
[i]))->code) != SET
|| !REG_P (SET_DEST (XVECEXP (pat, 0, i)))(((enum rtx_code) (((((((((pat)->u.fld[0]).rt_rtvec))->
elem[i]))->u.fld[0]).rt_rtx))->code) == REG))
    return false;
for ( ; i < len; i++)
  switch (GET_CODE (XVECEXP (pat, 0, i))((enum rtx_code) ((((((pat)->u.fld[0]).rt_rtvec))->elem
[i]))->code))
    {
    case CLOBBER:
if (XEXP (XVECEXP (pat, 0, i), 0)((((((((pat)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx) == const0_rtx(const_int_rtx[64]))
 return false;
break;
    default:
return false;
    }
return true;
2446}

2448/* Return whether INSN, a PARALLEL of N register SETs (and maybe some
 CLOBBERs), can be split into individual SETs in that order, without
 changing semantics.  */
2451static bool
2452can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
2453{
if (!insn_nothrow_p (insn))
  return false;

rtx pat = PATTERN (insn);

int i, j;
for (i = 0; i < n; i++)
  {
    if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i))((((((((pat)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[1]).rt_rtx)))
return false;

    rtx reg = SET_DEST (XVECEXP (pat, 0, i))((((((((pat)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx);

    for (j = i + 1; j < n; j++)
if (reg_referenced_p (reg, XVECEXP (pat, 0, j)(((((pat)->u.fld[0]).rt_rtvec))->elem[j])))
 return false;
  }

return true;
2473}

2475/* Return whether X is just a single_set, with the source
 a general_operand.  */
2477static bool
2478is_just_move (rtx_insn *x)
2479{
rtx set = single_set (x);
if (!set)
  return false;

return general_operand (SET_SRC (set)(((set)->u.fld[1]).rt_rtx), VOIDmode((void) 0, E_VOIDmode));
2485}

2487/* Callback function to count autoincs.  */

2489static int
2490count_auto_inc (rtx, rtx, rtx, rtx, rtx, void *arg)
2491{
(*((int *) arg))++;

return 0;
2495}

2497/* Try to combine the insns I0, I1 and I2 into I3.
 Here I0, I1 and I2 appear earlier than I3.
 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
 I3.

 If we are combining more than two insns and the resulting insn is not
 recognized, try splitting it into two insns.  If that happens, I2 and I3
 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
 Otherwise, I0, I1 and I2 are pseudo-deleted.

 Return 0 if the combination does not work.  Then nothing is changed.
 If we did the combination, return the insn at which combine should
 resume scanning.

 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
 new direct jump instruction.

 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
 been I3 passed to an earlier try_combine within the same basic
 block.  */

2518static rtx_insn *
2519try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
    int *new_direct_jump_p, rtx_insn *last_combined_insn)
2521{
/* New patterns for I3 and I2, respectively.  */
rtx newpat, newi2pat = 0;
rtvec newpat_vec_with_clobbers = 0;
int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
/* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
   dead.  */
int added_sets_0, added_sets_1, added_sets_2;
/* Total number of SETs to put into I3.  */
int total_sets;
/* Nonzero if I2's or I1's body now appears in I3.  */
int i2_is_used = 0, i1_is_used = 0;
/* INSN_CODEs for new I3, new I2, and user of condition code.  */
int insn_code_number, i2_code_number = 0, other_code_number = 0;
/* Contains I3 if the destination of I3 is used in its source, which means
   that the old life of I3 is being killed.  If that usage is placed into
   I2 and not in I3, a REG_DEAD note must be made.  */
rtx i3dest_killed = 0;
/* SET_DEST and SET_SRC of I2, I1 and I0.  */
rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
/* Copy of SET_SRC of I1 and I0, if needed.  */
rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
/* Set if I2DEST was reused as a scratch register.  */
bool i2scratch = false;
/* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
rtx i0pat = 0, i1pat = 0, i2pat = 0;
/* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
/* Notes that must be added to REG_NOTES in I3 and I2.  */
rtx new_i3_notes, new_i2_notes;
1
'new_i3_notes' declared without an initial value→
/* Notes that we substituted I3 into I2 instead of the normal case.  */
int i3_subst_into_i2 = 0;
/* Notes that I1, I2 or I3 is a MULT operation.  */
int have_mult = 0;
int swap_i2i3 = 0;
int split_i2i3 = 0;
int changed_i3_dest = 0;
bool i2_was_move = false, i3_was_move = false;
int n_auto_inc = 0;

int maxreg;
rtx_insn *temp_insn;
rtx temp_expr;
struct insn_link *link;
rtx other_pat = 0;
rtx new_other_notes;
int i;
scalar_int_mode dest_mode, temp_mode;
bool has_non_call_exception = false;

/* Immediately return if any of I0,I1,I2 are the same insn (I3 can
   never be).  */
if (i1 == i2 || i0 == i2 || (i0 && i0 == i1))
2
←
Assuming 'i1' is not equal to 'i2'→
3
←
Assuming 'i0' is not equal to 'i2'→
4
←
Assuming 'i0' is null→
  return 0;

/* Only try four-insn combinations when there's high likelihood of
   success.  Look for simple insns, such as loads of constants or
   binary operations involving a constant.  */
if (i04.1
'i0' is null
)
  {
    int i;
    int ngood = 0;
    int nshift = 0;
    rtx set0, set3;

    if (!flag_expensive_optimizationsglobal_options.x_flag_expensive_optimizations)
return 0;

    for (i = 0; i < 4; i++)
{
 rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
 rtx set = single_set (insn);
 rtx src;
 if (!set)
   continue;
 src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
 if (CONSTANT_P (src)((rtx_class[(int) (((enum rtx_code) (src)->code))]) == RTX_CONST_OBJ
))
   {
     ngood += 2;
     break;
   }
 else if (BINARY_P (src)(((rtx_class[(int) (((enum rtx_code) (src)->code))]) &
 (~3)) == (RTX_COMPARE & (~3))) && CONSTANT_P (XEXP (src, 1))((rtx_class[(int) (((enum rtx_code) ((((src)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
   ngood++;
 else if (GET_CODE (src)((enum rtx_code) (src)->code) == ASHIFT || GET_CODE (src)((enum rtx_code) (src)->code) == ASHIFTRT
   || GET_CODE (src)((enum rtx_code) (src)->code) == LSHIFTRT)
   nshift++;
}

    /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
are likely manipulating its value.  Ideally we'll be able to combine
all four insns into a bitfield insertion of some kind. 

Note the source in I0 might be inside a sign/zero extension and the
memory modes in I0 and I3 might be different.  So extract the address
from the destination of I3 and search for it in the source of I0.

In the event that there's a match but the source/dest do not actually
refer to the same memory, the worst that happens is we try some
combinations that we wouldn't have otherwise.  */
    if ((set0 = single_set (i0))
 /* Ensure the source of SET0 is a MEM, possibly buried inside
    an extension.  */
 && (GET_CODE (SET_SRC (set0))((enum rtx_code) ((((set0)->u.fld[1]).rt_rtx))->code) == MEM
     || ((GET_CODE (SET_SRC (set0))((enum rtx_code) ((((set0)->u.fld[1]).rt_rtx))->code) == ZERO_EXTEND
   || GET_CODE (SET_SRC (set0))((enum rtx_code) ((((set0)->u.fld[1]).rt_rtx))->code) == SIGN_EXTEND)
  && GET_CODE (XEXP (SET_SRC (set0), 0))((enum rtx_code) (((((((set0)->u.fld[1]).rt_rtx))->u.fld
[0]).rt_rtx))->code) == MEM))
 && (set3 = single_set (i3))
 /* Ensure the destination of SET3 is a MEM.  */
 && GET_CODE (SET_DEST (set3))((enum rtx_code) ((((set3)->u.fld[0]).rt_rtx))->code) == MEM
 /* Would it be better to extract the base address for the MEM
    in SET3 and look for that?  I don't have cases where it matters
    but I could envision such cases.  */
 && rtx_referenced_p (XEXP (SET_DEST (set3), 0)((((((set3)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx), SET_SRC (set0)(((set0)->u.fld[1]).rt_rtx)))
ngood += 2;

    if (ngood < 2 && nshift < 2)
return 0;
  }

/* Exit early if one of the insns involved can't be used for
   combinations.  */
if (CALL_P (i2)(((enum rtx_code) (i2)->code) == CALL_INSN)
5
←
Taking false branch→
6
←
Assuming field 'code' is not equal to CALL_INSN→
8
←
Taking false branch→
    || (i1 && CALL_P (i1)(((enum rtx_code) (i1)->code) == CALL_INSN))
7
←
Assuming 'i1' is null→
    || (i07.1
'i0' is null
 && CALL_P (i0)(((enum rtx_code) (i0)->code) == CALL_INSN))
    || cant_combine_insn_p (i3)
    || cant_combine_insn_p (i2)
    || (i17.2
'i1' is null
 && cant_combine_insn_p (i1))
    || (i07.3
'i0' is null
 && cant_combine_insn_p (i0))
    || likely_spilled_retval_p (i3))
  return 0;

combine_attempts++;
undobuf.other_insn = 0;

/* Reset the hard register usage information.  */
CLEAR_HARD_REG_SET (newpat_used_regs);

if (dump_file && (dump_flags & TDF_DETAILS))
9
←
Assuming 'dump_file' is null→
  {
    if (i0)
fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
    else if (i1)
fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
    else
fprintf (dump_file, "\nTrying %d -> %d:\n",
 INSN_UID (i2), INSN_UID (i3));

    if (i0)
dump_insn_slim (dump_file, i0);
    if (i1)
dump_insn_slim (dump_file, i1);
    dump_insn_slim (dump_file, i2);
    dump_insn_slim (dump_file, i3);
  }

/* If multiple insns feed into one of I2 or I3, they can be in any
   order.  To simplify the code below, reorder them in sequence.  */
if (i09.1
'i0' is null
 && DF_INSN_LUID (i0)((((df->insns[(INSN_UID (i0))]))->luid)) > DF_INSN_LUID (i2)((((df->insns[(INSN_UID (i2))]))->luid)))
  std::swap (i0, i2);
if (i09.2
'i0' is null
 && DF_INSN_LUID (i0)((((df->insns[(INSN_UID (i0))]))->luid)) > DF_INSN_LUID (i1)((((df->insns[(INSN_UID (i1))]))->luid)))
  std::swap (i0, i1);
if (i19.3
'i1' is null
 && DF_INSN_LUID (i1)((((df->insns[(INSN_UID (i1))]))->luid)) > DF_INSN_LUID (i2)((((df->insns[(INSN_UID (i2))]))->luid)))
  std::swap (i1, i2);

added_links_insn = 0;
added_notes_insn = 0;

/* First check for one important special case that the code below will
   not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
   and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
   we may be able to replace that destination with the destination of I3.
   This occurs in the common code where we compute both a quotient and
   remainder into a structure, in which case we want to do the computation
   directly into the structure to avoid register-register copies.

   Note that this case handles both multiple sets in I2 and also cases
   where I2 has a number of CLOBBERs inside the PARALLEL.

   We make very conservative checks below and only try to handle the
   most common cases of this.  For example, we only handle the case
   where I2 and I3 are adjacent to avoid making difficult register
   usage tests.  */

if (i19.4
'i1' is equal to null
 == 0 && NONJUMP_INSN_P (i3)(((enum rtx_code) (i3)->code) == INSN) && GET_CODE (PATTERN (i3))((enum rtx_code) (PATTERN (i3))->code) == SET
    && REG_P (SET_SRC (PATTERN (i3)))(((enum rtx_code) ((((PATTERN (i3))->u.fld[1]).rt_rtx))->
code) == REG)
    && REGNO (SET_SRC (PATTERN (i3)))(rhs_regno((((PATTERN (i3))->u.fld[1]).rt_rtx))) >= FIRST_PSEUDO_REGISTER76
    && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))(((PATTERN (i3))->u.fld[1]).rt_rtx))
    && GET_CODE (PATTERN (i2))((enum rtx_code) (PATTERN (i2))->code) == PARALLEL
    && ! side_effects_p (SET_DEST (PATTERN (i3))(((PATTERN (i3))->u.fld[0]).rt_rtx))
    /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
below would need to check what is inside (and reg_overlap_mentioned_p
doesn't support those codes anyway).  Don't allow those destinations;
the resulting insn isn't likely to be recognized anyway.  */
    && GET_CODE (SET_DEST (PATTERN (i3)))((enum rtx_code) ((((PATTERN (i3))->u.fld[0]).rt_rtx))->
code) != ZERO_EXTRACT
    && GET_CODE (SET_DEST (PATTERN (i3)))((enum rtx_code) ((((PATTERN (i3))->u.fld[0]).rt_rtx))->
code) != STRICT_LOW_PART
    && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3))(((PATTERN (i3))->u.fld[1]).rt_rtx),
		    SET_DEST (PATTERN (i3))(((PATTERN (i3))->u.fld[0]).rt_rtx))
    && next_active_insn (i2) == i3)
  {
    rtx p2 = PATTERN (i2);

    /* Make sure that the destination of I3,
which we are going to substitute into one output of I2,
is not used within another output of I2.  We must avoid making this:
(parallel [(set (mem (reg 69)) ...)
    (set (reg 69) ...)])
which is not well-defined as to order of actions.
(Besides, reload can't handle output reloads for this.)

The problem can also happen if the dest of I3 is a memory ref,
if another dest in I2 is an indirect memory ref.

Neither can this PARALLEL be an asm.  We do not allow combining
that usually (see can_combine_p), so do not here either.  */
    bool ok = true;
    for (i = 0; ok && i < XVECLEN (p2, 0)(((((p2)->u.fld[0]).rt_rtvec))->num_elem); i++)
{
 if ((GET_CODE (XVECEXP (p2, 0, i))((enum rtx_code) ((((((p2)->u.fld[0]).rt_rtvec))->elem[
i]))->code) == SET
      || GET_CODE (XVECEXP (p2, 0, i))((enum rtx_code) ((((((p2)->u.fld[0]).rt_rtvec))->elem[
i]))->code) == CLOBBER)
     && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3))(((PATTERN (i3))->u.fld[0]).rt_rtx),
			  SET_DEST (XVECEXP (p2, 0, i))((((((((p2)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld[
0]).rt_rtx)))
   ok = false;
 else if (GET_CODE (XVECEXP (p2, 0, i))((enum rtx_code) ((((((p2)->u.fld[0]).rt_rtvec))->elem[
i]))->code) == SET
   && GET_CODE (SET_SRC (XVECEXP (p2, 0, i)))((enum rtx_code) (((((((((p2)->u.fld[0]).rt_rtvec))->elem
[i]))->u.fld[1]).rt_rtx))->code) == ASM_OPERANDS)
   ok = false;
}

    if (ok)
for (i = 0; i < XVECLEN (p2, 0)(((((p2)->u.fld[0]).rt_rtvec))->num_elem); i++)
 if (GET_CODE (XVECEXP (p2, 0, i))((enum rtx_code) ((((((p2)->u.fld[0]).rt_rtvec))->elem[
i]))->code) == SET
     && SET_DEST (XVECEXP (p2, 0, i))((((((((p2)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld[
0]).rt_rtx) == SET_SRC (PATTERN (i3))(((PATTERN (i3))->u.fld[1]).rt_rtx))
   {
     combine_merges++;

     subst_insn = i3;
     subst_low_luid = DF_INSN_LUID (i2)((((df->insns[(INSN_UID (i2))]))->luid));

     added_sets_2 = added_sets_1 = added_sets_0 = 0;
     i2src = SET_SRC (XVECEXP (p2, 0, i))((((((((p2)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld[
1]).rt_rtx);
     i2dest = SET_DEST (XVECEXP (p2, 0, i))((((((((p2)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld[
0]).rt_rtx);
     i2dest_killed = dead_or_set_p (i2, i2dest);

     /* Replace the dest in I2 with our dest and make the resulting
 insn the new pattern for I3.  Then skip to where we validate
 the pattern.  Everything was set up above.  */
     SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)))do_SUBST (&(((((((((p2)->u.fld[0]).rt_rtvec))->elem
[i]))->u.fld[0]).rt_rtx)), ((((PATTERN (i3))->u.fld[0])
.rt_rtx)));
     newpat = p2;
     i3_subst_into_i2 = 1;
     goto validate_replacement;
   }
  }

/* If I2 is setting a pseudo to a constant and I3 is setting some
   sub-part of it to another constant, merge them by making a new
   constant.  */
if (i19.6
'i1' is equal to null
 == 0
    && (temp_expr = single_set (i2)) != 0
10
←
Assuming the condition is false→
    && is_a <scalar_int_mode> (GET_MODE (SET_DEST (temp_expr))((machine_mode) ((((temp_expr)->u.fld[0]).rt_rtx))->mode
), &temp_mode)
    && CONST_SCALAR_INT_P (SET_SRC (temp_expr))((((enum rtx_code) ((((temp_expr)->u.fld[1]).rt_rtx))->
code) == CONST_INT) || (((enum rtx_code) ((((temp_expr)->u
.fld[1]).rt_rtx))->code) == CONST_WIDE_INT))
    && GET_CODE (PATTERN (i3))((enum rtx_code) (PATTERN (i3))->code) == SET
    && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))((((enum rtx_code) ((((PATTERN (i3))->u.fld[1]).rt_rtx))->
code) == CONST_INT) || (((enum rtx_code) ((((PATTERN (i3))->
u.fld[1]).rt_rtx))->code) == CONST_WIDE_INT))
    && reg_subword_p (SET_DEST (PATTERN (i3))(((PATTERN (i3))->u.fld[0]).rt_rtx), SET_DEST (temp_expr)(((temp_expr)->u.fld[0]).rt_rtx)))
  {
    rtx dest = SET_DEST (PATTERN (i3))(((PATTERN (i3))->u.fld[0]).rt_rtx);
    rtx temp_dest = SET_DEST (temp_expr)(((temp_expr)->u.fld[0]).rt_rtx);
    int offset = -1;
    int width = 0;

    if (GET_CODE (dest)((enum rtx_code) (dest)->code) == ZERO_EXTRACT)
{
 if (CONST_INT_P (XEXP (dest, 1))(((enum rtx_code) ((((dest)->u.fld[1]).rt_rtx))->code) ==
 CONST_INT)
     && CONST_INT_P (XEXP (dest, 2))(((enum rtx_code) ((((dest)->u.fld[2]).rt_rtx))->code) ==
 CONST_INT)
     && is_a <scalar_int_mode> (GET_MODE (XEXP (dest, 0))((machine_mode) ((((dest)->u.fld[0]).rt_rtx))->mode),
			 &dest_mode))
   {
     width = INTVAL (XEXP (dest, 1))(((((dest)->u.fld[1]).rt_rtx))->u.hwint[0]);
     offset = INTVAL (XEXP (dest, 2))(((((dest)->u.fld[2]).rt_rtx))->u.hwint[0]);
     dest = XEXP (dest, 0)(((dest)->u.fld[0]).rt_rtx);
     if (BITS_BIG_ENDIAN0)
offset = GET_MODE_PRECISION (dest_mode) - width - offset;
   }
}
    else
{
 if (GET_CODE (dest)((enum rtx_code) (dest)->code) == STRICT_LOW_PART)
   dest = XEXP (dest, 0)(((dest)->u.fld[0]).rt_rtx);
 if (is_a <scalar_int_mode> (GET_MODE (dest)((machine_mode) (dest)->mode), &dest_mode))
   {
     width = GET_MODE_PRECISION (dest_mode);
     offset = 0;
   }
}

    if (offset >= 0)
{
 /* If this is the low part, we're done.  */
 if (subreg_lowpart_p (dest))
   ;
 /* Handle the case where inner is twice the size of outer.  */
 else if (GET_MODE_PRECISION (temp_mode)
   == 2 * GET_MODE_PRECISION (dest_mode))
   offset += GET_MODE_PRECISION (dest_mode);
 /* Otherwise give up for now.  */
 else
   offset = -1;
}

    if (offset >= 0)
{
 rtx inner = SET_SRC (PATTERN (i3))(((PATTERN (i3))->u.fld[1]).rt_rtx);
 rtx outer = SET_SRC (temp_expr)(((temp_expr)->u.fld[1]).rt_rtx);

 wide_int o = wi::insert (rtx_mode_t (outer, temp_mode),
		   rtx_mode_t (inner, dest_mode),
		   offset, width);

 combine_merges++;
 subst_insn = i3;
 subst_low_luid = DF_INSN_LUID (i2)((((df->insns[(INSN_UID (i2))]))->luid));
 added_sets_2 = added_sets_1 = added_sets_0 = 0;
 i2dest = temp_dest;
 i2dest_killed = dead_or_set_p (i2, i2dest);

 /* Replace the source in I2 with the new constant and make the
    resulting insn the new pattern for I3.  Then skip to where we
    validate the pattern.  Everything was set up above.  */
 SUBST (SET_SRC (temp_expr),do_SUBST (&((((temp_expr)->u.fld[1]).rt_rtx)), (immed_wide_int_const
 (o, temp_mode)))
 immed_wide_int_const (o, temp_mode))do_SUBST (&((((temp_expr)->u.fld[1]).rt_rtx)), (immed_wide_int_const
 (o, temp_mode)));

 newpat = PATTERN (i2);

        /* The dest of I3 has been replaced with the dest of I2.  */
        changed_i3_dest = 1;
 goto validate_replacement;
}
  }

/* If we have no I1 and I2 looks like:
(parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
   (set Y OP)])
   make up a dummy I1 that is
(set Y OP)
   and change I2 to be
(set (reg:CC X) (compare:CC Y (const_int 0)))

   (We can ignore any trailing CLOBBERs.)

   This undoes a previous combination and allows us to match a branch-and-
   decrement insn.  */

if (i110.1
'i1' is equal to null
 == 0
    && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
    && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))((enum mode_class) mode_class[((machine_mode) (((((((((PATTERN
 (i2))->u.fld[0]).rt_rtvec))->elem[0]))->u.fld[0]).rt_rtx
))->mode)])
 == MODE_CC)
    && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)))((enum rtx_code) (((((((((PATTERN (i2))->u.fld[0]).rt_rtvec
))->elem[0]))->u.fld[1]).rt_rtx))->code) == COMPARE
    && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1)(((((((((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[0]
))->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx) == const0_rtx(const_int_rtx[64])
    && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0)(((((((((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[0]
))->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx),
      SET_SRC (XVECEXP (PATTERN (i2), 0, 1))((((((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[1]))->
u.fld[1]).rt_rtx))
    && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))((((((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[0]))->
u.fld[0]).rt_rtx), i2, i3)
    && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))((((((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[1]))->
u.fld[0]).rt_rtx), i2, i3))
  {
    /* We make I1 with the same INSN_UID as I2.  This gives it
the same DF_INSN_LUID for value tracking.  Our fake I1 will
never appear in the insn stream so giving it the same INSN_UID
as I2 will not cause a problem.  */

    i1 = gen_rtx_INSN (VOIDmode((void) 0, E_VOIDmode), NULLnullptr, i2, BLOCK_FOR_INSN (i2),
	 XVECEXP (PATTERN (i2), 0, 1)(((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[1]), INSN_LOCATION (i2),
	 -1, NULL_RTX(rtx) 0);
    INSN_UID (i1) = INSN_UID (i2);

    SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0))do_SUBST (&(PATTERN (i2)), ((((((PATTERN (i2))->u.fld[
0]).rt_rtvec))->elem[0])));
    SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),do_SUBST (&(((((((PATTERN (i2))->u.fld[1]).rt_rtx))->
u.fld[0]).rt_rtx)), ((((PATTERN (i1))->u.fld[0]).rt_rtx)))
    SET_DEST (PATTERN (i1)))do_SUBST (&(((((((PATTERN (i2))->u.fld[1]).rt_rtx))->
u.fld[0]).rt_rtx)), ((((PATTERN (i1))->u.fld[0]).rt_rtx)));
    unsigned int regno = REGNO (SET_DEST (PATTERN (i1)))(rhs_regno((((PATTERN (i1))->u.fld[0]).rt_rtx)));
    SUBST_LINK (LOG_LINKS (i2),do_SUBST_LINK (&(uid_log_links[insn_uid_check (i2)]), alloc_insn_link
 (i1, regno, (uid_log_links[insn_uid_check (i2)])))
  alloc_insn_link (i1, regno, LOG_LINKS (i2)))do_SUBST_LINK (&(uid_log_links[insn_uid_check (i2)]), alloc_insn_link
 (i1, regno, (uid_log_links[insn_uid_check (i2)])));
  }

/* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
   make those two SETs separate I1 and I2 insns, and make an I0 that is
   the original I1.  */
if (i010.2
'i0' is equal to null
 == 0
    && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
    && can_split_parallel_of_n_reg_sets (i2, 2)
    && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))((((((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[0]))->
u.fld[0]).rt_rtx), i2, i3)
    && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))((((((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[1]))->
u.fld[0]).rt_rtx), i2, i3)
    && !reg_set_between_p  (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))((((((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[0]))->
u.fld[0]).rt_rtx), i2, i3)
    && !reg_set_between_p  (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))((((((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[1]))->
u.fld[0]).rt_rtx), i2, i3))
  {
    /* If there is no I1, there is no I0 either.  */
    i0 = i1;

    /* We make I1 with the same INSN_UID as I2.  This gives it
the same DF_INSN_LUID for value tracking.  Our fake I1 will
never appear in the insn stream so giving it the same INSN_UID
as I2 will not cause a problem.  */

    i1 = gen_rtx_INSN (VOIDmode((void) 0, E_VOIDmode), NULLnullptr, i2, BLOCK_FOR_INSN (i2),
	 XVECEXP (PATTERN (i2), 0, 0)(((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[0]), INSN_LOCATION (i2),
	 -1, NULL_RTX(rtx) 0);
    INSN_UID (i1) = INSN_UID (i2);

    SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1))do_SUBST (&(PATTERN (i2)), ((((((PATTERN (i2))->u.fld[
0]).rt_rtvec))->elem[1])));
  }

/* Verify that I2 and maybe I1 and I0 can be combined into I3.  */
if (!can_combine_p (i2, i3, i0, i1, NULLnullptr, NULLnullptr, &i2dest, &i2src))
11
←
Assuming the condition is false→
  {
    if (dump_file && (dump_flags & TDF_DETAILS))
fprintf (dump_file, "Can't combine i2 into i3\n");
    undo_all ();
    return 0;
  }
if (i111.1
'i1' is null
 && !can_combine_p (i1, i3, i0, NULLnullptr, i2, NULLnullptr, &i1dest, &i1src))
  {
    if (dump_file && (dump_flags & TDF_DETAILS))
fprintf (dump_file, "Can't combine i1 into i3\n");
    undo_all ();
    return 0;
  }
if (i011.2
'i0' is null
 && !can_combine_p (i0, i3, NULLnullptr, NULLnullptr, i1, i2, &i0dest, &i0src))
  {
    if (dump_file && (dump_flags & TDF_DETAILS))
fprintf (dump_file, "Can't combine i0 into i3\n");
    undo_all ();
    return 0;
  }

/* With non-call exceptions we can end up trying to combine multiple
   insns with possible EH side effects.  Make sure we can combine
   that to a single insn which means there must be at most one insn
   in the combination with an EH side effect.  */
if (cfun(cfun + 0)->can_throw_non_call_exceptions)
12
←
Assuming field 'can_throw_non_call_exceptions' is 0→
13
←
Taking false branch→
  {
    if (find_reg_note (i3, REG_EH_REGION, NULL_RTX(rtx) 0)
 || find_reg_note (i2, REG_EH_REGION, NULL_RTX(rtx) 0)
 || (i1 && find_reg_note (i1, REG_EH_REGION, NULL_RTX(rtx) 0))
 || (i0 && find_reg_note (i0, REG_EH_REGION, NULL_RTX(rtx) 0)))
{
 has_non_call_exception = true;
 if (insn_could_throw_p (i3)
     + insn_could_throw_p (i2)
     + (i1 ? insn_could_throw_p (i1) : 0)
     + (i0 ? insn_could_throw_p (i0) : 0) > 1)
   {
     if (dump_file && (dump_flags & TDF_DETAILS))
fprintf (dump_file, "Can't combine multiple insns with EH "
	 "side-effects\n");
     undo_all ();
     return 0;
   }
}
  }

/* Record whether i2 and i3 are trivial moves.  */
i2_was_move = is_just_move (i2);
i3_was_move = is_just_move (i3);

/* Record whether I2DEST is used in I2SRC and similarly for the other
   cases.  Knowing this will help in register status updating below.  */
i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
i1dest_in_i1src = i113.1
'i1' is null
 && reg_overlap_mentioned_p (i1dest, i1src);
i2dest_in_i1src = i113.2
'i1' is null
 && reg_overlap_mentioned_p (i2dest, i1src);
i0dest_in_i0src = i013.3
'i0' is null
 && reg_overlap_mentioned_p (i0dest, i0src);
i1dest_in_i0src = i013.4
'i0' is null
 && reg_overlap_mentioned_p (i1dest, i0src);
i2dest_in_i0src = i013.5
'i0' is null
 && reg_overlap_mentioned_p (i2dest, i0src);
i2dest_killed = dead_or_set_p (i2, i2dest);
i1dest_killed = i113.6
'i1' is null
 && dead_or_set_p (i1, i1dest);
i0dest_killed = i013.7
'i0' is null
 && dead_or_set_p (i0, i0dest);

/* For the earlier insns, determine which of the subsequent ones they
   feed.  */
i1_feeds_i2_n = i113.8
'i1' is null
 && insn_a_feeds_b (i1, i2);
i0_feeds_i1_n = i013.9
'i0' is null
 && insn_a_feeds_b (i0, i1);
i0_feeds_i2_n = (i013.10
'i0' is null
 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
	  : (!reg_overlap_mentioned_p (i1dest, i0dest)
	     && reg_overlap_mentioned_p (i0dest, i2src))));

/* Ensure that I3's pattern can be the destination of combines.  */
if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
	  i113.11
'i1' is null
 && i2dest_in_i1src && !i1_feeds_i2_n,
	  i013.12
'i0' is null
 && ((i2dest_in_i0src && !i0_feeds_i2_n)
		 || (i1dest_in_i0src && !i0_feeds_i1_n)),
	  &i3dest_killed))
  {
    undo_all ();
    return 0;
  }

/* See if any of the insns is a MULT operation.  Unless one is, we will
   reject a combination that is, since it must be slower.  Be conservative
   here.  */
if (GET_CODE (i2src)((enum rtx_code) (i2src)->code) == MULT
14
←
Taking false branch→
15
←
Assuming field 'code' is not equal to MULT→
    || (i115.1
'i1' is equal to null
 != 0 && GET_CODE (i1src)((enum rtx_code) (i1src)->code) == MULT)
    || (i015.2
'i0' is equal to null
 != 0 && GET_CODE (i0src)((enum rtx_code) (i0src)->code) == MULT)
    || (GET_CODE (PATTERN (i3))((enum rtx_code) (PATTERN (i3))->code) == SET
 && GET_CODE (SET_SRC (PATTERN (i3)))((enum rtx_code) ((((PATTERN (i3))->u.fld[1]).rt_rtx))->
code) == MULT))
  have_mult = 1;

/* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
   We used to do this EXCEPT in one case: I3 has a post-inc in an
   output operand.  However, that exception can give rise to insns like
mov r3,(r3)+
   which is a famous insn on the PDP-11 where the value of r3 used as the
   source was model-dependent.  Avoid this sort of thing.  */

3033#if 0
if (!(GET_CODE (PATTERN (i3))((enum rtx_code) (PATTERN (i3))->code) == SET
&& REG_P (SET_SRC (PATTERN (i3)))(((enum rtx_code) ((((PATTERN (i3))->u.fld[1]).rt_rtx))->
code) == REG)
&& MEM_P (SET_DEST (PATTERN (i3)))(((enum rtx_code) ((((PATTERN (i3))->u.fld[0]).rt_rtx))->
code) == MEM)
&& (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0))((enum rtx_code) (((((((PATTERN (i3))->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx))->code) == POST_INC
   || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0))((enum rtx_code) (((((((PATTERN (i3))->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx))->code) == POST_DEC)))
  /* It's not the exception.  */
3040#endif
  if (AUTO_INC_DEC0)
16
←
Taking false branch→
    {
rtx link;
for (link = REG_NOTES (i3)(((i3)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
 if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == REG_INC
     && (reg_overlap_mentioned_p (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), PATTERN (i2))
  || (i1 != 0
      && reg_overlap_mentioned_p (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), PATTERN (i1)))))
   {
     undo_all ();
     return 0;
   }
    }

/* See if the SETs in I1 or I2 need to be kept around in the merged
   instruction: whenever the value set there is still needed past I3.
   For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.

   For the SET in I1, we have two cases: if I1 and I2 independently feed
   into I3, the set in I1 needs to be kept around unless I1DEST dies
   or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
   in I1 needs to be kept around unless I1DEST dies or is set in either
   I2 or I3.  The same considerations apply to I0.  */

added_sets_2 = !dead_or_set_p (i3, i2dest);
17
←
Assuming the condition is false→

if (i117.1
'i1' is null
)
18
←
Taking false branch→
  added_sets_1 = !(dead_or_set_p (i3, i1dest)
     || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
else
  added_sets_1 = 0;

if (i018.1
'i0' is null
)
19
←
Taking false branch→
  added_sets_0 =  !(dead_or_set_p (i3, i0dest)
      || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
      || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
	  && dead_or_set_p (i2, i0dest)));
else
  added_sets_0 = 0;

/* We are about to copy insns for the case where they need to be kept
   around.  Check that they can be copied in the merged instruction.  */

if (targetm.cannot_copy_insn_p
20
←
Assuming field 'cannot_copy_insn_p' is null→
    && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
  {
    undo_all ();
    return 0;
  }

/* We cannot safely duplicate volatile references in any case.  */

if ((added_sets_220.1
'added_sets_2' is 0
 && volatile_refs_p (PATTERN (i2)))
    || (added_sets_120.2
'added_sets_1' is 0
 && volatile_refs_p (PATTERN (i1)))
    || (added_sets_020.3
'added_sets_0' is 0
 && volatile_refs_p (PATTERN (i0))))
  {
    undo_all ();
    return 0;
  }

/* Count how many auto_inc expressions there were in the original insns;
   we need to have the same number in the resulting patterns.  */

if (i020.4
'i0' is null
)
21
←
Taking false branch→
  for_each_inc_dec (PATTERN (i0), count_auto_inc, &n_auto_inc);
if (i121.1
'i1' is null
)
22
←
Taking false branch→
  for_each_inc_dec (PATTERN (i1), count_auto_inc, &n_auto_inc);
for_each_inc_dec (PATTERN (i2), count_auto_inc, &n_auto_inc);
for_each_inc_dec (PATTERN (i3), count_auto_inc, &n_auto_inc);

/* If the set in I2 needs to be kept around, we must make a copy of
   PATTERN (I2), so that when we substitute I1SRC for I1DEST in
   PATTERN (I2), we are only substituting for the original I1DEST, not into
   an already-substituted copy.  This also prevents making self-referential
   rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
   I2DEST.  */

if (added_sets_222.1
'added_sets_2' is 0
)
23
←
Taking false branch→
  {
    if (GET_CODE (PATTERN (i2))((enum rtx_code) (PATTERN (i2))->code) == PARALLEL)
i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((i2dest
)), ((copy_rtx (i2src))) );
    else
i2pat = copy_rtx (PATTERN (i2));
  }

if (added_sets_123.1
'added_sets_1' is 0
)
24
←
Taking false branch→
  {
    if (GET_CODE (PATTERN (i1))((enum rtx_code) (PATTERN (i1))->code) == PARALLEL)
i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((i1dest
)), ((copy_rtx (i1src))) );
    else
i1pat = copy_rtx (PATTERN (i1));
  }

if (added_sets_024.1
'added_sets_0' is 0
)
25
←
Taking false branch→
  {
    if (GET_CODE (PATTERN (i0))((enum rtx_code) (PATTERN (i0))->code) == PARALLEL)
i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((i0dest
)), ((copy_rtx (i0src))) );
    else
i0pat = copy_rtx (PATTERN (i0));
  }

combine_merges++;

/* Substitute in the latest insn for the regs set by the earlier ones.  */

maxreg = max_reg_num ();

subst_insn = i3;

/* Many machines have insns that can both perform an
   arithmetic operation and set the condition code.  These operations will
   be represented as a PARALLEL with the first element of the vector
   being a COMPARE of an arithmetic operation with the constant zero.
   The second element of the vector will set some pseudo to the result
   of the same arithmetic operation.  If we simplify the COMPARE, we won't
   match such a pattern and so will generate an extra insn.   Here we test
   for this case, where both the comparison and the operation result are
   needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
   I2SRC.  Later we will make the PARALLEL that contains I2.  */

if (i125.1
'i1' is equal to null
 == 0 && added_sets_225.2
'added_sets_2' is 0
 && GET_CODE (PATTERN (i3))((enum rtx_code) (PATTERN (i3))->code) == SET
    && GET_CODE (SET_SRC (PATTERN (i3)))((enum rtx_code) ((((PATTERN (i3))->u.fld[1]).rt_rtx))->
code) == COMPARE
    && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))(((enum rtx_code) (((((((PATTERN (i3))->u.fld[1]).rt_rtx))
->u.fld[1]).rt_rtx))->code) == CONST_INT)
    && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0)((((((PATTERN (i3))->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx
), i2dest))
  {
    rtx newpat_dest;
    rtx *cc_use_loc = NULLnullptr;
    rtx_insn *cc_use_insn = NULLnullptr;
    rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1)((((((PATTERN (i3))->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx
);
    machine_mode compare_mode, orig_compare_mode;
    enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
    scalar_int_mode mode;

    newpat = PATTERN (i3);
    newpat_dest = SET_DEST (newpat)(((newpat)->u.fld[0]).rt_rtx);
    compare_mode = orig_compare_mode = GET_MODE (newpat_dest)((machine_mode) (newpat_dest)->mode);

    if (undobuf.other_insn == 0
 && (cc_use_loc = find_single_use (SET_DEST (newpat)(((newpat)->u.fld[0]).rt_rtx), i3,
			    &cc_use_insn)))
{
 compare_code = orig_compare_code = GET_CODE (*cc_use_loc)((enum rtx_code) (*cc_use_loc)->code);
 if (is_a <scalar_int_mode> (GET_MODE (i2dest)((machine_mode) (i2dest)->mode), &mode))
   compare_code = simplify_compare_const (compare_code, mode,
				   op0, &op1);
 target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
}

    /* Do the rest only if op1 is const0_rtx, which may be the
result of simplification.  */
    if (op1 == const0_rtx(const_int_rtx[64]))
{
 /* If a single use of the CC is found, prepare to modify it
    when SELECT_CC_MODE returns a new CC-class mode, or when
    the above simplify_compare_const() returned a new comparison
    operator.  undobuf.other_insn is assigned the CC use insn
    when modifying it.  */
 if (cc_use_loc)
   {
3202#ifdef SELECT_CC_MODE
     machine_mode new_mode
= SELECT_CC_MODE (compare_code, op0, op1)ix86_cc_mode ((compare_code), (op0), (op1));
     if (new_mode != orig_compare_mode
  && can_change_dest_mode (SET_DEST (newpat)(((newpat)->u.fld[0]).rt_rtx),
			   added_sets_2, new_mode))
{
  unsigned int regno = REGNO (newpat_dest)(rhs_regno(newpat_dest));
  compare_mode = new_mode;
  if (regno < FIRST_PSEUDO_REGISTER76)
    newpat_dest = gen_rtx_REG (compare_mode, regno);
  else
    {
      subst_mode (regno, compare_mode);
      newpat_dest = regno_reg_rtx[regno];
    }
}
3219#endif
     /* Cases for modifying the CC-using comparison.  */
     if (compare_code != orig_compare_code
  /* ??? Do we need to verify the zero rtx?  */
  && XEXP (*cc_use_loc, 1)(((*cc_use_loc)->u.fld[1]).rt_rtx) == const0_rtx(const_int_rtx[64]))
{
  /* Replace cc_use_loc with entire new RTX.  */
  SUBST (*cc_use_loc,do_SUBST (&(*cc_use_loc), (gen_rtx_fmt_ee_stat ((compare_code
), (((machine_mode) (*cc_use_loc)->mode)), (newpat_dest), (
(const_int_rtx[64])) )))
	 gen_rtx_fmt_ee (compare_code, GET_MODE (*cc_use_loc),do_SUBST (&(*cc_use_loc), (gen_rtx_fmt_ee_stat ((compare_code
), (((machine_mode) (*cc_use_loc)->mode)), (newpat_dest), (
(const_int_rtx[64])) )))
			 newpat_dest, const0_rtx))do_SUBST (&(*cc_use_loc), (gen_rtx_fmt_ee_stat ((compare_code
), (((machine_mode) (*cc_use_loc)->mode)), (newpat_dest), (
(const_int_rtx[64])) )));
  undobuf.other_insn = cc_use_insn;
}
     else if (compare_mode != orig_compare_mode)
{
  /* Just replace the CC reg with a new mode.  */
  SUBST (XEXP (*cc_use_loc, 0), newpat_dest)do_SUBST (&((((*cc_use_loc)->u.fld[0]).rt_rtx)), (newpat_dest
));
  undobuf.other_insn = cc_use_insn;
}
   }

 /* Now we modify the current newpat:
    First, SET_DEST(newpat) is updated if the CC mode has been
    altered. For targets without SELECT_CC_MODE, this should be
    optimized away.  */
 if (compare_mode != orig_compare_mode)
   SUBST (SET_DEST (newpat), newpat_dest)do_SUBST (&((((newpat)->u.fld[0]).rt_rtx)), (newpat_dest
));
 /* This is always done to propagate i2src into newpat.  */
 SUBST (SET_SRC (newpat),do_SUBST (&((((newpat)->u.fld[1]).rt_rtx)), (gen_rtx_fmt_ee_stat
 ((COMPARE), ((compare_mode)), ((op0)), ((op1)) )))
 gen_rtx_COMPARE (compare_mode, op0, op1))do_SUBST (&((((newpat)->u.fld[1]).rt_rtx)), (gen_rtx_fmt_ee_stat
 ((COMPARE), ((compare_mode)), ((op0)), ((op1)) )));
 /* Create new version of i2pat if needed; the below PARALLEL
    creation needs this to work correctly.  */
 if (! rtx_equal_p (i2src, op0))
   i2pat = gen_rtx_SET (i2dest, op0)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((i2dest
)), ((op0)) );
 i2_is_used = 1;
}
  }

if (i2_is_used25.3
'i2_is_used' is equal to 0
 == 0)
26
←
Taking true branch→
  {
    /* It is possible that the source of I2 or I1 may be performing
an unneeded operation, such as a ZERO_EXTEND of something
that is known to have the high part zero.  Handle that case
by letting subst look at the inner insns.

Another way to do this would be to have a function that tries
to simplify a single insn instead of merging two or more
insns.  We don't do this because of the potential of infinite
loops and because of the potential extra memory required.
However, doing it the way we are is a bit of a kludge and
doesn't catch all cases.

But only do this if -fexpensive-optimizations since it slows
things down and doesn't usually win.

This is not done in the COMPARE case above because the
unmodified I2PAT is used in the PARALLEL and so a pattern
with a modified I2SRC would not match.  */

    if (flag_expensive_optimizationsglobal_options.x_flag_expensive_optimizations)
27
←
Assuming field 'x_flag_expensive_optimizations' is 0→
28
←
Taking false branch→
{
 /* Pass pc_rtx so no substitutions are done, just
    simplifications.  */
 if (i1)
   {
     subst_low_luid = DF_INSN_LUID (i1)((((df->insns[(INSN_UID (i1))]))->luid));
     i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
   }

 subst_low_luid = DF_INSN_LUID (i2)((((df->insns[(INSN_UID (i2))]))->luid));
 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
}

    n_occurrences = 0;		/* `subst' counts here */
    subst_low_luid = DF_INSN_LUID (i2)((((df->insns[(INSN_UID (i2))]))->luid));

    /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
copy of I2SRC each time we substitute it, in order to avoid creating
self-referential RTL when we will be substituting I1SRC for I1DEST
later.  Likewise if I0 feeds into I2, either directly or indirectly
through I1, and I0DEST is in I0SRC.  */
    newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
      (i1_feeds_i2_n28.1
'i1_feeds_i2_n' is 0
 && i1dest_in_i1src)
      || ((i0_feeds_i2_n28.2
'i0_feeds_i2_n' is 0
 || (i0_feeds_i1_n28.3
'i0_feeds_i1_n' is 0
 && i1_feeds_i2_n))
	  && i0dest_in_i0src));
    substed_i2 = 1;

    /* Record whether I2's body now appears within I3's body.  */
    i2_is_used = n_occurrences;
  }

/* If we already got a failure, don't try to do more.  Otherwise, try to
   substitute I1 if we have it.  */

if (i128.4
'i1' is null
 && GET_CODE (newpat)((enum rtx_code) (newpat)->code) != CLOBBER)
  {
    /* Before we can do this substitution, we must redo the test done
above (see detailed comments there) that ensures I1DEST isn't
mentioned in any SETs in NEWPAT that are field assignments.  */
    if (!combinable_i3pat (NULLnullptr, &newpat, i1dest, NULL_RTX(rtx) 0, NULL_RTX(rtx) 0,
	     0, 0, 0))
{
 undo_all ();
 return 0;
}

    n_occurrences = 0;
    subst_low_luid = DF_INSN_LUID (i1)((((df->insns[(INSN_UID (i1))]))->luid));

    /* If the following substitution will modify I1SRC, make a copy of it
for the case where it is substituted for I1DEST in I2PAT later.  */
    if (added_sets_2 && i1_feeds_i2_n)
i1src_copy = copy_rtx (i1src);

    /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
copy of I1SRC each time we substitute it, in order to avoid creating
self-referential RTL when we will be substituting I0SRC for I0DEST
later.  */
    newpat = subst (newpat, i1dest, i1src, 0, 0,
      i0_feeds_i1_n && i0dest_in_i0src);
    substed_i1 = 1;

    /* Record whether I1's body now appears within I3's body.  */
    i1_is_used = n_occurrences;
  }

/* Likewise for I0 if we have it.  */

if (i028.5
'i0' is null
 && GET_CODE (newpat)((enum rtx_code) (newpat)->code) != CLOBBER)
  {
    if (!combinable_i3pat (NULLnullptr, &newpat, i0dest, NULL_RTX(rtx) 0, NULL_RTX(rtx) 0,
	     0, 0, 0))
{
 undo_all ();
 return 0;
}

    /* If the following substitution will modify I0SRC, make a copy of it
for the case where it is substituted for I0DEST in I1PAT later.  */
    if (added_sets_1 && i0_feeds_i1_n)
i0src_copy = copy_rtx (i0src);
    /* And a copy for I0DEST in I2PAT substitution.  */
    if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
	   || (i0_feeds_i2_n)))
i0src_copy2 = copy_rtx (i0src);

    n_occurrences = 0;
    subst_low_luid = DF_INSN_LUID (i0)((((df->insns[(INSN_UID (i0))]))->luid));
    newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
    substed_i0 = 1;
  }

if (n_auto_inc)
29
←
Assuming 'n_auto_inc' is 0→
  {
    int new_n_auto_inc = 0;
    for_each_inc_dec (newpat, count_auto_inc, &new_n_auto_inc);

    if (n_auto_inc != new_n_auto_inc)
{
 if (dump_file && (dump_flags & TDF_DETAILS))
   fprintf (dump_file, "Number of auto_inc expressions changed\n");
 undo_all ();
 return 0;
}
  }

/* Fail if an autoincrement side-effect has been duplicated.  Be careful
   to count all the ways that I2SRC and I1SRC can be used.  */
if ((FIND_REG_INC_NOTE (i2, NULL_RTX)0 != 0
30
←
Taking false branch→
     && i2_is_used + added_sets_2 > 1)
    || (i130.2
'i1' is equal to null
 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX)0 != 0
 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
     > 1))
    || (i030.3
'i0' is equal to null
 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX)0 != 0
 && (n_occurrences + added_sets_0
     + (added_sets_1 && i0_feeds_i1_n)
     + (added_sets_2 && i0_feeds_i2_n)
     > 1))
    /* Fail if we tried to make a new register.  */
    || max_reg_num () != maxreg
31
←
Assuming the condition is false→
    /* Fail if we couldn't do something and have a CLOBBER.  */
    || GET_CODE (newpat)((enum rtx_code) (newpat)->code) == CLOBBER
32
←
Assuming field 'code' is not equal to CLOBBER→
    /* Fail if this new pattern is a MULT and we didn't have one before
at the outer level.  */
    || (GET_CODE (newpat)((enum rtx_code) (newpat)->code) == SET && GET_CODE (SET_SRC (newpat))((enum rtx_code) ((((newpat)->u.fld[1]).rt_rtx))->code) == MULT
33
←
Assuming field 'code' is not equal to SET→
 && ! have_mult))
  {
    undo_all ();
    return 0;
  }

/* If the actions of the earlier insns must be kept
   in addition to substituting them into the latest one,
   we must make a new PARALLEL for the latest insn
   to hold additional the SETs.  */

if (added_sets_033.1
'added_sets_0' is 0
 || added_sets_133.2
'added_sets_1' is 0
 || added_sets_233.3
'added_sets_2' is 0
)
34
←
Taking false branch→
  {
    int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
    combine_extras++;

    if (GET_CODE (newpat)((enum rtx_code) (newpat)->code) == PARALLEL)
{
 rtvec old = XVEC (newpat, 0)(((newpat)->u.fld[0]).rt_rtvec);
 total_sets = XVECLEN (newpat, 0)(((((newpat)->u.fld[0]).rt_rtvec))->num_elem) + extra_sets;
 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(rtvec_alloc (total_sets))) );
 memcpy (XVEC (newpat, 0)(((newpat)->u.fld[0]).rt_rtvec)->elem, &old->elem[0],
  sizeof (old->elem[0]) * old->num_elem);
}
    else
{
 rtx old = newpat;
 total_sets = 1 + extra_sets;
 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(rtvec_alloc (total_sets))) );
 XVECEXP (newpat, 0, 0)(((((newpat)->u.fld[0]).rt_rtvec))->elem[0]) = old;
}

    if (added_sets_0)
XVECEXP (newpat, 0, --total_sets)(((((newpat)->u.fld[0]).rt_rtvec))->elem[--total_sets]) = i0pat;

    if (added_sets_1)
{
 rtx t = i1pat;
 if (i0_feeds_i1_n)
   t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);

 XVECEXP (newpat, 0, --total_sets)(((((newpat)->u.fld[0]).rt_rtvec))->elem[--total_sets]) = t;
}
    if (added_sets_2)
{
 rtx t = i2pat;
 if (i1_feeds_i2_n)
   t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
       i0_feeds_i1_n && i0dest_in_i0src);
 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
   t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);

 XVECEXP (newpat, 0, --total_sets)(((((newpat)->u.fld[0]).rt_rtvec))->elem[--total_sets]) = t;
}
  }

validate_replacement:

/* Note which hard regs this insn has as inputs.  */
mark_used_regs_combine (newpat);

/* If recog_for_combine fails, it strips existing clobbers.  If we'll
   consider splitting this pattern, we might need these clobbers.  */
if (i134.1
'i1' is null
 && GET_CODE (newpat)((enum rtx_code) (newpat)->code) == PARALLEL
    && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1))((enum rtx_code) ((((((newpat)->u.fld[0]).rt_rtvec))->elem
[(((((newpat)->u.fld[0]).rt_rtvec))->num_elem) - 1]))->
code) == CLOBBER)
  {
    int len = XVECLEN (newpat, 0)(((((newpat)->u.fld[0]).rt_rtvec))->num_elem);

    newpat_vec_with_clobbers = rtvec_alloc (len);
    for (i = 0; i < len; i++)
RTVEC_ELT (newpat_vec_with_clobbers, i)((newpat_vec_with_clobbers)->elem[i]) = XVECEXP (newpat, 0, i)(((((newpat)->u.fld[0]).rt_rtvec))->elem[i]);
  }

/* We have recognized nothing yet.  */
insn_code_number = -1;

/* See if this is a PARALLEL of two SETs where one SET's destination is
   a register that is unused and this isn't marked as an instruction that
   might trap in an EH region.  In that case, we just need the other SET.
   We prefer this over the PARALLEL.

   This can occur when simplifying a divmod insn.  We *must* test for this
   case here because the code below that splits two independent SETs doesn't
   handle this case correctly when it updates the register status.

   It's pointless doing this if we originally had two sets, one from
   i3, and one from i2.  Combining then splitting the parallel results
   in the original i2 again plus an invalid insn (which we delete).
   The net effect is only to move instructions around, which makes
   debug info less accurate.

   If the remaining SET came from I2 its destination should not be used
   between I2 and I3.  See PR82024.  */

if (!(added_sets_234.2
'added_sets_2' is 0
 && i1 == 0)
    && is_parallel_of_n_reg_sets (newpat, 2)
    && asm_noperands (newpat) < 0)
  {
    rtx set0 = XVECEXP (newpat, 0, 0)(((((newpat)->u.fld[0]).rt_rtvec))->elem[0]);
    rtx set1 = XVECEXP (newpat, 0, 1)(((((newpat)->u.fld[0]).rt_rtvec))->elem[1]);
    rtx oldpat = newpat;

    if (((REG_P (SET_DEST (set1))(((enum rtx_code) ((((set1)->u.fld[0]).rt_rtx))->code) ==
 REG)
   && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)(((set1)->u.fld[0]).rt_rtx)))
  || (GET_CODE (SET_DEST (set1))((enum rtx_code) ((((set1)->u.fld[0]).rt_rtx))->code) == SUBREG
      && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1))((((((set1)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))))
 && insn_nothrow_p (i3)
 && !side_effects_p (SET_SRC (set1)(((set1)->u.fld[1]).rt_rtx)))
{
 newpat = set0;
 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
}

    else if (((REG_P (SET_DEST (set0))(((enum rtx_code) ((((set0)->u.fld[0]).rt_rtx))->code) ==
 REG)
 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)(((set0)->u.fld[0]).rt_rtx)))
|| (GET_CODE (SET_DEST (set0))((enum rtx_code) ((((set0)->u.fld[0]).rt_rtx))->code) == SUBREG
    && find_reg_note (i3, REG_UNUSED,
		      SUBREG_REG (SET_DEST (set0))((((((set0)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))))
      && insn_nothrow_p (i3)
      && !side_effects_p (SET_SRC (set0)(((set0)->u.fld[1]).rt_rtx)))
{
 rtx dest = SET_DEST (set1)(((set1)->u.fld[0]).rt_rtx);
 if (GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG)
   dest = SUBREG_REG (dest)(((dest)->u.fld[0]).rt_rtx);
 if (!reg_used_between_p (dest, i2, i3))
   {
     newpat = set1;
     insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);

     if (insn_code_number >= 0)
changed_i3_dest = 1;
   }
}

    if (insn_code_number < 0)
newpat = oldpat;
  }

/* Is the result of combination a valid instruction?  */
if (insn_code_number34.3
'insn_code_number' is < 0
 < 0)
35
←
Taking true branch→
  insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
36
←
Calling 'recog_for_combine'→
53
←
Returning from 'recog_for_combine'→

/* If we were combining three insns and the result is a simple SET
   with no ASM_OPERANDS that wasn't recognized, try to split it into two
   insns.  There are two ways to do this.  It can be split using a
   machine-specific method (like when you have an addition of a large
   constant) or by combine in the function find_split_point.  */

if (i153.1
'i1' is null
 && insn_code_number < 0 && GET_CODE (newpat)((enum rtx_code) (newpat)->code) == SET
    && asm_noperands (newpat) < 0)
  {
    rtx parallel, *split;
    rtx_insn *m_split_insn;

    /* See if the MD file can split NEWPAT.  If it can't, see if letting it
use I2DEST as a scratch register will help.  In the latter case,
convert I2DEST to the mode of the source of NEWPAT if we can.  */

    m_split_insn = combine_split_insns (newpat, i3);

    /* We can only use I2DEST as a scratch reg if it doesn't overlap any
inputs of NEWPAT.  */

    /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
possible to try that as a scratch reg.  This would require adding
more code to make it work though.  */

    if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
{
 machine_mode new_mode = GET_MODE (SET_DEST (newpat))((machine_mode) ((((newpat)->u.fld[0]).rt_rtx))->mode);

 /* ??? Reusing i2dest without resetting the reg_stat entry for it
    (temporarily, until we are committed to this instruction
    combination) does not work: for example, any call to nonzero_bits
    on the register (from a splitter in the MD file, for example)
    will get the old information, which is invalid.

    Since nowadays we can create registers during combine just fine,
    we should just create a new one here, not reuse i2dest.  */

 /* First try to split using the original register as a
    scratch register.  */
 parallel = gen_rtx_PARALLEL (VOIDmode,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, newpat, gen_rtx_fmt_e_stat ((CLOBBER), ((((void
) 0, E_VOIDmode))), ((i2dest)) )))) )
		       gen_rtvec (2, newpat,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, newpat, gen_rtx_fmt_e_stat ((CLOBBER), ((((void
) 0, E_VOIDmode))), ((i2dest)) )))) )
				  gen_rtx_CLOBBER (VOIDmode,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, newpat, gen_rtx_fmt_e_stat ((CLOBBER), ((((void
) 0, E_VOIDmode))), ((i2dest)) )))) )
						   i2dest)))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, newpat, gen_rtx_fmt_e_stat ((CLOBBER), ((((void
) 0, E_VOIDmode))), ((i2dest)) )))) );
 m_split_insn = combine_split_insns (parallel, i3);

 /* If that didn't work, try changing the mode of I2DEST if
    we can.  */
 if (m_split_insn == 0
     && new_mode != GET_MODE (i2dest)((machine_mode) (i2dest)->mode)
     && new_mode != VOIDmode((void) 0, E_VOIDmode)
     && can_change_dest_mode (i2dest, added_sets_2, new_mode))
   {
     machine_mode old_mode = GET_MODE (i2dest)((machine_mode) (i2dest)->mode);
     rtx ni2dest;

     if (REGNO (i2dest)(rhs_regno(i2dest)) < FIRST_PSEUDO_REGISTER76)
ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest)(rhs_regno(i2dest)));
     else
{
  subst_mode (REGNO (i2dest)(rhs_regno(i2dest)), new_mode);
  ni2dest = regno_reg_rtx[REGNO (i2dest)(rhs_regno(i2dest))];
}

     parallel = (gen_rtx_PARALLELgen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, newpat, gen_rtx_fmt_e_stat ((CLOBBER), ((((void
) 0, E_VOIDmode))), ((ni2dest)) )))) )
	  (VOIDmode,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, newpat, gen_rtx_fmt_e_stat ((CLOBBER), ((((void
) 0, E_VOIDmode))), ((ni2dest)) )))) )
	   gen_rtvec (2, newpat,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, newpat, gen_rtx_fmt_e_stat ((CLOBBER), ((((void
) 0, E_VOIDmode))), ((ni2dest)) )))) )
		      gen_rtx_CLOBBER (VOIDmode,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, newpat, gen_rtx_fmt_e_stat ((CLOBBER), ((((void
) 0, E_VOIDmode))), ((ni2dest)) )))) )
				       ni2dest)))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, newpat, gen_rtx_fmt_e_stat ((CLOBBER), ((((void
) 0, E_VOIDmode))), ((ni2dest)) )))) ));
     m_split_insn = combine_split_insns (parallel, i3);

     if (m_split_insn == 0
  && REGNO (i2dest)(rhs_regno(i2dest)) >= FIRST_PSEUDO_REGISTER76)
{
  struct undo *buf;

  adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)(rhs_regno(i2dest))], old_mode);
  buf = undobuf.undos;
  undobuf.undos = buf->next;
  buf->next = undobuf.frees;
  undobuf.frees = buf;
}
   }

 i2scratch = m_split_insn != 0;
}

    /* If recog_for_combine has discarded clobbers, try to use them
again for the split.  */
    if (m_split_insn == 0 && newpat_vec_with_clobbers)
{
 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers)gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(newpat_vec_with_clobbers)) );
 m_split_insn = combine_split_insns (parallel, i3);
}

    if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX(rtx) 0)
{
 rtx m_split_pat = PATTERN (m_split_insn);
 insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes);
 if (insn_code_number >= 0)
   newpat = m_split_pat;
}
    else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX(rtx) 0
      && (next_nonnote_nondebug_insn (i2) == i3
   || !modified_between_p (PATTERN (m_split_insn), i2, i3)))
{
 rtx i2set, i3set;
 rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
 newi2pat = PATTERN (m_split_insn);

 i3set = single_set (NEXT_INSN (m_split_insn));
 i2set = single_set (m_split_insn);

 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);

 /* If I2 or I3 has multiple SETs, we won't know how to track
    register status, so don't use these insns.  If I2's destination
    is used between I2 and I3, we also can't use these insns.  */

 if (i2_code_number >= 0 && i2set && i3set
     && (next_nonnote_nondebug_insn (i2) == i3
  || ! reg_used_between_p (SET_DEST (i2set)(((i2set)->u.fld[0]).rt_rtx), i2, i3)))
   insn_code_number = recog_for_combine (&newi3pat, i3,
				  &new_i3_notes);
 if (insn_code_number >= 0)
   newpat = newi3pat;

 /* It is possible that both insns now set the destination of I3.
    If so, we must show an extra use of it.  */

 if (insn_code_number >= 0)
   {
     rtx new_i3_dest = SET_DEST (i3set)(((i3set)->u.fld[0]).rt_rtx);
     rtx new_i2_dest = SET_DEST (i2set)(((i2set)->u.fld[0]).rt_rtx);

     while (GET_CODE (new_i3_dest)((enum rtx_code) (new_i3_dest)->code) == ZERO_EXTRACT
     || GET_CODE (new_i3_dest)((enum rtx_code) (new_i3_dest)->code) == STRICT_LOW_PART
     || GET_CODE (new_i3_dest)((enum rtx_code) (new_i3_dest)->code) == SUBREG)
new_i3_dest = XEXP (new_i3_dest, 0)(((new_i3_dest)->u.fld[0]).rt_rtx);

     while (GET_CODE (new_i2_dest)((enum rtx_code) (new_i2_dest)->code) == ZERO_EXTRACT
     || GET_CODE (new_i2_dest)((enum rtx_code) (new_i2_dest)->code) == STRICT_LOW_PART
     || GET_CODE (new_i2_dest)((enum rtx_code) (new_i2_dest)->code) == SUBREG)
new_i2_dest = XEXP (new_i2_dest, 0)(((new_i2_dest)->u.fld[0]).rt_rtx);

     if (REG_P (new_i3_dest)(((enum rtx_code) (new_i3_dest)->code) == REG)
  && REG_P (new_i2_dest)(((enum rtx_code) (new_i2_dest)->code) == REG)
  && REGNO (new_i3_dest)(rhs_regno(new_i3_dest)) == REGNO (new_i2_dest)(rhs_regno(new_i2_dest))
  && REGNO (new_i2_dest)(rhs_regno(new_i2_dest)) < reg_n_sets_max)
INC_REG_N_SETS (REGNO (new_i2_dest), 1)(regstat_n_sets_and_refs[(rhs_regno(new_i2_dest))].sets += 1);
   }
}

    /* If we can split it and use I2DEST, go ahead and see if that
helps things be recognized.  Verify that none of the registers
are set between I2 and I3.  */
    if (insn_code_number < 0
        && (split = find_split_point (&newpat, i3, false)) != 0
 /* We need I2DEST in the proper mode.  If it is a hard register
    or the only use of a pseudo, we can change its mode.
    Make sure we don't change a hard register to have a mode that
    isn't valid for it, or change the number of registers.  */
 && (GET_MODE (*split)((machine_mode) (*split)->mode) == GET_MODE (i2dest)((machine_mode) (i2dest)->mode)
     || GET_MODE (*split)((machine_mode) (*split)->mode) == VOIDmode((void) 0, E_VOIDmode)
     || can_change_dest_mode (i2dest, added_sets_2,
		       GET_MODE (*split)((machine_mode) (*split)->mode)))
 && (next_nonnote_nondebug_insn (i2) == i3
     || !modified_between_p (*split, i2, i3))
 /* We can't overwrite I2DEST if its value is still used by
    NEWPAT.  */
 && ! reg_referenced_p (i2dest, newpat)
 /* We should not split a possibly trapping part when we
    care about non-call EH and have REG_EH_REGION notes
    to distribute.  */
 && ! (cfun(cfun + 0)->can_throw_non_call_exceptions
&& has_non_call_exception
&& may_trap_p (*split)))
{
 rtx newdest = i2dest;
 enum rtx_code split_code = GET_CODE (*split)((enum rtx_code) (*split)->code);
 machine_mode split_mode = GET_MODE (*split)((machine_mode) (*split)->mode);
 bool subst_done = false;
 newi2pat = NULL_RTX(rtx) 0;

 i2scratch = true;

 /* *SPLIT may be part of I2SRC, so make sure we have the
    original expression around for later debug processing.
    We should not need I2SRC any more in other cases.  */
 if (MAY_HAVE_DEBUG_BIND_INSNSglobal_options.x_flag_var_tracking_assignments)
   i2src = copy_rtx (i2src);
 else
   i2src = NULLnullptr;

 /* Get NEWDEST as a register in the proper mode.  We have already
    validated that we can do this.  */
 if (GET_MODE (i2dest)((machine_mode) (i2dest)->mode) != split_mode && split_mode != VOIDmode((void) 0, E_VOIDmode))
   {
     if (REGNO (i2dest)(rhs_regno(i2dest)) < FIRST_PSEUDO_REGISTER76)
newdest = gen_rtx_REG (split_mode, REGNO (i2dest)(rhs_regno(i2dest)));
     else
{
  subst_mode (REGNO (i2dest)(rhs_regno(i2dest)), split_mode);
  newdest = regno_reg_rtx[REGNO (i2dest)(rhs_regno(i2dest))];
}
   }

 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
    an ASHIFT.  This can occur if it was inside a PLUS and hence
    appeared to be a memory address.  This is a kludge.  */
 if (split_code == MULT
     && CONST_INT_P (XEXP (*split, 1))(((enum rtx_code) ((((*split)->u.fld[1]).rt_rtx))->code
) == CONST_INT)
     && INTVAL (XEXP (*split, 1))(((((*split)->u.fld[1]).rt_rtx))->u.hwint[0]) > 0
     && (i = exact_log2 (UINTVAL (XEXP (*split, 1))((unsigned long) (((((*split)->u.fld[1]).rt_rtx))->u.hwint
[0])))) >= 0)
   {
     rtx i_rtx = gen_int_shift_amount (split_mode, i);
     SUBST (*split, gen_rtx_ASHIFT (split_mode,do_SUBST (&(*split), (gen_rtx_fmt_ee_stat ((ASHIFT), ((split_mode
)), (((((*split)->u.fld[0]).rt_rtx))), ((i_rtx)) )))
			     XEXP (*split, 0), i_rtx))do_SUBST (&(*split), (gen_rtx_fmt_ee_stat ((ASHIFT), ((split_mode
)), (((((*split)->u.fld[0]).rt_rtx))), ((i_rtx)) )));
     /* Update split_code because we may not have a multiply
 anymore.  */
     split_code = GET_CODE (*split)((enum rtx_code) (*split)->code);
   }

 /* Similarly for (plus (mult FOO (const_int pow2))).  */
 if (split_code == PLUS
     && GET_CODE (XEXP (*split, 0))((enum rtx_code) ((((*split)->u.fld[0]).rt_rtx))->code) == MULT
     && CONST_INT_P (XEXP (XEXP (*split, 0), 1))(((enum rtx_code) (((((((*split)->u.fld[0]).rt_rtx))->u
.fld[1]).rt_rtx))->code) == CONST_INT)
     && INTVAL (XEXP (XEXP (*split, 0), 1))((((((((*split)->u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx))
->u.hwint[0]) > 0
     && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1))((unsigned long) ((((((((*split)->u.fld[0]).rt_rtx))->u
.fld[1]).rt_rtx))->u.hwint[0])))) >= 0)
   {
     rtx nsplit = XEXP (*split, 0)(((*split)->u.fld[0]).rt_rtx);
     rtx i_rtx = gen_int_shift_amount (GET_MODE (nsplit)((machine_mode) (nsplit)->mode), i);
     SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit),do_SUBST (&((((*split)->u.fld[0]).rt_rtx)), (gen_rtx_fmt_ee_stat
 ((ASHIFT), ((((machine_mode) (nsplit)->mode))), (((((nsplit
)->u.fld[0]).rt_rtx))), ((i_rtx)) )))
				       XEXP (nsplit, 0),do_SUBST (&((((*split)->u.fld[0]).rt_rtx)), (gen_rtx_fmt_ee_stat
 ((ASHIFT), ((((machine_mode) (nsplit)->mode))), (((((nsplit
)->u.fld[0]).rt_rtx))), ((i_rtx)) )))
				       i_rtx))do_SUBST (&((((*split)->u.fld[0]).rt_rtx)), (gen_rtx_fmt_ee_stat
 ((ASHIFT), ((((machine_mode) (nsplit)->mode))), (((((nsplit
)->u.fld[0]).rt_rtx))), ((i_rtx)) )));
     /* Update split_code because we may not have a multiply
 anymore.  */
     split_code = GET_CODE (*split)((enum rtx_code) (*split)->code);
   }

3785#ifdef INSN_SCHEDULING
 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
    be written as a ZERO_EXTEND.  */
 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split))(((enum rtx_code) ((((*split)->u.fld[0]).rt_rtx))->code
) == MEM))
   {
     /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
 what it really is.  */
     if (load_extend_op (GET_MODE (SUBREG_REG (*split))((machine_mode) ((((*split)->u.fld[0]).rt_rtx))->mode))
  == SIGN_EXTEND)
SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,do_SUBST (&(*split), (gen_rtx_fmt_e_stat ((SIGN_EXTEND), (
(split_mode)), (((((*split)->u.fld[0]).rt_rtx))) )))
				    SUBREG_REG (*split)))do_SUBST (&(*split), (gen_rtx_fmt_e_stat ((SIGN_EXTEND), (
(split_mode)), (((((*split)->u.fld[0]).rt_rtx))) )));
     else
SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,do_SUBST (&(*split), (gen_rtx_fmt_e_stat ((ZERO_EXTEND), (
(split_mode)), (((((*split)->u.fld[0]).rt_rtx))) )))
				    SUBREG_REG (*split)))do_SUBST (&(*split), (gen_rtx_fmt_e_stat ((ZERO_EXTEND), (
(split_mode)), (((((*split)->u.fld[0]).rt_rtx))) )));
   }
3800#endif

 /* Attempt to split binary operators using arithmetic identities.  */
 if (BINARY_P (SET_SRC (newpat))(((rtx_class[(int) (((enum rtx_code) ((((newpat)->u.fld[1]
).rt_rtx))->code))]) & (~3)) == (RTX_COMPARE & (~3
)))
     && split_mode == GET_MODE (SET_SRC (newpat))((machine_mode) ((((newpat)->u.fld[1]).rt_rtx))->mode)
     && ! side_effects_p (SET_SRC (newpat)(((newpat)->u.fld[1]).rt_rtx)))
   {
     rtx setsrc = SET_SRC (newpat)(((newpat)->u.fld[1]).rt_rtx);
     machine_mode mode = GET_MODE (setsrc)((machine_mode) (setsrc)->mode);
     enum rtx_code code = GET_CODE (setsrc)((enum rtx_code) (setsrc)->code);
     rtx src_op0 = XEXP (setsrc, 0)(((setsrc)->u.fld[0]).rt_rtx);
     rtx src_op1 = XEXP (setsrc, 1)(((setsrc)->u.fld[1]).rt_rtx);

     /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
     if (rtx_equal_p (src_op0, src_op1))
{
  newi2pat = gen_rtx_SET (newdest, src_op0)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((newdest
)), ((src_op0)) );
  SUBST (XEXP (setsrc, 0), newdest)do_SUBST (&((((setsrc)->u.fld[0]).rt_rtx)), (newdest));
  SUBST (XEXP (setsrc, 1), newdest)do_SUBST (&((((setsrc)->u.fld[1]).rt_rtx)), (newdest));
  subst_done = true;
}
     /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
     else if ((code == PLUS || code == MULT)
       && GET_CODE (src_op0)((enum rtx_code) (src_op0)->code) == code
       && GET_CODE (XEXP (src_op0, 0))((enum rtx_code) ((((src_op0)->u.fld[0]).rt_rtx))->code
) == code
       && (INTEGRAL_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_INT || ((enum mode_class
) mode_class[mode]) == MODE_PARTIAL_INT || ((enum mode_class)
 mode_class[mode]) == MODE_COMPLEX_INT || ((enum mode_class) mode_class
[mode]) == MODE_VECTOR_BOOL || ((enum mode_class) mode_class[
mode]) == MODE_VECTOR_INT)
	   || (FLOAT_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_FLOAT || ((enum
 mode_class) mode_class[mode]) == MODE_DECIMAL_FLOAT || ((enum
 mode_class) mode_class[mode]) == MODE_COMPLEX_FLOAT || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_FLOAT)
	       && flag_unsafe_math_optimizationsglobal_options.x_flag_unsafe_math_optimizations)))
{
  rtx p = XEXP (XEXP (src_op0, 0), 0)((((((src_op0)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx);
  rtx q = XEXP (XEXP (src_op0, 0), 1)((((((src_op0)->u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx);
  rtx r = XEXP (src_op0, 1)(((src_op0)->u.fld[1]).rt_rtx);
  rtx s = src_op1;

  /* Split both "((X op Y) op X) op Y" and
     "((X op Y) op Y) op X" as "T op T" where T is
     "X op Y".  */
  if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
       || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
    {
      newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((newdest
)), (((((src_op0)->u.fld[0]).rt_rtx))) );
      SUBST (XEXP (setsrc, 0), newdest)do_SUBST (&((((setsrc)->u.fld[0]).rt_rtx)), (newdest));
      SUBST (XEXP (setsrc, 1), newdest)do_SUBST (&((((setsrc)->u.fld[1]).rt_rtx)), (newdest));
      subst_done = true;
    }
  /* Split "((X op X) op Y) op Y)" as "T op T" where
     T is "X op Y".  */
  else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
    {
      rtx tmp = simplify_gen_binary (code, mode, p, r);
      newi2pat = gen_rtx_SET (newdest, tmp)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((newdest
)), ((tmp)) );
      SUBST (XEXP (setsrc, 0), newdest)do_SUBST (&((((setsrc)->u.fld[0]).rt_rtx)), (newdest));
      SUBST (XEXP (setsrc, 1), newdest)do_SUBST (&((((setsrc)->u.fld[1]).rt_rtx)), (newdest));
      subst_done = true;
    }
}
   }

 if (!subst_done)
   {
     newi2pat = gen_rtx_SET (newdest, *split)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((newdest
)), ((*split)) );
     SUBST (*split, newdest)do_SUBST (&(*split), (newdest));
   }

 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);

 /* recog_for_combine might have added CLOBBERs to newi2pat.
    Make sure NEWPAT does not depend on the clobbered regs.  */
 if (GET_CODE (newi2pat)((enum rtx_code) (newi2pat)->code) == PARALLEL)
   for (i = XVECLEN (newi2pat, 0)(((((newi2pat)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
     if (GET_CODE (XVECEXP (newi2pat, 0, i))((enum rtx_code) ((((((newi2pat)->u.fld[0]).rt_rtvec))->
elem[i]))->code) == CLOBBER)
{
  rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0)((((((((newi2pat)->u.fld[0]).rt_rtvec))->elem[i]))->
u.fld[0]).rt_rtx);
  if (reg_overlap_mentioned_p (reg, newpat))
    {
      undo_all ();
      return 0;
    }
}

 /* If the split point was a MULT and we didn't have one before,
    don't use one now.  */
 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
}
  }

/* Check for a case where we loaded from memory in a narrow mode and
   then sign extended it, but we need both registers.  In that case,
   we have a PARALLEL with both loads from the same memory location.
   We can split this into a load from memory followed by a register-register
   copy.  This saves at least one insn, more if register allocation can
   eliminate the copy.

   We cannot do this if the destination of the first assignment is a
   condition code register.  We eliminate this case by making sure
   the SET_DEST and SET_SRC have the same mode.

   We cannot do this if the destination of the second assignment is
   a register that we have already assumed is zero-extended.  Similarly
   for a SUBREG of such a register.  */

else if (i153.2
'i1' is null
 && insn_code_number < 0 && asm_noperands (newpat) < 0
  && GET_CODE (newpat)((enum rtx_code) (newpat)->code) == PARALLEL
  && XVECLEN (newpat, 0)(((((newpat)->u.fld[0]).rt_rtvec))->num_elem) == 2
  && GET_CODE (XVECEXP (newpat, 0, 0))((enum rtx_code) ((((((newpat)->u.fld[0]).rt_rtvec))->elem
[0]))->code) == SET
  && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0)))((enum rtx_code) (((((((((newpat)->u.fld[0]).rt_rtvec))->
elem[0]))->u.fld[1]).rt_rtx))->code) == SIGN_EXTEND
  && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))((machine_mode) (((((((((newpat)->u.fld[0]).rt_rtvec))->
elem[0]))->u.fld[0]).rt_rtx))->mode)
      == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))((machine_mode) (((((((((newpat)->u.fld[0]).rt_rtvec))->
elem[0]))->u.fld[1]).rt_rtx))->mode))
  && GET_CODE (XVECEXP (newpat, 0, 1))((enum rtx_code) ((((((newpat)->u.fld[0]).rt_rtvec))->elem
[1]))->code) == SET
  && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1))((((((((newpat)->u.fld[0]).rt_rtvec))->elem[1]))->u.
fld[1]).rt_rtx),
	   XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)(((((((((((newpat)->u.fld[0]).rt_rtvec))->elem[0]))->
u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx))
  && !modified_between_p (SET_SRC (XVECEXP (newpat, 0, 1))((((((((newpat)->u.fld[0]).rt_rtvec))->elem[1]))->u.
fld[1]).rt_rtx), i2, i3)
  && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1)))((enum rtx_code) (((((((((newpat)->u.fld[0]).rt_rtvec))->
elem[1]))->u.fld[0]).rt_rtx))->code) != ZERO_EXTRACT
  && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1)))((enum rtx_code) (((((((((newpat)->u.fld[0]).rt_rtvec))->
elem[1]))->u.fld[0]).rt_rtx))->code) != STRICT_LOW_PART
  && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1))((((((((newpat)->u.fld[0]).rt_rtvec))->elem[1]))->u.
fld[0]).rt_rtx),
 (REG_P (temp_expr)(((enum rtx_code) (temp_expr)->code) == REG)
  && reg_stat[REGNO (temp_expr)(rhs_regno(temp_expr))].nonzero_bits != 0
  && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),(!maybe_le (((8) * (((global_options.x_ix86_isa_flags & (
1UL << 1)) != 0) ? 8 : 4)), GET_MODE_PRECISION (((machine_mode
) (temp_expr)->mode))))
	       BITS_PER_WORD)(!maybe_le (((8) * (((global_options.x_ix86_isa_flags & (
1UL << 1)) != 0) ? 8 : 4)), GET_MODE_PRECISION (((machine_mode
) (temp_expr)->mode))))
  && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),(!maybe_le ((8 * 4), GET_MODE_PRECISION (((machine_mode) (temp_expr
)->mode))))
	       HOST_BITS_PER_INT)(!maybe_le ((8 * 4), GET_MODE_PRECISION (((machine_mode) (temp_expr
)->mode))))
  && (reg_stat[REGNO (temp_expr)(rhs_regno(temp_expr))].nonzero_bits
      != GET_MODE_MASK (word_mode)mode_mask_array[word_mode])))
  && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1)))((enum rtx_code) (((((((((newpat)->u.fld[0]).rt_rtvec))->
elem[1]))->u.fld[0]).rt_rtx))->code) == SUBREG
 && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1)))(((((((((((newpat)->u.fld[0]).rt_rtvec))->elem[1]))->
u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx),
     (REG_P (temp_expr)(((enum rtx_code) (temp_expr)->code) == REG)
      && reg_stat[REGNO (temp_expr)(rhs_regno(temp_expr))].nonzero_bits != 0
      && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),(!maybe_le (((8) * (((global_options.x_ix86_isa_flags & (
1UL << 1)) != 0) ? 8 : 4)), GET_MODE_PRECISION (((machine_mode
) (temp_expr)->mode))))
		   BITS_PER_WORD)(!maybe_le (((8) * (((global_options.x_ix86_isa_flags & (
1UL << 1)) != 0) ? 8 : 4)), GET_MODE_PRECISION (((machine_mode
) (temp_expr)->mode))))
      && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),(!maybe_le ((8 * 4), GET_MODE_PRECISION (((machine_mode) (temp_expr
)->mode))))
		   HOST_BITS_PER_INT)(!maybe_le ((8 * 4), GET_MODE_PRECISION (((machine_mode) (temp_expr
)->mode))))
      && (reg_stat[REGNO (temp_expr)(rhs_regno(temp_expr))].nonzero_bits
	  != GET_MODE_MASK (word_mode)mode_mask_array[word_mode]))))
  && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1))((((((((newpat)->u.fld[0]).rt_rtvec))->elem[1]))->u.
fld[0]).rt_rtx),
			 SET_SRC (XVECEXP (newpat, 0, 1))((((((((newpat)->u.fld[0]).rt_rtvec))->elem[1]))->u.
fld[1]).rt_rtx))
  && ! find_reg_note (i3, REG_UNUSED,
	       SET_DEST (XVECEXP (newpat, 0, 0))((((((((newpat)->u.fld[0]).rt_rtvec))->elem[0]))->u.
fld[0]).rt_rtx)))
  {
    rtx ni2dest;

    newi2pat = XVECEXP (newpat, 0, 0)(((((newpat)->u.fld[0]).rt_rtvec))->elem[0]);
    ni2dest = SET_DEST (XVECEXP (newpat, 0, 0))((((((((newpat)->u.fld[0]).rt_rtvec))->elem[0]))->u.
fld[0]).rt_rtx);
    newpat = XVECEXP (newpat, 0, 1)(((((newpat)->u.fld[0]).rt_rtvec))->elem[1]);
    SUBST (SET_SRC (newpat),do_SUBST (&((((newpat)->u.fld[1]).rt_rtx)), (rtl_hooks
.gen_lowpart (((machine_mode) ((((newpat)->u.fld[1]).rt_rtx
))->mode), ni2dest)))
    gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest))do_SUBST (&((((newpat)->u.fld[1]).rt_rtx)), (rtl_hooks
.gen_lowpart (((machine_mode) ((((newpat)->u.fld[1]).rt_rtx
))->mode), ni2dest)));
    i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);

    if (i2_code_number >= 0)
insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);

    if (insn_code_number >= 0)
swap_i2i3 = 1;
  }

/* Similarly, check for a case where we have a PARALLEL of two independent
   SETs but we started with three insns.  In this case, we can do the sets
   as two separate insns.  This case occurs when some SET allows two
   other insns to combine, but the destination of that SET is still live.

   Also do this if we started with two insns and (at least) one of the
   resulting sets is a noop; this noop will be deleted later.

   Also do this if we started with two insns neither of which was a simple
   move.  */

else if (insn_code_number53.3
'insn_code_number' is < 0
 < 0 && asm_noperands (newpat) < 0
54
←
Assuming the condition is false→
  && GET_CODE (newpat)((enum rtx_code) (newpat)->code) == PARALLEL
  && XVECLEN (newpat, 0)(((((newpat)->u.fld[0]).rt_rtvec))->num_elem) == 2
  && GET_CODE (XVECEXP (newpat, 0, 0))((enum rtx_code) ((((((newpat)->u.fld[0]).rt_rtvec))->elem
[0]))->code) == SET
  && GET_CODE (XVECEXP (newpat, 0, 1))((enum rtx_code) ((((((newpat)->u.fld[0]).rt_rtvec))->elem
[1]))->code) == SET
  && (i1
      || set_noop_p (XVECEXP (newpat, 0, 0)(((((newpat)->u.fld[0]).rt_rtvec))->elem[0]))
      || set_noop_p (XVECEXP (newpat, 0, 1)(((((newpat)->u.fld[0]).rt_rtvec))->elem[1]))
      || (!i2_was_move && !i3_was_move))
  && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0)))((enum rtx_code) (((((((((newpat)->u.fld[0]).rt_rtvec))->
elem[0]))->u.fld[0]).rt_rtx))->code) != ZERO_EXTRACT
  && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0)))((enum rtx_code) (((((((((newpat)->u.fld[0]).rt_rtvec))->
elem[0]))->u.fld[0]).rt_rtx))->code) != STRICT_LOW_PART
  && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1)))((enum rtx_code) (((((((((newpat)->u.fld[0]).rt_rtvec))->
elem[1]))->u.fld[0]).rt_rtx))->code) != ZERO_EXTRACT
  && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1)))((enum rtx_code) (((((((((newpat)->u.fld[0]).rt_rtvec))->
elem[1]))->u.fld[0]).rt_rtx))->code) != STRICT_LOW_PART
  && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1))((((((((newpat)->u.fld[0]).rt_rtvec))->elem[1]))->u.
fld[0]).rt_rtx),
		  XVECEXP (newpat, 0, 0)(((((newpat)->u.fld[0]).rt_rtvec))->elem[0]))
  && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0))((((((((newpat)->u.fld[0]).rt_rtvec))->elem[0]))->u.
fld[0]).rt_rtx),
		  XVECEXP (newpat, 0, 1)(((((newpat)->u.fld[0]).rt_rtvec))->elem[1]))
  && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))((((((((newpat)->u.fld[0]).rt_rtvec))->elem[0]))->u.
fld[1]).rt_rtx))
 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))((((((((newpat)->u.fld[0]).rt_rtvec))->elem[1]))->u.
fld[1]).rt_rtx))))
  {
    rtx set0 = XVECEXP (newpat, 0, 0)(((((newpat)->u.fld[0]).rt_rtvec))->elem[0]);
    rtx set1 = XVECEXP (newpat, 0, 1)(((((newpat)->u.fld[0]).rt_rtvec))->elem[1]);

    /* Normally, it doesn't matter which of the two is done first, but
one which uses any regs/memory set in between i2 and i3 can't
be first.  The PARALLEL might also have been pre-existing in i3,
so we need to make sure that we won't wrongly hoist a SET to i2
that would conflict with a death note present in there, or would
have its dest modified between i2 and i3.  */
    if (!modified_between_p (SET_SRC (set1)(((set1)->u.fld[1]).rt_rtx), i2, i3)
 && !(REG_P (SET_DEST (set1))(((enum rtx_code) ((((set1)->u.fld[0]).rt_rtx))->code) ==
 REG)
      && find_reg_note (i2, REG_DEAD, SET_DEST (set1)(((set1)->u.fld[0]).rt_rtx)))
 && !(GET_CODE (SET_DEST (set1))((enum rtx_code) ((((set1)->u.fld[0]).rt_rtx))->code) == SUBREG
      && find_reg_note (i2, REG_DEAD,
		 SUBREG_REG (SET_DEST (set1))((((((set1)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx)))
 && !modified_between_p (SET_DEST (set1)(((set1)->u.fld[0]).rt_rtx), i2, i3)
 /* If I3 is a jump, ensure that set0 is a jump so that
    we do not create invalid RTL.  */
 && (!JUMP_P (i3)(((enum rtx_code) (i3)->code) == JUMP_INSN) || SET_DEST (set0)(((set0)->u.fld[0]).rt_rtx) == pc_rtx)
)
{
 newi2pat = set1;
 newpat = set0;
}
    else if (!modified_between_p (SET_SRC (set0)(((set0)->u.fld[1]).rt_rtx), i2, i3)
      && !(REG_P (SET_DEST (set0))(((enum rtx_code) ((((set0)->u.fld[0]).rt_rtx))->code) ==
 REG)
    && find_reg_note (i2, REG_DEAD, SET_DEST (set0)(((set0)->u.fld[0]).rt_rtx)))
      && !(GET_CODE (SET_DEST (set0))((enum rtx_code) ((((set0)->u.fld[0]).rt_rtx))->code) == SUBREG
    && find_reg_note (i2, REG_DEAD,
		      SUBREG_REG (SET_DEST (set0))((((((set0)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx)))
      && !modified_between_p (SET_DEST (set0)(((set0)->u.fld[0]).rt_rtx), i2, i3)
      /* If I3 is a jump, ensure that set1 is a jump so that
  we do not create invalid RTL.  */
      && (!JUMP_P (i3)(((enum rtx_code) (i3)->code) == JUMP_INSN) || SET_DEST (set1)(((set1)->u.fld[0]).rt_rtx) == pc_rtx)
     )
{
 newi2pat = set0;
 newpat = set1;
}
    else
{
 undo_all ();
 return 0;
}

    i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);

    if (i2_code_number >= 0)
{
 /* recog_for_combine might have added CLOBBERs to newi2pat.
    Make sure NEWPAT does not depend on the clobbered regs.  */
 if (GET_CODE (newi2pat)((enum rtx_code) (newi2pat)->code) == PARALLEL)
   {
     for (i = XVECLEN (newi2pat, 0)(((((newi2pat)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
if (GET_CODE (XVECEXP (newi2pat, 0, i))((enum rtx_code) ((((((newi2pat)->u.fld[0]).rt_rtvec))->
elem[i]))->code) == CLOBBER)
  {
    rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0)((((((((newi2pat)->u.fld[0]).rt_rtvec))->elem[i]))->
u.fld[0]).rt_rtx);
    if (reg_overlap_mentioned_p (reg, newpat))
      {
	undo_all ();
	return 0;
      }
  }
   }

 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);

 /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
    Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
    mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live.  */
 if (insn_code_number >= 0 && GET_CODE (newpat)((enum rtx_code) (newpat)->code) == PARALLEL)
   {
     for (i = XVECLEN (newpat, 0)(((((newpat)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
if (GET_CODE (XVECEXP (newpat, 0, i))((enum rtx_code) ((((((newpat)->u.fld[0]).rt_rtvec))->elem
[i]))->code) == CLOBBER)
  {
    rtx reg = XEXP (XVECEXP (newpat, 0, i), 0)((((((((newpat)->u.fld[0]).rt_rtvec))->elem[i]))->u.
fld[0]).rt_rtx);
    if (reg_overlap_mentioned_p (reg, SET_DEST (set0)(((set0)->u.fld[0]).rt_rtx))
	|| reg_overlap_mentioned_p (reg, SET_DEST (set1)(((set1)->u.fld[0]).rt_rtx)))
      {
	undo_all ();
	return 0;
      }
  }
   }

 if (insn_code_number >= 0)
   split_i2i3 = 1;
}
  }

/* If it still isn't recognized, fail and change things back the way they
   were.  */
if ((insn_code_number54.1
'insn_code_number' is < 0
 < 0
56
←
Taking false branch→
     /* Is the result a reasonable ASM_OPERANDS?  */
     && (! check_asm_operands (newpat) || added_sets_155.1
'added_sets_1' is 0
 || added_sets_255.2
'added_sets_2' is 0
)))
55
←
Assuming the condition is false→
  {
    undo_all ();
    return 0;
  }

/* If we had to change another insn, make sure it is valid also.  */
if (undobuf.other_insn)
57
←
Assuming field 'other_insn' is null→
58
←
Taking false branch→
  {
    CLEAR_HARD_REG_SET (newpat_used_regs);

    other_pat = PATTERN (undobuf.other_insn);
    other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
			     &new_other_notes);

    if (other_code_number < 0 && ! check_asm_operands (other_pat))
{
 undo_all ();
 return 0;
}
  }

/* Only allow this combination if insn_cost reports that the
   replacement instructions are cheaper than the originals.  */
if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
59
←
Calling 'combine_validate_cost'→
68
←
Returning from 'combine_validate_cost'→
69
←
Taking false branch→
  {
    undo_all ();
    return 0;
  }

if (MAY_HAVE_DEBUG_BIND_INSNSglobal_options.x_flag_var_tracking_assignments)
70
←
Assuming field 'x_flag_var_tracking_assignments' is 0→
71
←
Taking false branch→
  {
    struct undo *undo;

    for (undo = undobuf.undos; undo; undo = undo->next)
if (undo->kind == UNDO_MODE)
 {
   rtx reg = regno_reg_rtx[undo->where.regno];
   machine_mode new_mode = GET_MODE (reg)((machine_mode) (reg)->mode);
   machine_mode old_mode = undo->old_contents.m;

   /* Temporarily revert mode back.  */
   adjust_reg_mode (reg, old_mode);

   if (reg == i2dest && i2scratch)
     {
/* If we used i2dest as a scratch register with a
   different mode, substitute it for the original
   i2src while its original mode is temporarily
   restored, and then clear i2scratch so that we don't
   do it again later.  */
propagate_for_debug (i2, last_combined_insn, reg, i2src,
		     this_basic_block);
i2scratch = false;
/* Put back the new mode.  */
adjust_reg_mode (reg, new_mode);
     }
   else
     {
rtx tempreg = gen_raw_REG (old_mode, REGNO (reg)(rhs_regno(reg)));
rtx_insn *first, *last;

if (reg == i2dest)
  {
    first = i2;
    last = last_combined_insn;
  }
else
  {
    first = i3;
    last = undobuf.other_insn;
    gcc_assert (last)((void)(!(last) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 4151, __FUNCTION__), 0 : 0));
    if (DF_INSN_LUID (last)((((df->insns[(INSN_UID (last))]))->luid))
	< DF_INSN_LUID (last_combined_insn)((((df->insns[(INSN_UID (last_combined_insn))]))->luid)
))
      last = last_combined_insn;
  }

/* We're dealing with a reg that changed mode but not
   meaning, so we want to turn it into a subreg for
   the new mode.  However, because of REG sharing and
   because its mode had already changed, we have to do
   it in two steps.  First, replace any debug uses of
   reg, with its original mode temporarily restored,
   with this copy we have created; then, replace the
   copy with the SUBREG of the original shared reg,
   once again changed to the new mode.  */
propagate_for_debug (first, last, reg, tempreg,
		     this_basic_block);
adjust_reg_mode (reg, new_mode);
propagate_for_debug (first, last, tempreg,
		     lowpart_subreg (old_mode, reg, new_mode),
		     this_basic_block);
     }
 }
  }

/* If we will be able to accept this, we have made a
   change to the destination of I3.  This requires us to
   do a few adjustments.  */

if (changed_i3_dest71.1
'changed_i3_dest' is 0
)
72
←
Taking false branch→
  {
    PATTERN (i3) = newpat;
    adjust_for_new_dest (i3);
  }

/* We now know that we can do this combination.  Merge the insns and
   update the status of registers and LOG_LINKS.  */

if (undobuf.other_insn72.1
Field 'other_insn' is null
)
73
←
Taking false branch→
  {
    rtx note, next;

    PATTERN (undobuf.other_insn) = other_pat;

    /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
ensure that they are still valid.  Then add any non-duplicate
notes added by recog_for_combine.  */
    for (note = REG_NOTES (undobuf.other_insn)(((undobuf.other_insn)->u.fld[6]).rt_rtx); note; note = next)
{
 next = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx);

 if ((REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_DEAD
      && !reg_referenced_p (XEXP (note, 0)(((note)->u.fld[0]).rt_rtx),
		     PATTERN (undobuf.other_insn)))
     ||(REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_UNUSED
 && !reg_set_p (XEXP (note, 0)(((note)->u.fld[0]).rt_rtx),
		PATTERN (undobuf.other_insn)))
     /* Simply drop equal note since it may be no longer valid
 for other_insn.  It may be possible to record that CC
 register is changed and only discard those notes, but
 in practice it's unnecessary complication and doesn't
 give any meaningful improvement.

 See PR78559.  */
     || REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_EQUAL
     || REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_EQUIV)
   remove_note (undobuf.other_insn, note);
}

    distribute_notes  (new_other_notes, undobuf.other_insn,
	undobuf.other_insn, NULLnullptr, NULL_RTX(rtx) 0, NULL_RTX(rtx) 0,
	NULL_RTX(rtx) 0);
  }

if (swap_i2i373.1
'swap_i2i3' is 0
)
  {
    /* I3 now uses what used to be its destination and which is now
I2's destination.  This requires us to do a few adjustments.  */
    PATTERN (i3) = newpat;
    adjust_for_new_dest (i3);
  }

if (swap_i2i373.2
'swap_i2i3' is 0
 || split_i2i373.3
'split_i2i3' is 0
)
74
←
Taking false branch→
  {
    /* We might need a LOG_LINK from I3 to I2.  But then we used to
have one, so we still will.

However, some later insn might be using I2's dest and have
a LOG_LINK pointing at I3.  We should change it to point at
I2 instead.  */

    /* newi2pat is usually a SET here; however, recog_for_combine might
have added some clobbers.  */
    rtx x = newi2pat;
    if (GET_CODE (x)((enum rtx_code) (x)->code) == PARALLEL)
x = XVECEXP (newi2pat, 0, 0)(((((newi2pat)->u.fld[0]).rt_rtvec))->elem[0]);

    if (REG_P (SET_DEST (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
 || (GET_CODE (SET_DEST (x))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == SUBREG
     && REG_P (SUBREG_REG (SET_DEST (x)))(((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[
0]).rt_rtx))->code) == REG)))
{
 unsigned int regno = reg_or_subregno (SET_DEST (x)(((x)->u.fld[0]).rt_rtx));

 bool done = false;
 for (rtx_insn *insn = NEXT_INSN (i3);
      !done
      && insn
      && INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN))
      && BLOCK_FOR_INSN (insn) == this_basic_block;
      insn = NEXT_INSN (insn))
   {
     if (DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN))
continue;
     struct insn_link *link;
     FOR_EACH_LOG_LINK (link, insn)for ((link) = (uid_log_links[insn_uid_check (insn)]); (link);
 (link) = (link)->next)
if (link->insn == i3 && link->regno == regno)
  {
    link->insn = i2;
    done = true;
    break;
  }
   }
}
  }

{
  rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
  struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
  rtx midnotes = 0;
  int from_luid;
  /* Compute which registers we expect to eliminate.  newi2pat may be setting
     either i3dest or i2dest, so we must check it.  */
  rtx elim_i2 = ((newi2pat74.1
'newi2pat' is null
 && reg_set_p (i2dest, newi2pat))
77
←
'?' condition is false→
   || i2dest_in_i2src || i2dest_in_i1src75.1
'i2dest_in_i1src' is 0
 || i2dest_in_i0src

75.2	'i2dest_in_i0src' is 0

←

Assuming 'i2dest_in_i2src' is 0

→

4285 || !i2dest_killed

←

Assuming 'i2dest_killed' is not equal to 0

→

4286 ? 0 : i2dest); 4287 /* For i1, we need to compute both local elimination and global 4288 elimination information with respect to newi2pat because i1dest 4289 may be the same as i3dest, in which case newi2pat may be setting 4290 i1dest. Global information is used when distributing REG_DEAD 4291 note for i2 and i3, in which case it does matter if newi2pat sets 4292 i1dest or not. 4293 4294 Local information is used when distributing REG_DEAD note for i1, 4295 in which case it doesn't matter if newi2pat sets i1dest or not. 4296 See PR62151, if we have four insns combination: 4297 i0: r0 <- i0src 4298 i1: r1 <- i1src (using r0) 4299 REG_DEAD (r0) 4300 i2: r0 <- i2src (using r1) 4301 i3: r3 <- i3src (using r0) 4302 ix: using r0 4303 From i1's point of view, r0 is eliminated, no matter if it is set 4304 by newi2pat or not. In other words, REG_DEAD info for r0 in i1 4305 should be discarded. 4306 4307 Note local information only affects cases in forms like "I1->I2->I3", 4308 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like 4309 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or 4310 i0dest anyway. */ 4311 rtx local_elim_i1 = (i1

77.1	'i1' is equal to null

== 0 || i1dest_in_i1src || i1dest_in_i0src 4312 || !i1dest_killed 4313 ? 0 : i1dest); 4314 rtx elim_i1 = (local_elim_i1

77.2	'local_elim_i1' is equal to null

== 0 4315 || (newi2pat && reg_set_p (i1dest, newi2pat)) 4316 ? 0 : i1dest); 4317 /* Same case as i1. */ 4318 rtx local_elim_i0 = (i0

77.3	'i0' is equal to null

== 0 || i0dest_in_i0src || !i0dest_killed 4319 ? 0 : i0dest); 4320 rtx elim_i0 = (local_elim_i0

77.4	'local_elim_i0' is equal to null

== 0 4321 || (newi2pat && reg_set_p (i0dest, newi2pat)) 4322 ? 0 : i0dest); 4323 4324 /* Get the old REG_NOTES and LOG_LINKS from all our insns and 4325 clear them. */ 4326 i3notes = REG_NOTES (i3)(((i3)->u.fld[6]).rt_rtx), i3links = LOG_LINKS (i3)(uid_log_links[insn_uid_check (i3)]); 4327 i2notes = REG_NOTES (i2)(((i2)->u.fld[6]).rt_rtx), i2links = LOG_LINKS (i2)(uid_log_links[insn_uid_check (i2)]); 4328 if (i1

77.5	'i1' is null

)

←

Taking false branch

→

4329 i1notes = REG_NOTES (i1)(((i1)->u.fld[6]).rt_rtx), i1links = LOG_LINKS (i1)(uid_log_links[insn_uid_check (i1)]); 4330 if (i0

78.1	'i0' is null

)

←

Taking false branch

→

4331 i0notes = REG_NOTES (i0)(((i0)->u.fld[6]).rt_rtx), i0links = LOG_LINKS (i0)(uid_log_links[insn_uid_check (i0)]); 4332 4333 /* Ensure that we do not have something that should not be shared but 4334 occurs multiple times in the new insns. Check this by first 4335 resetting all the `used' flags and then copying anything is shared. */ 4336 4337 reset_used_flags (i3notes); 4338 reset_used_flags (i2notes); 4339 reset_used_flags (i1notes); 4340 reset_used_flags (i0notes); 4341 reset_used_flags (newpat); 4342 reset_used_flags (newi2pat); 4343 if (undobuf.other_insn)

←

Assuming field 'other_insn' is null

→

←

Taking false branch

→

4344 reset_used_flags (PATTERN (undobuf.other_insn)); 4345 4346 i3notes = copy_rtx_if_shared (i3notes); 4347 i2notes = copy_rtx_if_shared (i2notes); 4348 i1notes = copy_rtx_if_shared (i1notes); 4349 i0notes = copy_rtx_if_shared (i0notes); 4350 newpat = copy_rtx_if_shared (newpat); 4351 newi2pat = copy_rtx_if_shared (newi2pat); 4352 if (undobuf.other_insn)

←

Assuming field 'other_insn' is null

→

←

Taking false branch

→

4353 reset_used_flags (PATTERN (undobuf.other_insn)); 4354 4355 INSN_CODE (i3)(((i3)->u.fld[5]).rt_int) = insn_code_number; 4356 PATTERN (i3) = newpat; 4357 4358 if (CALL_P (i3)(((enum rtx_code) (i3)->code) == CALL_INSN) && CALL_INSN_FUNCTION_USAGE (i3)(((i3)->u.fld[7]).rt_rtx))

←

Assuming field 'code' is not equal to CALL_INSN

→

4359 { 4360 for (rtx link = CALL_INSN_FUNCTION_USAGE (i3)(((i3)->u.fld[7]).rt_rtx); link; 4361 link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx)) 4362 { 4363 if (substed_i2) 4364 { 4365 /* I2SRC must still be meaningful at this point. Some 4366 splitting operations can invalidate I2SRC, but those 4367 operations do not apply to calls. */ 4368 gcc_assert (i2src)((void)(!(i2src) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 4368, __FUNCTION__), 0 : 0)); 4369 XEXP (link, 0)(((link)->u.fld[0]).rt_rtx) = simplify_replace_rtx (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), 4370 i2dest, i2src); 4371 } 4372 if (substed_i1) 4373 XEXP (link, 0)(((link)->u.fld[0]).rt_rtx) = simplify_replace_rtx (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), 4374 i1dest, i1src); 4375 if (substed_i0) 4376 XEXP (link, 0)(((link)->u.fld[0]).rt_rtx) = simplify_replace_rtx (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), 4377 i0dest, i0src); 4378 } 4379 } 4380 4381 if (undobuf.other_insn

84.1	Field 'other_insn' is null

)

←

Taking false branch

→

4382 INSN_CODE (undobuf.other_insn)(((undobuf.other_insn)->u.fld[5]).rt_int) = other_code_number; 4383 4384 /* We had one special case above where I2 had more than one set and 4385 we replaced a destination of one of those sets with the destination 4386 of I3. In that case, we have to update LOG_LINKS of insns later 4387 in this basic block. Note that this (expensive) case is rare. 4388 4389 Also, in this case, we must pretend that all REG_NOTEs for I2 4390 actually came from I3, so that REG_UNUSED notes from I2 will be 4391 properly handled. */ 4392 4393 if (i3_subst_into_i2

85.1	'i3_subst_into_i2' is 0

)

←

Taking false branch

→

4394 { 4395 for (i = 0; i < XVECLEN (PATTERN (i2), 0)(((((PATTERN (i2))->u.fld[0]).rt_rtvec))->num_elem); i++) 4396 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i))((enum rtx_code) ((((((PATTERN (i2))->u.fld[0]).rt_rtvec))
->elem[i]))->code) == SET 4397 || GET_CODE (XVECEXP (PATTERN (i2), 0, i))((enum rtx_code) ((((((PATTERN (i2))->u.fld[0]).rt_rtvec))
->elem[i]))->code) == CLOBBER) 4398 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))(((enum rtx_code) (((((((((PATTERN (i2))->u.fld[0]).rt_rtvec
))->elem[i]))->u.fld[0]).rt_rtx))->code) == REG) 4399 && SET_DEST (XVECEXP (PATTERN (i2), 0, i))((((((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[i]))->
u.fld[0]).rt_rtx) != i2dest 4400 && ! find_reg_note (i2, REG_UNUSED, 4401 SET_DEST (XVECEXP (PATTERN (i2), 0, i))((((((((PATTERN (i2))->u.fld[0]).rt_rtvec))->elem[i]))->
u.fld[0]).rt_rtx))) 4402 for (temp_insn = NEXT_INSN (i2); 4403 temp_insn 4404 && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_exit_block_ptr) 4405 || BB_HEAD (this_basic_block)(this_basic_block)->il.x.head_ != temp_insn); 4406 temp_insn = NEXT_INSN (temp_insn)) 4407 if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn)((((enum rtx_code) (temp_insn)->code) == INSN) || (((enum rtx_code
) (temp_insn)->code) == JUMP_INSN) || (((enum rtx_code) (temp_insn
)->code) == CALL_INSN))) 4408 FOR_EACH_LOG_LINK (link, temp_insn)for ((link) = (uid_log_links[insn_uid_check (temp_insn)]); (link
); (link) = (link)->next) 4409 if (link->insn == i2) 4410 link->insn = i3; 4411 4412 if (i3notes) 4413 { 4414 rtx link = i3notes; 4415 while (XEXP (link, 1)(((link)->u.fld[1]).rt_rtx)) 4416 link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx); 4417 XEXP (link, 1)(((link)->u.fld[1]).rt_rtx) = i2notes; 4418 } 4419 else 4420 i3notes = i2notes; 4421 i2notes = 0; 4422 } 4423 4424 LOG_LINKS (i3)(uid_log_links[insn_uid_check (i3)]) = NULLnullptr; 4425 REG_NOTES (i3)(((i3)->u.fld[6]).rt_rtx) = 0; 4426 LOG_LINKS (i2)(uid_log_links[insn_uid_check (i2)]) = NULLnullptr; 4427 REG_NOTES (i2)(((i2)->u.fld[6]).rt_rtx) = 0; 4428 4429 if (newi2pat)

←

Assuming 'newi2pat' is null

→

4430 { 4431 if (MAY_HAVE_DEBUG_BIND_INSNSglobal_options.x_flag_var_tracking_assignments && i2scratch) 4432 propagate_for_debug (i2, last_combined_insn, i2dest, i2src, 4433 this_basic_block); 4434 INSN_CODE (i2)(((i2)->u.fld[5]).rt_int) = i2_code_number; 4435 PATTERN (i2) = newi2pat; 4436 } 4437 else 4438 { 4439 if (MAY_HAVE_DEBUG_BIND_INSNSglobal_options.x_flag_var_tracking_assignments && i2src)

←

Assuming field 'x_flag_var_tracking_assignments' is 0

→

4440 propagate_for_debug (i2, last_combined_insn, i2dest, i2src, 4441 this_basic_block); 4442 SET_INSN_DELETED (i2)set_insn_deleted (i2);; 4443 } 4444 4445 if (i1

88.1	'i1' is null

)

←

Taking false branch

→

4446 { 4447 LOG_LINKS (i1)(uid_log_links[insn_uid_check (i1)]) = NULLnullptr; 4448 REG_NOTES (i1)(((i1)->u.fld[6]).rt_rtx) = 0; 4449 if (MAY_HAVE_DEBUG_BIND_INSNSglobal_options.x_flag_var_tracking_assignments) 4450 propagate_for_debug (i1, last_combined_insn, i1dest, i1src, 4451 this_basic_block); 4452 SET_INSN_DELETED (i1)set_insn_deleted (i1);; 4453 } 4454 4455 if (i0

89.1	'i0' is null

)

←

Taking false branch

→

4456 { 4457 LOG_LINKS (i0)(uid_log_links[insn_uid_check (i0)]) = NULLnullptr; 4458 REG_NOTES (i0)(((i0)->u.fld[6]).rt_rtx) = 0; 4459 if (MAY_HAVE_DEBUG_BIND_INSNSglobal_options.x_flag_var_tracking_assignments) 4460 propagate_for_debug (i0, last_combined_insn, i0dest, i0src, 4461 this_basic_block); 4462 SET_INSN_DELETED (i0)set_insn_deleted (i0);; 4463 } 4464 4465 /* Get death notes for everything that is now used in either I3 or 4466 I2 and used to die in a previous insn. If we built two new 4467 patterns, move from I1 to I2 then I2 to I3 so that we get the 4468 proper movement on registers that I2 modifies. */ 4469 4470 if (i0

90.1	'i0' is null

)

←

Taking false branch

→

4471 from_luid = DF_INSN_LUID (i0)((((df->insns[(INSN_UID (i0))]))->luid)); 4472 else if (i1

91.1	'i1' is null

)

←

Taking false branch

→

4473 from_luid = DF_INSN_LUID (i1)((((df->insns[(INSN_UID (i1))]))->luid)); 4474 else 4475 from_luid = DF_INSN_LUID (i2)((((df->insns[(INSN_UID (i2))]))->luid)); 4476 if (newi2pat

92.1	'newi2pat' is null

)

←

Taking false branch

→

4477 move_deaths (newi2pat, NULL_RTX(rtx) 0, from_luid, i2, &midnotes); 4478 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes); 4479 4480 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ 4481 if (i3notes)

←

Assuming 'i3notes' is null

→

←

Taking false branch

→

4482 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULLnullptr, 4483 elim_i2, elim_i1, elim_i0); 4484 if (i2notes)

←

Assuming 'i2notes' is null

→

←

Taking false branch

→

4485 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULLnullptr, 4486 elim_i2, elim_i1, elim_i0); 4487 if (i1notes)

←

Assuming 'i1notes' is null

→

←

Taking false branch

→

4488 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULLnullptr, 4489 elim_i2, local_elim_i1, local_elim_i0); 4490 if (i0notes)

100

←

Assuming 'i0notes' is null

→

101

←

Taking false branch

→

4491 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULLnullptr, 4492 elim_i2, elim_i1, local_elim_i0); 4493 if (midnotes

101.1

'midnotes' is null

) 4494 distribute_notes (midnotes, NULLnullptr, i3, newi2pat ? i2 : NULLnullptr, 4495 elim_i2, elim_i1, elim_i0); 4496 4497 /* Distribute any notes added to I2 or I3 by recog_for_combine. We 4498 know these are REG_UNUSED and want them to go to the desired insn, 4499 so we always pass it as i3. */ 4500 4501 if (newi2pat

101.2

'newi2pat' is null

&& new_i2_notes) 4502 distribute_notes (new_i2_notes, i2, i2, NULLnullptr, NULL_RTX(rtx) 0, NULL_RTX(rtx) 0, 4503 NULL_RTX(rtx) 0); 4504 4505 if (new_i3_notes)

102

←

Branch condition evaluates to a garbage value

4506 distribute_notes (new_i3_notes, i3, i3, NULLnullptr, NULL_RTX(rtx) 0, NULL_RTX(rtx) 0, 4507 NULL_RTX(rtx) 0); 4508 4509 /* If I3DEST was used in I3SRC, it really died in I3. We may need to 4510 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets 4511 I3DEST, the death must be somewhere before I2, not I3. If we passed I3 4512 in that case, it might delete I2. Similarly for I2 and I1. 4513 Show an additional death due to the REG_DEAD note we make here. If 4514 we discard it in distribute_notes, we will decrement it again. */ 4515 4516 if (i3dest_killed) 4517 { 4518 rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX(rtx) 0); 4519 if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) 4520 distribute_notes (new_note, NULLnullptr, i2, NULLnullptr, elim_i2, 4521 elim_i1, elim_i0); 4522 else 4523 distribute_notes (new_note, NULLnullptr, i3, newi2pat ? i2 : NULLnullptr, 4524 elim_i2, elim_i1, elim_i0); 4525 } 4526 4527 if (i2dest_in_i2src) 4528 { 4529 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX(rtx) 0); 4530 if (newi2pat && reg_set_p (i2dest, newi2pat)) 4531 distribute_notes (new_note, NULLnullptr, i2, NULLnullptr, NULL_RTX(rtx) 0, 4532 NULL_RTX(rtx) 0, NULL_RTX(rtx) 0); 4533 else 4534 distribute_notes (new_note, NULLnullptr, i3, newi2pat ? i2 : NULLnullptr, 4535 NULL_RTX(rtx) 0, NULL_RTX(rtx) 0, NULL_RTX(rtx) 0); 4536 } 4537 4538 if (i1dest_in_i1src) 4539 { 4540 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX(rtx) 0); 4541 if (newi2pat && reg_set_p (i1dest, newi2pat)) 4542 distribute_notes (new_note, NULLnullptr, i2, NULLnullptr, NULL_RTX(rtx) 0, 4543 NULL_RTX(rtx) 0, NULL_RTX(rtx) 0); 4544 else 4545 distribute_notes (new_note, NULLnullptr, i3, newi2pat ? i2 : NULLnullptr, 4546 NULL_RTX(rtx) 0, NULL_RTX(rtx) 0, NULL_RTX(rtx) 0); 4547 } 4548 4549 if (i0dest_in_i0src) 4550 { 4551 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX(rtx) 0); 4552 if (newi2pat && reg_set_p (i0dest, newi2pat)) 4553 distribute_notes (new_note, NULLnullptr, i2, NULLnullptr, NULL_RTX(rtx) 0, 4554 NULL_RTX(rtx) 0, NULL_RTX(rtx) 0); 4555 else 4556 distribute_notes (new_note, NULLnullptr, i3, newi2pat ? i2 : NULLnullptr, 4557 NULL_RTX(rtx) 0, NULL_RTX(rtx) 0, NULL_RTX(rtx) 0); 4558 } 4559 4560 distribute_links (i3links); 4561 distribute_links (i2links); 4562 distribute_links (i1links); 4563 distribute_links (i0links); 4564 4565 if (REG_P (i2dest)(((enum rtx_code) (i2dest)->code) == REG)) 4566 { 4567 struct insn_link *link; 4568 rtx_insn *i2_insn = 0; 4569 rtx i2_val = 0, set; 4570 4571 /* The insn that used to set this register doesn't exist, and 4572 this life of the register may not exist either. See if one of 4573 I3's links points to an insn that sets I2DEST. If it does, 4574 that is now the last known value for I2DEST. If we don't update 4575 this and I2 set the register to a value that depended on its old 4576 contents, we will get confused. If this insn is used, thing 4577 will be set correctly in combine_instructions. */ 4578 FOR_EACH_LOG_LINK (link, i3)for ((link) = (uid_log_links[insn_uid_check (i3)]); (link); (
link) = (link)->next) 4579 if ((set = single_set (link->insn)) != 0 4580 && rtx_equal_p (i2dest, SET_DEST (set)(((set)->u.fld[0]).rt_rtx))) 4581 i2_insn = link->insn, i2_val = SET_SRC (set)(((set)->u.fld[1]).rt_rtx); 4582 4583 record_value_for_reg (i2dest, i2_insn, i2_val); 4584 4585 /* If the reg formerly set in I2 died only once and that was in I3, 4586 zero its use count so it won't make `reload' do any work. */ 4587 if (! added_sets_2 4588 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) 4589 && ! i2dest_in_i2src 4590 && REGNO (i2dest)(rhs_regno(i2dest)) < reg_n_sets_max) 4591 INC_REG_N_SETS (REGNO (i2dest), -1)(regstat_n_sets_and_refs[(rhs_regno(i2dest))].sets += -1); 4592 } 4593 4594 if (i1 && REG_P (i1dest)(((enum rtx_code) (i1dest)->code) == REG)) 4595 { 4596 struct insn_link *link; 4597 rtx_insn *i1_insn = 0; 4598 rtx i1_val = 0, set; 4599 4600 FOR_EACH_LOG_LINK (link, i3)for ((link) = (uid_log_links[insn_uid_check (i3)]); (link); (
link) = (link)->next) 4601 if ((set = single_set (link->insn)) != 0 4602 && rtx_equal_p (i1dest, SET_DEST (set)(((set)->u.fld[0]).rt_rtx))) 4603 i1_insn = link->insn, i1_val = SET_SRC (set)(((set)->u.fld[1]).rt_rtx); 4604 4605 record_value_for_reg (i1dest, i1_insn, i1_val); 4606 4607 if (! added_sets_1 4608 && ! i1dest_in_i1src 4609 && REGNO (i1dest)(rhs_regno(i1dest)) < reg_n_sets_max) 4610 INC_REG_N_SETS (REGNO (i1dest), -1)(regstat_n_sets_and_refs[(rhs_regno(i1dest))].sets += -1); 4611 } 4612 4613 if (i0 && REG_P (i0dest)(((enum rtx_code) (i0dest)->code) == REG)) 4614 { 4615 struct insn_link *link; 4616 rtx_insn *i0_insn = 0; 4617 rtx i0_val = 0, set; 4618 4619 FOR_EACH_LOG_LINK (link, i3)for ((link) = (uid_log_links[insn_uid_check (i3)]); (link); (
link) = (link)->next) 4620 if ((set = single_set (link->insn)) != 0 4621 && rtx_equal_p (i0dest, SET_DEST (set)(((set)->u.fld[0]).rt_rtx))) 4622 i0_insn = link->insn, i0_val = SET_SRC (set)(((set)->u.fld[1]).rt_rtx); 4623 4624 record_value_for_reg (i0dest, i0_insn, i0_val); 4625 4626 if (! added_sets_0 4627 && ! i0dest_in_i0src 4628 && REGNO (i0dest)(rhs_regno(i0dest)) < reg_n_sets_max) 4629 INC_REG_N_SETS (REGNO (i0dest), -1)(regstat_n_sets_and_refs[(rhs_regno(i0dest))].sets += -1); 4630 } 4631 4632 /* Update reg_stat[].nonzero_bits et al for any changes that may have 4633 been made to this insn. The order is important, because newi2pat 4634 can affect nonzero_bits of newpat. */ 4635 if (newi2pat) 4636 note_pattern_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULLnullptr); 4637 note_pattern_stores (newpat, set_nonzero_bits_and_sign_copies, NULLnullptr); 4638 } 4639 4640 if (undobuf.other_insn != NULL_RTX(rtx) 0) 4641 { 4642 if (dump_file) 4643 { 4644 fprintf (dump_file, "modifying other_insn "); 4645 dump_insn_slim (dump_file, undobuf.other_insn); 4646 } 4647 df_insn_rescan (undobuf.other_insn); 4648 } 4649 4650 if (i0 && !(NOTE_P (i0)(((enum rtx_code) (i0)->code) == NOTE) && (NOTE_KIND (i0)(((i0)->u.fld[4]).rt_int) == NOTE_INSN_DELETED))) 4651 { 4652 if (dump_file) 4653 { 4654 fprintf (dump_file, "modifying insn i0 "); 4655 dump_insn_slim (dump_file, i0); 4656 } 4657 df_insn_rescan (i0); 4658 } 4659 4660 if (i1 && !(NOTE_P (i1)(((enum rtx_code) (i1)->code) == NOTE) && (NOTE_KIND (i1)(((i1)->u.fld[4]).rt_int) == NOTE_INSN_DELETED))) 4661 { 4662 if (dump_file) 4663 { 4664 fprintf (dump_file, "modifying insn i1 "); 4665 dump_insn_slim (dump_file, i1); 4666 } 4667 df_insn_rescan (i1); 4668 } 4669 4670 if (i2 && !(NOTE_P (i2)(((enum rtx_code) (i2)->code) == NOTE) && (NOTE_KIND (i2)(((i2)->u.fld[4]).rt_int) == NOTE_INSN_DELETED))) 4671 { 4672 if (dump_file) 4673 { 4674 fprintf (dump_file, "modifying insn i2 "); 4675 dump_insn_slim (dump_file, i2); 4676 } 4677 df_insn_rescan (i2); 4678 } 4679 4680 if (i3 && !(NOTE_P (i3)(((enum rtx_code) (i3)->code) == NOTE) && (NOTE_KIND (i3)(((i3)->u.fld[4]).rt_int) == NOTE_INSN_DELETED))) 4681 { 4682 if (dump_file) 4683 { 4684 fprintf (dump_file, "modifying insn i3 "); 4685 dump_insn_slim (dump_file, i3); 4686 } 4687 df_insn_rescan (i3); 4688 } 4689 4690 /* Set new_direct_jump_p if a new return or simple jump instruction 4691 has been created. Adjust the CFG accordingly. */ 4692 if (returnjump_p (i3) || any_uncondjump_p (i3)) 4693 { 4694 *new_direct_jump_p = 1; 4695 mark_jump_label (PATTERN (i3), i3, 0); 4696 update_cfg_for_uncondjump (i3); 4697 } 4698 4699 if (undobuf.other_insn != NULL_RTX(rtx) 0 4700 && (returnjump_p (undobuf.other_insn) 4701 || any_uncondjump_p (undobuf.other_insn))) 4702 { 4703 *new_direct_jump_p = 1; 4704 update_cfg_for_uncondjump (undobuf.other_insn); 4705 } 4706 4707 if (GET_CODE (PATTERN (i3))((enum rtx_code) (PATTERN (i3))->code) == TRAP_IF 4708 && XEXP (PATTERN (i3), 0)(((PATTERN (i3))->u.fld[0]).rt_rtx) == const1_rtx(const_int_rtx[64 +1])) 4709 { 4710 basic_block bb = BLOCK_FOR_INSN (i3); 4711 gcc_assert (bb)((void)(!(bb) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 4711, __FUNCTION__), 0 : 0)); 4712 remove_edge (split_block (bb, i3)); 4713 emit_barrier_after_bb (bb); 4714 *new_direct_jump_p = 1; 4715 } 4716 4717 if (undobuf.other_insn 4718 && GET_CODE (PATTERN (undobuf.other_insn))((enum rtx_code) (PATTERN (undobuf.other_insn))->code) == TRAP_IF 4719 && XEXP (PATTERN (undobuf.other_insn), 0)(((PATTERN (undobuf.other_insn))->u.fld[0]).rt_rtx) == const1_rtx(const_int_rtx[64 +1])) 4720 { 4721 basic_block bb = BLOCK_FOR_INSN (undobuf.other_insn); 4722 gcc_assert (bb)((void)(!(bb) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 4722, __FUNCTION__), 0 : 0)); 4723 remove_edge (split_block (bb, undobuf.other_insn)); 4724 emit_barrier_after_bb (bb); 4725 *new_direct_jump_p = 1; 4726 } 4727 4728 /* A noop might also need cleaning up of CFG, if it comes from the 4729 simplification of a jump. */ 4730 if (JUMP_P (i3)(((enum rtx_code) (i3)->code) == JUMP_INSN) 4731 && GET_CODE (newpat)((enum rtx_code) (newpat)->code) == SET 4732 && SET_SRC (newpat)(((newpat)->u.fld[1]).rt_rtx) == pc_rtx 4733 && SET_DEST (newpat)(((newpat)->u.fld[0]).rt_rtx) == pc_rtx) 4734 { 4735 *new_direct_jump_p = 1; 4736 update_cfg_for_uncondjump (i3); 4737 } 4738 4739 if (undobuf.other_insn != NULL_RTX(rtx) 0 4740 && JUMP_P (undobuf.other_insn)(((enum rtx_code) (undobuf.other_insn)->code) == JUMP_INSN
) 4741 && GET_CODE (PATTERN (undobuf.other_insn))((enum rtx_code) (PATTERN (undobuf.other_insn))->code) == SET 4742 && SET_SRC (PATTERN (undobuf.other_insn))(((PATTERN (undobuf.other_insn))->u.fld[1]).rt_rtx) == pc_rtx 4743 && SET_DEST (PATTERN (undobuf.other_insn))(((PATTERN (undobuf.other_insn))->u.fld[0]).rt_rtx) == pc_rtx) 4744 { 4745 *new_direct_jump_p = 1; 4746 update_cfg_for_uncondjump (undobuf.other_insn); 4747 } 4748 4749 combine_successes++; 4750 undo_commit (); 4751 4752 rtx_insn *ret = newi2pat ? i2 : i3; 4753 if (added_links_insn && DF_INSN_LUID (added_links_insn)((((df->insns[(INSN_UID (added_links_insn))]))->luid)) < DF_INSN_LUID (ret)((((df->insns[(INSN_UID (ret))]))->luid))) 4754 ret = added_links_insn; 4755 if (added_notes_insn && DF_INSN_LUID (added_notes_insn)((((df->insns[(INSN_UID (added_notes_insn))]))->luid)) < DF_INSN_LUID (ret)((((df->insns[(INSN_UID (ret))]))->luid))) 4756 ret = added_notes_insn; 4757 4758 return ret; 4759} 4760

4761/* Get a marker for undoing to the current state. */ 4762 4763static void * 4764get_undo_marker (void) 4765{ 4766 return undobuf.undos; 4767} 4768 4769/* Undo the modifications up to the marker. */ 4770 4771static void 4772undo_to_marker (void *marker) 4773{ 4774 struct undo *undo, *next; 4775 4776 for (undo = undobuf.undos; undo != marker; undo = next) 4777 { 4778 gcc_assert (undo)((void)(!(undo) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 4778, __FUNCTION__), 0 : 0)); 4779 4780 next = undo->next; 4781 switch (undo->kind) 4782 { 4783 case UNDO_RTX: 4784 *undo->where.r = undo->old_contents.r; 4785 break; 4786 case UNDO_INT: 4787 *undo->where.i = undo->old_contents.i; 4788 break; 4789 case UNDO_MODE: 4790 adjust_reg_mode (regno_reg_rtx[undo->where.regno], 4791 undo->old_contents.m); 4792 break; 4793 case UNDO_LINKS: 4794 *undo->where.l = undo->old_contents.l; 4795 break; 4796 default: 4797 gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/combine.cc"
, 4797, __FUNCTION__)); 4798 } 4799 4800 undo->next = undobuf.frees; 4801 undobuf.frees = undo; 4802 } 4803 4804 undobuf.undos = (struct undo *) marker; 4805} 4806 4807/* Undo all the modifications recorded in undobuf. */ 4808 4809static void 4810undo_all (void) 4811{ 4812 undo_to_marker (0); 4813} 4814 4815/* We've committed to accepting the changes we made. Move all 4816 of the undos to the free list. */ 4817 4818static void 4819undo_commit (void) 4820{ 4821 struct undo *undo, *next; 4822 4823 for (undo = undobuf.undos; undo; undo = next) 4824 { 4825 next = undo->next; 4826 undo->next = undobuf.frees; 4827 undobuf.frees = undo; 4828 } 4829 undobuf.undos = 0; 4830} 4831

4832/* Find the innermost point within the rtx at LOC, possibly LOC itself, 4833 where we have an arithmetic expression and return that point. LOC will 4834 be inside INSN. 4835 4836 try_combine will call this function to see if an insn can be split into 4837 two insns. */ 4838 4839static rtx * 4840find_split_point (rtx *loc, rtx_insn *insn, bool set_src) 4841{ 4842 rtx x = *loc; 4843 enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code); 4844 rtx *split; 4845 unsigned HOST_WIDE_INTlong len = 0; 4846 HOST_WIDE_INTlong pos = 0; 4847 int unsignedp = 0; 4848 rtx inner = NULL_RTX(rtx) 0; 4849 scalar_int_mode mode, inner_mode; 4850 4851 /* First special-case some codes. */ 4852 switch (code) 4853 { 4854 case SUBREG: 4855#ifdef INSN_SCHEDULING 4856 /* If we are making a paradoxical SUBREG invalid, it becomes a split 4857 point. */ 4858 if (MEM_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == MEM
)) 4859 return loc; 4860#endif 4861 return find_split_point (&SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), insn, false); 4862 4863 case MEM: 4864 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it 4865 using LO_SUM and HIGH. */ 4866 if (HAVE_lo_sum0 && (GET_CODE (XEXP (x, 0))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == CONST 4867 || GET_CODE (XEXP (x, 0))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == SYMBOL_REF)) 4868 { 4869 machine_mode address_mode = get_address_mode (x); 4870 4871 SUBST (XEXP (x, 0),do_SUBST (&((((x)->u.fld[0]).rt_rtx)), (gen_rtx_fmt_ee_stat
((LO_SUM), ((address_mode)), ((gen_rtx_fmt_e_stat ((HIGH), (
(address_mode)), (((((x)->u.fld[0]).rt_rtx))) ))), (((((x)
->u.fld[0]).rt_rtx))) ))) 4872 gen_rtx_LO_SUM (address_mode,do_SUBST (&((((x)->u.fld[0]).rt_rtx)), (gen_rtx_fmt_ee_stat
((LO_SUM), ((address_mode)), ((gen_rtx_fmt_e_stat ((HIGH), (
(address_mode)), (((((x)->u.fld[0]).rt_rtx))) ))), (((((x)
->u.fld[0]).rt_rtx))) ))) 4873 gen_rtx_HIGH (address_mode, XEXP (x, 0)),do_SUBST (&((((x)->u.fld[0]).rt_rtx)), (gen_rtx_fmt_ee_stat
((LO_SUM), ((address_mode)), ((gen_rtx_fmt_e_stat ((HIGH), (
(address_mode)), (((((x)->u.fld[0]).rt_rtx))) ))), (((((x)
->u.fld[0]).rt_rtx))) ))) 4874 XEXP (x, 0)))do_SUBST (&((((x)->u.fld[0]).rt_rtx)), (gen_rtx_fmt_ee_stat
((LO_SUM), ((address_mode)), ((gen_rtx_fmt_e_stat ((HIGH), (
(address_mode)), (((((x)->u.fld[0]).rt_rtx))) ))), (((((x)
->u.fld[0]).rt_rtx))) ))); 4875 return &XEXP (XEXP (x, 0), 0)((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx); 4876 } 4877 4878 /* If we have a PLUS whose second operand is a constant and the 4879 address is not valid, perhaps we can split it up using 4880 the machine-specific way to split large constants. We use 4881 the first pseudo-reg (one of the virtual regs) as a placeholder; 4882 it will not remain in the result. */ 4883 if (GET_CODE (XEXP (x, 0))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == PLUS 4884 && CONST_INT_P (XEXP (XEXP (x, 0), 1))(((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[
1]).rt_rtx))->code) == CONST_INT) 4885 && ! memory_address_addr_space_p (GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), 4886 MEM_ADDR_SPACE (x)(get_mem_attrs (x)->addrspace))) 4887 { 4888 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER76]; 4889 rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((reg))
, (((((x)->u.fld[0]).rt_rtx))) ), 4890 subst_insn); 4891 4892 /* This should have produced two insns, each of which sets our 4893 placeholder. If the source of the second is a valid address, 4894 we can put both sources together and make a split point 4895 in the middle. */ 4896 4897 if (seq 4898 && NEXT_INSN (seq) != NULL_RTX(rtx) 0 4899 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX(rtx) 0 4900 && NONJUMP_INSN_P (seq)(((enum rtx_code) (seq)->code) == INSN) 4901 && GET_CODE (PATTERN (seq))((enum rtx_code) (PATTERN (seq))->code) == SET 4902 && SET_DEST (PATTERN (seq))(((PATTERN (seq))->u.fld[0]).rt_rtx) == reg 4903 && ! reg_mentioned_p (reg, 4904 SET_SRC (PATTERN (seq))(((PATTERN (seq))->u.fld[1]).rt_rtx)) 4905 && NONJUMP_INSN_P (NEXT_INSN (seq))(((enum rtx_code) (NEXT_INSN (seq))->code) == INSN) 4906 && GET_CODE (PATTERN (NEXT_INSN (seq)))((enum rtx_code) (PATTERN (NEXT_INSN (seq)))->code) == SET 4907 && SET_DEST (PATTERN (NEXT_INSN (seq)))(((PATTERN (NEXT_INSN (seq)))->u.fld[0]).rt_rtx) == reg 4908 && memory_address_addr_space_p 4909 (GET_MODE (x)((machine_mode) (x)->mode), SET_SRC (PATTERN (NEXT_INSN (seq)))(((PATTERN (NEXT_INSN (seq)))->u.fld[1]).rt_rtx), 4910 MEM_ADDR_SPACE (x)(get_mem_attrs (x)->addrspace))) 4911 { 4912 rtx src1 = SET_SRC (PATTERN (seq))(((PATTERN (seq))->u.fld[1]).rt_rtx); 4913 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)))(((PATTERN (NEXT_INSN (seq)))->u.fld[1]).rt_rtx); 4914 4915 /* Replace the placeholder in SRC2 with SRC1. If we can 4916 find where in SRC2 it was placed, that can become our 4917 split point and we can replace this address with SRC2. 4918 Just try two obvious places. */ 4919 4920 src2 = replace_rtx (src2, reg, src1); 4921 split = 0; 4922 if (XEXP (src2, 0)(((src2)->u.fld[0]).rt_rtx) == src1) 4923 split = &XEXP (src2, 0)(((src2)->u.fld[0]).rt_rtx); 4924 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))(rtx_format[(int) (((enum rtx_code) ((((src2)->u.fld[0]).rt_rtx
))->code))])[0] == 'e' 4925 && XEXP (XEXP (src2, 0), 0)((((((src2)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx) == src1) 4926 split = &XEXP (XEXP (src2, 0), 0)((((((src2)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx); 4927 4928 if (split) 4929 { 4930 SUBST (XEXP (x, 0), src2)do_SUBST (&((((x)->u.fld[0]).rt_rtx)), (src2)); 4931 return split; 4932 } 4933 } 4934 4935 /* If that didn't work and we have a nested plus, like: 4936 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2 4937 is valid address, try to split (REG1 * CONST1). */ 4938 if (GET_CODE (XEXP (XEXP (x, 0), 0))((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[0
]).rt_rtx))->code) == PLUS 4939 && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))(((rtx_class[(int) (((enum rtx_code) ((((((((((x)->u.fld[0
]).rt_rtx))->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
code))]) & (~1)) == (RTX_OBJ & (~1))) 4940 && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))(((rtx_class[(int) (((enum rtx_code) ((((((((((x)->u.fld[0
]).rt_rtx))->u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx))->
code))]) & (~1)) == (RTX_OBJ & (~1))) 4941 && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))((enum rtx_code) ((((((((((x)->u.fld[0]).rt_rtx))->u.fld
[0]).rt_rtx))->u.fld[0]).rt_rtx))->code) == SUBREG 4942 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),(((rtx_class[(int) (((enum rtx_code) (((((((((((((x)->u.fld
[0]).rt_rtx))->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx))->code))]) & (~1)) == (RTX_OBJ &
(~1))) 4943 0), 0)))(((rtx_class[(int) (((enum rtx_code) (((((((((((((x)->u.fld
[0]).rt_rtx))->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx))->code))]) & (~1)) == (RTX_OBJ &
(~1))))) 4944 { 4945 rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 0)(((((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx); 4946 XEXP (XEXP (XEXP (x, 0), 0), 0)(((((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx) = reg; 4947 if (memory_address_addr_space_p (GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), 4948 MEM_ADDR_SPACE (x)(get_mem_attrs (x)->addrspace))) 4949 { 4950 XEXP (XEXP (XEXP (x, 0), 0), 0)(((((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx) = tem; 4951 return &XEXP (XEXP (XEXP (x, 0), 0), 0)(((((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx); 4952 } 4953 XEXP (XEXP (XEXP (x, 0), 0), 0)(((((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx) = tem; 4954 } 4955 else if (GET_CODE (XEXP (XEXP (x, 0), 0))((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[0
]).rt_rtx))->code) == PLUS 4956 && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))(((rtx_class[(int) (((enum rtx_code) ((((((((((x)->u.fld[0
]).rt_rtx))->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
code))]) & (~1)) == (RTX_OBJ & (~1))) 4957 && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))(((rtx_class[(int) (((enum rtx_code) ((((((((((x)->u.fld[0
]).rt_rtx))->u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx))->
code))]) & (~1)) == (RTX_OBJ & (~1))) 4958 && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))((enum rtx_code) ((((((((((x)->u.fld[0]).rt_rtx))->u.fld
[0]).rt_rtx))->u.fld[1]).rt_rtx))->code) == SUBREG 4959 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),(((rtx_class[(int) (((enum rtx_code) (((((((((((((x)->u.fld
[0]).rt_rtx))->u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx))->
u.fld[0]).rt_rtx))->code))]) & (~1)) == (RTX_OBJ &
(~1))) 4960 0), 1)))(((rtx_class[(int) (((enum rtx_code) (((((((((((((x)->u.fld
[0]).rt_rtx))->u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx))->
u.fld[0]).rt_rtx))->code))]) & (~1)) == (RTX_OBJ &
(~1))))) 4961 { 4962 rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 1)(((((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[1]).rt_rtx); 4963 XEXP (XEXP (XEXP (x, 0), 0), 1)(((((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[1]).rt_rtx) = reg; 4964 if (memory_address_addr_space_p (GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), 4965 MEM_ADDR_SPACE (x)(get_mem_attrs (x)->addrspace))) 4966 { 4967 XEXP (XEXP (XEXP (x, 0), 0), 1)(((((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[1]).rt_rtx) = tem; 4968 return &XEXP (XEXP (XEXP (x, 0), 0), 1)(((((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[1]).rt_rtx); 4969 } 4970 XEXP (XEXP (XEXP (x, 0), 0), 1)(((((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[1]).rt_rtx) = tem; 4971 } 4972 4973 /* If that didn't work, perhaps the first operand is complex and 4974 needs to be computed separately, so make a split point there. 4975 This will occur on machines that just support REG + CONST 4976 and have a constant moved through some previous computation. */ 4977 if (!OBJECT_P (XEXP (XEXP (x, 0), 0))(((rtx_class[(int) (((enum rtx_code) (((((((x)->u.fld[0]).
rt_rtx))->u.fld[0]).rt_rtx))->code))]) & (~1)) == (
RTX_OBJ & (~1))) 4978 && ! (GET_CODE (XEXP (XEXP (x, 0), 0))((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[0
]).rt_rtx))->code) == SUBREG 4979 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))(((rtx_class[(int) (((enum rtx_code) ((((((((((x)->u.fld[0
]).rt_rtx))->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
code))]) & (~1)) == (RTX_OBJ & (~1))))) 4980 return &XEXP (XEXP (x, 0), 0)((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx); 4981 } 4982 4983 /* If we have a PLUS whose first operand is complex, try computing it 4984 separately by making a split there. */ 4985 if (GET_CODE (XEXP (x, 0))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == PLUS 4986 && ! memory_address_addr_space_p (GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), 4987 MEM_ADDR_SPACE (x)(get_mem_attrs (x)->addrspace)) 4988 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))(((rtx_class[(int) (((enum rtx_code) (((((((x)->u.fld[0]).
rt_rtx))->u.fld[0]).rt_rtx))->code))]) & (~1)) == (
RTX_OBJ & (~1))) 4989 && ! (GET_CODE (XEXP (XEXP (x, 0), 0))((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[0
]).rt_rtx))->code) == SUBREG 4990 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))(((rtx_class[(int) (((enum rtx_code) ((((((((((x)->u.fld[0
]).rt_rtx))->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
code))]) & (~1)) == (RTX_OBJ & (~1))))) 4991 return &XEXP (XEXP (x, 0), 0)((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx); 4992 break; 4993 4994 case SET: 4995 /* See if we can split SET_SRC as it stands. */ 4996 split = find_split_point (&SET_SRC (x)(((x)->u.fld[1]).rt_rtx), insn, true); 4997 if (split && split != &SET_SRC (x)(((x)->u.fld[1]).rt_rtx)) 4998 return split; 4999 5000 /* See if we can split SET_DEST as it stands. */ 5001 split = find_split_point (&SET_DEST (x)(((x)->u.fld[0]).rt_rtx), insn, false); 5002 if (split && split != &SET_DEST (x)(((x)->u.fld[0]).rt_rtx)) 5003 return split; 5004 5005 /* See if this is a bitfield assignment with everything constant. If 5006 so, this is an IOR of an AND, so split it into that. */ 5007 if (GET_CODE (SET_DEST (x))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == ZERO_EXTRACT 5008 && is_a <scalar_int_mode> (GET_MODE (XEXP (SET_DEST (x), 0))((machine_mode) (((((((x)->u.fld[0]).rt_rtx))->u.fld[0]
).rt_rtx))->mode), 5009 &inner_mode) 5010 && HWI_COMPUTABLE_MODE_P (inner_mode) 5011 && CONST_INT_P (XEXP (SET_DEST (x), 1))(((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[
1]).rt_rtx))->code) == CONST_INT) 5012 && CONST_INT_P (XEXP (SET_DEST (x), 2))(((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[
2]).rt_rtx))->code) == CONST_INT) 5013 && CONST_INT_P (SET_SRC (x))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
) 5014 && ((INTVAL (XEXP (SET_DEST (x), 1))((((((((x)->u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx))->
u.hwint[0]) 5015 + INTVAL (XEXP (SET_DEST (x), 2))((((((((x)->u.fld[0]).rt_rtx))->u.fld[2]).rt_rtx))->
u.hwint[0])) 5016 <= GET_MODE_PRECISION (inner_mode)) 5017 && ! side_effects_p (XEXP (SET_DEST (x), 0)((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))) 5018 { 5019 HOST_WIDE_INTlong pos = INTVAL (XEXP (SET_DEST (x), 2))((((((((x)->u.fld[0]).rt_rtx))->u.fld[2]).rt_rtx))->
u.hwint[0]); 5020 unsigned HOST_WIDE_INTlong len = INTVAL (XEXP (SET_DEST (x), 1))((((((((x)->u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx))->
u.hwint[0]); 5021 rtx dest = XEXP (SET_DEST (x), 0)((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx); 5022 unsigned HOST_WIDE_INTlong mask = (HOST_WIDE_INT_1U1UL << len) - 1; 5023 unsigned HOST_WIDE_INTlong src = INTVAL (SET_SRC (x))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) & mask; 5024 rtx or_mask; 5025 5026 if (BITS_BIG_ENDIAN0) 5027 pos = GET_MODE_PRECISION (inner_mode) - len - pos; 5028 5029 or_mask = gen_int_mode (src << pos, inner_mode); 5030 if (src == mask) 5031 SUBST (SET_SRC (x),do_SUBST (&((((x)->u.fld[1]).rt_rtx)), (simplify_gen_binary
(IOR, inner_mode, dest, or_mask))) 5032 simplify_gen_binary (IOR, inner_mode, dest, or_mask))do_SUBST (&((((x)->u.fld[1]).rt_rtx)), (simplify_gen_binary
(IOR, inner_mode, dest, or_mask))); 5033 else 5034 { 5035 rtx negmask = gen_int_mode (~(mask << pos), inner_mode); 5036 SUBST (SET_SRC (x),do_SUBST (&((((x)->u.fld[1]).rt_rtx)), (simplify_gen_binary
(IOR, inner_mode, simplify_gen_binary (AND, inner_mode, dest
, negmask), or_mask))) 5037 simplify_gen_binary (IOR, inner_mode,do_SUBST (&((((x)->u.fld[1]).rt_rtx)), (simplify_gen_binary
(IOR, inner_mode, simplify_gen_binary (AND, inner_mode, dest
, negmask), or_mask))) 5038 simplify_gen_binary (AND, inner_mode,do_SUBST (&((((x)->u.fld[1]).rt_rtx)), (simplify_gen_binary
(IOR, inner_mode, simplify_gen_binary (AND, inner_mode, dest
, negmask), or_mask))) 5039 dest, negmask),do_SUBST (&((((x)->u.fld[1]).rt_rtx)), (simplify_gen_binary
(IOR, inner_mode, simplify_gen_binary (AND, inner_mode, dest
, negmask), or_mask))) 5040 or_mask))do_SUBST (&((((x)->u.fld[1]).rt_rtx)), (simplify_gen_binary
(IOR, inner_mode, simplify_gen_binary (AND, inner_mode, dest
, negmask), or_mask))); 5041 } 5042 5043 SUBST (SET_DEST (x), dest)do_SUBST (&((((x)->u.fld[0]).rt_rtx)), (dest)); 5044 5045 split = find_split_point (&SET_SRC (x)(((x)->u.fld[1]).rt_rtx), insn, true); 5046 if (split && split != &SET_SRC (x)(((x)->u.fld[1]).rt_rtx)) 5047 return split; 5048 } 5049 5050 /* Otherwise, see if this is an operation that we can split into two. 5051 If so, try to split that. */ 5052 code = GET_CODE (SET_SRC (x))((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code); 5053 5054 switch (code) 5055 { 5056 case AND: 5057 /* If we are AND'ing with a large constant that is only a single 5058 bit and the result is only being used in a context where we 5059 need to know if it is zero or nonzero, replace it with a bit 5060 extraction. This will avoid the large constant, which might 5061 have taken more than one insn to make. If the constant were 5062 not a valid argument to the AND but took only one insn to make, 5063 this is no worse, but if it took more than one insn, it will 5064 be better. */ 5065 5066 if (CONST_INT_P (XEXP (SET_SRC (x), 1))(((enum rtx_code) (((((((x)->u.fld[1]).rt_rtx))->u.fld[
1]).rt_rtx))->code) == CONST_INT) 5067 && REG_P (XEXP (SET_SRC (x), 0))(((enum rtx_code) (((((((x)->u.fld[1]).rt_rtx))->u.fld[
0]).rt_rtx))->code) == REG) 5068 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1))((unsigned long) ((((((((x)->u.fld[1]).rt_rtx))->u.fld[
1]).rt_rtx))->u.hwint[0])))) >= 7 5069 && REG_P (SET_DEST (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
) 5070 && (split = find_single_use (SET_DEST (x)(((x)->u.fld[0]).rt_rtx), insn, NULLnullptr)) != 0 5071 && (GET_CODE (*split)((enum rtx_code) (*split)->code) == EQ || GET_CODE (*split)((enum rtx_code) (*split)->code) == NE) 5072 && XEXP (*split, 0)(((*split)->u.fld[0]).rt_rtx) == SET_DEST (x)(((x)->u.fld[0]).rt_rtx) 5073 && XEXP (*split, 1)(((*split)->u.fld[1]).rt_rtx) == const0_rtx(const_int_rtx[64])) 5074 { 5075 rtx extraction = make_extraction (GET_MODE (SET_DEST (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode), 5076 XEXP (SET_SRC (x), 0)((((((x)->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx), 5077 pos, NULL_RTX(rtx) 0, 1, 1, 0, 0); 5078 if (extraction != 0) 5079 { 5080 SUBST (SET_SRC (x), extraction)do_SUBST (&((((x)->u.fld[1]).rt_rtx)), (extraction)); 5081 return find_split_point (loc, insn, false); 5082 } 5083 } 5084 break; 5085 5086 case NE: 5087 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X 5088 is known to be on, this can be converted into a NEG of a shift. */ 5089 if (STORE_FLAG_VALUE1 == -1 && XEXP (SET_SRC (x), 1)((((((x)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx) == const0_rtx(const_int_rtx[64]) 5090 && GET_MODE (SET_SRC (x))((machine_mode) ((((x)->u.fld[1]).rt_rtx))->mode) == GET_MODE (XEXP (SET_SRC (x), 0))((machine_mode) (((((((x)->u.fld[1]).rt_rtx))->u.fld[0]
).rt_rtx))->mode) 5091 && ((pos = exact_log2 (nonzero_bits (XEXP (SET_SRC (x), 0)((((((x)->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx), 5092 GET_MODE (XEXP (SET_SRC (x),((machine_mode) (((((((x)->u.fld[1]).rt_rtx))->u.fld[0]
).rt_rtx))->mode) 5093 0))((machine_mode) (((((((x)->u.fld[1]).rt_rtx))->u.fld[0]
).rt_rtx))->mode)))) >= 1)) 5094 { 5095 machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0))((machine_mode) (((((((x)->u.fld[1]).rt_rtx))->u.fld[0]
).rt_rtx))->mode); 5096 rtx pos_rtx = gen_int_shift_amount (mode, pos); 5097 SUBST (SET_SRC (x),do_SUBST (&((((x)->u.fld[1]).rt_rtx)), (gen_rtx_fmt_e_stat
((NEG), ((mode)), ((gen_rtx_fmt_ee_stat ((LSHIFTRT), ((mode)
), ((((((((x)->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx))),
((pos_rtx)) ))) ))) 5098 gen_rtx_NEG (mode,do_SUBST (&((((x)->u.fld[1]).rt_rtx)), (gen_rtx_fmt_e_stat
((