/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc

Bug Summary

File:	build/gcc/recog.cc
Warning:	line 3075, column 4 Assigned value is garbage or undefined
Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-suse-linux -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name recog.cc -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -resource-dir /usr/lib64/clang/15.0.7 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/backward -internal-isystem /usr/lib64/clang/15.0.7/include -internal-isystem /usr/local/include -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../x86_64-suse-linux/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2023-03-27-141847-20772-1/report-Pn3VRq.plist -x c++ /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc
1/* Subroutines used by or related to instruction recognition.
 Copyright (C) 1987-2023 Free Software Foundation, Inc.

4This file is part of GCC.

6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8Software Foundation; either version 3, or (at your option) any later
9version.

11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14for more details.

16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3.  If not see
18<http://www.gnu.org/licenses/>.  */


21#include "config.h"
22#include "system.h"
23#include "coretypes.h"
24#include "backend.h"
25#include "target.h"
26#include "rtl.h"
27#include "tree.h"
28#include "cfghooks.h"
29#include "df.h"
30#include "memmodel.h"
31#include "tm_p.h"
32#include "insn-config.h"
33#include "regs.h"
34#include "emit-rtl.h"
35#include "recog.h"
36#include "insn-attr.h"
37#include "addresses.h"
38#include "cfgrtl.h"
39#include "cfgbuild.h"
40#include "cfgcleanup.h"
41#include "reload.h"
42#include "tree-pass.h"
43#include "function-abi.h"

45#ifndef STACK_POP_CODEPOST_INC
46#if STACK_GROWS_DOWNWARD1
47#define STACK_POP_CODEPOST_INC POST_INC
48#else
49#define STACK_POP_CODEPOST_INC POST_DEC
50#endif
51#endif

53static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx_insn *, bool);
54static void validate_replace_src_1 (rtx *, void *);
55static rtx_insn *split_insn (rtx_insn *);

57struct target_recog default_target_recog;
58#if SWITCHABLE_TARGET1
59struct target_recog *this_target_recog = &default_target_recog;
60#endif

62/* Nonzero means allow operands to be volatile.
 This should be 0 if you are generating rtl, such as if you are calling
 the functions in optabs.cc and expmed.cc (most of the time).
 This should be 1 if all valid insns need to be recognized,
 such as in reginfo.cc and final.cc and reload.cc.

 init_recog and init_recog_no_volatile are responsible for setting this.  */

70int volatile_ok;

72struct recog_data_d recog_data;

74/* Contains a vector of operand_alternative structures, such that
 operand OP of alternative A is at index A * n_operands + OP.
 Set up by preprocess_constraints.  */
77const operand_alternative *recog_op_alt;

79/* Used to provide recog_op_alt for asms.  */
80static operand_alternative asm_op_alt[MAX_RECOG_OPERANDS30
		      * MAX_RECOG_ALTERNATIVES35];

83/* On return from `constrain_operands', indicate which alternative
 was satisfied.  */

86int which_alternative;

88/* Nonzero after end of reload pass.
 Set to 1 or 0 by toplev.cc.
 Controls the significance of (SUBREG (MEM)).  */

92int reload_completed;

94/* Nonzero after thread_prologue_and_epilogue_insns has run.  */
95int epilogue_completed;

97/* Initialize data used by the function `recog'.
 This must be called once in the compilation of a function
 before any insn recognition may be done in the function.  */

101void
102init_recog_no_volatile (void)
103{
volatile_ok = 0;
105}

107void
108init_recog (void)
109{
volatile_ok = 1;
111}

113
114/* Return true if labels in asm operands BODY are LABEL_REFs.  */

116static bool
117asm_labels_ok (rtx body)
118{
rtx asmop;
int i;

asmop = extract_asm_operands (body);
if (asmop == NULL_RTX(rtx) 0)
  return true;

for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop)(((((asmop)->u.fld[5]).rt_rtvec))->num_elem); i++)
  if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i))((enum rtx_code) ((((((asmop)->u.fld[5]).rt_rtvec))->elem
[i]))->code) != LABEL_REF)
    return false;

return true;
131}

133/* Check that X is an insn-body for an `asm' with operands
 and that the operands mentioned in it are legitimate.  */

136int
137check_asm_operands (rtx x)
138{
int noperands;
rtx *operands;
const char **constraints;
int i;

if (!asm_labels_ok (x))
  return 0;

/* Post-reload, be more strict with things.  */
if (reload_completed)
  {
    /* ??? Doh!  We've not got the wrapping insn.  Cook one up.  */
    rtx_insn *insn = make_insn_raw (x);
    extract_insn (insn);
    constrain_operands (1, get_enabled_alternatives (insn));
    return which_alternative >= 0;
  }

noperands = asm_noperands (x);
if (noperands < 0)
  return 0;
if (noperands == 0)
  return 1;

operands = XALLOCAVEC (rtx, noperands)((rtx *) __builtin_alloca(sizeof (rtx) * (noperands)));
constraints = XALLOCAVEC (const char *, noperands)((const char * *) __builtin_alloca(sizeof (const char *) * (noperands
)));

decode_asm_operands (x, operands, NULLnullptr, constraints, NULLnullptr, NULLnullptr);

for (i = 0; i < noperands; i++)
  {
    const char *c = constraints[i];
    if (c[0] == '%')
c++;
    if (! asm_operand_ok (operands[i], c, constraints))
return 0;
  }

return 1;
178}
179
180/* Static data for the next two routines.  */

182struct change_t
183{
rtx object;
int old_code;
int old_len;
bool unshare;
rtx *loc;
rtx old;
190};

192static change_t *changes;
193static int changes_allocated;

195static int num_changes = 0;
196static int temporarily_undone_changes = 0;

198/* Validate a proposed change to OBJECT.  LOC is the location in the rtl
 at which NEW_RTX will be placed.  If NEW_LEN is >= 0, XVECLEN (NEW_RTX, 0)
 will also be changed to NEW_LEN, which is no greater than the current
 XVECLEN.  If OBJECT is zero, no validation is done, the change is
 simply made.

 Two types of objects are supported:  If OBJECT is a MEM, memory_address_p
 will be called with the address and mode as parameters.  If OBJECT is
 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
 the change in place.

 IN_GROUP is nonzero if this is part of a group of changes that must be
 performed as a group.  In that case, the changes will be stored.  The
 function `apply_change_group' will validate and apply the changes.

 If IN_GROUP is zero, this is a single change.  Try to recognize the insn
 or validate the memory reference with the change applied.  If the result
 is not valid for the machine, suppress the change and return zero.
 Otherwise, perform the change and return 1.  */

218static bool
219validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group,
   bool unshare, int new_len = -1)
221{
gcc_assert (temporarily_undone_changes == 0)((void)(!(temporarily_undone_changes == 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 222, __FUNCTION__), 0 : 0));
rtx old = *loc;

/* Single-element parallels aren't valid and won't match anything.
   Replace them with the single element.  */
if (new_len == 1 && GET_CODE (new_rtx)((enum rtx_code) (new_rtx)->code) == PARALLEL)
  {
    new_rtx = XVECEXP (new_rtx, 0, 0)(((((new_rtx)->u.fld[0]).rt_rtvec))->elem[0]);
    new_len = -1;
  }

if ((old == new_rtx || rtx_equal_p (old, new_rtx))
    && (new_len < 0 || XVECLEN (new_rtx, 0)(((((new_rtx)->u.fld[0]).rt_rtvec))->num_elem) == new_len))
  return 1;

gcc_assert ((in_group != 0 || num_changes == 0)((void)(!((in_group != 0 || num_changes == 0) && (new_len
 < 0 || new_rtx == *loc)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 238, __FUNCTION__), 0 : 0))
     && (new_len < 0 || new_rtx == *loc))((void)(!((in_group != 0 || num_changes == 0) && (new_len
 < 0 || new_rtx == *loc)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 238, __FUNCTION__), 0 : 0));

*loc = new_rtx;

/* Save the information describing this change.  */
if (num_changes >= changes_allocated)
  {
    if (changes_allocated == 0)
/* This value allows for repeated substitutions inside complex
  indexed addresses, or changes in up to 5 insns.  */
changes_allocated = MAX_RECOG_OPERANDS30 * 5;
    else
changes_allocated *= 2;

    changes = XRESIZEVEC (change_t, changes, changes_allocated)((change_t *) xrealloc ((void *) (changes), sizeof (change_t)
 * (changes_allocated)));
  }

changes[num_changes].object = object;
changes[num_changes].loc = loc;
changes[num_changes].old = old;
changes[num_changes].old_len = (new_len >= 0 ? XVECLEN (new_rtx, 0)(((((new_rtx)->u.fld[0]).rt_rtvec))->num_elem) : -1);
changes[num_changes].unshare = unshare;

if (new_len >= 0)
  XVECLEN (new_rtx, 0)(((((new_rtx)->u.fld[0]).rt_rtvec))->num_elem) = new_len;

if (object && !MEM_P (object)(((enum rtx_code) (object)->code) == MEM))
  {
    /* Set INSN_CODE to force rerecognition of insn.  Save old code in
case invalid.  */
    changes[num_changes].old_code = INSN_CODE (object)(((object)->u.fld[5]).rt_int);
    INSN_CODE (object)(((object)->u.fld[5]).rt_int) = -1;
  }

num_changes++;

/* If we are making a group of changes, return 1.  Otherwise, validate the
   change group we made.  */

if (in_group)
  return 1;
else
  return apply_change_group ();
281}

283/* Wrapper for validate_change_1 without the UNSHARE argument defaulting
 UNSHARE to false.  */

286bool
287validate_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
288{
return validate_change_1 (object, loc, new_rtx, in_group, false);
290}

292/* Wrapper for validate_change_1 without the UNSHARE argument defaulting
 UNSHARE to true.  */

295bool
296validate_unshare_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
297{
return validate_change_1 (object, loc, new_rtx, in_group, true);
299}

301/* Change XVECLEN (*LOC, 0) to NEW_LEN.  OBJECT, IN_GROUP and the return
 value are as for validate_change_1.  */

304bool
305validate_change_xveclen (rtx object, rtx *loc, int new_len, bool in_group)
306{
return validate_change_1 (object, loc, *loc, in_group, false, new_len);
308}

310/* Keep X canonicalized if some changes have made it non-canonical; only
 modifies the operands of X, not (for example) its code.  Simplifications
 are not the job of this routine.

 Return true if anything was changed.  */
315bool
316canonicalize_change_group (rtx_insn *insn, rtx x)
317{
if (COMMUTATIVE_P (x)(((rtx_class[(int) (((enum rtx_code) (x)->code))]) & (
~2)) == (RTX_COMM_COMPARE & (~2)))
    && swap_commutative_operands_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
  {
    /* Oops, the caller has made X no longer canonical.
Let's redo the changes in the correct order.  */
    rtx tem = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
    validate_unshare_change (insn, &XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), 1);
    validate_unshare_change (insn, &XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), tem, 1);
    return true;
  }
else
  return false;
330}

332/* Check if REG_INC argument in *data overlaps a stored REG.  */

334static void
335check_invalid_inc_dec (rtx reg, const_rtx, void *data)
336{
rtx *pinc = (rtx *) data;
if (*pinc == NULL_RTX(rtx) 0 || MEM_P (reg)(((enum rtx_code) (reg)->code) == MEM))
  return;
if (reg_overlap_mentioned_p (reg, *pinc))
  *pinc = NULL_RTX(rtx) 0;
342}

344/* This subroutine of apply_change_group verifies whether the changes to INSN
 were valid; i.e. whether INSN can still be recognized.

 If IN_GROUP is true clobbers which have to be added in order to
 match the instructions will be added to the current change group.
 Otherwise the changes will take effect immediately.  */

351int
352insn_invalid_p (rtx_insn *insn, bool in_group)
353{
rtx pat = PATTERN (insn);
int num_clobbers = 0;
/* If we are before reload and the pattern is a SET, see if we can add
   clobbers.  */
int icode = recog (pat, insn,
     (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET
      && ! reload_completed 
                    && ! reload_in_progress)
     ? &num_clobbers : 0);
int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;


/* If this is an asm and the operand aren't legal, then fail.  Likewise if
   this is not an asm and the insn wasn't recognized.  */
if ((is_asm && ! check_asm_operands (PATTERN (insn)))
    || (!is_asm && icode < 0))
  return 1;

/* If we have to add CLOBBERs, fail if we have to add ones that reference
   hard registers since our callers can't know if they are live or not.
   Otherwise, add them.  */
if (num_clobbers > 0)
  {
    rtx newpat;

    if (added_clobbers_hard_reg_p (icode))
return 1;

    newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(rtvec_alloc (num_clobbers + 1))) );
    XVECEXP (newpat, 0, 0)(((((newpat)->u.fld[0]).rt_rtvec))->elem[0]) = pat;
    add_clobbers (newpat, icode);
    if (in_group)
validate_change (insn, &PATTERN (insn), newpat, 1);
    else
PATTERN (insn) = pat = newpat;
  }

/* After reload, verify that all constraints are satisfied.  */
if (reload_completed)
  {
    extract_insn (insn);

    if (! constrain_operands (1, get_preferred_alternatives (insn)))
return 1;
  }

/* Punt if REG_INC argument overlaps some stored REG.  */
for (rtx link = FIND_REG_INC_NOTE (insn, NULL_RTX)0;
     link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
  if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == REG_INC)
    {
rtx reg = XEXP (link, 0)(((link)->u.fld[0]).rt_rtx);
note_stores (insn, check_invalid_inc_dec, &reg);
if (reg == NULL_RTX(rtx) 0)
 return 1;
    }

INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) = icode;
return 0;
413}

415/* Return number of changes made and not validated yet.  */
416int
417num_changes_pending (void)
418{
return num_changes;
420}

422/* Tentatively apply the changes numbered NUM and up.
 Return 1 if all changes are valid, zero otherwise.  */

425int
426verify_changes (int num)
427{
int i;
rtx last_validated = NULL_RTX(rtx) 0;

/* The changes have been applied and all INSN_CODEs have been reset to force
   rerecognition.

   The changes are valid if we aren't given an object, or if we are
   given a MEM and it still is a valid address, or if this is in insn
   and it is recognized.  In the latter case, if reload has completed,
   we also require that the operands meet the constraints for
   the insn.  */

for (i = num; i < num_changes; i++)
  {
    rtx object = changes[i].object;

    /* If there is no object to test or if it is the same as the one we
       already tested, ignore it.  */
    if (object == 0 || object == last_validated)
continue;

    if (MEM_P (object)(((enum rtx_code) (object)->code) == MEM))
{
 if (! memory_address_addr_space_p (GET_MODE (object)((machine_mode) (object)->mode),
			     XEXP (object, 0)(((object)->u.fld[0]).rt_rtx),
			     MEM_ADDR_SPACE (object)(get_mem_attrs (object)->addrspace)))
   break;
}
    else if (/* changes[i].old might be zero, e.g. when putting a
      REG_FRAME_RELATED_EXPR into a previously empty list.  */
      changes[i].old
      && REG_P (changes[i].old)(((enum rtx_code) (changes[i].old)->code) == REG)
      && asm_noperands (PATTERN (object)) > 0
      && register_asm_p (changes[i].old))
{
 /* Don't allow changes of hard register operands to inline
    assemblies if they have been defined as register asm ("x").  */
 break;
}
    else if (DEBUG_INSN_P (object)(((enum rtx_code) (object)->code) == DEBUG_INSN))
continue;
    else if (insn_invalid_p (as_a <rtx_insn *> (object), true))
{
 rtx pat = PATTERN (object);

 /* Perhaps we couldn't recognize the insn because there were
    extra CLOBBERs at the end.  If so, try to re-recognize
    without the last CLOBBER (later iterations will cause each of
    them to be eliminated, in turn).  But don't do this if we
    have an ASM_OPERAND.  */
 if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL
     && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1))((enum rtx_code) ((((((pat)->u.fld[0]).rt_rtvec))->elem
[(((((pat)->u.fld[0]).rt_rtvec))->num_elem) - 1]))->
code) == CLOBBER
     && asm_noperands (PATTERN (object)) < 0)
   {
     rtx newpat;

     if (XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem) == 2)
newpat = XVECEXP (pat, 0, 0)(((((pat)->u.fld[0]).rt_rtvec))->elem[0]);
     else
{
  int j;

  newpat
    = gen_rtx_PARALLEL (VOIDmode,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(rtvec_alloc ((((((pat)->u.fld[0]).rt_rtvec))->num_elem
) - 1))) )
			rtvec_alloc (XVECLEN (pat, 0) - 1))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(rtvec_alloc ((((((pat)->u.fld[0]).rt_rtvec))->num_elem
) - 1))) );
  for (j = 0; j < XVECLEN (newpat, 0)(((((newpat)->u.fld[0]).rt_rtvec))->num_elem); j++)
    XVECEXP (newpat, 0, j)(((((newpat)->u.fld[0]).rt_rtvec))->elem[j]) = XVECEXP (pat, 0, j)(((((pat)->u.fld[0]).rt_rtvec))->elem[j]);
}

     /* Add a new change to this group to replace the pattern
 with this new pattern.  Then consider this change
 as having succeeded.  The change we added will
 cause the entire call to fail if things remain invalid.

 Note that this can lose if a later change than the one
 we are processing specified &XVECEXP (PATTERN (object), 0, X)
 but this shouldn't occur.  */

     validate_change (object, &PATTERN (object), newpat, 1);
     continue;
   }
 else if (GET_CODE (pat)((enum rtx_code) (pat)->code) == USE || GET_CODE (pat)((enum rtx_code) (pat)->code) == CLOBBER
   || GET_CODE (pat)((enum rtx_code) (pat)->code) == VAR_LOCATION)
   /* If this insn is a CLOBBER or USE, it is always valid, but is
      never recognized.  */
   continue;
 else
   break;
}
    last_validated = object;
  }

return (i == num_changes);
521}

523/* A group of changes has previously been issued with validate_change
 and verified with verify_changes.  Call df_insn_rescan for each of
 the insn changed and clear num_changes.  */

527void
528confirm_change_group (void)
529{
int i;
rtx last_object = NULLnullptr;

gcc_assert (temporarily_undone_changes == 0)((void)(!(temporarily_undone_changes == 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 533, __FUNCTION__), 0 : 0));
for (i = 0; i < num_changes; i++)
  {
    rtx object = changes[i].object;

    if (changes[i].unshare)
*changes[i].loc = copy_rtx (*changes[i].loc);

    /* Avoid unnecessary rescanning when multiple changes to same instruction
       are made.  */
    if (object)
{
 if (object != last_object && last_object && INSN_P (last_object)(((((enum rtx_code) (last_object)->code) == INSN) || (((enum
 rtx_code) (last_object)->code) == JUMP_INSN) || (((enum rtx_code
) (last_object)->code) == CALL_INSN)) || (((enum rtx_code)
 (last_object)->code) == DEBUG_INSN)))
   df_insn_rescan (as_a <rtx_insn *> (last_object));
 last_object = object;
}
  }

if (last_object && INSN_P (last_object)(((((enum rtx_code) (last_object)->code) == INSN) || (((enum
 rtx_code) (last_object)->code) == JUMP_INSN) || (((enum rtx_code
) (last_object)->code) == CALL_INSN)) || (((enum rtx_code)
 (last_object)->code) == DEBUG_INSN)))
  df_insn_rescan (as_a <rtx_insn *> (last_object));
num_changes = 0;
554}

556/* Apply a group of changes previously issued with `validate_change'.
 If all changes are valid, call confirm_change_group and return 1,
 otherwise, call cancel_changes and return 0.  */

560int
561apply_change_group (void)
562{
if (verify_changes (0))
  {
    confirm_change_group ();
    return 1;
  }
else
  {
    cancel_changes (0);
    return 0;
  }
573}


576/* Return the number of changes so far in the current group.  */

578int
579num_validated_changes (void)
580{
return num_changes;
582}

584/* Retract the changes numbered NUM and up.  */

586void
587cancel_changes (int num)
588{
gcc_assert (temporarily_undone_changes == 0)((void)(!(temporarily_undone_changes == 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 589, __FUNCTION__), 0 : 0));
int i;

/* Back out all the changes.  Do this in the opposite order in which
   they were made.  */
for (i = num_changes - 1; i >= num; i--)
  {
    if (changes[i].old_len >= 0)
XVECLEN (*changes[i].loc, 0)(((((*changes[i].loc)->u.fld[0]).rt_rtvec))->num_elem) = changes[i].old_len;
    else
*changes[i].loc = changes[i].old;
    if (changes[i].object && !MEM_P (changes[i].object)(((enum rtx_code) (changes[i].object)->code) == MEM))
INSN_CODE (changes[i].object)(((changes[i].object)->u.fld[5]).rt_int) = changes[i].old_code;
  }
num_changes = num;
604}

606/* Swap the status of change NUM from being applied to not being applied,
 or vice versa.  */

609static void
610swap_change (int num)
611{
if (changes[num].old_len >= 0)
  std::swap (XVECLEN (*changes[num].loc, 0)(((((*changes[num].loc)->u.fld[0]).rt_rtvec))->num_elem
), changes[num].old_len);
else
  std::swap (*changes[num].loc, changes[num].old);
if (changes[num].object && !MEM_P (changes[num].object)(((enum rtx_code) (changes[num].object)->code) == MEM))
  std::swap (INSN_CODE (changes[num].object)(((changes[num].object)->u.fld[5]).rt_int), changes[num].old_code);
618}

620/* Temporarily undo all the changes numbered NUM and up, with a view
 to reapplying them later.  The next call to the changes machinery
 must be:

    redo_changes (NUM)

 otherwise things will end up in an invalid state.  */

628void
629temporarily_undo_changes (int num)
630{
gcc_assert (temporarily_undone_changes == 0 && num <= num_changes)((void)(!(temporarily_undone_changes == 0 && num <=
 num_changes) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 631, __FUNCTION__), 0 : 0));
for (int i = num_changes - 1; i >= num; i--)
  swap_change (i);
temporarily_undone_changes = num_changes - num;
635}

637/* Redo the changes that were temporarily undone by:

    temporarily_undo_changes (NUM).  */

641void
642redo_changes (int num)
643{
gcc_assert (temporarily_undone_changes == num_changes - num)((void)(!(temporarily_undone_changes == num_changes - num) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 644, __FUNCTION__), 0 : 0));
for (int i = num; i < num_changes; ++i)
  swap_change (i);
temporarily_undone_changes = 0;
648}

650/* Reduce conditional compilation elsewhere.  */
651/* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
 rtx.  */

654static void
655simplify_while_replacing (rtx *loc, rtx to, rtx_insn *object,
                        machine_mode op0_mode)
657{
rtx x = *loc;
enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
rtx new_rtx = NULL_RTX(rtx) 0;
scalar_int_mode is_mode;

if (SWAPPABLE_OPERANDS_P (x)((1 << (rtx_class[(int) (((enum rtx_code) (x)->code)
)])) & ((1 << RTX_COMM_ARITH) | (1 << RTX_COMM_COMPARE
) | (1 << RTX_COMPARE)))
    && swap_commutative_operands_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
  {
    validate_unshare_change (object, loc,
	       gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x) ? codegen_rtx_fmt_ee_stat ((((rtx_class[(int) (((enum rtx_code) (x)
->code))]) == RTX_COMM_ARITH) ? code : swap_condition (code
)), (((machine_mode) (x)->mode)), ((((x)->u.fld[1]).rt_rtx
)), ((((x)->u.fld[0]).rt_rtx)) )
			       : swap_condition (code),gen_rtx_fmt_ee_stat ((((rtx_class[(int) (((enum rtx_code) (x)
->code))]) == RTX_COMM_ARITH) ? code : swap_condition (code
)), (((machine_mode) (x)->mode)), ((((x)->u.fld[1]).rt_rtx
)), ((((x)->u.fld[0]).rt_rtx)) )
			       GET_MODE (x), XEXP (x, 1),gen_rtx_fmt_ee_stat ((((rtx_class[(int) (((enum rtx_code) (x)
->code))]) == RTX_COMM_ARITH) ? code : swap_condition (code
)), (((machine_mode) (x)->mode)), ((((x)->u.fld[1]).rt_rtx
)), ((((x)->u.fld[0]).rt_rtx)) )
			       XEXP (x, 0))gen_rtx_fmt_ee_stat ((((rtx_class[(int) (((enum rtx_code) (x)
->code))]) == RTX_COMM_ARITH) ? code : swap_condition (code
)), (((machine_mode) (x)->mode)), ((((x)->u.fld[1]).rt_rtx
)), ((((x)->u.fld[0]).rt_rtx)) ), 1);
    x = *loc;
    code = GET_CODE (x)((enum rtx_code) (x)->code);
  }

/* Canonicalize arithmetics with all constant operands.  */
switch (GET_RTX_CLASS (code)(rtx_class[(int) (code)]))
  {
  case RTX_UNARY:
    if (CONSTANT_P (XEXP (x, 0))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
new_rtx = simplify_unary_operation (code, GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx),
			    op0_mode);
    break;
  case RTX_COMM_ARITH:
  case RTX_BIN_ARITH:
    if (CONSTANT_P (XEXP (x, 0))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ) && CONSTANT_P (XEXP (x, 1))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
new_rtx = simplify_binary_operation (code, GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx),
			     XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));
    break;
  case RTX_COMPARE:
  case RTX_COMM_COMPARE:
    if (CONSTANT_P (XEXP (x, 0))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ) && CONSTANT_P (XEXP (x, 1))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
new_rtx = simplify_relational_operation (code, GET_MODE (x)((machine_mode) (x)->mode), op0_mode,
				 XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));
    break;
  default:
    break;
  }
if (new_rtx)
  {
    validate_change (object, loc, new_rtx, 1);
    return;
  }

switch (code)
  {
  case PLUS:
    /* If we have a PLUS whose second operand is now a CONST_INT, use
       simplify_gen_binary to try to simplify it.
       ??? We may want later to remove this, once simplification is
       separated from this function.  */
    if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
) && XEXP (x, 1)(((x)->u.fld[1]).rt_rtx) == to)
validate_change (object, loc,
	 simplify_gen_binary
	 (PLUS, GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)), 1);
    break;
  case MINUS:
    if (CONST_SCALAR_INT_P (XEXP (x, 1))((((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) ==
 CONST_INT) || (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx)
)->code) == CONST_WIDE_INT)))
validate_change (object, loc,
	 simplify_gen_binary
	 (PLUS, GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx),
	  simplify_gen_unary (NEG,
			      GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx),
			      GET_MODE (x)((machine_mode) (x)->mode))), 1);
    break;
  case ZERO_EXTEND:
  case SIGN_EXTEND:
    if (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) == VOIDmode((void) 0, E_VOIDmode))
{
 new_rtx = simplify_gen_unary (code, GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx),
		    op0_mode);
 /* If any of the above failed, substitute in something that
    we know won't be recognized.  */
 if (!new_rtx)
   new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx)gen_rtx_fmt_e_stat ((CLOBBER), ((((machine_mode) (x)->mode
))), (((const_int_rtx[64]))) );
 validate_change (object, loc, new_rtx, 1);
}
    break;
  case SUBREG:
    /* All subregs possible to simplify should be simplified.  */
    new_rtx = simplify_subreg (GET_MODE (x)((machine_mode) (x)->mode), SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), op0_mode,
	     SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg));

    /* Subregs of VOIDmode operands are incorrect.  */
    if (!new_rtx && GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) == VOIDmode((void) 0, E_VOIDmode))
new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx)gen_rtx_fmt_e_stat ((CLOBBER), ((((machine_mode) (x)->mode
))), (((const_int_rtx[64]))) );
    if (new_rtx)
validate_change (object, loc, new_rtx, 1);
    break;
  case ZERO_EXTRACT:
  case SIGN_EXTRACT:
    /* If we are replacing a register with memory, try to change the memory
       to be the mode required for memory in extract operations (this isn't
       likely to be an insertion operation; if it was, nothing bad will
       happen, we might just fail in some cases).  */

    if (MEM_P (XEXP (x, 0))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == MEM
)
 && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode), &is_mode)
 && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
 && CONST_INT_P (XEXP (x, 2))(((enum rtx_code) ((((x)->u.fld[2]).rt_rtx))->code) == CONST_INT
)
 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0)((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx),
			MEM_ADDR_SPACE (XEXP (x, 0))(get_mem_attrs ((((x)->u.fld[0]).rt_rtx))->addrspace))
 && !MEM_VOLATILE_P (XEXP (x, 0))(__extension__ ({ __typeof (((((x)->u.fld[0]).rt_rtx))) const
 _rtx = (((((x)->u.fld[0]).rt_rtx))); if (((enum rtx_code)
 (_rtx)->code) != MEM && ((enum rtx_code) (_rtx)->
code) != ASM_OPERANDS && ((enum rtx_code) (_rtx)->
code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P", _rtx
, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 762, __FUNCTION__); _rtx; })->volatil))
{
 int pos = INTVAL (XEXP (x, 2))(((((x)->u.fld[2]).rt_rtx))->u.hwint[0]);
 machine_mode new_mode = is_mode;
 if (GET_CODE (x)((enum rtx_code) (x)->code) == ZERO_EXTRACT && targetm.have_extzv ())
   new_mode = insn_data[targetm.code_for_extzv].operand[1].mode;
 else if (GET_CODE (x)((enum rtx_code) (x)->code) == SIGN_EXTRACT && targetm.have_extv ())
   new_mode = insn_data[targetm.code_for_extv].operand[1].mode;
 scalar_int_mode wanted_mode = (new_mode == VOIDmode((void) 0, E_VOIDmode)
			 ? word_mode
			 : as_a <scalar_int_mode> (new_mode));

 /* If we have a narrower mode, we can do something.  */
 if (GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
   {
     int offset = pos / BITS_PER_UNIT(8);
     rtx newmem;

     /* If the bytes and bits are counted differently, we
        must adjust the offset.  */
     if (BYTES_BIG_ENDIAN0 != BITS_BIG_ENDIAN0)
offset =
  (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) -
   offset);

     gcc_assert (GET_MODE_PRECISION (wanted_mode)((void)(!(GET_MODE_PRECISION (wanted_mode) == GET_MODE_BITSIZE
 (wanted_mode)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 788, __FUNCTION__), 0 : 0))
	  == GET_MODE_BITSIZE (wanted_mode))((void)(!(GET_MODE_PRECISION (wanted_mode) == GET_MODE_BITSIZE
 (wanted_mode)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 788, __FUNCTION__), 0 : 0));
     pos %= GET_MODE_BITSIZE (wanted_mode);

     newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset)adjust_address_1 ((((x)->u.fld[0]).rt_rtx), wanted_mode, offset
, 0, 1, 0, 0);

     validate_change (object, &XEXP (x, 2)(((x)->u.fld[2]).rt_rtx), GEN_INT (pos)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (pos)), 1);
     validate_change (object, &XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), newmem, 1);
   }
}

    break;

  default:
    break;
  }
803}

805/* Replace every occurrence of FROM in X with TO.  Mark each change with
 validate_change passing OBJECT.  */

808static void
809validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx_insn *object,
                      bool simplify)
811{
int i, j;
const char *fmt;
rtx x = *loc;
enum rtx_code code;
machine_mode op0_mode = VOIDmode((void) 0, E_VOIDmode);
int prev_changes = num_changes;

if (!x)
  return;

code = GET_CODE (x)((enum rtx_code) (x)->code);
fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
if (fmt[0] == 'e')
  op0_mode = GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);

/* X matches FROM if it is the same rtx or they are both referring to the
   same register in the same mode.  Avoid calling rtx_equal_p unless the
   operands look similar.  */

if (x == from
    || (REG_P (x)(((enum rtx_code) (x)->code) == REG) && REG_P (from)(((enum rtx_code) (from)->code) == REG)
 && GET_MODE (x)((machine_mode) (x)->mode) == GET_MODE (from)((machine_mode) (from)->mode)
 && REGNO (x)(rhs_regno(x)) == REGNO (from)(rhs_regno(from)))
    || (GET_CODE (x)((enum rtx_code) (x)->code) == GET_CODE (from)((enum rtx_code) (from)->code) && GET_MODE (x)((machine_mode) (x)->mode) == GET_MODE (from)((machine_mode) (from)->mode)
 && rtx_equal_p (x, from)))
  {
    validate_unshare_change (object, loc, to, 1);
    return;
  }

/* Call ourself recursively to perform the replacements.
   We must not replace inside already replaced expression, otherwise we
   get infinite recursion for replacements like (reg X)->(subreg (reg X))
   so we must special case shared ASM_OPERANDS.  */

if (GET_CODE (x)((enum rtx_code) (x)->code) == PARALLEL)
  {
    for (j = XVECLEN (x, 0)(((((x)->u.fld[0]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
{
 if (j && GET_CODE (XVECEXP (x, 0, j))((enum rtx_code) ((((((x)->u.fld[0]).rt_rtvec))->elem[j
]))->code) == SET
     && GET_CODE (SET_SRC (XVECEXP (x, 0, j)))((enum rtx_code) (((((((((x)->u.fld[0]).rt_rtvec))->elem
[j]))->u.fld[1]).rt_rtx))->code) == ASM_OPERANDS)
   {
     /* Verify that operands are really shared.  */
     gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, 0)))((void)(!((((((((((((x)->u.fld[0]).rt_rtvec))->elem[0])
)->u.fld[1]).rt_rtx))->u.fld[3]).rt_rtvec) == (((((((((
((x)->u.fld[0]).rt_rtvec))->elem[j]))->u.fld[1]).rt_rtx
))->u.fld[3]).rt_rtvec)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 857, __FUNCTION__), 0 : 0))
	  == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP((void)(!((((((((((((x)->u.fld[0]).rt_rtvec))->elem[0])
)->u.fld[1]).rt_rtx))->u.fld[3]).rt_rtvec) == (((((((((
((x)->u.fld[0]).rt_rtvec))->elem[j]))->u.fld[1]).rt_rtx
))->u.fld[3]).rt_rtvec)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 857, __FUNCTION__), 0 : 0))
					      (x, 0, j))))((void)(!((((((((((((x)->u.fld[0]).rt_rtvec))->elem[0])
)->u.fld[1]).rt_rtx))->u.fld[3]).rt_rtvec) == (((((((((
((x)->u.fld[0]).rt_rtvec))->elem[j]))->u.fld[1]).rt_rtx
))->u.fld[3]).rt_rtvec)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 857, __FUNCTION__), 0 : 0));
     validate_replace_rtx_1 (&SET_DEST (XVECEXP (x, 0, j))((((((((x)->u.fld[0]).rt_rtvec))->elem[j]))->u.fld[0
]).rt_rtx),
		      from, to, object, simplify);
   }
 else
   validate_replace_rtx_1 (&XVECEXP (x, 0, j)(((((x)->u.fld[0]).rt_rtvec))->elem[j]), from, to, object,
                                  simplify);
}
  }
else
  for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
    {
if (fmt[i] == 'e')
 validate_replace_rtx_1 (&XEXP (x, i)(((x)->u.fld[i]).rt_rtx), from, to, object, simplify);
else if (fmt[i] == 'E')
 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
   validate_replace_rtx_1 (&XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), from, to, object,
                                  simplify);
    }

/* If we didn't substitute, there is nothing more to do.  */
if (num_changes == prev_changes)
  return;

/* ??? The regmove is no more, so is this aberration still necessary?  */
/* Allow substituted expression to have different mode.  This is used by
   regmove to change mode of pseudo register.  */
if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) != VOIDmode((void) 0, E_VOIDmode))
  op0_mode = GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);

/* Do changes needed to keep rtx consistent.  Don't do any other
   simplifications, as it is not our job.  */
if (simplify)
  simplify_while_replacing (loc, to, object, op0_mode);
891}

893/* Try replacing every occurrence of FROM in subexpression LOC of INSN
 with TO.  After all changes have been made, validate by seeing
 if INSN is still valid.  */

897int
898validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc)
899{
validate_replace_rtx_1 (loc, from, to, insn, true);
return apply_change_group ();
902}

904/* Try replacing every occurrence of FROM in INSN with TO.  After all
 changes have been made, validate by seeing if INSN is still valid.  */

907int
908validate_replace_rtx (rtx from, rtx to, rtx_insn *insn)
909{
validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
return apply_change_group ();
912}

914/* Try replacing every occurrence of FROM in WHERE with TO.  Assume that WHERE
 is a part of INSN.  After all changes have been made, validate by seeing if
 INSN is still valid.
 validate_replace_rtx (from, to, insn) is equivalent to
 validate_replace_rtx_part (from, to, &PATTERN (insn), insn).  */

920int
921validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn)
922{
validate_replace_rtx_1 (where, from, to, insn, true);
return apply_change_group ();
925}

927/* Same as above, but do not simplify rtx afterwards.  */
928int
929validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where,
		      rtx_insn *insn)
931{
validate_replace_rtx_1 (where, from, to, insn, false);
return apply_change_group ();

935}

937/* Try replacing every occurrence of FROM in INSN with TO.  This also
 will replace in REG_EQUAL and REG_EQUIV notes.  */

940void
941validate_replace_rtx_group (rtx from, rtx to, rtx_insn *insn)
942{
rtx note;
validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
for (note = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); note; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
  if (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_EQUAL
|| REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_EQUIV)
    validate_replace_rtx_1 (&XEXP (note, 0)(((note)->u.fld[0]).rt_rtx), from, to, insn, true);
949}

951/* Function called by note_uses to replace used subexpressions.  */
952struct validate_replace_src_data
953{
rtx from;			/* Old RTX */
rtx to;			/* New RTX */
rtx_insn *insn;			/* Insn in which substitution is occurring.  */
957};

959static void
960validate_replace_src_1 (rtx *x, void *data)
961{
struct validate_replace_src_data *d
  = (struct validate_replace_src_data *) data;

validate_replace_rtx_1 (x, d->from, d->to, d->insn, true);
966}

968/* Try replacing every occurrence of FROM in INSN with TO, avoiding
 SET_DESTs.  */

971void
972validate_replace_src_group (rtx from, rtx to, rtx_insn *insn)
973{
struct validate_replace_src_data d;

d.from = from;
d.to = to;
d.insn = insn;
note_uses (&PATTERN (insn), validate_replace_src_1, &d);
980}

982/* Try simplify INSN.
 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
 pattern and return true if something was simplified.  */

986bool
987validate_simplify_insn (rtx_insn *insn)
988{
int i;
rtx pat = NULLnullptr;
rtx newpat = NULLnullptr;

pat = PATTERN (insn);

if (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET)
  {
    newpat = simplify_rtx (SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx));
    if (newpat && !rtx_equal_p (SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx), newpat))
validate_change (insn, &SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx), newpat, 1);
    newpat = simplify_rtx (SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx));
    if (newpat && !rtx_equal_p (SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx), newpat))
validate_change (insn, &SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx), newpat, 1);
  }
else if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
  for (i = 0; i < XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
    {
rtx s = XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]);

if (GET_CODE (XVECEXP (pat, 0, i))((enum rtx_code) ((((((pat)->u.fld[0]).rt_rtvec))->elem
[i]))->code) == SET)
 {
   newpat = simplify_rtx (SET_SRC (s)(((s)->u.fld[1]).rt_rtx));
   if (newpat && !rtx_equal_p (SET_SRC (s)(((s)->u.fld[1]).rt_rtx), newpat))
     validate_change (insn, &SET_SRC (s)(((s)->u.fld[1]).rt_rtx), newpat, 1);
   newpat = simplify_rtx (SET_DEST (s)(((s)->u.fld[0]).rt_rtx));
   if (newpat && !rtx_equal_p (SET_DEST (s)(((s)->u.fld[0]).rt_rtx), newpat))
     validate_change (insn, &SET_DEST (s)(((s)->u.fld[0]).rt_rtx), newpat, 1);
 }
    }
return ((num_changes_pending () > 0) && (apply_change_group () > 0));
1020}

1022/* Try to process the address of memory expression MEM.  Return true on
 success; leave the caller to clean up on failure.  */

1025bool
1026insn_propagation::apply_to_mem_1 (rtx mem)
1027{
auto old_num_changes = num_validated_changes ();
mem_depth += 1;
bool res = apply_to_rvalue_1 (&XEXP (mem, 0)(((mem)->u.fld[0]).rt_rtx));
mem_depth -= 1;
if (!res)
  return false;

if (old_num_changes != num_validated_changes ()
    && should_check_mems
    && !check_mem (old_num_changes, mem))
  return false;

return true;
1041}

1043/* Try to process the rvalue expression at *LOC.  Return true on success;
 leave the caller to clean up on failure.  */

1046bool
1047insn_propagation::apply_to_rvalue_1 (rtx *loc)
1048{
rtx x = *loc;
enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
machine_mode mode = GET_MODE (x)((machine_mode) (x)->mode);

auto old_num_changes = num_validated_changes ();
if (from && GET_CODE (x)((enum rtx_code) (x)->code) == GET_CODE (from)((enum rtx_code) (from)->code) && rtx_equal_p (x, from))
  {
    /* Don't replace register asms in asm statements; we mustn't
change the user's register allocation.  */
    if (REG_P (x)(((enum rtx_code) (x)->code) == REG)
 && HARD_REGISTER_P (x)((((rhs_regno(x))) < 76))
 && register_asm_p (x)
 && asm_noperands (PATTERN (insn)) > 0)
return false;

    if (should_unshare)
validate_unshare_change (insn, loc, to, 1);
    else
validate_change (insn, loc, to, 1);
    if (mem_depth && !REG_P (to)(((enum rtx_code) (to)->code) == REG) && !CONSTANT_P (to)((rtx_class[(int) (((enum rtx_code) (to)->code))]) == RTX_CONST_OBJ
))
{
 /* We're substituting into an address, but TO will have the
    form expected outside an address.  Canonicalize it if
    necessary.  */
 insn_propagation subprop (insn);
 subprop.mem_depth += 1;
 if (!subprop.apply_to_rvalue (loc))
   gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 1076, __FUNCTION__));
 if (should_unshare
     && num_validated_changes () != old_num_changes + 1)
   {
     /* TO is owned by someone else, so create a copy and
 return TO to its original form.  */
     rtx to = copy_rtx (*loc);
     cancel_changes (old_num_changes);
     validate_change (insn, loc, to, 1);
   }
}
    num_replacements += 1;
    should_unshare = true;
    result_flags |= UNSIMPLIFIED;
    return true;
  }

/* Recursively apply the substitution and see if we can simplify
   the result.  This specifically shouldn't use simplify_gen_* for
   speculative simplifications, since we want to avoid generating new
   expressions where possible.  */
auto old_result_flags = result_flags;
rtx newx = NULL_RTX(rtx) 0;
bool recurse_p = false;
switch (GET_RTX_CLASS (code)(rtx_class[(int) (code)]))
  {
  case RTX_UNARY:
    {
machine_mode op0_mode = GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
if (!apply_to_rvalue_1 (&XEXP (x, 0)(((x)->u.fld[0]).rt_rtx)))
 return false;
if (from && old_num_changes == num_validated_changes ())
 return true;

newx = simplify_unary_operation (code, mode, XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), op0_mode);
break;
    }

  case RTX_BIN_ARITH:
  case RTX_COMM_ARITH:
    {
if (!apply_to_rvalue_1 (&XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
   || !apply_to_rvalue_1 (&XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
 return false;
if (from && old_num_changes == num_validated_changes ())
 return true;

if (GET_RTX_CLASS (code)(rtx_class[(int) (code)]) == RTX_COMM_ARITH
   && swap_commutative_operands_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
 newx = simplify_gen_binary (code, mode, XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));
else
 newx = simplify_binary_operation (code, mode,
			    XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));
break;
    }

  case RTX_COMPARE:
  case RTX_COMM_COMPARE:
    {
machine_mode op_mode = (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) != VOIDmode((void) 0, E_VOIDmode)
		? GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode)
		: GET_MODE (XEXP (x, 1))((machine_mode) ((((x)->u.fld[1]).rt_rtx))->mode));
if (!apply_to_rvalue_1 (&XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
   || !apply_to_rvalue_1 (&XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
 return false;
if (from && old_num_changes == num_validated_changes ())
 return true;

newx = simplify_relational_operation (code, mode, op_mode,
			      XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));
break;
    }

  case RTX_TERNARY:
  case RTX_BITFIELD_OPS:
    {
machine_mode op0_mode = GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
if (!apply_to_rvalue_1 (&XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
   || !apply_to_rvalue_1 (&XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
   || !apply_to_rvalue_1 (&XEXP (x, 2)(((x)->u.fld[2]).rt_rtx)))
 return false;
if (from && old_num_changes == num_validated_changes ())
 return true;

newx = simplify_ternary_operation (code, mode, op0_mode,
			   XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx),
			   XEXP (x, 2)(((x)->u.fld[2]).rt_rtx));
break;
    }

  case RTX_EXTRA:
    if (code == SUBREG)
{
 machine_mode inner_mode = GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
 if (!apply_to_rvalue_1 (&SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx)))
   return false;
 if (from && old_num_changes == num_validated_changes ())
   return true;

 rtx inner = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
 newx = simplify_subreg (mode, inner, inner_mode, SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg));
 /* Reject the same cases that simplify_gen_subreg would.  */
 if (!newx
     && (GET_CODE (inner)((enum rtx_code) (inner)->code) == SUBREG
  || GET_CODE (inner)((enum rtx_code) (inner)->code) == CONCAT
  || GET_MODE (inner)((machine_mode) (inner)->mode) == VOIDmode((void) 0, E_VOIDmode)
  || !validate_subreg (mode, inner_mode,
		       inner, SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg))))
   {
     failure_reason = "would create an invalid subreg";
     return false;
   }
 break;
}
    else
recurse_p = true;
    break;

  case RTX_OBJ:
    if (code == LO_SUM)
{
 if (!apply_to_rvalue_1 (&XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
     || !apply_to_rvalue_1 (&XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
   return false;
 if (from && old_num_changes == num_validated_changes ())
   return true;

 /* (lo_sum (high x) y) -> y where x and y have the same base.  */
 rtx op0 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
 rtx op1 = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);
 if (GET_CODE (op0)((enum rtx_code) (op0)->code) == HIGH)
   {
     rtx base0, base1, offset0, offset1;
     split_const (XEXP (op0, 0)(((op0)->u.fld[0]).rt_rtx), &base0, &offset0);
     split_const (op1, &base1, &offset1);
     if (rtx_equal_p (base0, base1))
newx = op1;
   }
}
    else if (code == REG)
{
 if (from && REG_P (from)(((enum rtx_code) (from)->code) == REG) && reg_overlap_mentioned_p (x, from))
   {
     failure_reason = "inexact register overlap";
     return false;
   }
}
    else if (code == MEM)
return apply_to_mem_1 (x);
    else
recurse_p = true;
    break;

  case RTX_CONST_OBJ:
    break;

  case RTX_AUTOINC:
    if (from && reg_overlap_mentioned_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), from))
{
 failure_reason = "is subject to autoinc";
 return false;
}
    recurse_p = true;
    break;

  case RTX_MATCH:
  case RTX_INSN:
    gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 1243, __FUNCTION__));
  }

if (recurse_p)
  {
    const char *fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
    for (int i = 0; fmt[i]; i++)
switch (fmt[i])
 {
 case 'E':
   for (int j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
     if (!apply_to_rvalue_1 (&XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
return false;
   break;

 case 'e':
   if (XEXP (x, i)(((x)->u.fld[i]).rt_rtx) && !apply_to_rvalue_1 (&XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
     return false;
   break;
 }
  }
else if (newx && !rtx_equal_p (x, newx))
  {
    /* All substitutions made by OLD_NUM_CHANGES onwards have been
simplified.  */
    result_flags = ((result_flags & ~UNSIMPLIFIED)
      | (old_result_flags & UNSIMPLIFIED));

    if (should_note_simplifications)
note_simplification (old_num_changes, old_result_flags, x, newx);

    /* There's no longer any point unsharing the substitutions made
for subexpressions, since we'll just copy this one instead.  */
    bool unshare = false;
    for (int i = old_num_changes; i < num_changes; ++i)
{
 unshare |= changes[i].unshare;
 changes[i].unshare = false;
}
    if (unshare)
validate_unshare_change (insn, loc, newx, 1);
    else
validate_change (insn, loc, newx, 1);
  }

return true;
1289}

1291/* Try to process the lvalue expression at *LOC.  Return true on success;
 leave the caller to clean up on failure.  */

1294bool
1295insn_propagation::apply_to_lvalue_1 (rtx dest)
1296{
rtx old_dest = dest;
while (GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG
|| GET_CODE (dest)((enum rtx_code) (dest)->code) == ZERO_EXTRACT
|| GET_CODE (dest)((enum rtx_code) (dest)->code) == STRICT_LOW_PART)
  {
    if (GET_CODE (dest)((enum rtx_code) (dest)->code) == ZERO_EXTRACT
 && (!apply_to_rvalue_1 (&XEXP (dest, 1)(((dest)->u.fld[1]).rt_rtx))
     || !apply_to_rvalue_1 (&XEXP (dest, 2)(((dest)->u.fld[2]).rt_rtx))))
return false;
    dest = XEXP (dest, 0)(((dest)->u.fld[0]).rt_rtx);
  }

if (MEM_P (dest)(((enum rtx_code) (dest)->code) == MEM))
  return apply_to_mem_1 (dest);

/* Check whether the substitution is safe in the presence of this lvalue.  */
if (!from
    || dest == old_dest
    || !REG_P (dest)(((enum rtx_code) (dest)->code) == REG)
    || !reg_overlap_mentioned_p (dest, from))
  return true;

if (SUBREG_P (old_dest)(((enum rtx_code) (old_dest)->code) == SUBREG)
    && SUBREG_REG (old_dest)(((old_dest)->u.fld[0]).rt_rtx) == dest
    && !read_modify_subreg_p (old_dest))
  return true;

failure_reason = "is part of a read-write destination";
return false;
1326}

1328/* Try to process the instruction pattern at *LOC.  Return true on success;
 leave the caller to clean up on failure.  */

1331bool
1332insn_propagation::apply_to_pattern_1 (rtx *loc)
1333{
rtx body = *loc;
switch (GET_CODE (body)((enum rtx_code) (body)->code))
  {
  case COND_EXEC:
    return (apply_to_rvalue_1 (&COND_EXEC_TEST (body)(((body)->u.fld[0]).rt_rtx))
     && apply_to_pattern_1 (&COND_EXEC_CODE (body)(((body)->u.fld[1]).rt_rtx)));

  case PARALLEL:
    {
int last = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1;
for (int i = 0; i < last; ++i)
 if (!apply_to_pattern_1 (&XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i])))
   return false;
return apply_to_pattern_1 (&XVECEXP (body, 0, last)(((((body)->u.fld[0]).rt_rtvec))->elem[last]));
    }

  case ASM_OPERANDS:
    for (int i = 0, len = ASM_OPERANDS_INPUT_LENGTH (body)(((((body)->u.fld[3]).rt_rtvec))->num_elem); i < len; ++i)
if (!apply_to_rvalue_1 (&ASM_OPERANDS_INPUT (body, i)(((((body)->u.fld[3]).rt_rtvec))->elem[i])))
 return false;
    return true;

  case CLOBBER:
    return apply_to_lvalue_1 (XEXP (body, 0)(((body)->u.fld[0]).rt_rtx));

  case SET:
    return (apply_to_lvalue_1 (SET_DEST (body)(((body)->u.fld[0]).rt_rtx))
     && apply_to_rvalue_1 (&SET_SRC (body)(((body)->u.fld[1]).rt_rtx)));

  default:
    /* All the other possibilities never store and can use a normal
rtx walk.  This includes:

- USE
- TRAP_IF
- PREFETCH
- UNSPEC
- UNSPEC_VOLATILE.  */
    return apply_to_rvalue_1 (loc);
  }
1374}

1376/* Apply this insn_propagation object's simplification or substitution
 to the instruction pattern at LOC.  */

1379bool
1380insn_propagation::apply_to_pattern (rtx *loc)
1381{
unsigned int num_changes = num_validated_changes ();
bool res = apply_to_pattern_1 (loc);
if (!res)
  cancel_changes (num_changes);
return res;
1387}

1389/* Apply this insn_propagation object's simplification or substitution
 to the rvalue expression at LOC.  */

1392bool
1393insn_propagation::apply_to_rvalue (rtx *loc)
1394{
unsigned int num_changes = num_validated_changes ();
bool res = apply_to_rvalue_1 (loc);
if (!res)
  cancel_changes (num_changes);
return res;
1400}

1402/* Check whether INSN matches a specific alternative of an .md pattern.  */

1404bool
1405valid_insn_p (rtx_insn *insn)
1406{
recog_memoized (insn);
if (INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) < 0)
  return false;
extract_insn (insn);
/* We don't know whether the insn will be in code that is optimized
   for size or speed, so consider all enabled alternatives.  */
if (!constrain_operands (1, get_enabled_alternatives (insn)))
  return false;
return true;
1416}

1418/* Return true if OP is a valid general operand for machine mode MODE.
 This is either a register reference, a memory reference,
 or a constant.  In the case of a memory reference, the address
 is checked for general validity for the target machine.

 Register and memory references must have mode MODE in order to be valid,
 but some constants have no machine mode and are valid for any mode.

 If MODE is VOIDmode, OP is checked for validity for whatever mode
 it has.

 The main use of this function is as a predicate in match_operand
 expressions in the machine description.  */

1432bool
1433general_operand (rtx op, machine_mode mode)
1434{
enum rtx_code code = GET_CODE (op)((enum rtx_code) (op)->code);

if (mode == VOIDmode((void) 0, E_VOIDmode))
  mode = GET_MODE (op)((machine_mode) (op)->mode);

/* Don't accept CONST_INT or anything similar
   if the caller wants something floating.  */
if (GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode) && mode != VOIDmode((void) 0, E_VOIDmode)
    && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_INT
    && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_PARTIAL_INT)
  return false;

if (CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT)
    && mode != VOIDmode((void) 0, E_VOIDmode)
    && trunc_int_for_mode (INTVAL (op)((op)->u.hwint[0]), mode) != INTVAL (op)((op)->u.hwint[0]))
  return false;

if (CONSTANT_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ
))
  return ((GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode) || GET_MODE (op)((machine_mode) (op)->mode) == mode
    || mode == VOIDmode((void) 0, E_VOIDmode))
   && (! flag_picglobal_options.x_flag_pic || LEGITIMATE_PIC_OPERAND_P (op)legitimate_pic_operand_p (op))
   && targetm.legitimate_constant_p (mode == VOIDmode((void) 0, E_VOIDmode)
			      ? GET_MODE (op)((machine_mode) (op)->mode)
			      : mode, op));

/* Except for certain constants with VOIDmode, already checked for,
   OP's mode must match MODE if MODE specifies a mode.  */

if (GET_MODE (op)((machine_mode) (op)->mode) != mode)
  return false;

if (code == SUBREG)
  {
    rtx sub = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);

1470#ifdef INSN_SCHEDULING
    /* On machines that have insn scheduling, we want all memory
reference to be explicit, so outlaw paradoxical SUBREGs.
However, we must allow them after reload so that they can
get cleaned up by cleanup_subreg_operands.  */
    if (!reload_completed && MEM_P (sub)(((enum rtx_code) (sub)->code) == MEM)
 && paradoxical_subreg_p (op))
return false;
1478#endif
    /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
       may result in incorrect reference.  We should simplify all valid
       subregs of MEM anyway.  But allow this after reload because we
might be called from cleanup_subreg_operands.

??? This is a kludge.  */
    if (!reload_completed
 && maybe_ne (SUBREG_BYTE (op)(((op)->u.fld[1]).rt_subreg), 0)
 && MEM_P (sub)(((enum rtx_code) (sub)->code) == MEM))
return false;

    if (REG_P (sub)(((enum rtx_code) (sub)->code) == REG)
 && REGNO (sub)(rhs_regno(sub)) < FIRST_PSEUDO_REGISTER76
 && !REG_CAN_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)(targetm.can_change_mode_class (((machine_mode) (sub)->mode
), mode, (regclass_map[((rhs_regno(sub)))])))
 && GET_MODE_CLASS (GET_MODE (sub))((enum mode_class) mode_class[((machine_mode) (sub)->mode)
]) != MODE_COMPLEX_INT
 && GET_MODE_CLASS (GET_MODE (sub))((enum mode_class) mode_class[((machine_mode) (sub)->mode)
]) != MODE_COMPLEX_FLOAT
 /* LRA can generate some invalid SUBREGS just for matched
    operand reload presentation.  LRA needs to treat them as
    valid.  */
 && ! LRA_SUBREG_P (op)(__extension__ ({ __typeof ((op)) const _rtx = ((op)); if (((
enum rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag
 ("LRA_SUBREG_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 1498, __FUNCTION__); _rtx; })->jump))
return false;

    /* FLOAT_MODE subregs can't be paradoxical.  Combine will occasionally
create such rtl, and we must reject it.  */
    if (SCALAR_FLOAT_MODE_P (GET_MODE (op))(((enum mode_class) mode_class[((machine_mode) (op)->mode)
]) == MODE_FLOAT || ((enum mode_class) mode_class[((machine_mode
) (op)->mode)]) == MODE_DECIMAL_FLOAT)
 /* LRA can use subreg to store a floating point value in an
    integer mode.  Although the floating point and the
    integer modes need the same number of hard registers, the
    size of floating point mode can be less than the integer
    mode.  */
 && ! lra_in_progress 
 && paradoxical_subreg_p (op))
return false;

    op = sub;
    code = GET_CODE (op)((enum rtx_code) (op)->code);
  }

if (code == REG)
  return (REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76
   || in_hard_reg_set_p (operand_reg_set(this_target_hard_regs->x_operand_reg_set), GET_MODE (op)((machine_mode) (op)->mode), REGNO (op)(rhs_regno(op))));

if (code == MEM)
  {
    rtx y = XEXP (op, 0)(((op)->u.fld[0]).rt_rtx);

    if (! volatile_ok && MEM_VOLATILE_P (op)(__extension__ ({ __typeof ((op)) const _rtx = ((op)); if (((
enum rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 1525, __FUNCTION__); _rtx; })->volatil))
return false;

    /* Use the mem's mode, since it will be reloaded thus.  LRA can
generate move insn with invalid addresses which is made valid
and efficiently calculated by LRA through further numerous
transformations.  */
    if (lra_in_progress
 || memory_address_addr_space_p (GET_MODE (op)((machine_mode) (op)->mode), y, MEM_ADDR_SPACE (op)(get_mem_attrs (op)->addrspace)))
return true;
  }

return false;
1538}
1539
1540/* Return true if OP is a valid memory address for a memory reference
 of mode MODE.

 The main use of this function is as a predicate in match_operand
 expressions in the machine description.  */

1546bool
1547address_operand (rtx op, machine_mode mode)
1548{
/* Wrong mode for an address expr.  */
if (GET_MODE (op)((machine_mode) (op)->mode) != VOIDmode((void) 0, E_VOIDmode)
    && ! SCALAR_INT_MODE_P (GET_MODE (op))(((enum mode_class) mode_class[((machine_mode) (op)->mode)
]) == MODE_INT || ((enum mode_class) mode_class[((machine_mode
) (op)->mode)]) == MODE_PARTIAL_INT))
  return false;

return memory_address_p (mode, op)memory_address_addr_space_p ((mode), (op), 0);
1555}

1557/* Return true if OP is a register reference of mode MODE.
 If MODE is VOIDmode, accept a register in any mode.

 The main use of this function is as a predicate in match_operand
 expressions in the machine description.  */

1563bool
1564register_operand (rtx op, machine_mode mode)
1565{
if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG)
  {
    rtx sub = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);

    /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
because it is guaranteed to be reloaded into one.
Just make sure the MEM is valid in itself.
(Ideally, (SUBREG (MEM)...) should not exist after reload,
but currently it does result from (SUBREG (REG)...) where the
reg went on the stack.)  */
    if (!REG_P (sub)(((enum rtx_code) (sub)->code) == REG) && (reload_completed || !MEM_P (sub)(((enum rtx_code) (sub)->code) == MEM)))
return false;
  }
else if (!REG_P (op)(((enum rtx_code) (op)->code) == REG))
  return false;
return general_operand (op, mode);
1582}

1584/* Return true for a register in Pmode; ignore the tested mode.  */

1586bool
1587pmode_register_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED__attribute__ ((__unused__)))
1588{
return register_operand (op, Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))));
1590}

1592/* Return true if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
 or a hard register.  */

1595bool
1596scratch_operand (rtx op, machine_mode mode)
1597{
if (GET_MODE (op)((machine_mode) (op)->mode) != mode && mode != VOIDmode((void) 0, E_VOIDmode))
  return false;

return (GET_CODE (op)((enum rtx_code) (op)->code) == SCRATCH
 || (REG_P (op)(((enum rtx_code) (op)->code) == REG)
     && (lra_in_progress
  || (REGNO (op)(rhs_regno(op)) < FIRST_PSEUDO_REGISTER76
      && REGNO_REG_CLASS (REGNO (op))(regclass_map[((rhs_regno(op)))]) != NO_REGS))));
1606}

1608/* Return true if OP is a valid immediate operand for mode MODE.

 The main use of this function is as a predicate in match_operand
 expressions in the machine description.  */

1613bool
1614immediate_operand (rtx op, machine_mode mode)
1615{
/* Don't accept CONST_INT or anything similar
   if the caller wants something floating.  */
if (GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode) && mode != VOIDmode((void) 0, E_VOIDmode)
    && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_INT
    && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_PARTIAL_INT)
  return false;

if (CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT)
    && mode != VOIDmode((void) 0, E_VOIDmode)
    && trunc_int_for_mode (INTVAL (op)((op)->u.hwint[0]), mode) != INTVAL (op)((op)->u.hwint[0]))
  return false;

return (CONSTANT_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ
)
 && (GET_MODE (op)((machine_mode) (op)->mode) == mode || mode == VOIDmode((void) 0, E_VOIDmode)
     || GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode))
 && (! flag_picglobal_options.x_flag_pic || LEGITIMATE_PIC_OPERAND_P (op)legitimate_pic_operand_p (op))
 && targetm.legitimate_constant_p (mode == VOIDmode((void) 0, E_VOIDmode)
			    ? GET_MODE (op)((machine_mode) (op)->mode)
			    : mode, op));
1635}

1637/* Return true if OP is an operand that is a CONST_INT of mode MODE.  */

1639bool
1640const_int_operand (rtx op, machine_mode mode)
1641{
if (!CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT))
  return false;

if (mode != VOIDmode((void) 0, E_VOIDmode)
    && trunc_int_for_mode (INTVAL (op)((op)->u.hwint[0]), mode) != INTVAL (op)((op)->u.hwint[0]))
  return false;

return true;
1650}

1652#if TARGET_SUPPORTS_WIDE_INT1
1653/* Return true if OP is an operand that is a CONST_INT or CONST_WIDE_INT
 of mode MODE.  */
1655bool
1656const_scalar_int_operand (rtx op, machine_mode mode)
1657{
if (!CONST_SCALAR_INT_P (op)((((enum rtx_code) (op)->code) == CONST_INT) || (((enum rtx_code
) (op)->code) == CONST_WIDE_INT)))
  return false;

if (CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT))
  return const_int_operand (op, mode);

if (mode != VOIDmode((void) 0, E_VOIDmode))
  {
    scalar_int_mode int_mode = as_a <scalar_int_mode> (mode);
    int prec = GET_MODE_PRECISION (int_mode);
    int bitsize = GET_MODE_BITSIZE (int_mode);

    if (CONST_WIDE_INT_NUNITS (op)((int)__extension__ ({ __typeof ((op)) const _rtx = ((op)); if
 (((enum rtx_code) (_rtx)->code) != CONST_WIDE_INT) rtl_check_failed_flag
 ("CWI_GET_NUM_ELEM", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 1670, __FUNCTION__); _rtx; })->u2.num_elem) * HOST_BITS_PER_WIDE_INT64 > bitsize)
return false;

    if (prec == bitsize)
return true;
    else
{
 /* Multiword partial int.  */
 HOST_WIDE_INTlong x
   = CONST_WIDE_INT_ELT (op, CONST_WIDE_INT_NUNITS (op) - 1)((op)->u.hwiv.elem[((int)__extension__ ({ __typeof ((op)) const
 _rtx = ((op)); if (((enum rtx_code) (_rtx)->code) != CONST_WIDE_INT
) rtl_check_failed_flag ("CWI_GET_NUM_ELEM", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 1679, __FUNCTION__); _rtx; })->u2.num_elem) - 1]);
 return (sext_hwi (x, prec & (HOST_BITS_PER_WIDE_INT64 - 1)) == x);
}
  }
return true;
1684}

1686/* Return true if OP is an operand that is a constant integer or constant
 floating-point number of MODE.  */

1689bool
1690const_double_operand (rtx op, machine_mode mode)
1691{
return (GET_CODE (op)((enum rtx_code) (op)->code) == CONST_DOUBLE)
 && (GET_MODE (op)((machine_mode) (op)->mode) == mode || mode == VOIDmode((void) 0, E_VOIDmode));
1694}
1695#else
1696/* Return true if OP is an operand that is a constant integer or constant
 floating-point number of MODE.  */

1699bool
1700const_double_operand (rtx op, machine_mode mode)
1701{
/* Don't accept CONST_INT or anything similar
   if the caller wants something floating.  */
if (GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode) && mode != VOIDmode((void) 0, E_VOIDmode)
    && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_INT
    && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_PARTIAL_INT)
  return false;

return ((CONST_DOUBLE_P (op)(((enum rtx_code) (op)->code) == CONST_DOUBLE) || CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT))
 && (mode == VOIDmode((void) 0, E_VOIDmode) || GET_MODE (op)((machine_mode) (op)->mode) == mode
     || GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode)));
1712}
1713#endif
1714/* Return true if OP is a general operand that is not an immediate
 operand of mode MODE.  */

1717bool
1718nonimmediate_operand (rtx op, machine_mode mode)
1719{
return (general_operand (op, mode) && ! CONSTANT_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ
));
1721}

1723/* Return true if OP is a register reference or
 immediate value of mode MODE.  */

1726bool
1727nonmemory_operand (rtx op, machine_mode mode)
1728{
if (CONSTANT_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ
))
  return immediate_operand (op, mode);
return register_operand (op, mode);
1732}

1734/* Return true if OP is a valid operand that stands for pushing a
 value of mode MODE onto the stack.

 The main use of this function is as a predicate in match_operand
 expressions in the machine description.  */

1740bool
1741push_operand (rtx op, machine_mode mode)
1742{
if (!MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
  return false;

if (mode != VOIDmode((void) 0, E_VOIDmode) && GET_MODE (op)((machine_mode) (op)->mode) != mode)
  return false;

poly_int64 rounded_size = GET_MODE_SIZE (mode);

1751#ifdef PUSH_ROUNDING
rounded_size = PUSH_ROUNDING (MACRO_INT (rounded_size))ix86_push_rounding (((rounded_size).to_constant ()));
1753#endif

op = XEXP (op, 0)(((op)->u.fld[0]).rt_rtx);

if (known_eq (rounded_size, GET_MODE_SIZE (mode))(!maybe_ne (rounded_size, GET_MODE_SIZE (mode))))
  {
    if (GET_CODE (op)((enum rtx_code) (op)->code) != STACK_PUSH_CODEPRE_DEC)
return false;
  }
else
  {
    poly_int64 offset;
    if (GET_CODE (op)((enum rtx_code) (op)->code) != PRE_MODIFY
 || GET_CODE (XEXP (op, 1))((enum rtx_code) ((((op)->u.fld[1]).rt_rtx))->code) != PLUS
 || XEXP (XEXP (op, 1), 0)((((((op)->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx) != XEXP (op, 0)(((op)->u.fld[0]).rt_rtx)
 || !poly_int_rtx_p (XEXP (XEXP (op, 1), 1)((((((op)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx), &offset)
 || (STACK_GROWS_DOWNWARD1
     ? maybe_ne (offset, -rounded_size)
     : maybe_ne (offset, rounded_size)))
return false;
  }

return XEXP (op, 0)(((op)->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]);
1776}

1778/* Return true if OP is a valid operand that stands for popping a
 value of mode MODE off the stack.

 The main use of this function is as a predicate in match_operand
 expressions in the machine description.  */

1784bool
1785pop_operand (rtx op, machine_mode mode)
1786{
if (!MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
  return false;

if (mode != VOIDmode((void) 0, E_VOIDmode) && GET_MODE (op)((machine_mode) (op)->mode) != mode)
  return false;

op = XEXP (op, 0)(((op)->u.fld[0]).rt_rtx);

if (GET_CODE (op)((enum rtx_code) (op)->code) != STACK_POP_CODEPOST_INC)
  return false;

return XEXP (op, 0)(((op)->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]);
1799}

1801/* Return true if ADDR is a valid memory address
 for mode MODE in address space AS.  */

1804bool
1805memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED__attribute__ ((__unused__)),
	     rtx addr, addr_space_t as)
1807{
1808#ifdef GO_IF_LEGITIMATE_ADDRESS
gcc_assert (ADDR_SPACE_GENERIC_P (as))((void)(!(((as) == 0)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 1809, __FUNCTION__), 0 : 0));
GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
return false;

win:
return true;
1815#else
return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
1817#endif
1818}

1820/* Return true if OP is a valid memory reference with mode MODE,
 including a valid address.

 The main use of this function is as a predicate in match_operand
 expressions in the machine description.  */

1826bool
1827memory_operand (rtx op, machine_mode mode)
1828{
rtx inner;

if (! reload_completed)
  /* Note that no SUBREG is a memory operand before end of reload pass,
     because (SUBREG (MEM...)) forces reloading into a register.  */
  return MEM_P (op)(((enum rtx_code) (op)->code) == MEM) && general_operand (op, mode);

if (mode != VOIDmode((void) 0, E_VOIDmode) && GET_MODE (op)((machine_mode) (op)->mode) != mode)
  return false;

inner = op;
if (GET_CODE (inner)((enum rtx_code) (inner)->code) == SUBREG)
  inner = SUBREG_REG (inner)(((inner)->u.fld[0]).rt_rtx);

return (MEM_P (inner)(((enum rtx_code) (inner)->code) == MEM) && general_operand (op, mode));
1844}

1846/* Return true if OP is a valid indirect memory reference with mode MODE;
 that is, a memory reference whose address is a general_operand.  */

1849bool
1850indirect_operand (rtx op, machine_mode mode)
1851{
/* Before reload, a SUBREG isn't in memory (see memory_operand, above).  */
if (! reload_completed
    && GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG && MEM_P (SUBREG_REG (op))(((enum rtx_code) ((((op)->u.fld[0]).rt_rtx))->code) ==
 MEM))
  {
    if (mode != VOIDmode((void) 0, E_VOIDmode) && GET_MODE (op)((machine_mode) (op)->mode) != mode)
return false;

    /* The only way that we can have a general_operand as the resulting
address is if OFFSET is zero and the address already is an operand
or if the address is (plus Y (const_int -OFFSET)) and Y is an
operand.  */
    poly_int64 offset;
    rtx addr = strip_offset (XEXP (SUBREG_REG (op), 0)((((((op)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx), &offset);
    return (known_eq (offset + SUBREG_BYTE (op), 0)(!maybe_ne (offset + (((op)->u.fld[1]).rt_subreg), 0))
     && general_operand (addr, Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))));
  }

return (MEM_P (op)(((enum rtx_code) (op)->code) == MEM)
 && memory_operand (op, mode)
 && general_operand (XEXP (op, 0)(((op)->u.fld[0]).rt_rtx), Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))));
1872}

1874/* Return true if this is an ordered comparison operator (not including
 ORDERED and UNORDERED).  */

1877bool
1878ordered_comparison_operator (rtx op, machine_mode mode)
1879{
if (mode != VOIDmode((void) 0, E_VOIDmode) && GET_MODE (op)((machine_mode) (op)->mode) != mode)
  return false;
switch (GET_CODE (op)((enum rtx_code) (op)->code))
  {
  case EQ:
  case NE:
  case LT:
  case LTU:
  case LE:
  case LEU:
  case GT:
  case GTU:
  case GE:
  case GEU:
    return true;
  default:
    return false;
  }
1898}

1900/* Return true if this is a comparison operator.  This allows the use of
 MATCH_OPERATOR to recognize all the branch insns.  */

1903bool
1904comparison_operator (rtx op, machine_mode mode)
1905{
return ((mode == VOIDmode((void) 0, E_VOIDmode) || GET_MODE (op)((machine_mode) (op)->mode) == mode)
 && COMPARISON_P (op)(((rtx_class[(int) (((enum rtx_code) (op)->code))]) & (
~1)) == (RTX_COMPARE & (~1))));
1908}
1909
1910/* If BODY is an insn body that uses ASM_OPERANDS, return it.  */

1912rtx
1913extract_asm_operands (rtx body)
1914{
rtx tmp;
switch (GET_CODE (body)((enum rtx_code) (body)->code))
  {
  case ASM_OPERANDS:
    return body;

  case SET:
    /* Single output operand: BODY is (set OUTPUT (asm_operands ...)).  */
    tmp = SET_SRC (body)(((body)->u.fld[1]).rt_rtx);
    if (GET_CODE (tmp)((enum rtx_code) (tmp)->code) == ASM_OPERANDS)
return tmp;
    break;

  case PARALLEL:
    tmp = XVECEXP (body, 0, 0)(((((body)->u.fld[0]).rt_rtvec))->elem[0]);
    if (GET_CODE (tmp)((enum rtx_code) (tmp)->code) == ASM_OPERANDS)
return tmp;
    if (GET_CODE (tmp)((enum rtx_code) (tmp)->code) == SET)
{
 tmp = SET_SRC (tmp)(((tmp)->u.fld[1]).rt_rtx);
 if (GET_CODE (tmp)((enum rtx_code) (tmp)->code) == ASM_OPERANDS)
   return tmp;
}
    break;

  default:
    break;
  }
return NULLnullptr;
1944}

1946/* If BODY is an insn body that uses ASM_OPERANDS,
 return the number of operands (both input and output) in the insn.
 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
 return 0.
 Otherwise return -1.  */

1952int
1953asm_noperands (const_rtx body)
1954{
rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body)(const_cast<struct rtx_def *> (((body)))));
int i, n_sets = 0;

if (asm_op == NULLnullptr)
  {
    if (GET_CODE (body)((enum rtx_code) (body)->code) == PARALLEL && XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) >= 2
 && GET_CODE (XVECEXP (body, 0, 0))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[0]))->code) == ASM_INPUT)
{
 /* body is [(asm_input ...) (clobber (reg ...))...].  */
 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i > 0; i--)
   if (GET_CODE (XVECEXP (body, 0, i))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[i]))->code) != CLOBBER)
     return -1;
 return 0;
}
    return -1;
  }

if (GET_CODE (body)((enum rtx_code) (body)->code) == SET)
  n_sets = 1;
else if (GET_CODE (body)((enum rtx_code) (body)->code) == PARALLEL)
  {
    if (GET_CODE (XVECEXP (body, 0, 0))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[0]))->code) == SET)
{
 /* Multiple output operands, or 1 output plus some clobbers:
    body is
    [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...].  */
 /* Count backwards through CLOBBERs to determine number of SETs.  */
 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem); i > 0; i--)
   {
     if (GET_CODE (XVECEXP (body, 0, i - 1))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[i - 1]))->code) == SET)
break;
     if (GET_CODE (XVECEXP (body, 0, i - 1))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[i - 1]))->code) != CLOBBER)
return -1;
   }

 /* N_SETS is now number of output operands.  */
 n_sets = i;

 /* Verify that all the SETs we have
    came from a single original asm_operands insn
    (so that invalid combinations are blocked).  */
 for (i = 0; i < n_sets; i++)
   {
     rtx elt = XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i]);
     if (GET_CODE (elt)((enum rtx_code) (elt)->code) != SET)
return -1;
     if (GET_CODE (SET_SRC (elt))((enum rtx_code) ((((elt)->u.fld[1]).rt_rtx))->code) != ASM_OPERANDS)
return -1;
     /* If these ASM_OPERANDS rtx's came from different original insns
        then they aren't allowed together.  */
     if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))((((((elt)->u.fld[1]).rt_rtx))->u.fld[3]).rt_rtvec)
  != ASM_OPERANDS_INPUT_VEC (asm_op)(((asm_op)->u.fld[3]).rt_rtvec))
return -1;
   }
}
    else
{
 /* 0 outputs, but some clobbers:
    body is [(asm_operands ...) (clobber (reg ...))...].  */
 /* Make sure all the other parallel things really are clobbers.  */
 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i > 0; i--)
   if (GET_CODE (XVECEXP (body, 0, i))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[i]))->code) != CLOBBER)
     return -1;
}
  }

return (ASM_OPERANDS_INPUT_LENGTH (asm_op)(((((asm_op)->u.fld[3]).rt_rtvec))->num_elem)
 + ASM_OPERANDS_LABEL_LENGTH (asm_op)(((((asm_op)->u.fld[5]).rt_rtvec))->num_elem) + n_sets);
2023}

2025/* Assuming BODY is an insn body that uses ASM_OPERANDS,
 copy its operands (both input and output) into the vector OPERANDS,
 the locations of the operands within the insn into the vector OPERAND_LOCS,
 and the constraints for the operands into CONSTRAINTS.
 Write the modes of the operands into MODES.
 Write the location info into LOC.
 Return the assembler-template.
 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
 return the basic assembly string.

 If LOC, MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
 we don't store that info.  */

2038const char *
2039decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs,
     const char **constraints, machine_mode *modes,
     location_t *loc)
2042{
int nbase = 0, n, i;
rtx asmop;

switch (GET_CODE (body)((enum rtx_code) (body)->code))
  {
  case ASM_OPERANDS:
    /* Zero output asm: BODY is (asm_operands ...).  */
    asmop = body;
    break;

  case SET:
    /* Single output asm: BODY is (set OUTPUT (asm_operands ...)).  */
    asmop = SET_SRC (body)(((body)->u.fld[1]).rt_rtx);

    /* The output is in the SET.
Its constraint is in the ASM_OPERANDS itself.  */
    if (operands)
operands[0] = SET_DEST (body)(((body)->u.fld[0]).rt_rtx);
    if (operand_locs)
operand_locs[0] = &SET_DEST (body)(((body)->u.fld[0]).rt_rtx);
    if (constraints)
constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop)(((asmop)->u.fld[1]).rt_str);
    if (modes)
modes[0] = GET_MODE (SET_DEST (body))((machine_mode) ((((body)->u.fld[0]).rt_rtx))->mode);
    nbase = 1;
    break;

  case PARALLEL:
    {
int nparallel = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem); /* Includes CLOBBERs.  */

asmop = XVECEXP (body, 0, 0)(((((body)->u.fld[0]).rt_rtvec))->elem[0]);
if (GET_CODE (asmop)((enum rtx_code) (asmop)->code) == SET)
 {
   asmop = SET_SRC (asmop)(((asmop)->u.fld[1]).rt_rtx);

   /* At least one output, plus some CLOBBERs.  The outputs are in
      the SETs.  Their constraints are in the ASM_OPERANDS itself.  */
   for (i = 0; i < nparallel; i++)
     {
if (GET_CODE (XVECEXP (body, 0, i))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[i]))->code) == CLOBBER)
  break;		/* Past last SET */
gcc_assert (GET_CODE (XVECEXP (body, 0, i)) == SET)((void)(!(((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec
))->elem[i]))->code) == SET) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2085, __FUNCTION__), 0 : 0));
if (operands)
  operands[i] = SET_DEST (XVECEXP (body, 0, i))((((((((body)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx);
if (operand_locs)
  operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i))((((((((body)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx);
if (constraints)
  constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1)(((((((((((body)->u.fld[0]).rt_rtvec))->elem[i]))->u
.fld[1]).rt_rtx))->u.fld[1]).rt_str);
if (modes)
  modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)))((machine_mode) (((((((((body)->u.fld[0]).rt_rtvec))->elem
[i]))->u.fld[0]).rt_rtx))->mode);
     }
   nbase = i;
 }
else if (GET_CODE (asmop)((enum rtx_code) (asmop)->code) == ASM_INPUT)
 {
   if (loc)
     *loc = ASM_INPUT_SOURCE_LOCATION (asmop)(((asmop)->u.fld[1]).rt_uint);
   return XSTR (asmop, 0)(((asmop)->u.fld[0]).rt_str);
 }
break;
    }

  default:
    gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2107, __FUNCTION__));
  }

n = ASM_OPERANDS_INPUT_LENGTH (asmop)(((((asmop)->u.fld[3]).rt_rtvec))->num_elem);
for (i = 0; i < n; i++)
  {
    if (operand_locs)
operand_locs[nbase + i] = &ASM_OPERANDS_INPUT (asmop, i)(((((asmop)->u.fld[3]).rt_rtvec))->elem[i]);
    if (operands)
operands[nbase + i] = ASM_OPERANDS_INPUT (asmop, i)(((((asmop)->u.fld[3]).rt_rtvec))->elem[i]);
    if (constraints)
constraints[nbase + i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i)((((((((asmop)->u.fld[4]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_str);
    if (modes)
modes[nbase + i] = ASM_OPERANDS_INPUT_MODE (asmop, i)((machine_mode) ((((((asmop)->u.fld[4]).rt_rtvec))->elem
[i]))->mode);
  }
nbase += n;

n = ASM_OPERANDS_LABEL_LENGTH (asmop)(((((asmop)->u.fld[5]).rt_rtvec))->num_elem);
for (i = 0; i < n; i++)
  {
    if (operand_locs)
operand_locs[nbase + i] = &ASM_OPERANDS_LABEL (asmop, i)(((((asmop)->u.fld[5]).rt_rtvec))->elem[i]);
    if (operands)
operands[nbase + i] = ASM_OPERANDS_LABEL (asmop, i)(((((asmop)->u.fld[5]).rt_rtvec))->elem[i]);
    if (constraints)
constraints[nbase + i] = "";
    if (modes)
modes[nbase + i] = Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)));
  }

if (loc)
  *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop)(((asmop)->u.fld[6]).rt_uint);

return ASM_OPERANDS_TEMPLATE (asmop)(((asmop)->u.fld[0]).rt_str);
2141}

2143/* Parse inline assembly string STRING and determine which operands are
 referenced by % markers.  For the first NOPERANDS operands, set USED[I]
 to true if operand I is referenced.

 This is intended to distinguish barrier-like asms such as:

    asm ("" : "=m" (...));

 from real references such as:

    asm ("sw\t$0, %0" : "=m" (...));  */

2155void
2156get_referenced_operands (const char *string, bool *used,
	 unsigned int noperands)
2158{
memset (used, 0, sizeof (bool) * noperands);
const char *p = string;
while (*p)
  switch (*p)
    {
    case '%':
p += 1;
/* A letter followed by a digit indicates an operand number.  */
if (ISALPHA (p[0])(_sch_istable[(p[0]) & 0xff] & (unsigned short)(_sch_isalpha
)) && ISDIGIT (p[1])(_sch_istable[(p[1]) & 0xff] & (unsigned short)(_sch_isdigit
)))
 p += 1;
if (ISDIGIT (*p)(_sch_istable[(*p) & 0xff] & (unsigned short)(_sch_isdigit
)))
 {
   char *endptr;
   unsigned long opnum = strtoul (p, &endptr, 10);
   if (endptr != p && opnum < noperands)
     used[opnum] = true;
   p = endptr;
 }
else
 p += 1;
break;

    default:
p++;
break;
    }
2185}

2187/* Check if an asm_operand matches its constraints.
 Return > 0 if ok, = 0 if bad, < 0 if inconclusive.  */

2190int
2191asm_operand_ok (rtx op, const char *constraint, const char **constraints)
2192{
int result = 0;
bool incdec_ok = false;

/* Use constrain_operands after reload.  */
gcc_assert (!reload_completed)((void)(!(!reload_completed) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2197, __FUNCTION__), 0 : 0));

/* Empty constraint string is the same as "X,...,X", i.e. X for as
   many alternatives as required to match the other operands.  */
if (*constraint == '\0')
  result = 1;

while (*constraint)
  {
    enum constraint_num cn;
    char c = *constraint;
    int len;
    switch (c)
{
case ',':
 constraint++;
 continue;

case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
 /* If caller provided constraints pointer, look up
    the matching constraint.  Otherwise, our caller should have
    given us the proper matching constraint, but we can't
    actually fail the check if they didn't.  Indicate that
    results are inconclusive.  */
 if (constraints)
   {
     char *end;
     unsigned long match;

     match = strtoul (constraint, &end, 10);
     if (!result)
result = asm_operand_ok (op, constraints[match], NULLnullptr);
     constraint = (const char *) end;
   }
 else
   {
     do
constraint++;
     while (ISDIGIT (*constraint)(_sch_istable[(*constraint) & 0xff] & (unsigned short
)(_sch_isdigit)));
     if (! result)
result = -1;
   }
 continue;

 /* The rest of the compiler assumes that reloading the address
    of a MEM into a register will make it fit an 'o' constraint.
    That is, if it sees a MEM operand for an 'o' constraint,
    it assumes that (mem (base-reg)) will fit.

    That assumption fails on targets that don't have offsettable
    addresses at all.  We therefore need to treat 'o' asm
    constraints as a special case and only accept operands that
    are already offsettable, thus proving that at least one
    offsettable address exists.  */
case 'o': /* offsettable */
 if (offsettable_nonstrict_memref_p (op))
   result = 1;
 break;

case 'g':
 if (general_operand (op, VOIDmode((void) 0, E_VOIDmode)))
   result = 1;
 break;

case '<':
case '>':
 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
    to exist, excepting those that expand_call created.  Further,
    on some machines which do not have generalized auto inc/dec,
    an inc/dec is not a memory_operand.

    Match any memory and hope things are resolved after reload.  */
 incdec_ok = true;
 /* FALLTHRU */
default:
 cn = lookup_constraint (constraint);
 rtx mem = NULLnullptr;
 switch (get_constraint_type (cn))
   {
   case CT_REGISTER:
     if (!result
  && reg_class_for_constraint (cn) != NO_REGS
  && GET_MODE (op)((machine_mode) (op)->mode) != BLKmode((void) 0, E_BLKmode)
  && register_operand (op, VOIDmode((void) 0, E_VOIDmode)))
result = 1;
     break;

   case CT_CONST_INT:
     if (!result
  && CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT)
  && insn_const_int_ok_for_constraint (INTVAL (op)((op)->u.hwint[0]), cn))
result = 1;
     break;

   case CT_MEMORY:
   case CT_RELAXED_MEMORY:
     mem = op;
     /* Fall through.  */
   case CT_SPECIAL_MEMORY:
     /* Every memory operand can be reloaded to fit.  */
     if (!mem)
mem = extract_mem_from_operand (op);
     result = result || memory_operand (mem, VOIDmode((void) 0, E_VOIDmode));
     break;

   case CT_ADDRESS:
     /* Every address operand can be reloaded to fit.  */
     result = result || address_operand (op, VOIDmode((void) 0, E_VOIDmode));
     break;

   case CT_FIXED_FORM:
     result = result || constraint_satisfied_p (op, cn);
     break;
   }
 break;
}
    len = CONSTRAINT_LEN (c, constraint)insn_constraint_len (c,constraint);
    do
constraint++;
    while (--len && *constraint && *constraint != ',');
    if (len)
return 0;
  }

/* For operands without < or > constraints reject side-effects.  */
if (AUTO_INC_DEC0 && !incdec_ok && result && MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
  switch (GET_CODE (XEXP (op, 0))((enum rtx_code) ((((op)->u.fld[0]).rt_rtx))->code))
    {
    case PRE_INC:
    case POST_INC:
    case PRE_DEC:
    case POST_DEC:
    case PRE_MODIFY:
    case POST_MODIFY:
return 0;
    default:
break;
    }

return result;
2338}
2339
2340/* Given an rtx *P, if it is a sum containing an integer constant term,
 return the location (type rtx *) of the pointer to that constant term.
 Otherwise, return a null pointer.  */

2344rtx *
2345find_constant_term_loc (rtx *p)
2346{
rtx *tem;
enum rtx_code code = GET_CODE (*p)((enum rtx_code) (*p)->code);

/* If *P IS such a constant term, P is its location.  */

if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
    || code == CONST)
  return p;

/* Otherwise, if not a sum, it has no constant term.  */

if (GET_CODE (*p)((enum rtx_code) (*p)->code) != PLUS)
  return 0;

/* If one of the summands is constant, return its location.  */

if (XEXP (*p, 0)(((*p)->u.fld[0]).rt_rtx) && CONSTANT_P (XEXP (*p, 0))((rtx_class[(int) (((enum rtx_code) ((((*p)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
    && XEXP (*p, 1)(((*p)->u.fld[1]).rt_rtx) && CONSTANT_P (XEXP (*p, 1))((rtx_class[(int) (((enum rtx_code) ((((*p)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
  return p;

/* Otherwise, check each summand for containing a constant term.  */

if (XEXP (*p, 0)(((*p)->u.fld[0]).rt_rtx) != 0)
  {
    tem = find_constant_term_loc (&XEXP (*p, 0)(((*p)->u.fld[0]).rt_rtx));
    if (tem != 0)
return tem;
  }

if (XEXP (*p, 1)(((*p)->u.fld[1]).rt_rtx) != 0)
  {
    tem = find_constant_term_loc (&XEXP (*p, 1)(((*p)->u.fld[1]).rt_rtx));
    if (tem != 0)
return tem;
  }

return 0;
2384}
2385
2386/* Return true if OP is a memory reference whose address contains
 no side effects and remains valid after the addition of a positive
 integer less than the size of the object being referenced.

 We assume that the original address is valid and do not check it.

 This uses strict_memory_address_p as a subroutine, so
 don't use it before reload.  */

2395bool
2396offsettable_memref_p (rtx op)
2397{
return ((MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
 && offsettable_address_addr_space_p (1, GET_MODE (op)((machine_mode) (op)->mode), XEXP (op, 0)(((op)->u.fld[0]).rt_rtx),
			       MEM_ADDR_SPACE (op)(get_mem_attrs (op)->addrspace)));
2401}

2403/* Similar, but don't require a strictly valid mem ref:
 consider pseudo-regs valid as index or base regs.  */

2406bool
2407offsettable_nonstrict_memref_p (rtx op)
2408{
return ((MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
 && offsettable_address_addr_space_p (0, GET_MODE (op)((machine_mode) (op)->mode), XEXP (op, 0)(((op)->u.fld[0]).rt_rtx),
			       MEM_ADDR_SPACE (op)(get_mem_attrs (op)->addrspace)));
2412}

2414/* Return true if Y is a memory address which contains no side effects
 and would remain valid for address space AS after the addition of
 a positive integer less than the size of that mode.

 We assume that the original address is valid and do not check it.
 We do check that it is valid for narrower modes.

 If STRICTP is nonzero, we require a strictly valid address,
 for the sake of use in reload.cc.  */

2424bool
2425offsettable_address_addr_space_p (int strictp, machine_mode mode, rtx y,
		  addr_space_t as)
2427{
enum rtx_code ycode = GET_CODE (y)((enum rtx_code) (y)->code);
rtx z;
rtx y1 = y;
rtx *y2;
bool (*addressp) (machine_mode, rtx, addr_space_t) =
  (strictp ? strict_memory_address_addr_space_p
    : memory_address_addr_space_p);
poly_int64 mode_sz = GET_MODE_SIZE (mode);

if (CONSTANT_ADDRESS_P (y)constant_address_p (y))
  return true;

/* Adjusting an offsettable address involves changing to a narrower mode.
   Make sure that's OK.  */

if (mode_dependent_address_p (y, as))
  return false;

machine_mode address_mode = GET_MODE (y)((machine_mode) (y)->mode);
if (address_mode == VOIDmode((void) 0, E_VOIDmode))
  address_mode = targetm.addr_space.address_mode (as);
2449#ifdef POINTERS_EXTEND_UNSIGNED1
machine_mode pointer_mode = targetm.addr_space.pointer_mode (as);
2451#endif

/* ??? How much offset does an offsettable BLKmode reference need?
   Clearly that depends on the situation in which it's being used.
   However, the current situation in which we test 0xffffffff is
   less than ideal.  Caveat user.  */
if (known_eq (mode_sz, 0)(!maybe_ne (mode_sz, 0)))
  mode_sz = BIGGEST_ALIGNMENT(((global_options.x_target_flags & (1U << 12)) != 0
) ? 32 : (((global_options.x_ix86_isa_flags & (1UL <<
 15)) != 0) ? 512 : (((global_options.x_ix86_isa_flags & (
1UL << 8)) != 0) ? 256 : 128))) / BITS_PER_UNIT(8);

/* If the expression contains a constant term,
   see if it remains valid when max possible offset is added.  */

if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
  {
    bool good;

    y1 = *y2;
    *y2 = plus_constant (address_mode, *y2, mode_sz - 1);
    /* Use QImode because an odd displacement may be automatically invalid
for any wider mode.  But it should be valid for a single byte.  */
    good = (*addressp) (QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)), y, as);

    /* In any case, restore old contents of memory.  */
    *y2 = y1;
    return good;
  }

if (GET_RTX_CLASS (ycode)(rtx_class[(int) (ycode)]) == RTX_AUTOINC)
  return false;

/* The offset added here is chosen as the maximum offset that
   any instruction could need to add when operating on something
   of the specified mode.  We assume that if Y and Y+c are
   valid addresses then so is Y+d for all 0<d<c.  adjust_address will
   go inside a LO_SUM here, so we do so as well.  */
if (GET_CODE (y)((enum rtx_code) (y)->code) == LO_SUM
    && mode != BLKmode((void) 0, E_BLKmode)
    && known_le (mode_sz, GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)(!maybe_lt (get_mode_alignment (mode) / (8), mode_sz)))
  z = gen_rtx_LO_SUM (address_mode, XEXP (y, 0),gen_rtx_fmt_ee_stat ((LO_SUM), ((address_mode)), (((((y)->
u.fld[0]).rt_rtx))), ((plus_constant (address_mode, (((y)->
u.fld[1]).rt_rtx), mode_sz - 1))) )
	plus_constant (address_mode, XEXP (y, 1),gen_rtx_fmt_ee_stat ((LO_SUM), ((address_mode)), (((((y)->
u.fld[0]).rt_rtx))), ((plus_constant (address_mode, (((y)->
u.fld[1]).rt_rtx), mode_sz - 1))) )
		       mode_sz - 1))gen_rtx_fmt_ee_stat ((LO_SUM), ((address_mode)), (((((y)->
u.fld[0]).rt_rtx))), ((plus_constant (address_mode, (((y)->
u.fld[1]).rt_rtx), mode_sz - 1))) );
2492#ifdef POINTERS_EXTEND_UNSIGNED1
/* Likewise for a ZERO_EXTEND from pointer_mode.  */
else if (POINTERS_EXTEND_UNSIGNED1 > 0
  && GET_CODE (y)((enum rtx_code) (y)->code) == ZERO_EXTEND
  && GET_MODE (XEXP (y, 0))((machine_mode) ((((y)->u.fld[0]).rt_rtx))->mode) == pointer_mode)
  z = gen_rtx_ZERO_EXTEND (address_mode,gen_rtx_fmt_e_stat ((ZERO_EXTEND), ((address_mode)), ((plus_constant
 (pointer_mode, (((y)->u.fld[0]).rt_rtx), mode_sz - 1))) )
	     plus_constant (pointer_mode, XEXP (y, 0),gen_rtx_fmt_e_stat ((ZERO_EXTEND), ((address_mode)), ((plus_constant
 (pointer_mode, (((y)->u.fld[0]).rt_rtx), mode_sz - 1))) )
			    mode_sz - 1))gen_rtx_fmt_e_stat ((ZERO_EXTEND), ((address_mode)), ((plus_constant
 (pointer_mode, (((y)->u.fld[0]).rt_rtx), mode_sz - 1))) );
2500#endif
else
  z = plus_constant (address_mode, y, mode_sz - 1);

/* Use QImode because an odd displacement may be automatically invalid
   for any wider mode.  But it should be valid for a single byte.  */
return (*addressp) (QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)), z, as);
2507}

2509/* Return true if ADDR is an address-expression whose effect depends
 on the mode of the memory reference it is used in.

 ADDRSPACE is the address space associated with the address.

 Autoincrement addressing is a typical example of mode-dependence
 because the amount of the increment depends on the mode.  */

2517bool
2518mode_dependent_address_p (rtx addr, addr_space_t addrspace)
2519{
/* Auto-increment addressing with anything other than post_modify
   or pre_modify always introduces a mode dependency.  Catch such
   cases now instead of deferring to the target.  */
if (GET_CODE (addr)((enum rtx_code) (addr)->code) == PRE_INC
    || GET_CODE (addr)((enum rtx_code) (addr)->code) == POST_INC
    || GET_CODE (addr)((enum rtx_code) (addr)->code) == PRE_DEC
    || GET_CODE (addr)((enum rtx_code) (addr)->code) == POST_DEC)
  return true;

return targetm.mode_dependent_address_p (addr, addrspace);
2530}
2531
2532/* Return true if boolean attribute ATTR is supported.  */

2534static bool
2535have_bool_attr (bool_attr attr)
2536{
switch (attr)
  {
  case BA_ENABLED:
    return HAVE_ATTR_enabled1;
  case BA_PREFERRED_FOR_SIZE:
    return HAVE_ATTR_enabled1 || HAVE_ATTR_preferred_for_size1;
  case BA_PREFERRED_FOR_SPEED:
    return HAVE_ATTR_enabled1 || HAVE_ATTR_preferred_for_speed1;
  }
gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2546, __FUNCTION__));
2547}

2549/* Return the value of ATTR for instruction INSN.  */

2551static bool
2552get_bool_attr (rtx_insn *insn, bool_attr attr)
2553{
switch (attr)
  {
  case BA_ENABLED:
    return get_attr_enabled (insn);
  case BA_PREFERRED_FOR_SIZE:
    return get_attr_enabled (insn) && get_attr_preferred_for_size (insn);
  case BA_PREFERRED_FOR_SPEED:
    return get_attr_enabled (insn) && get_attr_preferred_for_speed (insn);
  }
gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2563, __FUNCTION__));
2564}

2566/* Like get_bool_attr_mask, but don't use the cache.  */

2568static alternative_mask
2569get_bool_attr_mask_uncached (rtx_insn *insn, bool_attr attr)
2570{
/* Temporarily install enough information for get_attr_<foo> to assume
   that the insn operands are already cached.  As above, the attribute
   mustn't depend on the values of operands, so we don't provide their
   real values here.  */
rtx_insn *old_insn = recog_data.insn;
int old_alternative = which_alternative;

recog_data.insn = insn;
alternative_mask mask = ALL_ALTERNATIVES((alternative_mask) -1);
int n_alternatives = insn_data[INSN_CODE (insn)(((insn)->u.fld[5]).rt_int)].n_alternatives;
for (int i = 0; i < n_alternatives; i++)
  {
    which_alternative = i;
    if (!get_bool_attr (insn, attr))
mask &= ~ALTERNATIVE_BIT (i)((alternative_mask) 1 << (i));
  }

recog_data.insn = old_insn;
which_alternative = old_alternative;
return mask;
2591}

2593/* Return the mask of operand alternatives that are allowed for INSN
 by boolean attribute ATTR.  This mask depends only on INSN and on
 the current target; it does not depend on things like the values of
 operands.  */

2598static alternative_mask
2599get_bool_attr_mask (rtx_insn *insn, bool_attr attr)
2600{
/* Quick exit for asms and for targets that don't use these attributes.  */
int code = INSN_CODE (insn)(((insn)->u.fld[5]).rt_int);
if (code < 0 || !have_bool_attr (attr))
  return ALL_ALTERNATIVES((alternative_mask) -1);

/* Calling get_attr_<foo> can be expensive, so cache the mask
   for speed.  */
if (!this_target_recog->x_bool_attr_masks[code][attr])
  this_target_recog->x_bool_attr_masks[code][attr]
    = get_bool_attr_mask_uncached (insn, attr);
return this_target_recog->x_bool_attr_masks[code][attr];
2612}

2614/* Return the set of alternatives of INSN that are allowed by the current
 target.  */

2617alternative_mask
2618get_enabled_alternatives (rtx_insn *insn)
2619{
return get_bool_attr_mask (insn, BA_ENABLED);
2621}

2623/* Return the set of alternatives of INSN that are allowed by the current
 target and are preferred for the current size/speed optimization
 choice.  */

2627alternative_mask
2628get_preferred_alternatives (rtx_insn *insn)
2629{
if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
  return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
else
  return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2634}

2636/* Return the set of alternatives of INSN that are allowed by the current
 target and are preferred for the size/speed optimization choice
 associated with BB.  Passing a separate BB is useful if INSN has not
 been emitted yet or if we are considering moving it to a different
 block.  */

2642alternative_mask
2643get_preferred_alternatives (rtx_insn *insn, basic_block bb)
2644{
if (optimize_bb_for_speed_p (bb))
  return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
else
  return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2649}

2651/* Assert that the cached boolean attributes for INSN are still accurate.
 The backend is required to define these attributes in a way that only
 depends on the current target (rather than operands, compiler phase,
 etc.).  */

2656bool
2657check_bool_attrs (rtx_insn *insn)
2658{
int code = INSN_CODE (insn)(((insn)->u.fld[5]).rt_int);
if (code >= 0)
  for (int i = 0; i <= BA_LAST; ++i)
    {
enum bool_attr attr = (enum bool_attr) i;
if (this_target_recog->x_bool_attr_masks[code][attr])
 gcc_assert (this_target_recog->x_bool_attr_masks[code][attr]((void)(!(this_target_recog->x_bool_attr_masks[code][attr]
 == get_bool_attr_mask_uncached (insn, attr)) ? fancy_abort (
"/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2666, __FUNCTION__), 0 : 0))
      == get_bool_attr_mask_uncached (insn, attr))((void)(!(this_target_recog->x_bool_attr_masks[code][attr]
 == get_bool_attr_mask_uncached (insn, attr)) ? fancy_abort (
"/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2666, __FUNCTION__), 0 : 0));
    }
return true;
2669}

2671/* Like extract_insn, but save insn extracted and don't extract again, when
 called again for the same insn expecting that recog_data still contain the
 valid information.  This is used primary by gen_attr infrastructure that
 often does extract insn again and again.  */
2675void
2676extract_insn_cached (rtx_insn *insn)
2677{
if (recog_data.insn == insn && INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) >= 0)
  return;
extract_insn (insn);
recog_data.insn = insn;
2682}

2684/* Do uncached extract_insn, constrain_operands and complain about failures.
 This should be used when extracting a pre-existing constrained instruction
 if the caller wants to know which alternative was chosen.  */
2687void
2688extract_constrain_insn (rtx_insn *insn)
2689{
extract_insn (insn);
if (!constrain_operands (reload_completed, get_enabled_alternatives (insn)))
  fatal_insn_not_found (insn)_fatal_insn_not_found (insn, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2692, __FUNCTION__);
2693}

2695/* Do cached extract_insn, constrain_operands and complain about failures.
 Used by insn_attrtab.  */
2697void
2698extract_constrain_insn_cached (rtx_insn *insn)
2699{
extract_insn_cached (insn);
if (which_alternative == -1
    && !constrain_operands (reload_completed,
	      get_enabled_alternatives (insn)))
  fatal_insn_not_found (insn)_fatal_insn_not_found (insn, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2704, __FUNCTION__);
2705}

2707/* Do cached constrain_operands on INSN and complain about failures.  */
2708int
2709constrain_operands_cached (rtx_insn *insn, int strict)
2710{
if (which_alternative == -1)
  return constrain_operands (strict, get_enabled_alternatives (insn));
else
  return 1;
2715}
2716
2717/* Analyze INSN and fill in recog_data.  */

2719void
2720extract_insn (rtx_insn *insn)
2721{
int i;
int icode;
int noperands;
rtx body = PATTERN (insn);

recog_data.n_operands = 0;
recog_data.n_alternatives = 0;
recog_data.n_dups = 0;
recog_data.is_asm = false;

switch (GET_CODE (body)((enum rtx_code) (body)->code))
  {
  case USE:
  case CLOBBER:
  case ASM_INPUT:
  case ADDR_VEC:
  case ADDR_DIFF_VEC:
  case VAR_LOCATION:
  case DEBUG_MARKER:
    return;

  case SET:
    if (GET_CODE (SET_SRC (body))((enum rtx_code) ((((body)->u.fld[1]).rt_rtx))->code) == ASM_OPERANDS)
goto asm_insn;
    else
goto normal_insn;
  case PARALLEL:
    if ((GET_CODE (XVECEXP (body, 0, 0))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[0]))->code) == SET
  && GET_CODE (SET_SRC (XVECEXP (body, 0, 0)))((enum rtx_code) (((((((((body)->u.fld[0]).rt_rtvec))->
elem[0]))->u.fld[1]).rt_rtx))->code) == ASM_OPERANDS)
 || GET_CODE (XVECEXP (body, 0, 0))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[0]))->code) == ASM_OPERANDS
 || GET_CODE (XVECEXP (body, 0, 0))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[0]))->code) == ASM_INPUT)
goto asm_insn;
    else
goto normal_insn;
  case ASM_OPERANDS:
  asm_insn:
    recog_data.n_operands = noperands = asm_noperands (body);
    if (noperands >= 0)
{
 /* This insn is an `asm' with operands.  */

 /* expand_asm_operands makes sure there aren't too many operands.  */
 gcc_assert (noperands <= MAX_RECOG_OPERANDS)((void)(!(noperands <= 30) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2764, __FUNCTION__), 0 : 0));

 /* Now get the operand values and constraints out of the insn.  */
 decode_asm_operands (body, recog_data.operand,
	       recog_data.operand_loc,
	       recog_data.constraints,
	       recog_data.operand_mode, NULLnullptr);
 memset (recog_data.is_operator, 0, sizeof recog_data.is_operator);
 if (noperands > 0)
   {
     const char *p =  recog_data.constraints[0];
     recog_data.n_alternatives = 1;
     while (*p)
recog_data.n_alternatives += (*p++ == ',');
   }
 recog_data.is_asm = true;
 break;
}
    fatal_insn_not_found (insn)_fatal_insn_not_found (insn, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2782, __FUNCTION__);

  default:
  normal_insn:
    /* Ordinary insn: recognize it, get the operands via insn_extract
and get the constraints.  */

    icode = recog_memoized (insn);
    if (icode < 0)
fatal_insn_not_found (insn)_fatal_insn_not_found (insn, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2791, __FUNCTION__);

    recog_data.n_operands = noperands = insn_data[icode].n_operands;
    recog_data.n_alternatives = insn_data[icode].n_alternatives;
    recog_data.n_dups = insn_data[icode].n_dups;

    insn_extract (insn);

    for (i = 0; i < noperands; i++)
{
 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
 recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator;
 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
 /* VOIDmode match_operands gets mode from their real operand.  */
 if (recog_data.operand_mode[i] == VOIDmode((void) 0, E_VOIDmode))
   recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i])((machine_mode) (recog_data.operand[i])->mode);
}
  }
for (i = 0; i < noperands; i++)
  recog_data.operand_type[i]
    = (recog_data.constraints[i][0] == '=' ? OP_OUT
: recog_data.constraints[i][0] == '+' ? OP_INOUT
: OP_IN);

gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES)((void)(!(recog_data.n_alternatives <= 35) ? fancy_abort (
"/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2815, __FUNCTION__), 0 : 0));

recog_data.insn = NULLnullptr;
which_alternative = -1;
2819}

2821/* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS
 operands, N_ALTERNATIVES alternatives and constraint strings
 CONSTRAINTS.  OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries
 and CONSTRAINTS has N_OPERANDS entries.  OPLOC should be passed in
 if the insn is an asm statement and preprocessing should take the
 asm operands into account, e.g. to determine whether they could be
 addresses in constraints that require addresses; it should then
 point to an array of pointers to each operand.  */

2830void
2831preprocess_constraints (int n_operands, int n_alternatives,
	const char **constraints,
	operand_alternative *op_alt_base,
	rtx **oploc)
2835{
for (int i = 0; i < n_operands; i++)
  {
    int j;
    struct operand_alternative *op_alt;
    const char *p = constraints[i];

    op_alt = op_alt_base;

    for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
{
 op_alt[i].cl = NO_REGS;
 op_alt[i].constraint = p;
 op_alt[i].matches = -1;
 op_alt[i].matched = -1;

 if (*p == '\0' || *p == ',')
   {
     op_alt[i].anything_ok = 1;
     continue;
   }

 for (;;)
   {
     char c = *p;
     if (c == '#')
do
  c = *++p;
while (c != ',' && c != '\0');
     if (c == ',' || c == '\0')
{
  p++;
  break;
}

     switch (c)
{
case '?':
  op_alt[i].reject += 6;
  break;
case '!':
  op_alt[i].reject += 600;
  break;
case '&':
  op_alt[i].earlyclobber = 1;
  break;

case '0': case '1': case '2': case '3': case '4':
case '5': case '6': case '7': case '8': case '9':
  {
    char *end;
    op_alt[i].matches = strtoul (p, &end, 10);
    op_alt[op_alt[i].matches].matched = i;
    p = end;
  }
  continue;

case 'X':
  op_alt[i].anything_ok = 1;
  break;

case 'g':
  op_alt[i].cl =
   reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[(int) op_alt[i].cl][(int) GENERAL_REGS];
  break;

default:
  enum constraint_num cn = lookup_constraint (p);
  enum reg_class cl;
  switch (get_constraint_type (cn))
    {
    case CT_REGISTER:
      cl = reg_class_for_constraint (cn);
      if (cl != NO_REGS)
	op_alt[i].cl = reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[op_alt[i].cl][cl];
      break;

    case CT_CONST_INT:
      break;

    case CT_MEMORY:
    case CT_SPECIAL_MEMORY:
    case CT_RELAXED_MEMORY:
      op_alt[i].memory_ok = 1;
      break;

    case CT_ADDRESS:
      if (oploc && !address_operand (*oploc[i], VOIDmode((void) 0, E_VOIDmode)))
	break;

      op_alt[i].is_address = 1;
      op_alt[i].cl
	= (reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)
	   [(int) op_alt[i].cl]
	   [(int) base_reg_class (VOIDmode((void) 0, E_VOIDmode), ADDR_SPACE_GENERIC0,
				  ADDRESS, SCRATCH)]);
      break;

    case CT_FIXED_FORM:
      break;
    }
  break;
}
     p += CONSTRAINT_LEN (c, p)insn_constraint_len (c,p);
   }
}
  }
2942}

2944/* Return an array of operand_alternative instructions for
 instruction ICODE.  */

2947const operand_alternative *
2948preprocess_insn_constraints (unsigned int icode)
2949{
gcc_checking_assert (IN_RANGE (icode, 0, NUM_INSN_CODES - 1))((void)(!(((unsigned long) (icode) - (unsigned long) (0) <=
 (unsigned long) (NUM_INSN_CODES - 1) - (unsigned long) (0)))
 ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 2950, __FUNCTION__), 0 : 0));
if (this_target_recog->x_op_alt[icode])
  return this_target_recog->x_op_alt[icode];

int n_operands = insn_data[icode].n_operands;
if (n_operands == 0)
  return 0;
/* Always provide at least one alternative so that which_op_alt ()
   works correctly.  If the instruction has 0 alternatives (i.e. all
   constraint strings are empty) then each operand in this alternative
   will have anything_ok set.  */
int n_alternatives = MAX (insn_data[icode].n_alternatives, 1)((insn_data[icode].n_alternatives) > (1) ? (insn_data[icode
].n_alternatives) : (1));
int n_entries = n_operands * n_alternatives;

operand_alternative *op_alt = XCNEWVEC (operand_alternative, n_entries)((operand_alternative *) xcalloc ((n_entries), sizeof (operand_alternative
)));
const char **constraints = XALLOCAVEC (const char *, n_operands)((const char * *) __builtin_alloca(sizeof (const char *) * (n_operands
)));

for (int i = 0; i < n_operands; ++i)
  constraints[i] = insn_data[icode].operand[i].constraint;
preprocess_constraints (n_operands, n_alternatives, constraints, op_alt,
	  NULLnullptr);

this_target_recog->x_op_alt[icode] = op_alt;
return op_alt;
2974}

2976/* After calling extract_insn, you can use this function to extract some
 information from the constraint strings into a more usable form.
 The collected data is stored in recog_op_alt.  */

2980void
2981preprocess_constraints (rtx_insn *insn)
2982{
int icode = INSN_CODE (insn)(((insn)->u.fld[5]).rt_int);
if (icode >= 0)
  recog_op_alt = preprocess_insn_constraints (icode);
else
  {
    int n_operands = recog_data.n_operands;
    int n_alternatives = recog_data.n_alternatives;
    int n_entries = n_operands * n_alternatives;
    memset (asm_op_alt, 0, n_entries * sizeof (operand_alternative));
    preprocess_constraints (n_operands, n_alternatives,
	      recog_data.constraints, asm_op_alt,
	      NULLnullptr);
    recog_op_alt = asm_op_alt;
  }
2997}

2999/* Check the operands of an insn against the insn's operand constraints
 and return 1 if they match any of the alternatives in ALTERNATIVES.

 The information about the insn's operands, constraints, operand modes
 etc. is obtained from the global variables set up by extract_insn.

 WHICH_ALTERNATIVE is set to a number which indicates which
 alternative of constraints was matched: 0 for the first alternative,
 1 for the next, etc.

 In addition, when two operands are required to match
 and it happens that the output operand is (reg) while the
 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
 make the output operand look like the input.
 This is because the output operand is the one the template will print.

 This is used in final, just before printing the assembler code and by
 the routines that determine an insn's attribute.

 If STRICT is a positive nonzero value, it means that we have been
 called after reload has been completed.  In that case, we must
 do all checks strictly.  If it is zero, it means that we have been called
 before reload has completed.  In that case, we first try to see if we can
 find an alternative that matches strictly.  If not, we try again, this
 time assuming that reload will fix up the insn.  This provides a "best
 guess" for the alternative and is used to compute attributes of insns prior
 to reload.  A negative value of STRICT is used for this internal call.  */

3027struct funny_match
3028{
int this_op, other;
3030};

3032int
3033constrain_operands (int strict, alternative_mask alternatives)
3034{
const char *constraints[MAX_RECOG_OPERANDS30];
int matching_operands[MAX_RECOG_OPERANDS30];
int earlyclobber[MAX_RECOG_OPERANDS30];
int c;

struct funny_match funny_match[MAX_RECOG_OPERANDS30];
int funny_match_index;

which_alternative = 0;
if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
1
Assuming field 'n_operands' is not equal to 0→
2
←
Assuming field 'n_alternatives' is not equal to 0→
3
←
Taking false branch→
  return 1;

for (c = 0; c < recog_data.n_operands; c++)
4
←
Assuming 'c' is < field 'n_operands'→
5
←
Loop condition is true.  Entering loop body→
6
←
Assuming 'c' is >= field 'n_operands'→
7
←
Loop condition is false. Execution continues on line 3052→
  constraints[c] = recog_data.constraints[c];

do
  {
    int seen_earlyclobber_at = -1;
    int opno;
    int lose = 0;
    funny_match_index = 0;

    if (!TEST_BIT (alternatives, which_alternative)(((alternatives) >> (which_alternative)) & 1))
8
←
Assuming the condition is false→
9
←
Taking false branch→
{
 int i;

 for (i = 0; i < recog_data.n_operands; i++)
   constraints[i] = skip_alternative (constraints[i]);

 which_alternative++;
 continue;
}

    for (opno = 0; opno < recog_data.n_operands; opno++)
10
←
Loop condition is true.  Entering loop body→
11
←
Loop condition is false. Execution continues on line 3071→
matching_operands[opno] = -1;

    for (opno = 0; opno < recog_data.n_operands; opno++)
12
←
Loop condition is true.  Entering loop body→
22
←
The value 1 is assigned to 'opno'→
23
←
Assuming 'opno' is < field 'n_operands'→
24
←
Loop condition is true.  Entering loop body→
{
 rtx op = recog_data.operand[opno];
 machine_mode mode = GET_MODE (op)((machine_mode) (op)->mode);
 const char *p = constraints[opno];
25
←
Assigned value is garbage or undefined
 int offset = 0;
 int win = 0;
 int val;
 int len;

 earlyclobber[opno] = 0;

 /* A unary operator may be accepted by the predicate, but it
    is irrelevant for matching constraints.  */
 /* For special_memory_operand, there could be a memory operand inside,
    and it would cause a mismatch for constraint_satisfied_p.  */
 if (UNARY_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_UNARY
) && op == extract_mem_from_operand (op))
13
←
Assuming the condition is true→
14
←
Assuming the condition is false→
15
←
Taking false branch→
   op = XEXP (op, 0)(((op)->u.fld[0]).rt_rtx);

 if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG)
16
←
Assuming field 'code' is not equal to SUBREG→
   {
     if (REG_P (SUBREG_REG (op))(((enum rtx_code) ((((op)->u.fld[0]).rt_rtx))->code) ==
 REG)
  && REGNO (SUBREG_REG (op))(rhs_regno((((op)->u.fld[0]).rt_rtx))) < FIRST_PSEUDO_REGISTER76)
offset = subreg_regno_offset (REGNO (SUBREG_REG (op))(rhs_regno((((op)->u.fld[0]).rt_rtx))),
			      GET_MODE (SUBREG_REG (op))((machine_mode) ((((op)->u.fld[0]).rt_rtx))->mode),
			      SUBREG_BYTE (op)(((op)->u.fld[1]).rt_subreg),
			      GET_MODE (op)((machine_mode) (op)->mode));
     op = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);
   }

 /* An empty constraint or empty alternative
    allows anything which matched the pattern.  */
 if (*p == 0 || *p == ',')
17
←
Assuming the condition is true→
   win = 1;

 do
20
←
Loop condition is false.  Exiting loop→
   switch (c = *p, len = CONSTRAINT_LEN (c, p)insn_constraint_len (c,p), c)
18
←
Control jumps to 'case 0:'  at line 3109→
     {
     case '\0':
len = 0;
break;
19
←
 Execution continues on line 3267→
     case ',':
c = '\0';
break;

     case '#':
/* Ignore rest of this alternative as far as
   constraint checking is concerned.  */
do
  p++;
while (*p && *p != ',');
len = 0;
break;

     case '&':
earlyclobber[opno] = 1;
if (seen_earlyclobber_at < 0)
  seen_earlyclobber_at = opno;
break;

     case '0':  case '1':  case '2':  case '3':  case '4':
     case '5':  case '6':  case '7':  case '8':  case '9':
{
  /* This operand must be the same as a previous one.
     This kind of constraint is used for instructions such
     as add when they take only two operands.

     Note that the lower-numbered operand is passed first.

     If we are not testing strictly, assume that this
     constraint will be satisfied.  */

  char *end;
  int match;

  match = strtoul (p, &end, 10);
  p = end;

  if (strict < 0)
    val = 1;
  else
    {
      rtx op1 = recog_data.operand[match];
      rtx op2 = recog_data.operand[opno];

      /* A unary operator may be accepted by the predicate,
	 but it is irrelevant for matching constraints.  */
      if (UNARY_P (op1)((rtx_class[(int) (((enum rtx_code) (op1)->code))]) == RTX_UNARY
))
	op1 = XEXP (op1, 0)(((op1)->u.fld[0]).rt_rtx);
      if (UNARY_P (op2)((rtx_class[(int) (((enum rtx_code) (op2)->code))]) == RTX_UNARY
))
	op2 = XEXP (op2, 0)(((op2)->u.fld[0]).rt_rtx);

      val = operands_match_p (op1, op2);
    }

  matching_operands[opno] = match;
  matching_operands[match] = opno;

  if (val != 0)
    win = 1;

  /* If output is *x and input is *--x, arrange later
     to change the output to *--x as well, since the
     output op is the one that will be printed.  */
  if (val == 2 && strict > 0)
    {
      funny_match[funny_match_index].this_op = opno;
      funny_match[funny_match_index++].other = match;
    }
}
len = 0;
break;

     case 'p':
/* p is used for address_operands.  When we are called by
   gen_reload, no one will have checked that the address is
   strictly valid, i.e., that all pseudos requiring hard regs
   have gotten them.  We also want to make sure we have a
   valid mode.  */
if ((GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode)
     || SCALAR_INT_MODE_P (GET_MODE (op))(((enum mode_class) mode_class[((machine_mode) (op)->mode)
]) == MODE_INT || ((enum mode_class) mode_class[((machine_mode
) (op)->mode)]) == MODE_PARTIAL_INT))
    && (strict <= 0
	|| (strict_memory_address_pstrict_memory_address_addr_space_p ((recog_data.operand_mode[
opno]), (op), 0)
	     (recog_data.operand_mode[opno], op)strict_memory_address_addr_space_p ((recog_data.operand_mode[
opno]), (op), 0))))
  win = 1;
break;

/* No need to check general_operand again;
   it was done in insn-recog.cc.  Well, except that reload
   doesn't check the validity of its replacements, but
   that should only matter when there's a bug.  */
     case 'g':
/* Anything goes unless it is a REG and really has a hard reg
   but the hard reg is not in the class GENERAL_REGS.  */
if (REG_P (op)(((enum rtx_code) (op)->code) == REG))
  {
    if (strict < 0
	|| GENERAL_REGS == ALL_REGS
	|| (reload_in_progress
	    && REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76)
	|| reg_fits_class_p (op, GENERAL_REGS, offset, mode))
      win = 1;
  }
else if (strict < 0 || general_operand (op, mode))
  win = 1;
break;

     default:
{
  enum constraint_num cn = lookup_constraint (p);
  enum reg_class cl = reg_class_for_constraint (cn);
  if (cl != NO_REGS)
    {
      if (strict < 0
	  || (strict == 0
	      && REG_P (op)(((enum rtx_code) (op)->code) == REG)
	      && REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76)
	  || (strict == 0 && GET_CODE (op)((enum rtx_code) (op)->code) == SCRATCH)
	  || (REG_P (op)(((enum rtx_code) (op)->code) == REG)
	      && reg_fits_class_p (op, cl, offset, mode)))
        win = 1;
    }

  else if (constraint_satisfied_p (op, cn))
    win = 1;

  else if (insn_extra_memory_constraint (cn)
	   /* Every memory operand can be reloaded to fit.  */
	   && ((strict < 0 && MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
	       /* Before reload, accept what reload can turn
		  into a mem.  */
	       || (strict < 0 && CONSTANT_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ
))
	       /* Before reload, accept a pseudo or hard register,
		  since LRA can turn it into a mem.  */
	       || (strict < 0 && targetm.lra_p () && REG_P (op)(((enum rtx_code) (op)->code) == REG))
	       /* During reload, accept a pseudo  */
	       || (reload_in_progress && REG_P (op)(((enum rtx_code) (op)->code) == REG)
		   && REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76)))
    win = 1;
  else if (insn_extra_address_constraint (cn)
	   /* Every address operand can be reloaded to fit.  */
	   && strict < 0)
    win = 1;
  /* Cater to architectures like IA-64 that define extra memory
     constraints without using define_memory_constraint.  */
  else if (reload_in_progress
	   && REG_P (op)(((enum rtx_code) (op)->code) == REG)
	   && REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76
	   && reg_renumber[REGNO (op)(rhs_regno(op))] < 0
	   && reg_equiv_mem (REGNO (op))(*reg_equivs)[((rhs_regno(op)))].mem != 0
	   && constraint_satisfied_p
	      (reg_equiv_mem (REGNO (op))(*reg_equivs)[((rhs_regno(op)))].mem, cn))
    win = 1;
  break;
}
     }
 while (p += len, c);

 constraints[opno] = p;
 /* If this operand did not win somehow,
    this alternative loses.  */
 if (! win20.1
'win' is 1
)
21
←
Taking false branch→
   lose = 1;
}
    /* This alternative won; the operands are ok.
Change whichever operands this alternative says to change.  */
    if (! lose)
{
 int opno, eopno;

 /* See if any earlyclobber operand conflicts with some other
    operand.  */

 if (strict > 0  && seen_earlyclobber_at >= 0)
   for (eopno = seen_earlyclobber_at;
 eopno < recog_data.n_operands;
 eopno++)
     /* Ignore earlyclobber operands now in memory,
 because we would often report failure when we have
 two memory operands, one of which was formerly a REG.  */
     if (earlyclobber[eopno]
  && REG_P (recog_data.operand[eopno])(((enum rtx_code) (recog_data.operand[eopno])->code) == REG
))
for (opno = 0; opno < recog_data.n_operands; opno++)
  if ((MEM_P (recog_data.operand[opno])(((enum rtx_code) (recog_data.operand[opno])->code) == MEM
)
       || recog_data.operand_type[opno] != OP_OUT)
      && opno != eopno
      /* Ignore things like match_operator operands.  */
      && *recog_data.constraints[opno] != 0
      && ! (matching_operands[opno] == eopno
	    && operands_match_p (recog_data.operand[opno],
				 recog_data.operand[eopno]))
      && ! safe_from_earlyclobber (recog_data.operand[opno],
				   recog_data.operand[eopno]))
    lose = 1;

 if (! lose)
   {
     while (--funny_match_index >= 0)
{
  recog_data.operand[funny_match[funny_match_index].other]
    = recog_data.operand[funny_match[funny_match_index].this_op];
}

     /* For operands without < or > constraints reject side-effects.  */
     if (AUTO_INC_DEC0 && recog_data.is_asm)
{
  for (opno = 0; opno < recog_data.n_operands; opno++)
    if (MEM_P (recog_data.operand[opno])(((enum rtx_code) (recog_data.operand[opno])->code) == MEM
))
      switch (GET_CODE (XEXP (recog_data.operand[opno], 0))((enum rtx_code) ((((recog_data.operand[opno])->u.fld[0]).
rt_rtx))->code))
	{
	case PRE_INC:
	case POST_INC:
	case PRE_DEC:
	case POST_DEC:
	case PRE_MODIFY:
	case POST_MODIFY:
	  if (strchr (recog_data.constraints[opno], '<') == NULLnullptr
	      && strchr (recog_data.constraints[opno], '>')
		 == NULLnullptr)
	    return 0;
	  break;
	default:
	  break;
	}
}

     return 1;
   }
}

    which_alternative++;
  }
while (which_alternative < recog_data.n_alternatives);

which_alternative = -1;
/* If we are about to reject this, but we are not to test strictly,
   try a very loose test.  Only return failure if it fails also.  */
if (strict == 0)
  return constrain_operands (-1, alternatives);
else
  return 0;
3352}

3354/* Return true iff OPERAND (assumed to be a REG rtx)
 is a hard reg in class CLASS when its regno is offset by OFFSET
 and changed to mode MODE.
 If REG occupies multiple hard regs, all of them must be in CLASS.  */

3359bool
3360reg_fits_class_p (const_rtx operand, reg_class_t cl, int offset,
  machine_mode mode)
3362{
unsigned int regno = REGNO (operand)(rhs_regno(operand));

if (cl == NO_REGS)
  return false;

/* Regno must not be a pseudo register.  Offset may be negative.  */
return (HARD_REGISTER_NUM_P (regno)((regno) < 76)
 && HARD_REGISTER_NUM_P (regno + offset)((regno + offset) < 76)
 && in_hard_reg_set_p (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[(int) cl], mode, 
		regno + offset));
3373}
3374
3375/* Split single instruction.  Helper function for split_all_insns and
 split_all_insns_noflow.  Return last insn in the sequence if successful,
 or NULL if unsuccessful.  */

3379static rtx_insn *
3380split_insn (rtx_insn *insn)
3381{
/* Split insns here to get max fine-grain parallelism.  */
rtx_insn *first = PREV_INSN (insn);
rtx_insn *last = try_split (PATTERN (insn), insn, 1);
rtx insn_set, last_set, note;

if (last == insn)
  return NULLnullptr;

/* If the original instruction was a single set that was known to be
   equivalent to a constant, see if we can say the same about the last
   instruction in the split sequence.  The two instructions must set
   the same destination.  */
insn_set = single_set (insn);
if (insn_set)
  {
    last_set = single_set (last);
    if (last_set && rtx_equal_p (SET_DEST (last_set)(((last_set)->u.fld[0]).rt_rtx), SET_DEST (insn_set)(((insn_set)->u.fld[0]).rt_rtx)))
{
 note = find_reg_equal_equiv_note (insn);
 if (note && CONSTANT_P (XEXP (note, 0))((rtx_class[(int) (((enum rtx_code) ((((note)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
   set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0)(((note)->u.fld[0]).rt_rtx));
 else if (CONSTANT_P (SET_SRC (insn_set))((rtx_class[(int) (((enum rtx_code) ((((insn_set)->u.fld[1
]).rt_rtx))->code))]) == RTX_CONST_OBJ))
   set_unique_reg_note (last, REG_EQUAL,
		 copy_rtx (SET_SRC (insn_set)(((insn_set)->u.fld[1]).rt_rtx)));
}
  }

/* try_split returns the NOTE that INSN became.  */
SET_INSN_DELETED (insn)set_insn_deleted (insn);;

/* ??? Coddle to md files that generate subregs in post-reload
   splitters instead of computing the proper hard register.  */
if (reload_completed && first != last)
  {
    first = NEXT_INSN (first);
    for (;;)
{
 if (INSN_P (first)(((((enum rtx_code) (first)->code) == INSN) || (((enum rtx_code
) (first)->code) == JUMP_INSN) || (((enum rtx_code) (first
)->code) == CALL_INSN)) || (((enum rtx_code) (first)->code
) == DEBUG_INSN)))
   cleanup_subreg_operands (first);
 if (first == last)
   break;
 first = NEXT_INSN (first);
}
  }

return last;
3428}

3430/* Split all insns in the function.  If UPD_LIFE, update life info after.  */

3432void
3433split_all_insns (void)
3434{
bool changed;
bool need_cfg_cleanup = false;
basic_block bb;

auto_sbitmap blocks (last_basic_block_for_fn (cfun)(((cfun + 0))->cfg->x_last_basic_block));
bitmap_clear (blocks);
changed = false;

FOR_EACH_BB_REVERSE_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_exit_block_ptr->prev_bb
; bb != ((cfun + 0))->cfg->x_entry_block_ptr; bb = bb->
prev_bb)
  {
    rtx_insn *insn, *next;
    bool finish = false;

    rtl_profile_for_bb (bb);
    for (insn = BB_HEAD (bb)(bb)->il.x.head_; !finish ; insn = next)
{
 /* Can't use `next_real_insn' because that might go across
    CODE_LABELS and short-out basic blocks.  */
 next = NEXT_INSN (insn);
 finish = (insn == BB_END (bb)(bb)->il.x.rtl->end_);

 /* If INSN has a REG_EH_REGION note and we split INSN, the
    resulting split may not have/need REG_EH_REGION notes.

    If that happens and INSN was the last reference to the
    given EH region, then the EH region will become unreachable.
    We cannot leave the unreachable blocks in the CFG as that
    will trigger a checking failure.

    So track if INSN has a REG_EH_REGION note.  If so and we
    split INSN, then trigger a CFG cleanup.  */
 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX(rtx) 0);
 if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
   {
     rtx set = single_set (insn);

     /* Don't split no-op move insns.  These should silently
 disappear later in final.  Splitting such insns would
 break the code that handles LIBCALL blocks.  */
     if (set && set_noop_p (set))
{
  /* Nops get in the way while scheduling, so delete them
     now if register allocation has already been done.  It
     is too risky to try to do this before register
     allocation, and there are unlikely to be very many
     nops then anyways.  */
  if (reload_completed)
      delete_insn_and_edges (insn);
  if (note)
    need_cfg_cleanup = true;
}
     else
{
  if (split_insn (insn))
    {
      bitmap_set_bit (blocks, bb->index);
      changed = true;
      if (note)
	need_cfg_cleanup = true;
    }
}
   }
}
  }

default_rtl_profile ();
if (changed)
  {
    find_many_sub_basic_blocks (blocks);

    /* Splitting could drop an REG_EH_REGION if it potentially
trapped in its original form, but does not in its split
form.  Consider a FLOAT_TRUNCATE which splits into a memory
store/load pair and -fnon-call-exceptions.  */
    if (need_cfg_cleanup)
cleanup_cfg (0);
  }

checking_verify_flow_info ();
3514}

3516/* Same as split_all_insns, but do not expect CFG to be available.
 Used by machine dependent reorg passes.  */

3519unsigned int
3520split_all_insns_noflow (void)
3521{
rtx_insn *next, *insn;

for (insn = get_insns (); insn; insn = next)
  {
    next = NEXT_INSN (insn);
    if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
{
 /* Don't split no-op move insns.  These should silently
    disappear later in final.  Splitting such insns would
    break the code that handles LIBCALL blocks.  */
 rtx set = single_set (insn);
 if (set && set_noop_p (set))
   {
     /* Nops get in the way while scheduling, so delete them
 now if register allocation has already been done.  It
 is too risky to try to do this before register
 allocation, and there are unlikely to be very many
 nops then anyways.

 ??? Should we use delete_insn when the CFG isn't valid?  */
     if (reload_completed)
delete_insn_and_edges (insn);
   }
 else
   split_insn (insn);
}
  }
return 0;
3550}
3551
3552struct peep2_insn_data
3553{
rtx_insn *insn;
regset live_before;
3556};

3558static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP25 + 1];
3559static int peep2_current;

3561static bool peep2_do_rebuild_jump_labels;
3562static bool peep2_do_cleanup_cfg;

3564/* The number of instructions available to match a peep2.  */
3565int peep2_current_count;

3567/* A marker indicating the last insn of the block.  The live_before regset
 for this element is correct, indicating DF_LIVE_OUT for the block.  */
3569#define PEEP2_EOBinvalid_insn_rtx invalid_insn_rtx

3571/* Wrap N to fit into the peep2_insn_data buffer.  */

3573static int
3574peep2_buf_position (int n)
3575{
if (n >= MAX_INSNS_PER_PEEP25 + 1)
  n -= MAX_INSNS_PER_PEEP25 + 1;
return n;
3579}

3581/* Return the Nth non-note insn after `current', or return NULL_RTX if it
 does not exist.  Used by the recognizer to find the next insn to match
 in a multi-insn pattern.  */

3585rtx_insn *
3586peep2_next_insn (int n)
3587{
gcc_assert (n <= peep2_current_count)((void)(!(n <= peep2_current_count) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3588, __FUNCTION__), 0 : 0));

n = peep2_buf_position (peep2_current + n);

return peep2_insn_data[n].insn;
3593}

3595/* Return true if REGNO is dead before the Nth non-note insn
 after `current'.  */

3598int
3599peep2_regno_dead_p (int ofs, int regno)
3600{
gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1)((void)(!(ofs < 5 + 1) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3601, __FUNCTION__), 0 : 0));

ofs = peep2_buf_position (peep2_current + ofs);

gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX)((void)(!(peep2_insn_data[ofs].insn != (rtx) 0) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3605, __FUNCTION__), 0 : 0));

return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno)bitmap_bit_p (peep2_insn_data[ofs].live_before, regno);
3608}

3610/* Similarly for a REG.  */

3612int
3613peep2_reg_dead_p (int ofs, rtx reg)
3614{
gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1)((void)(!(ofs < 5 + 1) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3615, __FUNCTION__), 0 : 0));

ofs = peep2_buf_position (peep2_current + ofs);

gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX)((void)(!(peep2_insn_data[ofs].insn != (rtx) 0) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3619, __FUNCTION__), 0 : 0));

unsigned int end_regno = END_REGNO (reg);
for (unsigned int regno = REGNO (reg)(rhs_regno(reg)); regno < end_regno; ++regno)
  if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno)bitmap_bit_p (peep2_insn_data[ofs].live_before, regno))
    return 0;
return 1;
3626}

3628/* Regno offset to be used in the register search.  */
3629static int search_ofs;

3631/* Try to find a hard register of mode MODE, matching the register class in
 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
 remains available until the end of LAST_INSN.  LAST_INSN may be NULL_RTX,
 in which case the only condition is that the register must be available
 before CURRENT_INSN.
 Registers that already have bits set in REG_SET will not be considered.

 If an appropriate register is available, it will be returned and the
 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
 returned.  */

3642rtx
3643peep2_find_free_register (int from, int to, const char *class_str,
	  machine_mode mode, HARD_REG_SET *reg_set)
3645{
enum reg_class cl;
HARD_REG_SET live;
df_ref def;
int i;

gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1)((void)(!(from < 5 + 1) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3651, __FUNCTION__), 0 : 0));
gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1)((void)(!(to < 5 + 1) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3652, __FUNCTION__), 0 : 0));

from = peep2_buf_position (peep2_current + from);
to = peep2_buf_position (peep2_current + to);

gcc_assert (peep2_insn_data[from].insn != NULL_RTX)((void)(!(peep2_insn_data[from].insn != (rtx) 0) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3657, __FUNCTION__), 0 : 0));
REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before)do { CLEAR_HARD_REG_SET (live); reg_set_to_hard_reg_set (&
live, peep2_insn_data[from].live_before); } while (0);

while (from != to)
  {
    gcc_assert (peep2_insn_data[from].insn != NULL_RTX)((void)(!(peep2_insn_data[from].insn != (rtx) 0) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3662, __FUNCTION__), 0 : 0));

    /* Don't use registers set or clobbered by the insn.  */
    FOR_EACH_INSN_DEF (def, peep2_insn_data[from].insn)for (def = (((df->insns[(INSN_UID (peep2_insn_data[from].insn
))]))->defs); def; def = ((def)->base.next_loc))
SET_HARD_REG_BIT (live, DF_REF_REGNO (def)((def)->base.regno));

    from = peep2_buf_position (from + 1);
  }

cl = reg_class_for_constraint (lookup_constraint (class_str));

for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
  {
    int raw_regno, regno, success, j;

    /* Distribute the free registers as much as possible.  */
    raw_regno = search_ofs + i;
    if (raw_regno >= FIRST_PSEUDO_REGISTER76)
raw_regno -= FIRST_PSEUDO_REGISTER76;
3681#ifdef REG_ALLOC_ORDER{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17
, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48
, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 }
    regno = reg_alloc_order(this_target_hard_regs->x_reg_alloc_order)[raw_regno];
3683#else
    regno = raw_regno;
3685#endif

    /* Can it support the mode we need?  */
    if (!targetm.hard_regno_mode_ok (regno, mode))
continue;

    success = 1;
    for (j = 0; success && j < hard_regno_nregs (regno, mode); j++)
{
 /* Don't allocate fixed registers.  */
 if (fixed_regs(this_target_hard_regs->x_fixed_regs)[regno + j])
   {
     success = 0;
     break;
   }
 /* Don't allocate global registers.  */
 if (global_regs[regno + j])
   {
     success = 0;
     break;
   }
 /* Make sure the register is of the right class.  */
 if (! TEST_HARD_REG_BIT (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[cl], regno + j))
   {
     success = 0;
     break;
   }
 /* And that we don't create an extra save/restore.  */
 if (! crtl(&x_rtl)->abi->clobbers_full_reg_p (regno + j)
     && ! df_regs_ever_live_p (regno + j))
   {
     success = 0;
     break;
   }

 if (! targetm.hard_regno_scratch_ok (regno + j))
   {
     success = 0;
     break;
   }

 /* And we don't clobber traceback for noreturn functions.  */
 if ((regno + j == FRAME_POINTER_REGNUM19
      || regno + j == HARD_FRAME_POINTER_REGNUM6)
     && (! reload_completed || frame_pointer_needed((&x_rtl)->frame_pointer_needed)))
   {
     success = 0;
     break;
   }

 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
     || TEST_HARD_REG_BIT (live, regno + j))
   {
     success = 0;
     break;
   }
}

    if (success)
{
 add_to_hard_reg_set (reg_set, mode, regno);

 /* Start the next search with the next register.  */
 if (++raw_regno >= FIRST_PSEUDO_REGISTER76)
   raw_regno = 0;
 search_ofs = raw_regno;

 return gen_rtx_REG (mode, regno);
}
  }

search_ofs = 0;
return NULL_RTX(rtx) 0;
3758}

3760/* Forget all currently tracked instructions, only remember current
 LIVE regset.  */

3763static void
3764peep2_reinit_state (regset live)
3765{
int i;

/* Indicate that all slots except the last holds invalid data.  */
for (i = 0; i < MAX_INSNS_PER_PEEP25; ++i)
  peep2_insn_data[i].insn = NULLnullptr;
peep2_current_count = 0;

/* Indicate that the last slot contains live_after data.  */
peep2_insn_data[MAX_INSNS_PER_PEEP25].insn = PEEP2_EOBinvalid_insn_rtx;
peep2_current = MAX_INSNS_PER_PEEP25;

COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live)bitmap_copy (peep2_insn_data[5].live_before, live);
3778}

3780/* Copies frame related info of an insn (OLD_INSN) to the single
 insn (NEW_INSN) that was obtained by splitting OLD_INSN.  */

3783void
3784copy_frame_info_to_split_insn (rtx_insn *old_insn, rtx_insn *new_insn)
3785{
bool any_note = false;
rtx note;

if (!RTX_FRAME_RELATED_P (old_insn)(__extension__ ({ __typeof ((old_insn)) const _rtx = ((old_insn
)); if (((enum rtx_code) (_rtx)->code) != DEBUG_INSN &&
 ((enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != CALL_INSN && ((enum rtx_code) (
_rtx)->code) != JUMP_INSN && ((enum rtx_code) (_rtx
)->code) != BARRIER && ((enum rtx_code) (_rtx)->
code) != SET) rtl_check_failed_flag ("RTX_FRAME_RELATED_P",_rtx
, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3789, __FUNCTION__); _rtx; })->frame_related))
  return;

RTX_FRAME_RELATED_P (new_insn)(__extension__ ({ __typeof ((new_insn)) const _rtx = ((new_insn
)); if (((enum rtx_code) (_rtx)->code) != DEBUG_INSN &&
 ((enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != CALL_INSN && ((enum rtx_code) (
_rtx)->code) != JUMP_INSN && ((enum rtx_code) (_rtx
)->code) != BARRIER && ((enum rtx_code) (_rtx)->
code) != SET) rtl_check_failed_flag ("RTX_FRAME_RELATED_P",_rtx
, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3792, __FUNCTION__); _rtx; })->frame_related) = 1;

/* Allow the backend to fill in a note during the split.  */
for (note = REG_NOTES (new_insn)(((new_insn)->u.fld[6]).rt_rtx); note ; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
  switch (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)))
    {
    case REG_FRAME_RELATED_EXPR:
    case REG_CFA_DEF_CFA:
    case REG_CFA_ADJUST_CFA:
    case REG_CFA_OFFSET:
    case REG_CFA_REGISTER:
    case REG_CFA_EXPRESSION:
    case REG_CFA_RESTORE:
    case REG_CFA_SET_VDRAP:
      any_note = true;
      break;
    default:
      break;
    }

/* If the backend didn't supply a note, copy one over.  */
if (!any_note)
  for (note = REG_NOTES (old_insn)(((old_insn)->u.fld[6]).rt_rtx); note ; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
    switch (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)))
      {
      case REG_FRAME_RELATED_EXPR:
      case REG_CFA_DEF_CFA:
      case REG_CFA_ADJUST_CFA:
      case REG_CFA_OFFSET:
      case REG_CFA_REGISTER:
      case REG_CFA_EXPRESSION:
      case REG_CFA_RESTORE:
      case REG_CFA_SET_VDRAP:
        add_reg_note (new_insn, REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)), XEXP (note, 0)(((note)->u.fld[0]).rt_rtx));
        any_note = true;
        break;
      default:
        break;
      }

/* If there still isn't a note, make sure the unwind info sees the
   same expression as before the split.  */
if (!any_note)
  {
    rtx old_set, new_set;

    /* The old insn had better have been simple, or annotated.  */
    old_set = single_set (old_insn);
    gcc_assert (old_set != NULL)((void)(!(old_set != nullptr) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3840, __FUNCTION__), 0 : 0));

    new_set = single_set (new_insn);
    if (!new_set || !rtx_equal_p (new_set, old_set))
      add_reg_note (new_insn, REG_FRAME_RELATED_EXPR, old_set);
  }

/* Copy prologue/epilogue status.  This is required in order to keep
   proper placement of EPILOGUE_BEG and the DW_CFA_remember_state.  */
maybe_copy_prologue_epilogue_insn (old_insn, new_insn);
3850}

3852/* While scanning basic block BB, we found a match of length MATCH_LEN,
 starting at INSN.  Perform the replacement, removing the old insns and
 replacing them with ATTEMPT.  Returns the last insn emitted, or NULL
 if the replacement is rejected.  */

3857static rtx_insn *
3858peep2_attempt (basic_block bb, rtx_insn *insn, int match_len, rtx_insn *attempt)
3859{
int i;
rtx_insn *last, *before_try, *x;
rtx eh_note, as_note;
rtx_insn *old_insn;
rtx_insn *new_insn;
bool was_call = false;

/* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
   match more than one insn, or to be split into more than one insn.  */
old_insn = peep2_insn_data[peep2_current].insn;
if (RTX_FRAME_RELATED_P (old_insn)(__extension__ ({ __typeof ((old_insn)) const _rtx = ((old_insn
)); if (((enum rtx_code) (_rtx)->code) != DEBUG_INSN &&
 ((enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != CALL_INSN && ((enum rtx_code) (
_rtx)->code) != JUMP_INSN && ((enum rtx_code) (_rtx
)->code) != BARRIER && ((enum rtx_code) (_rtx)->
code) != SET) rtl_check_failed_flag ("RTX_FRAME_RELATED_P",_rtx
, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3870, __FUNCTION__); _rtx; })->frame_related))
  {
    if (match_len != 0)
return NULLnullptr;

    /* Look for one "active" insn.  I.e. ignore any "clobber" insns that
may be in the stream for the purpose of register allocation.  */
    if (active_insn_p (attempt))
new_insn = attempt;
    else
new_insn = next_active_insn (attempt);
    if (next_active_insn (new_insn))
return NULLnullptr;

    /* We have a 1-1 replacement.  Copy over any frame-related info.  */
    copy_frame_info_to_split_insn (old_insn, new_insn);
  }

/* If we are splitting a CALL_INSN, look for the CALL_INSN
   in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
   cfg-related call notes.  */
for (i = 0; i <= match_len; ++i)
  {
    int j;
    rtx note;

    j = peep2_buf_position (peep2_current + i);
    old_insn = peep2_insn_data[j].insn;
    if (!CALL_P (old_insn)(((enum rtx_code) (old_insn)->code) == CALL_INSN))
continue;
    was_call = true;

    new_insn = attempt;
    while (new_insn != NULL_RTX(rtx) 0)
{
 if (CALL_P (new_insn)(((enum rtx_code) (new_insn)->code) == CALL_INSN))
   break;
 new_insn = NEXT_INSN (new_insn);
}

    gcc_assert (new_insn != NULL_RTX)((void)(!(new_insn != (rtx) 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3910, __FUNCTION__), 0 : 0));

    CALL_INSN_FUNCTION_USAGE (new_insn)(((new_insn)->u.fld[7]).rt_rtx)
= CALL_INSN_FUNCTION_USAGE (old_insn)(((old_insn)->u.fld[7]).rt_rtx);
    SIBLING_CALL_P (new_insn)(__extension__ ({ __typeof ((new_insn)) const _rtx = ((new_insn
)); if (((enum rtx_code) (_rtx)->code) != CALL_INSN) rtl_check_failed_flag
 ("SIBLING_CALL_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3914, __FUNCTION__); _rtx; })->jump) = SIBLING_CALL_P (old_insn)(__extension__ ({ __typeof ((old_insn)) const _rtx = ((old_insn
)); if (((enum rtx_code) (_rtx)->code) != CALL_INSN) rtl_check_failed_flag
 ("SIBLING_CALL_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3914, __FUNCTION__); _rtx; })->jump);

    for (note = REG_NOTES (old_insn)(((old_insn)->u.fld[6]).rt_rtx);
  note;
  note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
switch (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)))
 {
 case REG_NORETURN:
 case REG_SETJMP:
 case REG_TM:
 case REG_CALL_NOCF_CHECK:
   add_reg_note (new_insn, REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)),
	  XEXP (note, 0)(((note)->u.fld[0]).rt_rtx));
   break;
 default:
   /* Discard all other reg notes.  */
   break;
 }

    /* Croak if there is another call in the sequence.  */
    while (++i <= match_len)
{
 j = peep2_buf_position (peep2_current + i);
 old_insn = peep2_insn_data[j].insn;
 gcc_assert (!CALL_P (old_insn))((void)(!(!(((enum rtx_code) (old_insn)->code) == CALL_INSN
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3938, __FUNCTION__), 0 : 0));
}
    break;
  }

/* If we matched any instruction that had a REG_ARGS_SIZE, then
   move those notes over to the new sequence.  */
as_note = NULLnullptr;
for (i = match_len; i >= 0; --i)
  {
    int j = peep2_buf_position (peep2_current + i);
    old_insn = peep2_insn_data[j].insn;

    as_note = find_reg_note (old_insn, REG_ARGS_SIZE, NULLnullptr);
    if (as_note)
break;
  }

i = peep2_buf_position (peep2_current + match_len);
eh_note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX(rtx) 0);

/* Replace the old sequence with the new.  */
rtx_insn *peepinsn = peep2_insn_data[i].insn;
last = emit_insn_after_setloc (attempt,
		 peep2_insn_data[i].insn,
		 INSN_LOCATION (peepinsn));
if (JUMP_P (peepinsn)(((enum rtx_code) (peepinsn)->code) == JUMP_INSN) && JUMP_P (last)(((enum rtx_code) (last)->code) == JUMP_INSN))
  CROSSING_JUMP_P (last)(__extension__ ({ __typeof ((last)) const _rtx = ((last)); if
 (((enum rtx_code) (_rtx)->code) != JUMP_INSN) rtl_check_failed_flag
 ("CROSSING_JUMP_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3965, __FUNCTION__); _rtx; })->jump) = CROSSING_JUMP_P (peepinsn)(__extension__ ({ __typeof ((peepinsn)) const _rtx = ((peepinsn
)); if (((enum rtx_code) (_rtx)->code) != JUMP_INSN) rtl_check_failed_flag
 ("CROSSING_JUMP_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 3965, __FUNCTION__); _rtx; })->jump);
before_try = PREV_INSN (insn);
delete_insn_chain (insn, peep2_insn_data[i].insn, false);

/* Re-insert the EH_REGION notes.  */
if (eh_note || (was_call && nonlocal_goto_handler_labels((&x_rtl)->x_nonlocal_goto_handler_labels)))
  {
    edge eh_edge;
    edge_iterator ei;

    FOR_EACH_EDGE (eh_edge, ei, bb->succs)for ((ei) = ei_start_1 (&((bb->succs))); ei_cond ((ei)
, &(eh_edge)); ei_next (&(ei)))
if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
 break;

    if (eh_note)
copy_reg_eh_region_note_backward (eh_note, last, before_try);

    if (eh_edge)
for (x = last; x != before_try; x = PREV_INSN (x))
 if (x != BB_END (bb)(bb)->il.x.rtl->end_
     && (can_throw_internal (x)
  || can_nonlocal_goto (x)))
   {
     edge nfte, nehe;
     int flags;

     nfte = split_block (bb, x);
     flags = (eh_edge->flags
       & (EDGE_EH | EDGE_ABNORMAL));
     if (CALL_P (x)(((enum rtx_code) (x)->code) == CALL_INSN))
flags |= EDGE_ABNORMAL_CALL;
     nehe = make_edge (nfte->src, eh_edge->dest,
		flags);

     nehe->probability = eh_edge->probability;
     nfte->probability = nehe->probability.invert ();

     peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest);
     bb = nfte->src;
     eh_edge = nehe;
   }

    /* Converting possibly trapping insn to non-trapping is
possible.  Zap dummy outgoing edges.  */
    peep2_do_cleanup_cfg |= purge_dead_edges (bb);
  }

/* Re-insert the ARGS_SIZE notes.  */
if (as_note)
  fixup_args_size_notes (before_try, last, get_args_size (as_note));

/* Scan the new insns for embedded side effects and add appropriate
   REG_INC notes.  */
if (AUTO_INC_DEC0)
  for (x = last; x != before_try; x = PREV_INSN (x))
    if (NONDEBUG_INSN_P (x)((((enum rtx_code) (x)->code) == INSN) || (((enum rtx_code
) (x)->code) == JUMP_INSN) || (((enum rtx_code) (x)->code
) == CALL_INSN)))
add_auto_inc_notes (x, PATTERN (x));

/* If we generated a jump instruction, it won't have
   JUMP_LABEL set.  Recompute after we're done.  */
for (x = last; x != before_try; x = PREV_INSN (x))
  if (JUMP_P (x)(((enum rtx_code) (x)->code) == JUMP_INSN))
    {
peep2_do_rebuild_jump_labels = true;
break;
    }

return last;
4033}

4035/* After performing a replacement in basic block BB, fix up the life
 information in our buffer.  LAST is the last of the insns that we
 emitted as a replacement.  PREV is the insn before the start of
 the replacement.  MATCH_LEN is the number of instructions that were
 matched, and which now need to be replaced in the buffer.  */

4041static void
4042peep2_update_life (basic_block bb, int match_len, rtx_insn *last,
   rtx_insn *prev)
4044{
int i = peep2_buf_position (peep2_current + match_len + 1);
rtx_insn *x;
regset_head live;

INIT_REG_SET (&live)bitmap_initialize (&live, &reg_obstack);
COPY_REG_SET (&live, peep2_insn_data[i].live_before)bitmap_copy (&live, peep2_insn_data[i].live_before);

gcc_assert (peep2_current_count >= match_len + 1)((void)(!(peep2_current_count >= match_len + 1) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 4052, __FUNCTION__), 0 : 0));
peep2_current_count -= match_len + 1;

x = last;
do
  {
    if (INSN_P (x)(((((enum rtx_code) (x)->code) == INSN) || (((enum rtx_code
) (x)->code) == JUMP_INSN) || (((enum rtx_code) (x)->code
) == CALL_INSN)) || (((enum rtx_code) (x)->code) == DEBUG_INSN
)))
{
 df_insn_rescan (x);
 if (peep2_current_count < MAX_INSNS_PER_PEEP25)
   {
     peep2_current_count++;
     if (--i < 0)
i = MAX_INSNS_PER_PEEP25;
     peep2_insn_data[i].insn = x;
     df_simulate_one_insn_backwards (bb, x, &live);
     COPY_REG_SET (peep2_insn_data[i].live_before, &live)bitmap_copy (peep2_insn_data[i].live_before, &live);
   }
}
    x = PREV_INSN (x);
  }
while (x != prev);
CLEAR_REG_SET (&live)bitmap_clear (&live);

peep2_current = i;
4077}

4079/* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
 Return true if we added it, false otherwise.  The caller will try to match
 peepholes against the buffer if we return false; otherwise it will try to
 add more instructions to the buffer.  */

4084static bool
4085peep2_fill_buffer (basic_block bb, rtx_insn *insn, regset live)
4086{
int pos;

/* Once we have filled the maximum number of insns the buffer can hold,
   allow the caller to match the insns against peepholes.  We wait until
   the buffer is full in case the target has similar peepholes of different
   length; we always want to match the longest if possible.  */
if (peep2_current_count == MAX_INSNS_PER_PEEP25)
  return false;

/* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
   any other pattern, lest it change the semantics of the frame info.  */
if (RTX_FRAME_RELATED_P (insn)(__extension__ ({ __typeof ((insn)) const _rtx = ((insn)); if
 (((enum rtx_code) (_rtx)->code) != DEBUG_INSN && (
(enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != CALL_INSN && ((enum rtx_code) (
_rtx)->code) != JUMP_INSN && ((enum rtx_code) (_rtx
)->code) != BARRIER && ((enum rtx_code) (_rtx)->
code) != SET) rtl_check_failed_flag ("RTX_FRAME_RELATED_P",_rtx
, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 4098, __FUNCTION__); _rtx; })->frame_related))
  {
    /* Let the buffer drain first.  */
    if (peep2_current_count > 0)
return false;
    /* Now the insn will be the only thing in the buffer.  */
  }

pos = peep2_buf_position (peep2_current + peep2_current_count);
peep2_insn_data[pos].insn = insn;
COPY_REG_SET (peep2_insn_data[pos].live_before, live)bitmap_copy (peep2_insn_data[pos].live_before, live);
peep2_current_count++;

df_simulate_one_insn_forwards (bb, insn, live);
return true;
4113}

4115/* Perform the peephole2 optimization pass.  */

4117static void
4118peephole2_optimize (void)
4119{
rtx_insn *insn;
bitmap live;
int i;
basic_block bb;

peep2_do_cleanup_cfg = false;
peep2_do_rebuild_jump_labels = false;

df_set_flags (DF_LR_RUN_DCE);
df_note_add_problem ();
df_analyze ();

/* Initialize the regsets we're going to use.  */
for (i = 0; i < MAX_INSNS_PER_PEEP25 + 1; ++i)
  peep2_insn_data[i].live_before = BITMAP_ALLOCbitmap_alloc (&reg_obstack);
search_ofs = 0;
live = BITMAP_ALLOCbitmap_alloc (&reg_obstack);

FOR_EACH_BB_REVERSE_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_exit_block_ptr->prev_bb
; bb != ((cfun + 0))->cfg->x_entry_block_ptr; bb = bb->
prev_bb)
  {
    bool past_end = false;
    int pos;

    rtl_profile_for_bb (bb);

    /* Start up propagation.  */
    bitmap_copy (live, DF_LR_IN (bb)(&(df_lr_get_bb_info ((bb)->index))->in));
    df_simulate_initialize_forwards (bb, live);
    peep2_reinit_state (live);

    insn = BB_HEAD (bb)(bb)->il.x.head_;
    for (;;)
{
 rtx_insn *attempt, *head;
 int match_len;

 if (!past_end && !NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)))
   {
   next_insn:
     insn = NEXT_INSN (insn);
     if (insn == NEXT_INSN (BB_END (bb)(bb)->il.x.rtl->end_))
past_end = true;
     continue;
   }
 if (!past_end && peep2_fill_buffer (bb, insn, live))
   goto next_insn;

 /* If we did not fill an empty buffer, it signals the end of the
    block.  */
 if (peep2_current_count == 0)
   break;

 /* The buffer filled to the current maximum, so try to match.  */

 pos = peep2_buf_position (peep2_current + peep2_current_count);
 peep2_insn_data[pos].insn = PEEP2_EOBinvalid_insn_rtx;
 COPY_REG_SET (peep2_insn_data[pos].live_before, live)bitmap_copy (peep2_insn_data[pos].live_before, live);

 /* Match the peephole.  */
 head = peep2_insn_data[peep2_current].insn;
 attempt = peephole2_insns (PATTERN (head), head, &match_len);
 if (attempt != NULLnullptr)
   {
     rtx_insn *last = peep2_attempt (bb, head, match_len, attempt);
     if (last)
{
  peep2_update_life (bb, match_len, last, PREV_INSN (attempt));
  continue;
}
   }

 /* No match: advance the buffer by one insn.  */
 peep2_current = peep2_buf_position (peep2_current + 1);
 peep2_current_count--;
}
  }

default_rtl_profile ();
for (i = 0; i < MAX_INSNS_PER_PEEP25 + 1; ++i)
  BITMAP_FREE (peep2_insn_data[i].live_before)((void) (bitmap_obstack_free ((bitmap) peep2_insn_data[i].live_before
), (peep2_insn_data[i].live_before) = (bitmap) nullptr));
BITMAP_FREE (live)((void) (bitmap_obstack_free ((bitmap) live), (live) = (bitmap
) nullptr));
if (peep2_do_rebuild_jump_labels)
  rebuild_jump_labels (get_insns ());
if (peep2_do_cleanup_cfg)
  cleanup_cfg (CLEANUP_CFG_CHANGED64);
4205}

4207/* Common predicates for use with define_bypass.  */

4209/* Helper function for store_data_bypass_p, handle just a single SET
 IN_SET.  */

4212static bool
4213store_data_bypass_p_1 (rtx_insn *out_insn, rtx in_set)
4214{
if (!MEM_P (SET_DEST (in_set))(((enum rtx_code) ((((in_set)->u.fld[0]).rt_rtx))->code
) == MEM))
  return false;

rtx out_set = single_set (out_insn);
if (out_set)
  return !reg_mentioned_p (SET_DEST (out_set)(((out_set)->u.fld[0]).rt_rtx), SET_DEST (in_set)(((in_set)->u.fld[0]).rt_rtx));

rtx out_pat = PATTERN (out_insn);
if (GET_CODE (out_pat)((enum rtx_code) (out_pat)->code) != PARALLEL)
  return false;

for (int i = 0; i < XVECLEN (out_pat, 0)(((((out_pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
  {
    rtx out_exp = XVECEXP (out_pat, 0, i)(((((out_pat)->u.fld[0]).rt_rtvec))->elem[i]);

    if (GET_CODE (out_exp)((enum rtx_code) (out_exp)->code) == CLOBBER || GET_CODE (out_exp)((enum rtx_code) (out_exp)->code) == USE)
continue;

    gcc_assert (GET_CODE (out_exp) == SET)((void)(!(((enum rtx_code) (out_exp)->code) == SET) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 4233, __FUNCTION__), 0 : 0));

    if (reg_mentioned_p (SET_DEST (out_exp)(((out_exp)->u.fld[0]).rt_rtx), SET_DEST (in_set)(((in_set)->u.fld[0]).rt_rtx)))
return false;
  }

return true;
4240}

4242/* True if the dependency between OUT_INSN and IN_INSN is on the store
 data not the address operand(s) of the store.  IN_INSN and OUT_INSN
 must be either a single_set or a PARALLEL with SETs inside.  */

4246int
4247store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
4248{
rtx in_set = single_set (in_insn);
if (in_set)
  return store_data_bypass_p_1 (out_insn, in_set);

rtx in_pat = PATTERN (in_insn);
if (GET_CODE (in_pat)((enum rtx_code) (in_pat)->code) != PARALLEL)
  return false;

for (int i = 0; i < XVECLEN (in_pat, 0)(((((in_pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
  {
    rtx in_exp = XVECEXP (in_pat, 0, i)(((((in_pat)->u.fld[0]).rt_rtvec))->elem[i]);

    if (GET_CODE (in_exp)((enum rtx_code) (in_exp)->code) == CLOBBER || GET_CODE (in_exp)((enum rtx_code) (in_exp)->code) == USE)
continue;

    gcc_assert (GET_CODE (in_exp) == SET)((void)(!(((enum rtx_code) (in_exp)->code) == SET) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 4264, __FUNCTION__), 0 : 0));

    if (!store_data_bypass_p_1 (out_insn, in_exp))
return false;
  }

return true;
4271}

4273/* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
 condition, and not the THEN or ELSE branch.  OUT_INSN may be either a single
 or multiple set; IN_INSN should be single_set for truth, but for convenience
 of insn categorization may be any JUMP or CALL insn.  */

4278int
4279if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
4280{
rtx out_set, in_set;

in_set = single_set (in_insn);
if (! in_set)
  {
    gcc_assert (JUMP_P (in_insn) || CALL_P (in_insn))((void)(!((((enum rtx_code) (in_insn)->code) == JUMP_INSN)
 || (((enum rtx_code) (in_insn)->code) == CALL_INSN)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 4286, __FUNCTION__), 0 : 0));
    return false;
  }

if (GET_CODE (SET_SRC (in_set))((enum rtx_code) ((((in_set)->u.fld[1]).rt_rtx))->code) != IF_THEN_ELSE)
  return false;
in_set = SET_SRC (in_set)(((in_set)->u.fld[1]).rt_rtx);

out_set = single_set (out_insn);
if (out_set)
  {
    if (reg_mentioned_p (SET_DEST (out_set)(((out_set)->u.fld[0]).rt_rtx), XEXP (in_set, 1)(((in_set)->u.fld[1]).rt_rtx))
 || reg_mentioned_p (SET_DEST (out_set)(((out_set)->u.fld[0]).rt_rtx), XEXP (in_set, 2)(((in_set)->u.fld[2]).rt_rtx)))
return false;
  }
else
  {
    rtx out_pat;
    int i;

    out_pat = PATTERN (out_insn);
    gcc_assert (GET_CODE (out_pat) == PARALLEL)((void)(!(((enum rtx_code) (out_pat)->code) == PARALLEL) ?
 fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 4307, __FUNCTION__), 0 : 0));

    for (i = 0; i < XVECLEN (out_pat, 0)(((((out_pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
{
 rtx exp = XVECEXP (out_pat, 0, i)(((((out_pat)->u.fld[0]).rt_rtvec))->elem[i]);

 if (GET_CODE (exp)((enum rtx_code) (exp)->code) == CLOBBER)
   continue;

 gcc_assert (GET_CODE (exp) == SET)((void)(!(((enum rtx_code) (exp)->code) == SET) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.cc"
, 4316, __FUNCTION__), 0 : 0));

 if (reg_mentioned_p (SET_DEST (out_set)(((out_set)->u.fld[0]).rt_rtx), XEXP (in_set, 1)(((in_set)->u.fld[1]).rt_rtx))
     || reg_mentioned_p (SET_DEST (out_set)(((out_set)->u.fld[0]).rt_rtx), XEXP (in_set, 2)(((in_set)->u.fld[2]).rt_rtx)))
   return false;
}
  }

return true;
4325}
4326
4327static unsigned int
4328rest_of_handle_peephole2 (void)
4329{
if (HAVE_peephole21)
  peephole2_optimize ();

return 0;
4334}

4336namespace {

4338const pass_data pass_data_peephole2 =
4339{
RTL_PASS, /* type */
"peephole2", /* name */
OPTGROUP_NONE, /* optinfo_flags */
TV_PEEPHOLE2, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
TODO_df_finish(1 << 17), /* todo_flags_finish */
4349};

4351class pass_peephole2 : public rtl_opt_pass
4352{
4353public:
pass_peephole2 (gcc::context *ctxt)
  : rtl_opt_pass (pass_data_peephole2, ctxt)
{}

/* opt_pass methods: */
/* The epiphany backend creates a second instance of this pass, so we need
   a clone method.  */
opt_pass * clone () final override { return new pass_peephole2 (m_ctxt); }
bool gate (function *) final override
{
  return (optimizeglobal_options.x_optimize > 0 && flag_peephole2global_options.x_flag_peephole2);
}
unsigned int execute (function *) final override
  {
    return rest_of_handle_peephole2 ();
  }

4371}; // class pass_peephole2

4373} // anon namespace

4375rtl_opt_pass *
4376make_pass_peephole2 (gcc::context *ctxt)
4377{
return new pass_peephole2 (ctxt);
4379}

4381namespace {

4383const pass_data pass_data_split_all_insns =
4384{
RTL_PASS, /* type */
"split1", /* name */
OPTGROUP_NONE, /* optinfo_flags */
TV_NONE, /* tv_id */
0, /* properties_required */
PROP_rtl_split_insns(1 << 17), /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
0, /* todo_flags_finish */
4394};

4396class pass_split_all_insns : public rtl_opt_pass
4397{
4398public:
pass_split_all_insns (gcc::context *ctxt)
  : rtl_opt_pass (pass_data_split_all_insns, ctxt)
{}

/* opt_pass methods: */
/* The epiphany backend creates a second instance of this pass, so
   we need a clone method.  */
opt_pass * clone () final override
{
  return new pass_split_all_insns (m_ctxt);
}
unsigned int execute (function *) final override
  {
    split_all_insns ();
    return 0;
  }

4416}; // class pass_split_all_insns

4418} // anon namespace

4420rtl_opt_pass *
4421make_pass_split_all_insns (gcc::context *ctxt)
4422{
return new pass_split_all_insns (ctxt);
4424}

4426namespace {

4428const pass_data pass_data_split_after_reload =
4429{
RTL_PASS, /* type */
"split2", /* name */
OPTGROUP_NONE, /* optinfo_flags */
TV_NONE, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
0, /* todo_flags_finish */
4439};

4441class pass_split_after_reload : public rtl_opt_pass
4442{
4443public:
pass_split_after_reload (gcc::context *ctxt)
  : rtl_opt_pass (pass_data_split_after_reload, ctxt)
{}

/* opt_pass methods: */
bool gate (function *) final override
  {
    /* If optimizing, then go ahead and split insns now.  */
    return optimizeglobal_options.x_optimize > 0;
  }

unsigned int execute (function *) final override
  {
    split_all_insns ();
    return 0;
  }

4461}; // class pass_split_after_reload

4463} // anon namespace

4465rtl_opt_pass *
4466make_pass_split_after_reload (gcc::context *ctxt)
4467{
return new pass_split_after_reload (ctxt);
4469}

4471static bool
4472enable_split_before_sched2 (void)
4473{
4474#ifdef INSN_SCHEDULING
return optimizeglobal_options.x_optimize > 0 && flag_schedule_insns_after_reloadglobal_options.x_flag_schedule_insns_after_reload;
4476#else
return false;
4478#endif
4479}

4481namespace {

4483const pass_data pass_data_split_before_sched2 =
4484{
RTL_PASS, /* type */
"split3", /* name */
OPTGROUP_NONE, /* optinfo_flags */
TV_NONE, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
0, /* todo_flags_finish */
4494};

4496class pass_split_before_sched2 : public rtl_opt_pass
4497{
4498public:
pass_split_before_sched2 (gcc::context *ctxt)
  : rtl_opt_pass (pass_data_split_before_sched2, ctxt)
{}

/* opt_pass methods: */
bool gate (function *) final override
  {
    return enable_split_before_sched2 ();
  }

unsigned int execute (function *) final override
  {
    split_all_insns ();
    return 0;
  }

4515}; // class pass_split_before_sched2

4517} // anon namespace

4519rtl_opt_pass *
4520make_pass_split_before_sched2 (gcc::context *ctxt)
4521{
return new pass_split_before_sched2 (ctxt);
4523}

4525namespace {

4527const pass_data pass_data_split_before_regstack =
4528{
RTL_PASS, /* type */
"split4", /* name */
OPTGROUP_NONE, /* optinfo_flags */
TV_NONE, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
0, /* todo_flags_finish */
4538};

4540class pass_split_before_regstack : public rtl_opt_pass
4541{
4542public:
pass_split_before_regstack (gcc::context *ctxt)
  : rtl_opt_pass (pass_data_split_before_regstack, ctxt)
{}

/* opt_pass methods: */
bool gate (function *) final override;
unsigned int execute (function *) final override
  {
    split_all_insns ();
    return 0;
  }

4555}; // class pass_split_before_regstack

4557bool
4558pass_split_before_regstack::gate (function *)
4559{
4560#if HAVE_ATTR_length1 && defined (STACK_REGS)
/* If flow2 creates new instructions which need splitting
   and scheduling after reload is not done, they might not be
   split until final which doesn't allow splitting
   if HAVE_ATTR_length.  Selective scheduling can result in
   further instructions that need splitting.  */
4566#ifdef INSN_SCHEDULING
return !enable_split_before_sched2 () || flag_selective_scheduling2global_options.x_flag_selective_scheduling2;
4568#else
return !enable_split_before_sched2 ();
4570#endif
4571#else
return false;
4573#endif
4574}

4576} // anon namespace

4578rtl_opt_pass *
4579make_pass_split_before_regstack (gcc::context *ctxt)
4580{
return new pass_split_before_regstack (ctxt);
4582}

4584namespace {

4586const pass_data pass_data_split_for_shorten_branches =
4587{
RTL_PASS, /* type */
"split5", /* name */
OPTGROUP_NONE, /* optinfo_flags */
TV_NONE, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
0, /* todo_flags_finish */
4597};

4599class pass_split_for_shorten_branches : public rtl_opt_pass
4600{
4601public:
pass_split_for_shorten_branches (gcc::context *ctxt)
  : rtl_opt_pass (pass_data_split_for_shorten_branches, ctxt)
{}

/* opt_pass methods: */
bool gate (function *) final override
  {
    /* The placement of the splitting that we do for shorten_branches
depends on whether regstack is used by the target or not.  */
4611#if HAVE_ATTR_length1 && !defined (STACK_REGS)
    return true;
4613#else
    return false;
4615#endif
  }

unsigned int execute (function *) final override
  {
    return split_all_insns_noflow ();
  }

4623}; // class pass_split_for_shorten_branches

4625} // anon namespace

4627rtl_opt_pass *
4628make_pass_split_for_shorten_branches (gcc::context *ctxt)
4629{
return new pass_split_for_shorten_branches (ctxt);
4631}

4633/* (Re)initialize the target information after a change in target.  */

4635void
4636recog_init ()
4637{
/* The information is zero-initialized, so we don't need to do anything
   first time round.  */
if (!this_target_recog->x_initialized)
  {
    this_target_recog->x_initialized = true;
    return;
  }
memset (this_target_recog->x_bool_attr_masks, 0,
 sizeof (this_target_recog->x_bool_attr_masks));
for (unsigned int i = 0; i < NUM_INSN_CODES; ++i)
  if (this_target_recog->x_op_alt[i])
    {
free (this_target_recog->x_op_alt[i]);
this_target_recog->x_op_alt[i] = 0;
    }
4653}