/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc

Bug Summary

File:	build/gcc/postreload.cc
Warning:	line 558, column 28 The left operand of '==' is a garbage value
Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-suse-linux -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name postreload.cc -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -resource-dir /usr/lib64/clang/15.0.7 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/backward -internal-isystem /usr/lib64/clang/15.0.7/include -internal-isystem /usr/local/include -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../x86_64-suse-linux/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2023-03-27-141847-20772-1/report-ivYuw7.plist -x c++ /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc
1/* Perform simple optimizations to clean up the result of reload.
 Copyright (C) 1987-2023 Free Software Foundation, Inc.

4This file is part of GCC.

6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8Software Foundation; either version 3, or (at your option) any later
9version.

11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14for more details.

16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3.  If not see
18<http://www.gnu.org/licenses/>.  */

20#include "config.h"
21#include "system.h"
22#include "coretypes.h"
23#include "backend.h"
24#include "target.h"
25#include "rtl.h"
26#include "tree.h"
27#include "predict.h"
28#include "df.h"
29#include "memmodel.h"
30#include "tm_p.h"
31#include "optabs.h"
32#include "regs.h"
33#include "emit-rtl.h"
34#include "recog.h"

36#include "cfgrtl.h"
37#include "cfgbuild.h"
38#include "cfgcleanup.h"
39#include "reload.h"
40#include "cselib.h"
41#include "tree-pass.h"
42#include "dbgcnt.h"
43#include "function-abi.h"
44#include "rtl-iter.h"

46static bool reload_cse_simplify (rtx_insn *, rtx);
47static void reload_cse_regs_1 (void);
48static int reload_cse_simplify_set (rtx, rtx_insn *);
49static int reload_cse_simplify_operands (rtx_insn *, rtx);

51static void reload_combine (void);
52static void reload_combine_note_use (rtx *, rtx_insn *, int, rtx);
53static void reload_combine_note_store (rtx, const_rtx, void *);

55static bool reload_cse_move2add (rtx_insn *);
56static void move2add_note_store (rtx, const_rtx, void *);

58/* Call cse / combine like post-reload optimization phases.
 FIRST is the first instruction.  */

61static void
62reload_cse_regs (rtx_insn *first ATTRIBUTE_UNUSED__attribute__ ((__unused__)))
63{
bool moves_converted;
reload_cse_regs_1 ();
reload_combine ();
moves_converted = reload_cse_move2add (first);
if (flag_expensive_optimizationsglobal_options.x_flag_expensive_optimizations)
  {
    if (moves_converted)
reload_combine ();
    reload_cse_regs_1 ();
  }
74}

76/* Try to simplify INSN.  Return true if the CFG may have changed.  */
77static bool
78reload_cse_simplify (rtx_insn *insn, rtx testreg)
79{
rtx body = PATTERN (insn);
basic_block insn_bb = BLOCK_FOR_INSN (insn);
unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs)vec_safe_length (insn_bb->succs);

/* If NO_FUNCTION_CSE has been set by the target, then we should not try
   to cse function calls.  */
if (NO_FUNCTION_CSE1 && CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
  return false;

/* Remember if this insn has been sp += const_int.  */
rtx sp_set = set_for_reg_notes (insn);
rtx sp_addend = NULL_RTX(rtx) 0;
if (sp_set
    && SET_DEST (sp_set)(((sp_set)->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
    && GET_CODE (SET_SRC (sp_set))((enum rtx_code) ((((sp_set)->u.fld[1]).rt_rtx))->code) == PLUS
    && XEXP (SET_SRC (sp_set), 0)((((((sp_set)->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
    && CONST_INT_P (XEXP (SET_SRC (sp_set), 1))(((enum rtx_code) (((((((sp_set)->u.fld[1]).rt_rtx))->u
.fld[1]).rt_rtx))->code) == CONST_INT))
  sp_addend = XEXP (SET_SRC (sp_set), 1)((((((sp_set)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx);

if (GET_CODE (body)((enum rtx_code) (body)->code) == SET)
  {
    int count = 0;

    /* Simplify even if we may think it is a no-op.
       We may think a memory load of a value smaller than WORD_SIZE
       is redundant because we haven't taken into account possible
       implicit extension.  reload_cse_simplify_set() will bring
       this out, so it's safer to simplify before we delete.  */
    count += reload_cse_simplify_set (body, insn);

    if (!count && cselib_redundant_set_p (body))
{
 if (check_for_inc_dec (insn))
   delete_insn_and_edges (insn);
 /* We're done with this insn.  */
 goto done;
}

    if (count > 0)
apply_change_group ();
    else
reload_cse_simplify_operands (insn, testreg);
  }
else if (GET_CODE (body)((enum rtx_code) (body)->code) == PARALLEL)
  {
    int i;
    int count = 0;
    rtx value = NULL_RTX(rtx) 0;

    /* Registers mentioned in the clobber list for an asm cannot be reused
within the body of the asm.  Invalidate those registers now so that
we don't try to substitute values for them.  */
    if (asm_noperands (body) >= 0)
{
 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; --i)
   {
     rtx part = XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i]);
     if (GET_CODE (part)((enum rtx_code) (part)->code) == CLOBBER && REG_P (XEXP (part, 0))(((enum rtx_code) ((((part)->u.fld[0]).rt_rtx))->code) ==
 REG))
cselib_invalidate_rtx (XEXP (part, 0)(((part)->u.fld[0]).rt_rtx));
   }
}

    /* If every action in a PARALLEL is a noop, we can delete
the entire PARALLEL.  */
    for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; --i)
{
 rtx part = XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i]);
 if (GET_CODE (part)((enum rtx_code) (part)->code) == SET)
   {
     if (! cselib_redundant_set_p (part))
break;
     if (REG_P (SET_DEST (part))(((enum rtx_code) ((((part)->u.fld[0]).rt_rtx))->code) ==
 REG)
  && REG_FUNCTION_VALUE_P (SET_DEST (part))(__extension__ ({ __typeof (((((part)->u.fld[0]).rt_rtx)))
 const _rtx = (((((part)->u.fld[0]).rt_rtx))); if (((enum rtx_code
) (_rtx)->code) != REG && ((enum rtx_code) (_rtx)->
code) != PARALLEL) rtl_check_failed_flag ("REG_FUNCTION_VALUE_P"
,_rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 152, __FUNCTION__); _rtx; })->return_val))
{
  if (value)
    break;
  value = SET_DEST (part)(((part)->u.fld[0]).rt_rtx);
}
   }
 else if (GET_CODE (part)((enum rtx_code) (part)->code) != CLOBBER && GET_CODE (part)((enum rtx_code) (part)->code) != USE)
   break;
}

    if (i < 0)
{
 if (check_for_inc_dec (insn))
   delete_insn_and_edges (insn);
 /* We're done with this insn.  */
 goto done;
}

    /* It's not a no-op, but we can try to simplify it.  */
    for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; --i)
if (GET_CODE (XVECEXP (body, 0, i))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[i]))->code) == SET)
 count += reload_cse_simplify_set (XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i]), insn);

    if (count > 0)
apply_change_group ();
    else
reload_cse_simplify_operands (insn, testreg);
  }

/* If sp += const_int insn is changed into sp = reg;, add REG_EQUAL
   note so that the stack_adjustments pass can undo it if beneficial.  */
if (sp_addend
    && SET_DEST (sp_set)(((sp_set)->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
    && REG_P (SET_SRC (sp_set))(((enum rtx_code) ((((sp_set)->u.fld[1]).rt_rtx))->code
) == REG))
  set_dst_reg_note (insn, REG_EQUAL,
      gen_rtx_PLUS (Pmode, stack_pointer_rtx,gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
)), ((sp_addend)) )
		    sp_addend)gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
)), ((sp_addend)) ), stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]));

191done:
return (EDGE_COUNT (insn_bb->succs)vec_safe_length (insn_bb->succs) != insn_bb_succs);
193}

195/* Do a very simple CSE pass over the hard registers.

 This function detects no-op moves where we happened to assign two
 different pseudo-registers to the same hard register, and then
 copied one to the other.  Reload will generate a useless
 instruction copying a register to itself.

 This function also detects cases where we load a value from memory
 into two different registers, and (if memory is more expensive than
 registers) changes it to simply copy the first register into the
 second register.

 Another optimization is performed that scans the operands of each
 instruction to see whether the value is already available in a
 hard register.  It then replaces the operand with the hard register
 if possible, much like an optional reload would.  */

212static void
213reload_cse_regs_1 (void)
214{
bool cfg_changed = false;
basic_block bb;
rtx_insn *insn;
rtx testreg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER(((76)) + 5) + 1);

cselib_init (CSELIB_RECORD_MEMORY);
init_alias_analysis ();

FOR_EACH_BB_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_entry_block_ptr->next_bb
; bb != ((cfun + 0))->cfg->x_exit_block_ptr; bb = bb->
next_bb)
  FOR_BB_INSNS (bb, insn)for ((insn) = (bb)->il.x.head_; (insn) && (insn) !=
 NEXT_INSN ((bb)->il.x.rtl->end_); (insn) = NEXT_INSN (
insn))
    {
if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
 cfg_changed |= reload_cse_simplify (insn, testreg);

cselib_process_insn (insn);
    }

/* Clean up.  */
end_alias_analysis ();
cselib_finish ();
if (cfg_changed)
  cleanup_cfg (0);
237}

239/* Try to simplify a single SET instruction.  SET is the set pattern.
 INSN is the instruction it came from.
 This function only handles one case: if we set a register to a value
 which is not a register, we try to find that value in some other register
 and change the set into a register copy.  */

245static int
246reload_cse_simplify_set (rtx set, rtx_insn *insn)
247{
int did_change = 0;
int dreg;
rtx src;
reg_class_t dclass;
int old_cost;
cselib_val *val;
struct elt_loc_list *l;
enum rtx_code extend_op = UNKNOWN;
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));

dreg = true_regnum (SET_DEST (set)(((set)->u.fld[0]).rt_rtx));
if (dreg < 0)
  return 0;

src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
if (side_effects_p (src) || true_regnum (src) >= 0)
  return 0;

dclass = REGNO_REG_CLASS (dreg)(regclass_map[(dreg)]);

/* When replacing a memory with a register, we need to honor assumptions
   that combine made wrt the contents of sign bits.  We'll do this by
   generating an extend instruction instead of a reg->reg copy.  Thus
   the destination must be a register that we can widen.  */
if (MEM_P (src)(((enum rtx_code) (src)->code) == MEM)
    && (extend_op = load_extend_op (GET_MODE (src)((machine_mode) (src)->mode))) != UNKNOWN
    && !REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 REG))
  return 0;

val = cselib_lookup (src, GET_MODE (SET_DEST (set))((machine_mode) ((((set)->u.fld[0]).rt_rtx))->mode), 0, VOIDmode((void) 0, E_VOIDmode));
if (! val)
  return 0;

/* If memory loads are cheaper than register copies, don't change them.  */
if (MEM_P (src)(((enum rtx_code) (src)->code) == MEM))
  old_cost = memory_move_cost (GET_MODE (src)((machine_mode) (src)->mode), dclass, true);
else if (REG_P (src)(((enum rtx_code) (src)->code) == REG))
  old_cost = register_move_cost (GET_MODE (src)((machine_mode) (src)->mode),
		   REGNO_REG_CLASS (REGNO (src))(regclass_map[((rhs_regno(src)))]), dclass);
else
  old_cost = set_src_cost (src, GET_MODE (SET_DEST (set))((machine_mode) ((((set)->u.fld[0]).rt_rtx))->mode), speed);

for (l = val->locs; l; l = l->next)
  {
    rtx this_rtx = l->loc;
    int this_cost;

    if (CONSTANT_P (this_rtx)((rtx_class[(int) (((enum rtx_code) (this_rtx)->code))]) ==
 RTX_CONST_OBJ) && ! references_value_p (this_rtx, 0))
{
 if (extend_op != UNKNOWN)
   {
     wide_int result;

     if (!CONST_SCALAR_INT_P (this_rtx)((((enum rtx_code) (this_rtx)->code) == CONST_INT) || (((enum
 rtx_code) (this_rtx)->code) == CONST_WIDE_INT)))
continue;

     switch (extend_op)
{
case ZERO_EXTEND:
  result = wide_int::from (rtx_mode_t (this_rtx,
				       GET_MODE (src)((machine_mode) (src)->mode)),
			   BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
 1)) != 0) ? 8 : 4)), UNSIGNED);
  break;
case SIGN_EXTEND:
  result = wide_int::from (rtx_mode_t (this_rtx,
				       GET_MODE (src)((machine_mode) (src)->mode)),
			   BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
 1)) != 0) ? 8 : 4)), SIGNED);
  break;
default:
  gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 317, __FUNCTION__));
}
     this_rtx = immed_wide_int_const (result, word_mode);
   }

 this_cost = set_src_cost (this_rtx, GET_MODE (SET_DEST (set))((machine_mode) ((((set)->u.fld[0]).rt_rtx))->mode), speed);
}
    else if (REG_P (this_rtx)(((enum rtx_code) (this_rtx)->code) == REG))
{
 if (extend_op != UNKNOWN)
   {
     this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx)gen_rtx_fmt_e_stat ((extend_op), (word_mode), (this_rtx) );
     this_cost = set_src_cost (this_rtx, word_mode, speed);
   }
 else
   this_cost = register_move_cost (GET_MODE (this_rtx)((machine_mode) (this_rtx)->mode),
			    REGNO_REG_CLASS (REGNO (this_rtx))(regclass_map[((rhs_regno(this_rtx)))]),
			    dclass);
}
    else
continue;

    /* If equal costs, prefer registers over anything else.  That
tends to lead to smaller instructions on some machines.  */
    if (this_cost < old_cost
 || (this_cost == old_cost
     && REG_P (this_rtx)(((enum rtx_code) (this_rtx)->code) == REG)
     && !REG_P (SET_SRC (set))(((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) ==
 REG)))
{
 if (extend_op != UNKNOWN
     && REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)),(targetm.can_change_mode_class (((machine_mode) ((((set)->
u.fld[0]).rt_rtx))->mode), word_mode, (regclass_map[((rhs_regno
((((set)->u.fld[0]).rt_rtx))))])))
			GET_MODE (SET_DEST (set)), word_mode)(targetm.can_change_mode_class (((machine_mode) ((((set)->
u.fld[0]).rt_rtx))->mode), word_mode, (regclass_map[((rhs_regno
((((set)->u.fld[0]).rt_rtx))))]))))
   {
     rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx))));
     ORIGINAL_REGNO (wide_dest)(__extension__ ({ __typeof ((wide_dest)) const _rtx = ((wide_dest
)); if (((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
 ("ORIGINAL_REGNO", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 351, __FUNCTION__); _rtx; })->u2.original_regno) = ORIGINAL_REGNO (SET_DEST (set))(__extension__ ({ __typeof (((((set)->u.fld[0]).rt_rtx))) const
 _rtx = (((((set)->u.fld[0]).rt_rtx))); if (((enum rtx_code
) (_rtx)->code) != REG) rtl_check_failed_flag ("ORIGINAL_REGNO"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 351, __FUNCTION__); _rtx; })->u2.original_regno);
     validate_change (insn, &SET_DEST (set)(((set)->u.fld[0]).rt_rtx), wide_dest, 1);
   }

 validate_unshare_change (insn, &SET_SRC (set)(((set)->u.fld[1]).rt_rtx), this_rtx, 1);
 old_cost = this_cost, did_change = 1;
}
  }

return did_change;
361}

363/* Try to replace operands in INSN with equivalent values that are already
 in registers.  This can be viewed as optional reloading.

 For each non-register operand in the insn, see if any hard regs are
 known to be equivalent to that operand.  Record the alternatives which
 can accept these hard registers.  Among all alternatives, select the
 ones which are better or equal to the one currently matching, where
 "better" is in terms of '?' and '!' constraints.  Among the remaining
 alternatives, select the one which replaces most operands with
 hard registers.  */

374static int
375reload_cse_simplify_operands (rtx_insn *insn, rtx testreg)
376{
int i, j;

/* For each operand, all registers that are equivalent to it.  */
HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS30];

const char *constraints[MAX_RECOG_OPERANDS30];

/* Vector recording how bad an alternative is.  */
int *alternative_reject;
/* Vector recording how many registers can be introduced by choosing
   this alternative.  */
int *alternative_nregs;
/* Array of vectors recording, for each operand and each alternative,
   which hard register to substitute, or -1 if the operand should be
   left as it is.  */
int *op_alt_regno[MAX_RECOG_OPERANDS30];
/* Array of alternatives, sorted in order of decreasing desirability.  */
int *alternative_order;

extract_constrain_insn (insn);

if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
1
Assuming field 'n_alternatives' is not equal to 0→
2
←
Assuming field 'n_operands' is not equal to 0→
3
←
Taking false branch→
  return 0;

alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives)((int *) __builtin_alloca(sizeof (int) * (recog_data.n_alternatives
)));
alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives)((int *) __builtin_alloca(sizeof (int) * (recog_data.n_alternatives
)));
alternative_order = XALLOCAVEC (int, recog_data.n_alternatives)((int *) __builtin_alloca(sizeof (int) * (recog_data.n_alternatives
)));
memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));

/* For each operand, find out which regs are equivalent.  */
for (i = 0; i < recog_data.n_operands; i++)
4
←
Assuming 'i' is >= field 'n_operands'→
5
←
Loop condition is false. Execution continues on line 486→
  {
    cselib_val *v;
    struct elt_loc_list *l;
    rtx op;

    CLEAR_HARD_REG_SET (equiv_regs[i]);

    /* cselib blows up on CODE_LABELs.  Trying to fix that doesn't seem
right, so avoid the problem here.  Similarly NOTE_INSN_DELETED_LABEL.
Likewise if we have a constant and the insn pattern doesn't tell us
the mode we need.  */
    if (LABEL_P (recog_data.operand[i])(((enum rtx_code) (recog_data.operand[i])->code) == CODE_LABEL
)
 || (NOTE_P (recog_data.operand[i])(((enum rtx_code) (recog_data.operand[i])->code) == NOTE)
     && NOTE_KIND (recog_data.operand[i])(((recog_data.operand[i])->u.fld[4]).rt_int) == NOTE_INSN_DELETED_LABEL)
 || (CONSTANT_P (recog_data.operand[i])((rtx_class[(int) (((enum rtx_code) (recog_data.operand[i])->
code))]) == RTX_CONST_OBJ)
     && recog_data.operand_mode[i] == VOIDmode((void) 0, E_VOIDmode)))
continue;

    op = recog_data.operand[i];
    if (MEM_P (op)(((enum rtx_code) (op)->code) == MEM) && load_extend_op (GET_MODE (op)((machine_mode) (op)->mode)) != UNKNOWN)
{
 rtx set = single_set (insn);

 /* We might have multiple sets, some of which do implicit
    extension.  Punt on this for now.  */
 if (! set)
   continue;
 /* If the destination is also a MEM or a STRICT_LOW_PART, no
    extension applies.
    Also, if there is an explicit extension, we don't have to
    worry about an implicit one.  */
 else if (MEM_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 MEM)
   || GET_CODE (SET_DEST (set))((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) == STRICT_LOW_PART
   || GET_CODE (SET_SRC (set))((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) == ZERO_EXTEND
   || GET_CODE (SET_SRC (set))((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) == SIGN_EXTEND)
   ; /* Continue ordinary processing.  */
 /* If the register cannot change mode to word_mode, it follows that
    it cannot have been used in word_mode.  */
 else if (REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 REG)
   && !REG_CAN_CHANGE_MODE_P (REGNO (SET_DEST (set)),(targetm.can_change_mode_class (((machine_mode) ((((set)->
u.fld[0]).rt_rtx))->mode), word_mode, (regclass_map[((rhs_regno
((((set)->u.fld[0]).rt_rtx))))])))
			      GET_MODE (SET_DEST (set)),(targetm.can_change_mode_class (((machine_mode) ((((set)->
u.fld[0]).rt_rtx))->mode), word_mode, (regclass_map[((rhs_regno
((((set)->u.fld[0]).rt_rtx))))])))
			      word_mode)(targetm.can_change_mode_class (((machine_mode) ((((set)->
u.fld[0]).rt_rtx))->mode), word_mode, (regclass_map[((rhs_regno
((((set)->u.fld[0]).rt_rtx))))]))))
   ; /* Continue ordinary processing.  */
 /* If this is a straight load, make the extension explicit.  */
 else if (REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 REG)
   && recog_data.n_operands == 2
   && SET_SRC (set)(((set)->u.fld[1]).rt_rtx) == op
   && SET_DEST (set)(((set)->u.fld[0]).rt_rtx) == recog_data.operand[1-i])
   {
     validate_change (insn, recog_data.operand_loc[i],
	       gen_rtx_fmt_e (load_extend_op (GET_MODE (op)),gen_rtx_fmt_e_stat ((load_extend_op (((machine_mode) (op)->
mode))), (word_mode), (op) )
			      word_mode, op)gen_rtx_fmt_e_stat ((load_extend_op (((machine_mode) (op)->
mode))), (word_mode), (op) ),
	       1);
     validate_change (insn, recog_data.operand_loc[1-i],
	       gen_rtx_REG (word_mode, REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx)))),
	       1);
     if (! apply_change_group ())
return 0;
     return reload_cse_simplify_operands (insn, testreg);
   }
 else
   /* ??? There might be arithmetic operations with memory that are
      safe to optimize, but is it worth the trouble?  */
   continue;
}

    if (side_effects_p (op))
continue;
    v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode((void) 0, E_VOIDmode));
    if (! v)
continue;

    for (l = v->locs; l; l = l->next)
if (REG_P (l->loc)(((enum rtx_code) (l->loc)->code) == REG))
 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)(rhs_regno(l->loc)));
  }

alternative_mask preferred = get_preferred_alternatives (insn);
for (i = 0; i < recog_data.n_operands; i++)
6
←
Assuming 'i' is < field 'n_operands'→
7
←
Loop condition is true.  Entering loop body→
  {
    machine_mode mode;
    int regno;
    const char *p;

    op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives)((int *) __builtin_alloca(sizeof (int) * (recog_data.n_alternatives
)));
    for (j = 0; j < recog_data.n_alternatives; j++)
8
←
Assuming 'j' is >= field 'n_alternatives'→
9
←
Loop condition is false. Execution continues on line 497→
op_alt_regno[i][j] = -1;

    p = constraints[i] = recog_data.constraints[i];
    mode = recog_data.operand_mode[i];

    /* Add the reject values for each alternative given by the constraints
for this operand.  */
    j = 0;
    while (*p != '\0')
10
←
Assuming the condition is false→
11
←
Loop condition is false. Execution continues on line 516→
{
 char c = *p++;
 if (c == ',')
   j++;
 else if (c == '?')
   alternative_reject[j] += 3;
 else if (c == '!')
   alternative_reject[j] += 300;
}

    /* We won't change operands which are already registers.  We
also don't want to modify output operands.  */
    regno = true_regnum (recog_data.operand[i]);
    if (regno >= 0
12
←
Assuming 'regno' is < 0→
13
←
Taking false branch→
 || constraints[i][0] == '='
 || constraints[i][0] == '+')
continue;

    for (regno = 0; regno < FIRST_PSEUDO_REGISTER76; regno++)
14
←
Loop condition is true.  Entering loop body→
{
 enum reg_class rclass = NO_REGS;

 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
15
←
Assuming the condition is false→
16
←
Taking false branch→
   continue;

 set_mode_and_regno (testreg, mode, regno);

 /* We found a register equal to this operand.  Now look for all
    alternatives that can accept this register and have not been
    assigned a register they can use yet.  */
 j = 0;
17
←
The value 0 is assigned to 'j'→
 p = constraints[i];
 for (;;)
18
←
Loop condition is true.  Entering loop body→
   {
     char c = *p;

     switch (c)
19
←
Control jumps to 'case 0:'  at line 553→
{
case 'g':
  rclass = reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[rclass][GENERAL_REGS];
  break;

default:
  rclass
    = (reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)
       [rclass]
       [reg_class_for_constraint (lookup_constraint (p))]);
  break;

case ',': case '\0':
  /* See if REGNO fits this alternative, and set it up as the
     replacement register if we don't have one for this
     alternative yet and the operand being replaced is not
     a cheap CONST_INT.  */
  if (op_alt_regno[i][j] == -1
20
←
The left operand of '==' is a garbage value
      && TEST_BIT (preferred, j)(((preferred) >> (j)) & 1)
      && reg_fits_class_p (testreg, rclass, 0, mode)
      && (!CONST_INT_P (recog_data.operand[i])(((enum rtx_code) (recog_data.operand[i])->code) == CONST_INT
)
	  || (set_src_cost (recog_data.operand[i], mode,
			    optimize_bb_for_speed_p
			     (BLOCK_FOR_INSN (insn)))
	      > set_src_cost (testreg, mode,
			      optimize_bb_for_speed_p
			       (BLOCK_FOR_INSN (insn))))))
    {
      alternative_nregs[j]++;
      op_alt_regno[i][j] = regno;
    }
  j++;
  rclass = NO_REGS;
  break;
}
     p += CONSTRAINT_LEN (c, p)insn_constraint_len (c,p);

     if (c == '\0')
break;
   }
}
  }

/* The loop below sets alternative_order[0] but -Wmaybe-uninitialized
   can't know that.  Clear it here to avoid the warning.  */
alternative_order[0] = 0;
gcc_assert (!recog_data.n_alternatives((void)(!(!recog_data.n_alternatives || (which_alternative >=
&& which_alternative < recog_data.n_alternatives
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 589, __FUNCTION__), 0 : 0))
     || (which_alternative >= 0((void)(!(!recog_data.n_alternatives || (which_alternative >=
&& which_alternative < recog_data.n_alternatives
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 589, __FUNCTION__), 0 : 0))
  && which_alternative < recog_data.n_alternatives))((void)(!(!recog_data.n_alternatives || (which_alternative >=
&& which_alternative < recog_data.n_alternatives
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 589, __FUNCTION__), 0 : 0));

/* Record all alternatives which are better or equal to the currently
   matching one in the alternative_order array.  */
for (i = j = 0; i < recog_data.n_alternatives; i++)
  if (alternative_reject[i] <= alternative_reject[which_alternative])
    alternative_order[j++] = i;
recog_data.n_alternatives = j;

/* Sort it.  Given a small number of alternatives, a dumb algorithm
   won't hurt too much.  */
for (i = 0; i < recog_data.n_alternatives - 1; i++)
  {
    int best = i;
    int best_reject = alternative_reject[alternative_order[i]];
    int best_nregs = alternative_nregs[alternative_order[i]];

    for (j = i + 1; j < recog_data.n_alternatives; j++)
{
 int this_reject = alternative_reject[alternative_order[j]];
 int this_nregs = alternative_nregs[alternative_order[j]];

 if (this_reject < best_reject
     || (this_reject == best_reject && this_nregs > best_nregs))
   {
     best = j;
     best_reject = this_reject;
     best_nregs = this_nregs;
   }
}

    std::swap (alternative_order[best], alternative_order[i]);
  }

/* Substitute the operands as determined by op_alt_regno for the best
   alternative.  */
j = alternative_order[0];

for (i = 0; i < recog_data.n_operands; i++)
  {
    machine_mode mode = recog_data.operand_mode[i];
    if (op_alt_regno[i][j] == -1)
continue;

    validate_change (insn, recog_data.operand_loc[i],
       gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
  }

for (i = recog_data.n_dups - 1; i >= 0; i--)
  {
    int op = recog_data.dup_num[i];
    machine_mode mode = recog_data.operand_mode[op];

    if (op_alt_regno[op][j] == -1)
continue;

    validate_change (insn, recog_data.dup_loc[i],
       gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
  }

return apply_change_group ();
650}
651
652/* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
 addressing now.
 This code might also be useful when reload gave up on reg+reg addressing
 because of clashes between the return register and INDEX_REG_CLASS.  */

657/* The maximum number of uses of a register we can keep track of to
 replace them with reg+reg addressing.  */
659#define RELOAD_COMBINE_MAX_USES16 16

661/* Describes a recorded use of a register.  */
662struct reg_use
663{
/* The insn where a register has been used.  */
rtx_insn *insn;
/* Points to the memory reference enclosing the use, if any, NULL_RTX
   otherwise.  */
rtx containing_mem;
/* Location of the register within INSN.  */
rtx *usep;
/* The reverse uid of the insn.  */
int ruid;
673};

675/* If the register is used in some unknown fashion, USE_INDEX is negative.
 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
 indicates where it is first set or clobbered.
 Otherwise, USE_INDEX is the index of the last encountered use of the
 register (which is first among these we have seen since we scan backwards).
 USE_RUID indicates the first encountered, i.e. last, of these uses.
 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
 with a constant offset; OFFSET contains this constant in that case.
 STORE_RUID is always meaningful if we only want to use a value in a
 register in a different place: it denotes the next insn in the insn
 stream (i.e. the last encountered) that sets or clobbers the register.
 REAL_STORE_RUID is similar, but clobbers are ignored when updating it.
 EXPR is the expression used when storing the register.  */
688static struct
{
  struct reg_use reg_use[RELOAD_COMBINE_MAX_USES16];
  rtx offset;
  int use_index;
  int store_ruid;
  int real_store_ruid;
  int use_ruid;
  bool all_offsets_match;
  rtx expr;
} reg_state[FIRST_PSEUDO_REGISTER76];

700/* Reverse linear uid.  This is increased in reload_combine while scanning
 the instructions from last to first.  It is used to set last_label_ruid
 and the store_ruid / use_ruid fields in reg_state.  */
703static int reload_combine_ruid;

705/* The RUID of the last label we encountered in reload_combine.  */
706static int last_label_ruid;

708/* The RUID of the last jump we encountered in reload_combine.  */
709static int last_jump_ruid;

711/* The register numbers of the first and last index register.  A value of
 -1 in LAST_INDEX_REG indicates that we've previously computed these
 values and found no suitable index registers.  */
714static int first_index_reg = -1;
715static int last_index_reg;

717#define LABEL_LIVE(LABEL)(label_live[(((LABEL)->u.fld[5]).rt_int) - min_labelno]) \
(label_live[CODE_LABEL_NUMBER (LABEL)(((LABEL)->u.fld[5]).rt_int) - min_labelno])

720/* Subroutine of reload_combine_split_ruids, called to fix up a single
 ruid pointed to by *PRUID if it is higher than SPLIT_RUID.  */

723static inline void
724reload_combine_split_one_ruid (int *pruid, int split_ruid)
725{
if (*pruid > split_ruid)
  (*pruid)++;
728}

730/* Called when we insert a new insn in a position we've already passed in
 the scan.  Examine all our state, increasing all ruids that are higher
 than SPLIT_RUID by one in order to make room for a new insn.  */

734static void
735reload_combine_split_ruids (int split_ruid)
736{
unsigned i;

reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid);
reload_combine_split_one_ruid (&last_label_ruid, split_ruid);
reload_combine_split_one_ruid (&last_jump_ruid, split_ruid);

for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
  {
    int j, idx = reg_state[i].use_index;
    reload_combine_split_one_ruid (&reg_state[i].use_ruid, split_ruid);
    reload_combine_split_one_ruid (&reg_state[i].store_ruid, split_ruid);
    reload_combine_split_one_ruid (&reg_state[i].real_store_ruid,
		     split_ruid);
    if (idx < 0)
continue;
    for (j = idx; j < RELOAD_COMBINE_MAX_USES16; j++)
{
 reload_combine_split_one_ruid (&reg_state[i].reg_use[j].ruid,
			 split_ruid);
}
  }
758}

760/* Called when we are about to rescan a previously encountered insn with
 reload_combine_note_use after modifying some part of it.  This clears all
 information about uses in that particular insn.  */

764static void
765reload_combine_purge_insn_uses (rtx_insn *insn)
766{
unsigned i;

for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
  {
    int j, k, idx = reg_state[i].use_index;
    if (idx < 0)
continue;
    j = k = RELOAD_COMBINE_MAX_USES16;
    while (j-- > idx)
{
 if (reg_state[i].reg_use[j].insn != insn)
   {
     k--;
     if (k != j)
reg_state[i].reg_use[k] = reg_state[i].reg_use[j];
   }
}
    reg_state[i].use_index = k;
  }
786}

788/* Called when we need to forget about all uses of REGNO after an insn
 which is identified by RUID.  */

791static void
792reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid)
793{
int j, k, idx = reg_state[regno].use_index;
if (idx < 0)
  return;
j = k = RELOAD_COMBINE_MAX_USES16;
while (j-- > idx)
  {
    if (reg_state[regno].reg_use[j].ruid >= ruid)
{
 k--;
 if (k != j)
   reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j];
}
  }
reg_state[regno].use_index = k;
808}

810/* Find the use of REGNO with the ruid that is highest among those
 lower than RUID_LIMIT, and return it if it is the only use of this
 reg in the insn.  Return NULL otherwise.  */

814static struct reg_use *
815reload_combine_closest_single_use (unsigned regno, int ruid_limit)
816{
int i, best_ruid = 0;
int use_idx = reg_state[regno].use_index;
struct reg_use *retval;

if (use_idx < 0)
  return NULLnullptr;
retval = NULLnullptr;
for (i = use_idx; i < RELOAD_COMBINE_MAX_USES16; i++)
  {
    struct reg_use *use = reg_state[regno].reg_use + i; 
    int this_ruid = use->ruid;
    if (this_ruid >= ruid_limit)
continue;
    if (this_ruid > best_ruid)
{
 best_ruid = this_ruid;
 retval = use;
}
    else if (this_ruid == best_ruid)
retval = NULLnullptr;
  }
if (last_label_ruid >= best_ruid)
  return NULLnullptr;
return retval;
841}

843/* After we've moved an add insn, fix up any debug insns that occur
 between the old location of the add and the new location.  REG is
 the destination register of the add insn; REPLACEMENT is the
 SET_SRC of the add.  FROM and TO specify the range in which we
 should make this change on debug insns.  */

849static void
850fixup_debug_insns (rtx reg, rtx replacement, rtx_insn *from, rtx_insn *to)
851{
rtx_insn *insn;
for (insn = from; insn != to; insn = NEXT_INSN (insn))
  {
    rtx t;

    if (!DEBUG_BIND_INSN_P (insn)((((enum rtx_code) (insn)->code) == DEBUG_INSN) &&
 (((enum rtx_code) (PATTERN (insn))->code) == VAR_LOCATION
)))
continue;
    
    t = INSN_VAR_LOCATION_LOC (insn)((((((__extension__ ({ __typeof (PATTERN (insn)) const _rtx =
 (PATTERN (insn)); if (((enum rtx_code) (_rtx)->code) != VAR_LOCATION
) rtl_check_failed_flag ("INSN_VAR_LOCATION", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 860, __FUNCTION__); _rtx; }))))->u.fld[1]).rt_rtx));
    t = simplify_replace_rtx (t, reg, replacement);
    validate_change (insn, &INSN_VAR_LOCATION_LOC (insn)((((((__extension__ ({ __typeof (PATTERN (insn)) const _rtx =
 (PATTERN (insn)); if (((enum rtx_code) (_rtx)->code) != VAR_LOCATION
) rtl_check_failed_flag ("INSN_VAR_LOCATION", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 862, __FUNCTION__); _rtx; }))))->u.fld[1]).rt_rtx)), t, 0);
  }
864}

866/* Subroutine of reload_combine_recognize_const_pattern.  Try to replace REG
 with SRC in the insn described by USE, taking costs into account.  Return
 true if we made the replacement.  */

870static bool
871try_replace_in_use (struct reg_use *use, rtx reg, rtx src)
872{
rtx_insn *use_insn = use->insn;
rtx mem = use->containing_mem;
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn));

if (mem != NULL_RTX(rtx) 0)
  {
    addr_space_t as = MEM_ADDR_SPACE (mem)(get_mem_attrs (mem)->addrspace);
    rtx oldaddr = XEXP (mem, 0)(((mem)->u.fld[0]).rt_rtx);
    rtx newaddr = NULL_RTX(rtx) 0;
    int old_cost = address_cost (oldaddr, GET_MODE (mem)((machine_mode) (mem)->mode), as, speed);
    int new_cost;

    newaddr = simplify_replace_rtx (oldaddr, reg, src);
    if (memory_address_addr_space_p (GET_MODE (mem)((machine_mode) (mem)->mode), newaddr, as))
{
 XEXP (mem, 0)(((mem)->u.fld[0]).rt_rtx) = newaddr;
 new_cost = address_cost (newaddr, GET_MODE (mem)((machine_mode) (mem)->mode), as, speed);
 XEXP (mem, 0)(((mem)->u.fld[0]).rt_rtx) = oldaddr;
 if (new_cost <= old_cost
     && validate_change (use_insn,
		  &XEXP (mem, 0)(((mem)->u.fld[0]).rt_rtx), newaddr, 0))
   return true;
}
  }
else
  {
    rtx new_set = single_set (use_insn);
    if (new_set
 && REG_P (SET_DEST (new_set))(((enum rtx_code) ((((new_set)->u.fld[0]).rt_rtx))->code
) == REG)
 && GET_CODE (SET_SRC (new_set))((enum rtx_code) ((((new_set)->u.fld[1]).rt_rtx))->code
) == PLUS
 && REG_P (XEXP (SET_SRC (new_set), 0))(((enum rtx_code) (((((((new_set)->u.fld[1]).rt_rtx))->
u.fld[0]).rt_rtx))->code) == REG)
 && CONSTANT_P (XEXP (SET_SRC (new_set), 1))((rtx_class[(int) (((enum rtx_code) (((((((new_set)->u.fld
[1]).rt_rtx))->u.fld[1]).rt_rtx))->code))]) == RTX_CONST_OBJ
))
{
 rtx new_src;
 machine_mode mode = GET_MODE (SET_DEST (new_set))((machine_mode) ((((new_set)->u.fld[0]).rt_rtx))->mode);
 int old_cost = set_src_cost (SET_SRC (new_set)(((new_set)->u.fld[1]).rt_rtx), mode, speed);

 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg))((void)(!(rtx_equal_p (((((((new_set)->u.fld[1]).rt_rtx))->
u.fld[0]).rt_rtx), reg)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 910, __FUNCTION__), 0 : 0));
 new_src = simplify_replace_rtx (SET_SRC (new_set)(((new_set)->u.fld[1]).rt_rtx), reg, src);

 if (set_src_cost (new_src, mode, speed) <= old_cost
     && validate_change (use_insn, &SET_SRC (new_set)(((new_set)->u.fld[1]).rt_rtx),
		  new_src, 0))
   return true;
}
  }
return false;
920}

922/* Called by reload_combine when scanning INSN.  This function tries to detect
 patterns where a constant is added to a register, and the result is used
 in an address.
 Return true if no further processing is needed on INSN; false if it wasn't
 recognized and should be handled normally.  */

928static bool
929reload_combine_recognize_const_pattern (rtx_insn *insn)
930{
int from_ruid = reload_combine_ruid;
rtx set, pat, reg, src, addreg;
unsigned int regno;
struct reg_use *use;
bool must_move_add;
rtx_insn *add_moved_after_insn = NULLnullptr;
int add_moved_after_ruid = 0;
int clobbered_regno = -1;

set = single_set (insn);
if (set == NULL_RTX(rtx) 0)
  return false;

reg = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);
src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
if (!REG_P (reg)(((enum rtx_code) (reg)->code) == REG)
    || REG_NREGS (reg)((&(reg)->u.reg)->nregs) != 1
    || GET_MODE (reg)((machine_mode) (reg)->mode) != Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
    || reg == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
  return false;

regno = REGNO (reg)(rhs_regno(reg));

/* We look for a REG1 = REG2 + CONSTANT insn, followed by either
   uses of REG1 inside an address, or inside another add insn.  If
   possible and profitable, merge the addition into subsequent
   uses.  */
if (GET_CODE (src)((enum rtx_code) (src)->code) != PLUS
    || !REG_P (XEXP (src, 0))(((enum rtx_code) ((((src)->u.fld[0]).rt_rtx))->code) ==
 REG)
    || !CONSTANT_P (XEXP (src, 1))((rtx_class[(int) (((enum rtx_code) ((((src)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
  return false;

addreg = XEXP (src, 0)(((src)->u.fld[0]).rt_rtx);
must_move_add = rtx_equal_p (reg, addreg);

pat = PATTERN (insn);
if (must_move_add && set != pat)
  {
    /* We have to be careful when moving the add; apart from the
single_set there may also be clobbers.  Recognize one special
case, that of one clobber alongside the set (likely a clobber
of the CC register).  */
    gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL)((void)(!(((enum rtx_code) (PATTERN (insn))->code) == PARALLEL
) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 973, __FUNCTION__), 0 : 0));
    if (XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem) != 2 || XVECEXP (pat, 0, 0)(((((pat)->u.fld[0]).rt_rtvec))->elem[0]) != set
 || GET_CODE (XVECEXP (pat, 0, 1))((enum rtx_code) ((((((pat)->u.fld[0]).rt_rtvec))->elem
[1]))->code) != CLOBBER
 || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))(((enum rtx_code) (((((((((pat)->u.fld[0]).rt_rtvec))->
elem[1]))->u.fld[0]).rt_rtx))->code) == REG))
return false;
    clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0))(rhs_regno(((((((((pat)->u.fld[0]).rt_rtvec))->elem[1])
)->u.fld[0]).rt_rtx)));
  }

do
  {
    use = reload_combine_closest_single_use (regno, from_ruid);

    if (use)
/* Start the search for the next use from here.  */
from_ruid = use->ruid;

    if (use && GET_MODE (*use->usep)((machine_mode) (*use->usep)->mode) == Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))))
{
 bool delete_add = false;
 rtx_insn *use_insn = use->insn;
 int use_ruid = use->ruid;

 /* Avoid moving the add insn past a jump.  */
 if (must_move_add && use_ruid <= last_jump_ruid)
   break;

 /* If the add clobbers another hard reg in parallel, don't move
    it past a real set of this hard reg.  */
 if (must_move_add && clobbered_regno >= 0
     && reg_state[clobbered_regno].real_store_ruid >= use_ruid)
   break;

 gcc_assert (reg_state[regno].store_ruid <= use_ruid)((void)(!(reg_state[regno].store_ruid <= use_ruid) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 1005, __FUNCTION__), 0 : 0));
 /* Avoid moving a use of ADDREG past a point where it is stored.  */
 if (reg_state[REGNO (addreg)(rhs_regno(addreg))].store_ruid > use_ruid)
   break;

 /* We also must not move the addition past an insn that sets
    the same register, unless we can combine two add insns.  */
 if (must_move_add && reg_state[regno].store_ruid == use_ruid)
   {
     if (use->containing_mem == NULL_RTX(rtx) 0)
delete_add = true;
     else
break;
   }

 if (try_replace_in_use (use, reg, src))
   {
     reload_combine_purge_insn_uses (use_insn);
     reload_combine_note_use (&PATTERN (use_insn), use_insn,
		       use_ruid, NULL_RTX(rtx) 0);

     if (delete_add)
{
  fixup_debug_insns (reg, src, insn, use_insn);
  delete_insn (insn);
  return true;
}
     if (must_move_add)
{
  add_moved_after_insn = use_insn;
  add_moved_after_ruid = use_ruid;
}
     continue;
   }
}
    /* If we get here, we couldn't handle this use.  */
    if (must_move_add)
break;
  }
while (use);

if (!must_move_add || add_moved_after_insn == NULL_RTX(rtx) 0)
  /* Process the add normally.  */
  return false;

fixup_debug_insns (reg, src, insn, add_moved_after_insn);

reorder_insns (insn, insn, add_moved_after_insn);
reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid);
reload_combine_split_ruids (add_moved_after_ruid - 1);
reload_combine_note_use (&PATTERN (insn), insn,
	   add_moved_after_ruid, NULL_RTX(rtx) 0);
reg_state[regno].store_ruid = add_moved_after_ruid;

return true;
1060}

1062/* Called by reload_combine when scanning INSN.  Try to detect a pattern we
 can handle and improve.  Return true if no further processing is needed on
 INSN; false if it wasn't recognized and should be handled normally.  */

1066static bool
1067reload_combine_recognize_pattern (rtx_insn *insn)
1068{
rtx set, reg, src;

set = single_set (insn);
if (set == NULL_RTX(rtx) 0)
  return false;

reg = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);
src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
if (!REG_P (reg)(((enum rtx_code) (reg)->code) == REG) || REG_NREGS (reg)((&(reg)->u.reg)->nregs) != 1)
  return false;

unsigned int regno = REGNO (reg)(rhs_regno(reg));
machine_mode mode = GET_MODE (reg)((machine_mode) (reg)->mode);

if (reg_state[regno].use_index < 0
    || reg_state[regno].use_index >= RELOAD_COMBINE_MAX_USES16)
  return false;

for (int i = reg_state[regno].use_index;
     i < RELOAD_COMBINE_MAX_USES16; i++)
  {
    struct reg_use *use = reg_state[regno].reg_use + i;
    if (GET_MODE (*use->usep)((machine_mode) (*use->usep)->mode) != mode)
return false;
    /* Don't try to adjust (use (REGX)).  */
    if (GET_CODE (PATTERN (use->insn))((enum rtx_code) (PATTERN (use->insn))->code) == USE
 && &XEXP (PATTERN (use->insn), 0)(((PATTERN (use->insn))->u.fld[0]).rt_rtx) == use->usep)
return false;
  }

/* Look for (set (REGX) (CONST_INT))
   (set (REGX) (PLUS (REGX) (REGY)))
   ...
   ... (MEM (REGX)) ...
   and convert it to
   (set (REGZ) (CONST_INT))
   ...
   ... (MEM (PLUS (REGZ) (REGY)))... .

   First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
   and that we know all uses of REGX before it dies.
   Also, explicitly check that REGX != REGY; our life information
   does not yet show whether REGY changes in this insn.  */

if (GET_CODE (src)((enum rtx_code) (src)->code) == PLUS
    && reg_state[regno].all_offsets_match
    && last_index_reg != -1
    && REG_P (XEXP (src, 1))(((enum rtx_code) ((((src)->u.fld[1]).rt_rtx))->code) ==
 REG)
    && rtx_equal_p (XEXP (src, 0)(((src)->u.fld[0]).rt_rtx), reg)
    && !rtx_equal_p (XEXP (src, 1)(((src)->u.fld[1]).rt_rtx), reg)
    && last_label_ruid < reg_state[regno].use_ruid)
  {
    rtx base = XEXP (src, 1)(((src)->u.fld[1]).rt_rtx);
    rtx_insn *prev = prev_nonnote_nondebug_insn (insn);
    rtx prev_set = prev ? single_set (prev) : NULL_RTX(rtx) 0;
    rtx index_reg = NULL_RTX(rtx) 0;
    rtx reg_sum = NULL_RTX(rtx) 0;
    int i;

    /* Now we need to set INDEX_REG to an index register (denoted as
REGZ in the illustration above) and REG_SUM to the expression
register+register that we want to use to substitute uses of REG
(typically in MEMs) with.  First check REG and BASE for being
index registers; we can use them even if they are not dead.  */
    if (TEST_HARD_REG_BIT (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[INDEX_REG_CLASSINDEX_REGS], regno)
 || TEST_HARD_REG_BIT (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[INDEX_REG_CLASSINDEX_REGS],
		REGNO (base)(rhs_regno(base))))
{
 index_reg = reg;
 reg_sum = src;
}
    else
{
 /* Otherwise, look for a free index register.  Since we have
    checked above that neither REG nor BASE are index registers,
    if we find anything at all, it will be different from these
    two registers.  */
 for (i = first_index_reg; i <= last_index_reg; i++)
   {
     if (TEST_HARD_REG_BIT (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[INDEX_REG_CLASSINDEX_REGS], i)
  && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES16
  && reg_state[i].store_ruid <= reg_state[regno].use_ruid
  && (crtl(&x_rtl)->abi->clobbers_full_reg_p (i)
      || df_regs_ever_live_p (i))
  && (!frame_pointer_needed((&x_rtl)->frame_pointer_needed) || i != HARD_FRAME_POINTER_REGNUM6)
  && !fixed_regs(this_target_hard_regs->x_fixed_regs)[i] && !global_regs[i]
  && hard_regno_nregs (i, GET_MODE (reg)((machine_mode) (reg)->mode)) == 1
  && targetm.hard_regno_scratch_ok (i))
{
  index_reg = gen_rtx_REG (GET_MODE (reg)((machine_mode) (reg)->mode), i);
  reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base)gen_rtx_fmt_ee_stat ((PLUS), ((((machine_mode) (reg)->mode
))), ((index_reg)), ((base)) );
  break;
}
   }
}

    /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
(REGY), i.e. BASE, is not clobbered before the last use we'll
create.  */
    if (reg_sum
 && prev_set
 && CONST_INT_P (SET_SRC (prev_set))(((enum rtx_code) ((((prev_set)->u.fld[1]).rt_rtx))->code
) == CONST_INT)
 && rtx_equal_p (SET_DEST (prev_set)(((prev_set)->u.fld[0]).rt_rtx), reg)
 && (reg_state[REGNO (base)(rhs_regno(base))].store_ruid
     <= reg_state[regno].use_ruid))
{
 /* Change destination register and, if necessary, the constant
    value in PREV, the constant loading instruction.  */
 validate_change (prev, &SET_DEST (prev_set)(((prev_set)->u.fld[0]).rt_rtx), index_reg, 1);
 if (reg_state[regno].offset != const0_rtx(const_int_rtx[64]))
   {
     HOST_WIDE_INTlong c
= trunc_int_for_mode (UINTVAL (SET_SRC (prev_set))((unsigned long) (((((prev_set)->u.fld[1]).rt_rtx))->u.
hwint[0]))
		      + UINTVAL (reg_state[regno].offset)((unsigned long) ((reg_state[regno].offset)->u.hwint[0])),
		      GET_MODE (index_reg)((machine_mode) (index_reg)->mode));
     validate_change (prev, &SET_SRC (prev_set)(((prev_set)->u.fld[1]).rt_rtx), GEN_INT (c)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (c)), 1);
   }

 /* Now for every use of REG that we have recorded, replace REG
    with REG_SUM.  */
 for (i = reg_state[regno].use_index;
      i < RELOAD_COMBINE_MAX_USES16; i++)
   validate_unshare_change (reg_state[regno].reg_use[i].insn,
		     reg_state[regno].reg_use[i].usep,
		     /* Each change must have its own
			replacement.  */
		     reg_sum, 1);

 if (apply_change_group ())
   {
     struct reg_use *lowest_ruid = NULLnullptr;

     /* For every new use of REG_SUM, we have to record the use
 of BASE therein, i.e. operand 1.  */
     for (i = reg_state[regno].use_index;
   i < RELOAD_COMBINE_MAX_USES16; i++)
{
  struct reg_use *use = reg_state[regno].reg_use + i;
  reload_combine_note_use (&XEXP (*use->usep, 1)(((*use->usep)->u.fld[1]).rt_rtx), use->insn,
			   use->ruid, use->containing_mem);
  if (lowest_ruid == NULLnullptr || use->ruid < lowest_ruid->ruid)
    lowest_ruid = use;
}

     fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn);

     /* Delete the reg-reg addition.  */
     delete_insn (insn);

     if (reg_state[regno].offset != const0_rtx(const_int_rtx[64]))
/* Previous REG_EQUIV / REG_EQUAL notes for PREV
   are now invalid.  */
remove_reg_equal_equiv_notes (prev);

     reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES16;
     return true;
   }
}
  }
return false;
1229}

1231static void
1232reload_combine (void)
1233{
rtx_insn *insn, *prev;
basic_block bb;
unsigned int r;
int min_labelno, n_labels;
HARD_REG_SET ever_live_at_start, *label_live;

/* To avoid wasting too much time later searching for an index register,
   determine the minimum and maximum index register numbers.  */
if (INDEX_REG_CLASSINDEX_REGS == NO_REGS)
  last_index_reg = -1;
else if (first_index_reg == -1 && last_index_reg == 0)
  {
    for (r = 0; r < FIRST_PSEUDO_REGISTER76; r++)
if (TEST_HARD_REG_BIT (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[INDEX_REG_CLASSINDEX_REGS], r))
 {
   if (first_index_reg == -1)
     first_index_reg = r;

   last_index_reg = r;
 }

    /* If no index register is available, we can quit now.  Set LAST_INDEX_REG
to -1 so we'll know to quit early the next time we get here.  */
    if (first_index_reg == -1)
{
 last_index_reg = -1;
 return;
}
  }

/* Set up LABEL_LIVE and EVER_LIVE_AT_START.  The register lifetime
   information is a bit fuzzy immediately after reload, but it's
   still good enough to determine which registers are live at a jump
   destination.  */
min_labelno = get_first_label_num ();
n_labels = max_label_num () - min_labelno;
label_live = XNEWVEC (HARD_REG_SET, n_labels)((HARD_REG_SET *) xmalloc (sizeof (HARD_REG_SET) * (n_labels)
));
CLEAR_HARD_REG_SET (ever_live_at_start);

FOR_EACH_BB_REVERSE_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_exit_block_ptr->prev_bb
; bb != ((cfun + 0))->cfg->x_entry_block_ptr; bb = bb->
prev_bb)
  {
    insn = BB_HEAD (bb)(bb)->il.x.head_;
    if (LABEL_P (insn)(((enum rtx_code) (insn)->code) == CODE_LABEL))
{
 HARD_REG_SET live;
 bitmap live_in = df_get_live_in (bb);

 REG_SET_TO_HARD_REG_SET (live, live_in)do { CLEAR_HARD_REG_SET (live); reg_set_to_hard_reg_set (&
live, live_in); } while (0);
 compute_use_by_pseudos (&live, live_in);
 LABEL_LIVE (insn)(label_live[(((insn)->u.fld[5]).rt_int) - min_labelno]) = live;
 ever_live_at_start |= live;
}
  }

/* Initialize last_label_ruid, reload_combine_ruid and reg_state.  */
last_label_ruid = last_jump_ruid = reload_combine_ruid = 0;
for (r = 0; r < FIRST_PSEUDO_REGISTER76; r++)
  {
    reg_state[r].store_ruid = 0;
    reg_state[r].real_store_ruid = 0;
    if (fixed_regs(this_target_hard_regs->x_fixed_regs)[r])
reg_state[r].use_index = -1;
    else
reg_state[r].use_index = RELOAD_COMBINE_MAX_USES16;
  }

for (insn = get_last_insn (); insn; insn = prev)
  {
    bool control_flow_insn;
    rtx note;

    prev = PREV_INSN (insn);

    /* We cannot do our optimization across labels.  Invalidating all the use
information we have would be costly, so we just note where the label
is and then later disable any optimization that would cross it.  */
    if (LABEL_P (insn)(((enum rtx_code) (insn)->code) == CODE_LABEL))
last_label_ruid = reload_combine_ruid;
    else if (BARRIER_P (insn)(((enum rtx_code) (insn)->code) == BARRIER))
{
 /* Crossing a barrier resets all the use information.  */
 for (r = 0; r < FIRST_PSEUDO_REGISTER76; r++)
   if (! fixed_regs(this_target_hard_regs->x_fixed_regs)[r])
     reg_state[r].use_index = RELOAD_COMBINE_MAX_USES16;
}
    else if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)) && volatile_insn_p (PATTERN (insn)))
/* Optimizations across insns being marked as volatile must be
  prevented.  All the usage information is invalidated
  here.  */
for (r = 0; r < FIRST_PSEUDO_REGISTER76; r++)
 if (! fixed_regs(this_target_hard_regs->x_fixed_regs)[r]
     && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES16)
   reg_state[r].use_index = -1;

    if (! NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)))
continue;

    reload_combine_ruid++;

    control_flow_insn = control_flow_insn_p (insn);
    if (control_flow_insn)
last_jump_ruid = reload_combine_ruid;

    if (reload_combine_recognize_const_pattern (insn)
 || reload_combine_recognize_pattern (insn))
continue;

    note_stores (insn, reload_combine_note_store, NULLnullptr);

    if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
{
 rtx link;
 HARD_REG_SET used_regs = insn_callee_abi (insn).full_reg_clobbers ();

 for (r = 0; r < FIRST_PSEUDO_REGISTER76; r++)
   if (TEST_HARD_REG_BIT (used_regs, r))
     {
reg_state[r].use_index = RELOAD_COMBINE_MAX_USES16;
reg_state[r].store_ruid = reload_combine_ruid;
     }

 for (link = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx); link;
      link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
   {
     rtx setuse = XEXP (link, 0)(((link)->u.fld[0]).rt_rtx);
     rtx usage_rtx = XEXP (setuse, 0)(((setuse)->u.fld[0]).rt_rtx);

     if (GET_CODE (setuse)((enum rtx_code) (setuse)->code) == USE && REG_P (usage_rtx)(((enum rtx_code) (usage_rtx)->code) == REG))
       {
  unsigned int end_regno = END_REGNO (usage_rtx);
  for (unsigned int i = REGNO (usage_rtx)(rhs_regno(usage_rtx)); i < end_regno; ++i)
    reg_state[i].use_index = -1;
        }
    }
}

    if (control_flow_insn && !ANY_RETURN_P (PATTERN (insn))(((enum rtx_code) (PATTERN (insn))->code) == RETURN || ((enum
 rtx_code) (PATTERN (insn))->code) == SIMPLE_RETURN))
{
 /* Non-spill registers might be used at the call destination in
    some unknown fashion, so we have to mark the unknown use.  */
 HARD_REG_SET *live;

 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
     && JUMP_LABEL (insn)(((insn)->u.fld[7]).rt_rtx))
   {
     if (ANY_RETURN_P (JUMP_LABEL (insn))(((enum rtx_code) ((((insn)->u.fld[7]).rt_rtx))->code) ==
 RETURN || ((enum rtx_code) ((((insn)->u.fld[7]).rt_rtx))->
code) == SIMPLE_RETURN))
live = NULLnullptr;
     else
live = &LABEL_LIVE (JUMP_LABEL (insn))(label_live[((((((insn)->u.fld[7]).rt_rtx))->u.fld[5]).
rt_int) - min_labelno]);
   }
 else
   live = &ever_live_at_start;

 if (live)
   for (r = 0; r < FIRST_PSEUDO_REGISTER76; r++)
     if (TEST_HARD_REG_BIT (*live, r))
reg_state[r].use_index = -1;
}

    reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid,
	       NULL_RTX(rtx) 0);

    for (note = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); note; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
{
 if (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_INC && REG_P (XEXP (note, 0))(((enum rtx_code) ((((note)->u.fld[0]).rt_rtx))->code) ==
 REG))
   {
     int regno = REGNO (XEXP (note, 0))(rhs_regno((((note)->u.fld[0]).rt_rtx)));
     reg_state[regno].store_ruid = reload_combine_ruid;
     reg_state[regno].real_store_ruid = reload_combine_ruid;
     reg_state[regno].use_index = -1;
   }
}
  }

free (label_live);
1409}

1411/* Check if DST is a register or a subreg of a register; if it is,
 update store_ruid, real_store_ruid and use_index in the reg_state
 structure accordingly.  Called via note_stores from reload_combine.  */

1415static void
1416reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED__attribute__ ((__unused__)))
1417{
int regno = 0;
int i;
machine_mode mode = GET_MODE (dst)((machine_mode) (dst)->mode);

if (GET_CODE (dst)((enum rtx_code) (dst)->code) == SUBREG)
  {
    regno = subreg_regno_offset (REGNO (SUBREG_REG (dst))(rhs_regno((((dst)->u.fld[0]).rt_rtx))),
		   GET_MODE (SUBREG_REG (dst))((machine_mode) ((((dst)->u.fld[0]).rt_rtx))->mode),
		   SUBREG_BYTE (dst)(((dst)->u.fld[1]).rt_subreg),
		   GET_MODE (dst)((machine_mode) (dst)->mode));
    dst = SUBREG_REG (dst)(((dst)->u.fld[0]).rt_rtx);
  }

/* Some targets do argument pushes without adding REG_INC notes.  */

if (MEM_P (dst)(((enum rtx_code) (dst)->code) == MEM))
  {
    dst = XEXP (dst, 0)(((dst)->u.fld[0]).rt_rtx);
    if (GET_CODE (dst)((enum rtx_code) (dst)->code) == PRE_INC || GET_CODE (dst)((enum rtx_code) (dst)->code) == POST_INC
 || GET_CODE (dst)((enum rtx_code) (dst)->code) == PRE_DEC || GET_CODE (dst)((enum rtx_code) (dst)->code) == POST_DEC
 || GET_CODE (dst)((enum rtx_code) (dst)->code) == PRE_MODIFY || GET_CODE (dst)((enum rtx_code) (dst)->code) == POST_MODIFY)
{
 unsigned int end_regno = END_REGNO (XEXP (dst, 0)(((dst)->u.fld[0]).rt_rtx));
 for (unsigned int i = REGNO (XEXP (dst, 0))(rhs_regno((((dst)->u.fld[0]).rt_rtx))); i < end_regno; ++i)
   {
     /* We could probably do better, but for now mark the register
 as used in an unknown fashion and set/clobbered at this
 insn.  */
     reg_state[i].use_index = -1;
     reg_state[i].store_ruid = reload_combine_ruid;
     reg_state[i].real_store_ruid = reload_combine_ruid;
   }
}
    else
      return;
  }

if (!REG_P (dst)(((enum rtx_code) (dst)->code) == REG))
  return;
regno += REGNO (dst)(rhs_regno(dst));

/* note_stores might have stripped a STRICT_LOW_PART, so we have to be
   careful with registers / register parts that are not full words.
   Similarly for ZERO_EXTRACT.  */
if (GET_CODE (SET_DEST (set))((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) == ZERO_EXTRACT
    || GET_CODE (SET_DEST (set))((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) == STRICT_LOW_PART)
  {
    for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--)
{
 reg_state[i].use_index = -1;
 reg_state[i].store_ruid = reload_combine_ruid;
 reg_state[i].real_store_ruid = reload_combine_ruid;
}
  }
else
  {
    for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--)
{
 reg_state[i].store_ruid = reload_combine_ruid;
 if (GET_CODE (set)((enum rtx_code) (set)->code) == SET)
   reg_state[i].real_store_ruid = reload_combine_ruid;
 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES16;
}
  }
1482}

1484/* XP points to a piece of rtl that has to be checked for any uses of
 registers.
 *XP is the pattern of INSN, or a part of it.
 Called from reload_combine, and recursively by itself.  */
1488static void
1489reload_combine_note_use (rtx *xp, rtx_insn *insn, int ruid, rtx containing_mem)
1490{
rtx x = *xp;
enum rtx_code code = x->code;
const char *fmt;
int i, j;
rtx offset = const0_rtx(const_int_rtx[64]); /* For the REG case below.  */

switch (code)
  {
  case SET:
    if (REG_P (SET_DEST (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
))
{
 reload_combine_note_use (&SET_SRC (x)(((x)->u.fld[1]).rt_rtx), insn, ruid, NULL_RTX(rtx) 0);
 return;
}
    break;

  case USE:
    /* If this is the USE of a return value, we can't change it.  */
    if (REG_P (XEXP (x, 0))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
) && REG_FUNCTION_VALUE_P (XEXP (x, 0))(__extension__ ({ __typeof (((((x)->u.fld[0]).rt_rtx))) const
 _rtx = (((((x)->u.fld[0]).rt_rtx))); if (((enum rtx_code)
 (_rtx)->code) != REG && ((enum rtx_code) (_rtx)->
code) != PARALLEL) rtl_check_failed_flag ("REG_FUNCTION_VALUE_P"
,_rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 1509, __FUNCTION__); _rtx; })->return_val))
{
 /* Mark the return register as used in an unknown fashion.  */
 rtx reg = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
 unsigned int end_regno = END_REGNO (reg);
 for (unsigned int regno = REGNO (reg)(rhs_regno(reg)); regno < end_regno; ++regno)
   reg_state[regno].use_index = -1;
 return;
}
    break;

  case CLOBBER:
    if (REG_P (SET_DEST (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
))
{
 /* No spurious CLOBBERs of pseudo registers may remain.  */
 gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER)((void)(!((rhs_regno((((x)->u.fld[0]).rt_rtx))) < 76) ?
 fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 1524, __FUNCTION__), 0 : 0));
 return;
}
    break;

  case PLUS:
    /* We are interested in (plus (reg) (const_int)) .  */
    if (!REG_P (XEXP (x, 0))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
 || !CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
))
break;
    offset = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);
    x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
    /* Fall through.  */
  case REG:
    {
int regno = REGNO (x)(rhs_regno(x));
int use_index;
int nregs;

/* No spurious USEs of pseudo registers may remain.  */
gcc_assert (regno < FIRST_PSEUDO_REGISTER)((void)(!(regno < 76) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 1544, __FUNCTION__), 0 : 0));

nregs = REG_NREGS (x)((&(x)->u.reg)->nregs);

/* We can't substitute into multi-hard-reg uses.  */
if (nregs > 1)
 {
   while (--nregs >= 0)
     reg_state[regno + nregs].use_index = -1;
   return;
 }

/* We may be called to update uses in previously seen insns.
  Don't add uses beyond the last store we saw.  */
if (ruid < reg_state[regno].store_ruid)
 return;

/* If this register is already used in some unknown fashion, we
  can't do anything.
  If we decrement the index from zero to -1, we can't store more
  uses, so this register becomes used in an unknown fashion.  */
use_index = --reg_state[regno].use_index;
if (use_index < 0)
 return;

if (use_index == RELOAD_COMBINE_MAX_USES16 - 1)
 {
   /* This is the first use of this register we have seen since we
      marked it as dead.  */
   reg_state[regno].offset = offset;
   reg_state[regno].all_offsets_match = true;
   reg_state[regno].use_ruid = ruid;
 }
else
 {
   if (reg_state[regno].use_ruid > ruid)
     reg_state[regno].use_ruid = ruid;

   if (! rtx_equal_p (offset, reg_state[regno].offset))
     reg_state[regno].all_offsets_match = false;
 }

reg_state[regno].reg_use[use_index].insn = insn;
reg_state[regno].reg_use[use_index].ruid = ruid;
reg_state[regno].reg_use[use_index].containing_mem = containing_mem;
reg_state[regno].reg_use[use_index].usep = xp;
return;
    }

  case MEM:
    containing_mem = x;
    break;

  default:
    break;
  }

/* Recursively process the components of X.  */
fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'e')
reload_combine_note_use (&XEXP (x, i)(((x)->u.fld[i]).rt_rtx), insn, ruid, containing_mem);
    else if (fmt[i] == 'E')
{
 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
   reload_combine_note_use (&XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), insn, ruid,
		     containing_mem);
}
  }
1614}
1615
1616/* See if we can reduce the cost of a constant by replacing a move
 with an add.  We track situations in which a register is set to a
 constant or to a register plus a constant.  */
1619/* We cannot do our optimization across labels.  Invalidating all the
 information about register contents we have would be costly, so we
 use move2add_last_label_luid to note where the label is and then
 later disable any optimization that would cross it.
 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
 are only valid if reg_set_luid[n] is greater than
 move2add_last_label_luid.
 For a set that established a new (potential) base register with
 non-constant value, we use move2add_luid from the place where the
 setting insn is encountered; registers based off that base then
 get the same reg_set_luid.  Constants all get
 move2add_last_label_luid + 1 as their reg_set_luid.  */
1631static int reg_set_luid[FIRST_PSEUDO_REGISTER76];

1633/* If reg_base_reg[n] is negative, register n has been set to
 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
 If reg_base_reg[n] is non-negative, register n has been set to the
 sum of reg_offset[n] and the value of register reg_base_reg[n]
 before reg_set_luid[n], calculated in mode reg_mode[n] .
 For multi-hard-register registers, all but the first one are
 recorded as BLKmode in reg_mode.  Setting reg_mode to VOIDmode
 marks it as invalid.  */
1641static HOST_WIDE_INTlong reg_offset[FIRST_PSEUDO_REGISTER76];
1642static int reg_base_reg[FIRST_PSEUDO_REGISTER76];
1643static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER76];
1644static machine_mode reg_mode[FIRST_PSEUDO_REGISTER76];

1646/* move2add_luid is linearly increased while scanning the instructions
 from first to last.  It is used to set reg_set_luid in
 reload_cse_move2add and move2add_note_store.  */
1649static int move2add_luid;

1651/* move2add_last_label_luid is set whenever a label is found.  Labels
 invalidate all previously collected reg_offset data.  */
1653static int move2add_last_label_luid;

1655/* ??? We don't know how zero / sign extension is handled, hence we
 can't go from a narrower to a wider mode.  */
1657#define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE)(GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) || (GET_MODE_SIZE
 (OUTMODE) <= GET_MODE_SIZE (INMODE) && (targetm.truly_noop_truncation
 (GET_MODE_PRECISION (OUTMODE), GET_MODE_PRECISION (INMODE)))
)) \
(GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
     && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)(targetm.truly_noop_truncation (GET_MODE_PRECISION (OUTMODE),
 GET_MODE_PRECISION (INMODE)))))

1662/* Record that REG is being set to a value with the mode of REG.  */

1664static void
1665move2add_record_mode (rtx reg)
1666{
int regno, nregs;
machine_mode mode = GET_MODE (reg)((machine_mode) (reg)->mode);

if (GET_CODE (reg)((enum rtx_code) (reg)->code) == SUBREG)
  {
    regno = subreg_regno (reg);
    nregs = subreg_nregs (reg);
  }
else if (REG_P (reg)(((enum rtx_code) (reg)->code) == REG))
  {
    regno = REGNO (reg)(rhs_regno(reg));
    nregs = REG_NREGS (reg)((&(reg)->u.reg)->nregs);
  }
else
  gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 1681, __FUNCTION__));
for (int i = nregs - 1; i > 0; i--)
  reg_mode[regno + i] = BLKmode((void) 0, E_BLKmode);
reg_mode[regno] = mode;
1685}

1687/* Record that REG is being set to the sum of SYM and OFF.  */

1689static void
1690move2add_record_sym_value (rtx reg, rtx sym, rtx off)
1691{
int regno = REGNO (reg)(rhs_regno(reg));

move2add_record_mode (reg);
reg_set_luid[regno] = move2add_luid;
reg_base_reg[regno] = -1;
reg_symbol_ref[regno] = sym;
reg_offset[regno] = INTVAL (off)((off)->u.hwint[0]);
1699}

1701/* Check if REGNO contains a valid value in MODE.  */

1703static bool
1704move2add_valid_value_p (int regno, scalar_int_mode mode)
1705{
if (reg_set_luid[regno] <= move2add_last_label_luid)
  return false;

if (mode != reg_mode[regno])
  {
    scalar_int_mode old_mode;
    if (!is_a <scalar_int_mode> (reg_mode[regno], &old_mode)
 || !MODES_OK_FOR_MOVE2ADD (mode, old_mode)(GET_MODE_SIZE (mode) == GET_MODE_SIZE (old_mode) || (GET_MODE_SIZE
 (mode) <= GET_MODE_SIZE (old_mode) && (targetm.truly_noop_truncation
 (GET_MODE_PRECISION (mode), GET_MODE_PRECISION (old_mode))))
)
 || !REG_CAN_CHANGE_MODE_P (regno, old_mode, mode)(targetm.can_change_mode_class (old_mode, mode, (regclass_map
[(regno)]))))
return false;
    /* The value loaded into regno in reg_mode[regno] is also valid in
mode after truncation only if (REG:mode regno) is the lowpart of
(REG:reg_mode[regno] regno).  Now, for big endian, the starting
regno of the lowpart might be different.  */
    poly_int64 s_off = subreg_lowpart_offset (mode, old_mode);
    s_off = subreg_regno_offset (regno, old_mode, s_off, mode);
    if (maybe_ne (s_off, 0))
/* We could in principle adjust regno, check reg_mode[regno] to be
  BLKmode, and return s_off to the caller (vs. -1 for failure),
  but we currently have no callers that could make use of this
  information.  */
return false;
  }

for (int i = end_hard_regno (mode, regno) - 1; i > regno; i--)
  if (reg_mode[i] != BLKmode((void) 0, E_BLKmode))
    return false;
return true;
1734}

1736/* This function is called with INSN that sets REG (of mode MODE)
 to (SYM + OFF), while REG is known to already have value (SYM + offset).
 This function tries to change INSN into an add instruction
 (set (REG) (plus (REG) (OFF - offset))) using the known value.
 It also updates the information about REG's known value.
 Return true if we made a change.  */

1743static bool
1744move2add_use_add2_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off,
	rtx_insn *insn)
1746{
rtx pat = PATTERN (insn);
rtx src = SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx);
int regno = REGNO (reg)(rhs_regno(reg));
rtx new_src = gen_int_mode (UINTVAL (off)((unsigned long) ((off)->u.hwint[0])) - reg_offset[regno], mode);
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
bool changed = false;

/* (set (reg) (plus (reg) (const_int 0))) is not canonical;
   use (set (reg) (reg)) instead.
   We don't delete this insn, nor do we convert it into a
   note, to avoid losing register notes or the return
   value flag.  jump2 already knows how to get rid of
   no-op moves.  */
if (new_src == const0_rtx(const_int_rtx[64]))
  {
    /* If the constants are different, this is a
truncation, that, if turned into (set (reg)
(reg)), would be discarded.  Maybe we should
try a truncMN pattern?  */
    if (INTVAL (off)((off)->u.hwint[0]) == reg_offset [regno])
changed = validate_change (insn, &SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx), reg, 0);
  }
else
  {
    struct full_rtx_costs oldcst, newcst;
    rtx tem = gen_rtx_PLUS (mode, reg, new_src)gen_rtx_fmt_ee_stat ((PLUS), ((mode)), ((reg)), ((new_src)) );

    get_full_set_rtx_cost (pat, &oldcst);
    SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx) = tem;
    get_full_set_rtx_cost (pat, &newcst);
    SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx) = src;

    if (costs_lt_p (&newcst, &oldcst, speed)
 && have_add2_insn (reg, new_src))
changed = validate_change (insn, &SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx), tem, 0);	
    else if (sym == NULL_RTX(rtx) 0 && mode != BImode(scalar_int_mode ((scalar_int_mode::from_int) E_BImode)))
{
 scalar_int_mode narrow_mode;
 FOR_EACH_MODE_UNTIL (narrow_mode, mode)for ((narrow_mode) = (get_narrowest_mode (mode)); (narrow_mode
) != (mode); mode_iterator::get_known_next (&(narrow_mode
)))
   {
     if (have_insn_for (STRICT_LOW_PART, narrow_mode)
  && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)mode_mask_array[narrow_mode])
      == (INTVAL (off)((off)->u.hwint[0]) & ~GET_MODE_MASK (narrow_mode)mode_mask_array[narrow_mode])))
{
  rtx narrow_reg = gen_lowpart_common (narrow_mode, reg);
  rtx narrow_src = gen_int_mode (INTVAL (off)((off)->u.hwint[0]),
				 narrow_mode);
  rtx new_set
    = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode,gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((gen_rtx_fmt_e_stat
 ((STRICT_LOW_PART), ((((void) 0, E_VOIDmode))), ((narrow_reg
)) ))), ((narrow_src)) )
					    narrow_reg),gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((gen_rtx_fmt_e_stat
 ((STRICT_LOW_PART), ((((void) 0, E_VOIDmode))), ((narrow_reg
)) ))), ((narrow_src)) )
		   narrow_src)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((gen_rtx_fmt_e_stat
 ((STRICT_LOW_PART), ((((void) 0, E_VOIDmode))), ((narrow_reg
)) ))), ((narrow_src)) );
  get_full_set_rtx_cost (new_set, &newcst);
  if (costs_lt_p (&newcst, &oldcst, speed))
    {
      changed = validate_change (insn, &PATTERN (insn),
				 new_set, 0);
      if (changed)
	break;
    }
}
   }
}
  }
move2add_record_sym_value (reg, sym, off);
return changed;
1812}


1815/* This function is called with INSN that sets REG (of mode MODE) to
 (SYM + OFF), but REG doesn't have known value (SYM + offset).  This
 function tries to find another register which is known to already have
 value (SYM + offset) and change INSN into an add instruction
 (set (REG) (plus (the found register) (OFF - offset))) if such
 a register is found.  It also updates the information about
 REG's known value.
 Return true iff we made a change.  */

1824static bool
1825move2add_use_add3_insn (scalar_int_mode mode, rtx reg, rtx sym, rtx off,
	rtx_insn *insn)
1827{
rtx pat = PATTERN (insn);
rtx src = SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx);
int regno = REGNO (reg)(rhs_regno(reg));
int min_regno = 0;
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
int i;
bool changed = false;
struct full_rtx_costs oldcst, newcst, mincst;
rtx plus_expr;

init_costs_to_max (&mincst);
get_full_set_rtx_cost (pat, &oldcst);

plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx)gen_rtx_fmt_ee_stat ((PLUS), ((((machine_mode) (reg)->mode
))), ((reg)), (((const_int_rtx[64]))) );
SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx) = plus_expr;

for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
  if (move2add_valid_value_p (i, mode)
&& reg_base_reg[i] < 0
&& reg_symbol_ref[i] != NULL_RTX(rtx) 0
&& rtx_equal_p (sym, reg_symbol_ref[i]))
    {
rtx new_src = gen_int_mode (UINTVAL (off)((unsigned long) ((off)->u.hwint[0])) - reg_offset[i],
		    GET_MODE (reg)((machine_mode) (reg)->mode));
/* (set (reg) (plus (reg) (const_int 0))) is not canonical;
  use (set (reg) (reg)) instead.
  We don't delete this insn, nor do we convert it into a
  note, to avoid losing register notes or the return
  value flag.  jump2 already knows how to get rid of
  no-op moves.  */
if (new_src == const0_rtx(const_int_rtx[64]))
 {
   init_costs_to_zero (&mincst);
   min_regno = i;
   break;
 }
else
 {
   XEXP (plus_expr, 1)(((plus_expr)->u.fld[1]).rt_rtx) = new_src;
   get_full_set_rtx_cost (pat, &newcst);

   if (costs_lt_p (&newcst, &mincst, speed))
     {
mincst = newcst;
min_regno = i;
     }
 }
    }
SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx) = src;

if (costs_lt_p (&mincst, &oldcst, speed))
  {
    rtx tem;

    tem = gen_rtx_REG (GET_MODE (reg)((machine_mode) (reg)->mode), min_regno);
    if (i != min_regno)
{
 rtx new_src = gen_int_mode (UINTVAL (off)((unsigned long) ((off)->u.hwint[0])) - reg_offset[min_regno],
		      GET_MODE (reg)((machine_mode) (reg)->mode));
 tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src)gen_rtx_fmt_ee_stat ((PLUS), ((((machine_mode) (reg)->mode
))), ((tem)), ((new_src)) );
}
    if (validate_change (insn, &SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx), tem, 0))
changed = true;
  }
reg_set_luid[regno] = move2add_luid;
move2add_record_sym_value (reg, sym, off);
return changed;
1895}

1897/* Convert move insns with constant inputs to additions if they are cheaper.
 Return true if any changes were made.  */
1899static bool
1900reload_cse_move2add (rtx_insn *first)
1901{
int i;
rtx_insn *insn;
bool changed = false;

for (i = FIRST_PSEUDO_REGISTER76 - 1; i >= 0; i--)
  {
    reg_set_luid[i] = 0;
    reg_offset[i] = 0;
    reg_base_reg[i] = 0;
    reg_symbol_ref[i] = NULL_RTX(rtx) 0;
    reg_mode[i] = VOIDmode((void) 0, E_VOIDmode);
  }

move2add_last_label_luid = 0;
move2add_luid = 2;
for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
  {
    rtx pat, note;

    if (LABEL_P (insn)(((enum rtx_code) (insn)->code) == CODE_LABEL))
{
 move2add_last_label_luid = move2add_luid;
 /* We're going to increment move2add_luid twice after a
    label, so that we can use move2add_last_label_luid + 1 as
    the luid for constants.  */
 move2add_luid++;
 continue;
}
    if (! INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
continue;
    pat = PATTERN (insn);
    /* For simplicity, we only perform this optimization on
straightforward SETs.  */
    scalar_int_mode mode;
    if (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET
 && REG_P (SET_DEST (pat))(((enum rtx_code) ((((pat)->u.fld[0]).rt_rtx))->code) ==
 REG)
 && is_a <scalar_int_mode> (GET_MODE (SET_DEST (pat))((machine_mode) ((((pat)->u.fld[0]).rt_rtx))->mode), &mode))
{
 rtx reg = SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx);
 int regno = REGNO (reg)(rhs_regno(reg));
 rtx src = SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx);

 /* Check if we have valid information on the contents of this
    register in the mode of REG.  */
 if (move2add_valid_value_p (regno, mode)
            && dbg_cnt (cse2_move2add))
   {
     /* Try to transform (set (REGX) (CONST_INT A))
		  ...
		  (set (REGX) (CONST_INT B))
 to
		  (set (REGX) (CONST_INT A))
		  ...
		  (set (REGX) (plus (REGX) (CONST_INT B-A)))
 or
		  (set (REGX) (CONST_INT A))
		  ...
		  (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
     */

     if (CONST_INT_P (src)(((enum rtx_code) (src)->code) == CONST_INT)
  && reg_base_reg[regno] < 0
  && reg_symbol_ref[regno] == NULL_RTX(rtx) 0)
{
  changed |= move2add_use_add2_insn (mode, reg, NULL_RTX(rtx) 0,
				     src, insn);
  continue;
}

     /* Try to transform (set (REGX) (REGY))
		  (set (REGX) (PLUS (REGX) (CONST_INT A)))
		  ...
		  (set (REGX) (REGY))
		  (set (REGX) (PLUS (REGX) (CONST_INT B)))
 to
		  (set (REGX) (REGY))
		  (set (REGX) (PLUS (REGX) (CONST_INT A)))
		  ...
		  (set (REGX) (plus (REGX) (CONST_INT B-A)))  */
     else if (REG_P (src)(((enum rtx_code) (src)->code) == REG)
       && reg_set_luid[regno] == reg_set_luid[REGNO (src)(rhs_regno(src))]
       && reg_base_reg[regno] == reg_base_reg[REGNO (src)(rhs_regno(src))]
       && move2add_valid_value_p (REGNO (src)(rhs_regno(src)), mode))
{
  rtx_insn *next = next_nonnote_nondebug_insn (insn);
  rtx set = NULL_RTX(rtx) 0;
  if (next)
    set = single_set (next);
  if (set
      && SET_DEST (set)(((set)->u.fld[0]).rt_rtx) == reg
      && GET_CODE (SET_SRC (set))((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) == PLUS
      && XEXP (SET_SRC (set), 0)((((((set)->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx) == reg
      && CONST_INT_P (XEXP (SET_SRC (set), 1))(((enum rtx_code) (((((((set)->u.fld[1]).rt_rtx))->u.fld
[1]).rt_rtx))->code) == CONST_INT))
    {
      rtx src3 = XEXP (SET_SRC (set), 1)((((((set)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx);
      unsigned HOST_WIDE_INTlong added_offset = UINTVAL (src3)((unsigned long) ((src3)->u.hwint[0]));
      HOST_WIDE_INTlong base_offset = reg_offset[REGNO (src)(rhs_regno(src))];
      HOST_WIDE_INTlong regno_offset = reg_offset[regno];
      rtx new_src =
	gen_int_mode (added_offset
		      + base_offset
		      - regno_offset,
		      mode);
      bool success = false;
      bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));

      if (new_src == const0_rtx(const_int_rtx[64]))
	/* See above why we create (set (reg) (reg)) here.  */
	success
	  = validate_change (next, &SET_SRC (set)(((set)->u.fld[1]).rt_rtx), reg, 0);
      else
	{
	  rtx old_src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
	  struct full_rtx_costs oldcst, newcst;
	  rtx tem = gen_rtx_PLUS (mode, reg, new_src)gen_rtx_fmt_ee_stat ((PLUS), ((mode)), ((reg)), ((new_src)) );

	  get_full_set_rtx_cost (set, &oldcst);
	  SET_SRC (set)(((set)->u.fld[1]).rt_rtx) = tem;
	  get_full_set_src_cost (tem, mode, &newcst);
	  SET_SRC (set)(((set)->u.fld[1]).rt_rtx) = old_src;
	  costs_add_n_insns (&oldcst, 1);

	  if (costs_lt_p (&newcst, &oldcst, speed)
	      && have_add2_insn (reg, new_src))
	    {
	      rtx newpat = gen_rtx_SET (reg, tem)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((reg))
, ((tem)) );
	      success
		= validate_change (next, &PATTERN (next),
				   newpat, 0);
	    }
	}
      if (success)
	delete_insn (insn);
      changed |= success;
      insn = next;
      move2add_record_mode (reg);
      reg_offset[regno]
	= trunc_int_for_mode (added_offset + base_offset,
			      mode);
      continue;
    }
}
   }

 /* Try to transform
    (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
    ...
    (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
    to
    (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
    ...
    (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A))))  */
 if ((GET_CODE (src)((enum rtx_code) (src)->code) == SYMBOL_REF
      || (GET_CODE (src)((enum rtx_code) (src)->code) == CONST
   && GET_CODE (XEXP (src, 0))((enum rtx_code) ((((src)->u.fld[0]).rt_rtx))->code) == PLUS
   && GET_CODE (XEXP (XEXP (src, 0), 0))((enum rtx_code) (((((((src)->u.fld[0]).rt_rtx))->u.fld
[0]).rt_rtx))->code) == SYMBOL_REF
   && CONST_INT_P (XEXP (XEXP (src, 0), 1))(((enum rtx_code) (((((((src)->u.fld[0]).rt_rtx))->u.fld
[1]).rt_rtx))->code) == CONST_INT)))
     && dbg_cnt (cse2_move2add))
   {
     rtx sym, off;

     if (GET_CODE (src)((enum rtx_code) (src)->code) == SYMBOL_REF)
{
  sym = src;
  off = const0_rtx(const_int_rtx[64]);
}
     else
{
  sym = XEXP (XEXP (src, 0), 0)((((((src)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx);
  off = XEXP (XEXP (src, 0), 1)((((((src)->u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx);
}

     /* If the reg already contains the value which is sum of
 sym and some constant value, we can use an add2 insn.  */
     if (move2add_valid_value_p (regno, mode)
  && reg_base_reg[regno] < 0
  && reg_symbol_ref[regno] != NULL_RTX(rtx) 0
  && rtx_equal_p (sym, reg_symbol_ref[regno]))
changed |= move2add_use_add2_insn (mode, reg, sym, off, insn);

     /* Otherwise, we have to find a register whose value is sum
 of sym and some constant value.  */
     else
changed |= move2add_use_add3_insn (mode, reg, sym, off, insn);

     continue;
   }
}

    for (note = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); note; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
{
 if (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_INC
     && REG_P (XEXP (note, 0))(((enum rtx_code) ((((note)->u.fld[0]).rt_rtx))->code) ==
 REG))
   {
     /* Reset the information about this register.  */
     int regno = REGNO (XEXP (note, 0))(rhs_regno((((note)->u.fld[0]).rt_rtx)));
     if (regno < FIRST_PSEUDO_REGISTER76)
{
  move2add_record_mode (XEXP (note, 0)(((note)->u.fld[0]).rt_rtx));
  reg_mode[regno] = VOIDmode((void) 0, E_VOIDmode);
}
   }
}

    /* There are no REG_INC notes for SP autoinc.  */
    subrtx_var_iterator::array_type array;
    FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (insn), NONCONST)for (subrtx_var_iterator iter (array, PATTERN (insn), rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
{
 rtx mem = *iter;
 if (mem
     && MEM_P (mem)(((enum rtx_code) (mem)->code) == MEM)
     && GET_RTX_CLASS (GET_CODE (XEXP (mem, 0)))(rtx_class[(int) (((enum rtx_code) ((((mem)->u.fld[0]).rt_rtx
))->code))]) == RTX_AUTOINC)
   {
     if (XEXP (XEXP (mem, 0), 0)((((((mem)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
reg_mode[STACK_POINTER_REGNUM7] = VOIDmode((void) 0, E_VOIDmode);
   }
}

    note_stores (insn, move2add_note_store, insn);

    /* If INSN is a conditional branch, we try to extract an
implicit set out of it.  */
    if (any_condjump_p (insn))
{
 rtx cnd = fis_get_condition (insn);

 if (cnd != NULL_RTX(rtx) 0
     && GET_CODE (cnd)((enum rtx_code) (cnd)->code) == NE
     && REG_P (XEXP (cnd, 0))(((enum rtx_code) ((((cnd)->u.fld[0]).rt_rtx))->code) ==
 REG)
     && !reg_set_p (XEXP (cnd, 0)(((cnd)->u.fld[0]).rt_rtx), insn)
     /* The following two checks, which are also in
 move2add_note_store, are intended to reduce the
 number of calls to gen_rtx_SET to avoid memory
 allocation if possible.  */
     && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0)))(((enum mode_class) mode_class[((machine_mode) ((((cnd)->u
.fld[0]).rt_rtx))->mode)]) == MODE_INT || ((enum mode_class
) mode_class[((machine_mode) ((((cnd)->u.fld[0]).rt_rtx))->
mode)]) == MODE_PARTIAL_INT)
     && REG_NREGS (XEXP (cnd, 0))((&((((cnd)->u.fld[0]).rt_rtx))->u.reg)->nregs) == 1
     && CONST_INT_P (XEXP (cnd, 1))(((enum rtx_code) ((((cnd)->u.fld[1]).rt_rtx))->code) ==
 CONST_INT))
   {
     rtx implicit_set =
gen_rtx_SET (XEXP (cnd, 0), XEXP (cnd, 1))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), (((((cnd
)->u.fld[0]).rt_rtx))), (((((cnd)->u.fld[1]).rt_rtx))) );
     move2add_note_store (SET_DEST (implicit_set)(((implicit_set)->u.fld[0]).rt_rtx), implicit_set, insn);
   }
}

    /* If this is a CALL_INSN, all call used registers are stored with
unknown values.  */
    if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
{
 function_abi callee_abi = insn_callee_abi (insn);
 for (i = FIRST_PSEUDO_REGISTER76 - 1; i >= 0; i--)
   if (reg_mode[i] != VOIDmode((void) 0, E_VOIDmode)
&& reg_mode[i] != BLKmode((void) 0, E_BLKmode)
&& callee_abi.clobbers_reg_p (reg_mode[i], i))
     /* Reset the information about this register.  */
     reg_mode[i] = VOIDmode((void) 0, E_VOIDmode);
}
  }
return changed;
2160}

2162/* SET is a SET or CLOBBER that sets DST.  DATA is the insn which
 contains SET.
 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
 Called from reload_cse_move2add via note_stores.  */

2167static void
2168move2add_note_store (rtx dst, const_rtx set, void *data)
2169{
rtx_insn *insn = (rtx_insn *) data;
unsigned int regno = 0;
scalar_int_mode mode;

if (GET_CODE (dst)((enum rtx_code) (dst)->code) == SUBREG)
  regno = subreg_regno (dst);
else if (REG_P (dst)(((enum rtx_code) (dst)->code) == REG))
  regno = REGNO (dst)(rhs_regno(dst));
else
  return;

if (!is_a <scalar_int_mode> (GET_MODE (dst)((machine_mode) (dst)->mode), &mode))
  goto invalidate;

if (GET_CODE (set)((enum rtx_code) (set)->code) == SET)
  {
    rtx note, sym = NULL_RTX(rtx) 0;
    rtx off;

    note = find_reg_equal_equiv_note (insn);
    if (note && GET_CODE (XEXP (note, 0))((enum rtx_code) ((((note)->u.fld[0]).rt_rtx))->code) == SYMBOL_REF)
{
 sym = XEXP (note, 0)(((note)->u.fld[0]).rt_rtx);
 off = const0_rtx(const_int_rtx[64]);
}
    else if (note && GET_CODE (XEXP (note, 0))((enum rtx_code) ((((note)->u.fld[0]).rt_rtx))->code) == CONST
      && GET_CODE (XEXP (XEXP (note, 0), 0))((enum rtx_code) (((((((note)->u.fld[0]).rt_rtx))->u.fld
[0]).rt_rtx))->code) == PLUS
      && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0))((enum rtx_code) ((((((((((note)->u.fld[0]).rt_rtx))->u
.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->code) == SYMBOL_REF
      && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))(((enum rtx_code) ((((((((((note)->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx))->code) == CONST_INT
))
{
 sym = XEXP (XEXP (XEXP (note, 0), 0), 0)(((((((((note)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx);
 off = XEXP (XEXP (XEXP (note, 0), 0), 1)(((((((((note)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx))->
u.fld[1]).rt_rtx);
}

    if (sym != NULL_RTX(rtx) 0)
{
 move2add_record_sym_value (dst, sym, off);
 return;
}
  }

if (GET_CODE (set)((enum rtx_code) (set)->code) == SET
    && GET_CODE (SET_DEST (set))((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) != ZERO_EXTRACT
    && GET_CODE (SET_DEST (set))((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) != STRICT_LOW_PART)
  {
    rtx src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
    rtx base_reg;
    unsigned HOST_WIDE_INTlong offset;
    int base_regno;

    switch (GET_CODE (src)((enum rtx_code) (src)->code))
{
case PLUS:
 if (REG_P (XEXP (src, 0))(((enum rtx_code) ((((src)->u.fld[0]).rt_rtx))->code) ==
 REG))
   {
     base_reg = XEXP (src, 0)(((src)->u.fld[0]).rt_rtx);

     if (CONST_INT_P (XEXP (src, 1))(((enum rtx_code) ((((src)->u.fld[1]).rt_rtx))->code) ==
 CONST_INT))
offset = UINTVAL (XEXP (src, 1))((unsigned long) (((((src)->u.fld[1]).rt_rtx))->u.hwint
[0]));
     else if (REG_P (XEXP (src, 1))(((enum rtx_code) ((((src)->u.fld[1]).rt_rtx))->code) ==
 REG)
       && move2add_valid_value_p (REGNO (XEXP (src, 1))(rhs_regno((((src)->u.fld[1]).rt_rtx))), mode))
{
  if (reg_base_reg[REGNO (XEXP (src, 1))(rhs_regno((((src)->u.fld[1]).rt_rtx)))] < 0
      && reg_symbol_ref[REGNO (XEXP (src, 1))(rhs_regno((((src)->u.fld[1]).rt_rtx)))] == NULL_RTX(rtx) 0)
    offset = reg_offset[REGNO (XEXP (src, 1))(rhs_regno((((src)->u.fld[1]).rt_rtx)))];
  /* Maybe the first register is known to be a
     constant.  */
  else if (move2add_valid_value_p (REGNO (base_reg)(rhs_regno(base_reg)), mode)
	   && reg_base_reg[REGNO (base_reg)(rhs_regno(base_reg))] < 0
	   && reg_symbol_ref[REGNO (base_reg)(rhs_regno(base_reg))] == NULL_RTX(rtx) 0)
    {
      offset = reg_offset[REGNO (base_reg)(rhs_regno(base_reg))];
      base_reg = XEXP (src, 1)(((src)->u.fld[1]).rt_rtx);
    }
  else
    goto invalidate;
}
     else
goto invalidate;

     break;
   }

 goto invalidate;

case REG:
 base_reg = src;
 offset = 0;
 break;

case CONST_INT:
 /* Start tracking the register as a constant.  */
 reg_base_reg[regno] = -1;
 reg_symbol_ref[regno] = NULL_RTX(rtx) 0;
 reg_offset[regno] = INTVAL (SET_SRC (set))(((((set)->u.fld[1]).rt_rtx))->u.hwint[0]);
 /* We assign the same luid to all registers set to constants.  */
 reg_set_luid[regno] = move2add_last_label_luid + 1;
 move2add_record_mode (dst);
 return;

default:
 goto invalidate;
}

    base_regno = REGNO (base_reg)(rhs_regno(base_reg));
    /* If information about the base register is not valid, set it
up as a new base register, pretending its value is known
starting from the current insn.  */
    if (!move2add_valid_value_p (base_regno, mode))
{
 reg_base_reg[base_regno] = base_regno;
 reg_symbol_ref[base_regno] = NULL_RTX(rtx) 0;
 reg_offset[base_regno] = 0;
 reg_set_luid[base_regno] = move2add_luid;
 gcc_assert (GET_MODE (base_reg) == mode)((void)(!(((machine_mode) (base_reg)->mode) == mode) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/postreload.cc"
, 2284, __FUNCTION__), 0 : 0));
 move2add_record_mode (base_reg);
}

    /* Copy base information from our base register.  */
    reg_set_luid[regno] = reg_set_luid[base_regno];
    reg_base_reg[regno] = reg_base_reg[base_regno];
    reg_symbol_ref[regno] = reg_symbol_ref[base_regno];

    /* Compute the sum of the offsets or constants.  */
    reg_offset[regno]
= trunc_int_for_mode (offset + reg_offset[base_regno], mode);

    move2add_record_mode (dst);
  }
else
  {
  invalidate:
    /* Invalidate the contents of the register.  */
    move2add_record_mode (dst);
    reg_mode[regno] = VOIDmode((void) 0, E_VOIDmode);
  }
2306}
2307
2308namespace {

2310const pass_data pass_data_postreload_cse =
2311{
RTL_PASS, /* type */
"postreload", /* name */
OPTGROUP_NONE, /* optinfo_flags */
TV_RELOAD_CSE_REGS, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
TODO_df_finish(1 << 17), /* todo_flags_finish */
2321};

2323class pass_postreload_cse : public rtl_opt_pass
2324{
2325public:
pass_postreload_cse (gcc::context *ctxt)
  : rtl_opt_pass (pass_data_postreload_cse, ctxt)
{}

/* opt_pass methods: */
bool gate (function *) final override
{
  return (optimizeglobal_options.x_optimize > 0 && reload_completed);
}

unsigned int execute (function *) final override;

2338}; // class pass_postreload_cse

2340unsigned int
2341pass_postreload_cse::execute (function *fun)
2342{
if (!dbg_cnt (postreload_cse))
  return 0;

/* Do a very simple CSE pass over just the hard registers.  */
reload_cse_regs (get_insns ());
/* Reload_cse_regs can eliminate potentially-trapping MEMs.
   Remove any EH edges associated with them.  */
if (fun->can_throw_non_call_exceptions
    && purge_all_dead_edges ())
  cleanup_cfg (0);

return 0;
2355}

2357} // anon namespace

2359rtl_opt_pass *
2360make_pass_postreload_cse (gcc::context *ctxt)
2361{
return new pass_postreload_cse (ctxt);
2363}