/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc

Bug Summary

File:	build/gcc/reload1.cc
Warning:	line 3403, column 32 Assigned value is garbage or undefined
Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-suse-linux -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name reload1.cc -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -resource-dir /usr/lib64/clang/15.0.7 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/backward -internal-isystem /usr/lib64/clang/15.0.7/include -internal-isystem /usr/local/include -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../x86_64-suse-linux/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2023-03-27-141847-20772-1/report-p9yjGA.plist -x c++ /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc
1/* Reload pseudo regs into hard regs for insns that require hard regs.
 Copyright (C) 1987-2023 Free Software Foundation, Inc.

4This file is part of GCC.

6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8Software Foundation; either version 3, or (at your option) any later
9version.

11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14for more details.

16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3.  If not see
18<http://www.gnu.org/licenses/>.  */

20#include "config.h"
21#include "system.h"
22#include "coretypes.h"
23#include "backend.h"
24#include "target.h"
25#include "rtl.h"
26#include "tree.h"
27#include "predict.h"
28#include "df.h"
29#include "memmodel.h"
30#include "tm_p.h"
31#include "optabs.h"
32#include "regs.h"
33#include "ira.h"
34#include "recog.h"

36#include "rtl-error.h"
37#include "expr.h"
38#include "addresses.h"
39#include "cfgrtl.h"
40#include "cfgbuild.h"
41#include "reload.h"
42#include "except.h"
43#include "dumpfile.h"
44#include "rtl-iter.h"
45#include "function-abi.h"

47/* This file contains the reload pass of the compiler, which is
 run after register allocation has been done.  It checks that
 each insn is valid (operands required to be in registers really
 are in registers of the proper class) and fixes up invalid ones
 by copying values temporarily into registers for the insns
 that need them.

 The results of register allocation are described by the vector
 reg_renumber; the insns still contain pseudo regs, but reg_renumber
 can be used to find which hard reg, if any, a pseudo reg is in.

 The technique we always use is to free up a few hard regs that are
 called ``reload regs'', and for each place where a pseudo reg
 must be in a hard reg, copy it temporarily into one of the reload regs.

 Reload regs are allocated locally for every instruction that needs
 reloads.  When there are pseudos which are allocated to a register that
 has been chosen as a reload reg, such pseudos must be ``spilled''.
 This means that they go to other hard regs, or to stack slots if no other
 available hard regs can be found.  Spilling can invalidate more
 insns, requiring additional need for reloads, so we must keep checking
 until the process stabilizes.

 For machines with different classes of registers, we must keep track
 of the register class needed for each reload, and make sure that
 we allocate enough reload registers of each class.

 The file reload.cc contains the code that checks one insn for
 validity and reports the reloads that it needs.  This file
 is in charge of scanning the entire rtl code, accumulating the
 reload needs, spilling, assigning reload registers to use for
 fixing up each insn, and generating the new insns to copy values
 into the reload registers.  */
80
81struct target_reload default_target_reload;
82#if SWITCHABLE_TARGET1
83struct target_reload *this_target_reload = &default_target_reload;
84#endif

86#define spill_indirect_levels(this_target_reload->x_spill_indirect_levels)			\
(this_target_reload->x_spill_indirect_levels)

89/* During reload_as_needed, element N contains a REG rtx for the hard reg
 into which reg N has been reloaded (perhaps for a previous insn).  */
91static rtx *reg_last_reload_reg;

93/* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
 for an output reload that stores into reg N.  */
95static regset_head reg_has_output_reload;

97/* Indicates which hard regs are reload-registers for an output reload
 in the current insn.  */
99static HARD_REG_SET reg_is_output_reload;

101/* Widest mode in which each pseudo reg is referred to (via subreg).  */
102static machine_mode *reg_max_ref_mode;

104/* Vector to remember old contents of reg_renumber before spilling.  */
105static short *reg_old_renumber;

107/* During reload_as_needed, element N contains the last pseudo regno reloaded
 into hard register N.  If that pseudo reg occupied more than one register,
 reg_reloaded_contents points to that pseudo for each spill register in
 use; all of these must remain set for an inheritance to occur.  */
111static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER76];

113/* During reload_as_needed, element N contains the insn for which
 hard register N was last used.   Its contents are significant only
 when reg_reloaded_valid is set for this register.  */
116static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER76];

118/* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid.  */
119static HARD_REG_SET reg_reloaded_valid;
120/* Indicate if the register was dead at the end of the reload.
 This is only valid if reg_reloaded_contents is set and valid.  */
122static HARD_REG_SET reg_reloaded_dead;

124/* Number of spill-regs so far; number of valid elements of spill_regs.  */
125static int n_spills;

127/* In parallel with spill_regs, contains REG rtx's for those regs.
 Holds the last rtx used for any given reg, or 0 if it has never
 been used for spilling yet.  This rtx is reused, provided it has
 the proper mode.  */
131static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER76];

133/* In parallel with spill_regs, contains nonzero for a spill reg
 that was stored after the last time it was used.
 The precise value is the insn generated to do the store.  */
136static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER76];

138/* This is the register that was stored with spill_reg_store.  This is a
 copy of reload_out / reload_out_reg when the value was stored; if
 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg.  */
141static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER76];

143/* This table is the inverse mapping of spill_regs:
 indexed by hard reg number,
 it contains the position of that reg in spill_regs,
 or -1 for something that is not in spill_regs.

 ?!?  This is no longer accurate.  */
149static short spill_reg_order[FIRST_PSEUDO_REGISTER76];

151/* This reg set indicates registers that can't be used as spill registers for
 the currently processed insn.  These are the hard registers which are live
 during the insn, but not allocated to pseudos, as well as fixed
 registers.  */
155static HARD_REG_SET bad_spill_regs;

157/* These are the hard registers that can't be used as spill register for any
 insn.  This includes registers used for user variables and registers that
 we can't eliminate.  A register that appears in this set also can't be used
 to retry register allocation.  */
161static HARD_REG_SET bad_spill_regs_global;

163/* Describes order of use of registers for reloading
 of spilled pseudo-registers.  `n_spills' is the number of
 elements that are actually valid; new ones are added at the end.

 Both spill_regs and spill_reg_order are used on two occasions:
 once during find_reload_regs, where they keep track of the spill registers
 for a single insn, but also during reload_as_needed where they show all
 the registers ever used by reload.  For the latter case, the information
 is calculated during finish_spills.  */
172static short spill_regs[FIRST_PSEUDO_REGISTER76];

174/* This vector of reg sets indicates, for each pseudo, which hard registers
 may not be used for retrying global allocation because the register was
 formerly spilled from one of them.  If we allowed reallocating a pseudo to
 a register that it was already allocated to, reload might not
 terminate.  */
179static HARD_REG_SET *pseudo_previous_regs;

181/* This vector of reg sets indicates, for each pseudo, which hard
 registers may not be used for retrying global allocation because they
 are used as spill registers during one of the insns in which the
 pseudo is live.  */
185static HARD_REG_SET *pseudo_forbidden_regs;

187/* All hard regs that have been used as spill registers for any insn are
 marked in this set.  */
189static HARD_REG_SET used_spill_regs;

191/* Index of last register assigned as a spill register.  We allocate in
 a round-robin fashion.  */
193static int last_spill_reg;

195/* Record the stack slot for each spilled hard register.  */
196static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER76];

198/* Width allocated so far for that stack slot.  */
199static poly_uint64_pod spill_stack_slot_width[FIRST_PSEUDO_REGISTER76];

201/* Record which pseudos needed to be spilled.  */
202static regset_head spilled_pseudos;

204/* Record which pseudos changed their allocation in finish_spills.  */
205static regset_head changed_allocation_pseudos;

207/* Used for communication between order_regs_for_reload and count_pseudo.
 Used to avoid counting one pseudo twice.  */
209static regset_head pseudos_counted;

211/* First uid used by insns created by reload in this function.
 Used in find_equiv_reg.  */
213int reload_first_uid;

215/* Flag set by local-alloc or global-alloc if anything is live in
 a call-clobbered reg across calls.  */
217int caller_save_needed;

219/* Set to 1 while reload_as_needed is operating.
 Required by some machines to handle any generated moves differently.  */
221int reload_in_progress = 0;

223/* This obstack is used for allocation of rtl during register elimination.
 The allocated storage can be freed once find_reloads has processed the
 insn.  */
226static struct obstack reload_obstack;

228/* Points to the beginning of the reload_obstack.  All insn_chain structures
 are allocated first.  */
230static char *reload_startobj;

232/* The point after all insn_chain structures.  Used to quickly deallocate
 memory allocated in copy_reloads during calculate_needs_all_insns.  */
234static char *reload_firstobj;

236/* This points before all local rtl generated by register elimination.
 Used to quickly free all memory after processing one insn.  */
238static char *reload_insn_firstobj;

240/* List of insn_chain instructions, one for every insn that reload needs to
 examine.  */
242class insn_chain *reload_insn_chain;

244/* TRUE if we potentially left dead insns in the insn stream and want to
 run DCE immediately after reload, FALSE otherwise.  */
246static bool need_dce;

248/* List of all insns needing reloads.  */
249static class insn_chain *insns_need_reload;
250
251/* This structure is used to record information about register eliminations.
 Each array entry describes one possible way of eliminating a register
 in favor of another.   If there is more than one way of eliminating a
 particular register, the most preferred should be specified first.  */

256struct elim_table
257{
int from;			/* Register number to be eliminated.  */
int to;			/* Register number used as replacement.  */
poly_int64_pod initial_offset; /* Initial difference between values.  */
int can_eliminate;		/* Nonzero if this elimination can be done.  */
int can_eliminate_previous;	/* Value returned by TARGET_CAN_ELIMINATE
		   target hook in previous scan over insns
		   made by reload.  */
poly_int64_pod offset;	/* Current offset between the two regs.  */
poly_int64_pod previous_offset; /* Offset at end of previous insn.  */
int ref_outside_mem;		/* "to" has been referenced outside a MEM.  */
rtx from_rtx;			/* REG rtx for the register to be eliminated.
		   We cannot simply compare the number since
		   we might then spuriously replace a hard
		   register corresponding to a pseudo
		   assigned to the reg to be eliminated.  */
rtx to_rtx;			/* REG rtx for the replacement.  */
274};

276static struct elim_table *reg_eliminate = 0;

278/* This is an intermediate structure to initialize the table.  It has
 exactly the members provided by ELIMINABLE_REGS.  */
280static const struct elim_table_1
281{
const int from;
const int to;
284} reg_eliminate_1[] =

ELIMINABLE_REGS{{ 16, 7}, { 16, 6}, { 19, 7}, { 19, 6}};

288#define NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0])) ARRAY_SIZE (reg_eliminate_1)(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))

290/* Record the number of pending eliminations that have an offset not equal
 to their initial offset.  If nonzero, we use a new copy of each
 replacement result in any insns encountered.  */
293int num_not_at_initial_offset;

295/* Count the number of registers that we may be able to eliminate.  */
296static int num_eliminable;
297/* And the number of registers that are equivalent to a constant that
 can be eliminated to frame_pointer / arg_pointer + constant.  */
299static int num_eliminable_invariants;

301/* For each label, we record the offset of each elimination.  If we reach
 a label by more than one path and an offset differs, we cannot do the
 elimination.  This information is indexed by the difference of the
 number of the label and the first label number.  We can't offset the
 pointer itself as this can cause problems on machines with segmented
 memory.  The first table is an array of flags that records whether we
 have yet encountered a label and the second table is an array of arrays,
 one entry in the latter array for each elimination.  */

310static int first_label_num;
311static char *offsets_known_at;
312static poly_int64_pod (*offsets_at)[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))];

314vec<reg_equivs_t, va_gc> *reg_equivs;

316/* Stack of addresses where an rtx has been changed.  We can undo the 
 changes by popping items off the stack and restoring the original
 value at each location. 

 We use this simplistic undo capability rather than copy_rtx as copy_rtx
 will not make a deep copy of a normally sharable rtx, such as
 (const (plus (symbol_ref) (const_int))).  If such an expression appears
 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
 rtx expression would be changed.  See PR 42431.  */

326typedef rtx *rtx_p;
327static vec<rtx_p> substitute_stack;

329/* Number of labels in the current function.  */

331static int num_labels;
332
333static void replace_pseudos_in (rtx *, machine_mode, rtx);
334static void maybe_fix_stack_asms (void);
335static void copy_reloads (class insn_chain *);
336static void calculate_needs_all_insns (int);
337static int find_reg (class insn_chain *, int);
338static void find_reload_regs (class insn_chain *);
339static void select_reload_regs (void);
340static void delete_caller_save_insns (void);

342static void spill_failure (rtx_insn *, enum reg_class);
343static void count_spilled_pseudo (int, int, int);
344static void delete_dead_insn (rtx_insn *);
345static void alter_reg (int, int, bool);
346static void set_label_offsets (rtx, rtx_insn *, int);
347static void check_eliminable_occurrences (rtx);
348static void elimination_effects (rtx, machine_mode);
349static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool);
350static int eliminate_regs_in_insn (rtx_insn *, int);
351static void update_eliminable_offsets (void);
352static void mark_not_eliminable (rtx, const_rtx, void *);
353static void set_initial_elim_offsets (void);
354static bool verify_initial_elim_offsets (void);
355static void set_initial_label_offsets (void);
356static void set_offsets_for_label (rtx_insn *);
357static void init_eliminable_invariants (rtx_insn *, bool);
358static void init_elim_table (void);
359static void free_reg_equiv (void);
360static void update_eliminables (HARD_REG_SET *);
361static bool update_eliminables_and_spill (void);
362static void elimination_costs_in_insn (rtx_insn *);
363static void spill_hard_reg (unsigned int, int);
364static int finish_spills (int);
365static void scan_paradoxical_subregs (rtx);
366static void count_pseudo (int);
367static void order_regs_for_reload (class insn_chain *);
368static void reload_as_needed (int);
369static void forget_old_reloads_1 (rtx, const_rtx, void *);
370static void forget_marked_reloads (regset);
371static int reload_reg_class_lower (const void *, const void *);
372static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
		    machine_mode);
374static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
		     machine_mode);
376static int reload_reg_free_p (unsigned int, int, enum reload_type);
377static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
			rtx, rtx, int, int);
379static int free_for_value_p (int, machine_mode, int, enum reload_type,
	     rtx, rtx, int, int);
381static int allocate_reload_reg (class insn_chain *, int, int);
382static int conflicts_with_override (rtx);
383static void failed_reload (rtx_insn *, int);
384static int set_reload_reg (int, int);
385static void choose_reload_regs_init (class insn_chain *, rtx *);
386static void choose_reload_regs (class insn_chain *);
387static void emit_input_reload_insns (class insn_chain *, struct reload *,
		     rtx, int);
389static void emit_output_reload_insns (class insn_chain *, struct reload *,
		      int);
391static void do_input_reload (class insn_chain *, struct reload *, int);
392static void do_output_reload (class insn_chain *, struct reload *, int);
393static void emit_reload_insns (class insn_chain *);
394static void delete_output_reload (rtx_insn *, int, int, rtx);
395static void delete_address_reloads (rtx_insn *, rtx_insn *);
396static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
397static void inc_for_reload (rtx, rtx, rtx, poly_int64);
398static void substitute (rtx *, const_rtx, rtx);
399static bool gen_reload_chain_without_interm_reg_p (int, int);
400static int reloads_conflict (int, int);
401static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
402static rtx_insn *emit_insn_if_valid_for_reload (rtx);
403
404/* Initialize the reload pass.  This is called at the beginning of compilation
 and may be called again if the target is reinitialized.  */

407void
408init_reload (void)
409{
int i;

/* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
   Set spill_indirect_levels to the number of levels such addressing is
   permitted, zero if it is not permitted at all.  */

rtx tem
  = gen_rtx_MEM (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))),
   gen_rtx_PLUS (Pmode,gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((gen_rtx_REG ((global_options.x_ix86_pmode == PMODE_DI ?
 (scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) : (
scalar_int_mode ((scalar_int_mode::from_int) E_SImode))), (((
76)) + 5) + 1))), ((gen_int_mode (4, (global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
)))) )
		 gen_rtx_REG (Pmode,gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((gen_rtx_REG ((global_options.x_ix86_pmode == PMODE_DI ?
 (scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) : (
scalar_int_mode ((scalar_int_mode::from_int) E_SImode))), (((
76)) + 5) + 1))), ((gen_int_mode (4, (global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
)))) )
			      LAST_VIRTUAL_REGISTER + 1),gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((gen_rtx_REG ((global_options.x_ix86_pmode == PMODE_DI ?
 (scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) : (
scalar_int_mode ((scalar_int_mode::from_int) E_SImode))), (((
76)) + 5) + 1))), ((gen_int_mode (4, (global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
)))) )
		 gen_int_mode (4, Pmode))gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((gen_rtx_REG ((global_options.x_ix86_pmode == PMODE_DI ?
 (scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) : (
scalar_int_mode ((scalar_int_mode::from_int) E_SImode))), (((
76)) + 5) + 1))), ((gen_int_mode (4, (global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
)))) ));
spill_indirect_levels(this_target_reload->x_spill_indirect_levels) = 0;

while (memory_address_p (QImode, tem)memory_address_addr_space_p (((scalar_int_mode ((scalar_int_mode
::from_int) E_QImode))), (tem), 0))
  {
    spill_indirect_levels(this_target_reload->x_spill_indirect_levels)++;
    tem = gen_rtx_MEM (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), tem);
  }

/* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)).  */

tem = gen_rtx_MEM (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), gen_rtx_SYMBOL_REF (Pmode, "foo")gen_rtx_fmt_s0_stat ((SYMBOL_REF), (((global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), (("foo")) ));
indirect_symref_ok(this_target_reload->x_indirect_symref_ok) = memory_address_p (QImode, tem)memory_address_addr_space_p (((scalar_int_mode ((scalar_int_mode
::from_int) E_QImode))), (tem), 0);

/* See if reg+reg is a valid (and offsettable) address.  */

for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
  {
    tem = gen_rtx_PLUS (Pmode,gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((gen_rtx_REG ((global_options.x_ix86_pmode == PMODE_DI ?
 (scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) : (
scalar_int_mode ((scalar_int_mode::from_int) E_SImode))), 6))
), ((gen_rtx_REG ((global_options.x_ix86_pmode == PMODE_DI ? (
scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode
 ((scalar_int_mode::from_int) E_SImode))), i))) )
	  gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((gen_rtx_REG ((global_options.x_ix86_pmode == PMODE_DI ?
 (scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) : (
scalar_int_mode ((scalar_int_mode::from_int) E_SImode))), 6))
), ((gen_rtx_REG ((global_options.x_ix86_pmode == PMODE_DI ? (
scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode
 ((scalar_int_mode::from_int) E_SImode))), i))) )
	  gen_rtx_REG (Pmode, i))gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((gen_rtx_REG ((global_options.x_ix86_pmode == PMODE_DI ?
 (scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) : (
scalar_int_mode ((scalar_int_mode::from_int) E_SImode))), 6))
), ((gen_rtx_REG ((global_options.x_ix86_pmode == PMODE_DI ? (
scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode
 ((scalar_int_mode::from_int) E_SImode))), i))) );

    /* This way, we make sure that reg+reg is an offsettable address.  */
    tem = plus_constant (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), tem, 4);

    for (int mode = 0; mode < MAX_MACHINE_MODE; mode++)
if (!double_reg_address_ok(this_target_reload->x_double_reg_address_ok)[mode]
   && memory_address_p ((enum machine_mode)mode, tem)memory_address_addr_space_p (((enum machine_mode)mode), (tem)
, 0))
 double_reg_address_ok(this_target_reload->x_double_reg_address_ok)[mode] = 1;
  }

/* Initialize obstack for our rtl allocation.  */
if (reload_startobj == NULLnullptr)
  {
    gcc_obstack_init (&reload_obstack)_obstack_begin (((&reload_obstack)), (memory_block_pool::
block_size), (0), (mempool_obstack_chunk_alloc), (mempool_obstack_chunk_free
));
    reload_startobj = XOBNEWVAR (&reload_obstack, char, 0)((char *) __extension__ ({ struct obstack *__h = ((&reload_obstack
)); __extension__ ({ struct obstack *__o = (__h); size_t __len
 = (((0))); if (__extension__ ({ struct obstack const *__o1 =
 (__o); (size_t) (__o1->chunk_limit - __o1->next_free);
 }) < __len) _obstack_newchunk (__o, __len); ((void) ((__o
)->next_free += (__len))); }); __extension__ ({ struct obstack
 *__o1 = (__h); void *__value = (void *) __o1->object_base
; if (__o1->next_free == __value) __o1->maybe_empty_object
 = 1; __o1->next_free = (sizeof (ptrdiff_t) < sizeof (void
 *) ? ((__o1->object_base) + (((__o1->next_free) - (__o1
->object_base) + (__o1->alignment_mask)) & ~(__o1->
alignment_mask))) : (char *) (((ptrdiff_t) (__o1->next_free
) + (__o1->alignment_mask)) & ~(__o1->alignment_mask
))); if ((size_t) (__o1->next_free - (char *) __o1->chunk
) > (size_t) (__o1->chunk_limit - (char *) __o1->chunk
)) __o1->next_free = __o1->chunk_limit; __o1->object_base
 = __o1->next_free; __value; }); }));
  }

INIT_REG_SET (&spilled_pseudos)bitmap_initialize (&spilled_pseudos, &reg_obstack);
INIT_REG_SET (&changed_allocation_pseudos)bitmap_initialize (&changed_allocation_pseudos, &reg_obstack
);
INIT_REG_SET (&pseudos_counted)bitmap_initialize (&pseudos_counted, &reg_obstack);
462}

464/* List of insn chains that are currently unused.  */
465static class insn_chain *unused_insn_chains = 0;

467/* Allocate an empty insn_chain structure.  */
468class insn_chain *
469new_insn_chain (void)
470{
class insn_chain *c;

if (unused_insn_chains == 0)
  {
    c = XOBNEW (&reload_obstack, class insn_chain)((class insn_chain *) __extension__ ({ struct obstack *__h = (
(&reload_obstack)); __extension__ ({ struct obstack *__o =
 (__h); size_t __len = ((sizeof (class insn_chain))); if (__extension__
 ({ struct obstack const *__o1 = (__o); (size_t) (__o1->chunk_limit
 - __o1->next_free); }) < __len) _obstack_newchunk (__o
, __len); ((void) ((__o)->next_free += (__len))); }); __extension__
 ({ struct obstack *__o1 = (__h); void *__value = (void *) __o1
->object_base; if (__o1->next_free == __value) __o1->
maybe_empty_object = 1; __o1->next_free = (sizeof (ptrdiff_t
) < sizeof (void *) ? ((__o1->object_base) + (((__o1->
next_free) - (__o1->object_base) + (__o1->alignment_mask
)) & ~(__o1->alignment_mask))) : (char *) (((ptrdiff_t
) (__o1->next_free) + (__o1->alignment_mask)) & ~(__o1
->alignment_mask))); if ((size_t) (__o1->next_free - (char
 *) __o1->chunk) > (size_t) (__o1->chunk_limit - (char
 *) __o1->chunk)) __o1->next_free = __o1->chunk_limit
; __o1->object_base = __o1->next_free; __value; }); }));
    INIT_REG_SET (&c->live_throughout)bitmap_initialize (&c->live_throughout, &reg_obstack
);
    INIT_REG_SET (&c->dead_or_set)bitmap_initialize (&c->dead_or_set, &reg_obstack);
  }
else
  {
    c = unused_insn_chains;
    unused_insn_chains = c->next;
  }
c->is_caller_save_insn = 0;
c->need_operand_change = 0;
c->need_reload = 0;
c->need_elim = 0;
return c;
489}

491/* Small utility function to set all regs in hard reg set TO which are
 allocated to pseudos in regset FROM.  */

494void
495compute_use_by_pseudos (HARD_REG_SET *to, regset from)
496{
unsigned int regno;
reg_set_iterator rsi;

EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)for (bmp_iter_set_init (&(rsi), (from), (76), &(regno
)); bmp_iter_set (&(rsi), &(regno)); bmp_iter_next (&
(rsi), &(regno)))
  {
    int r = reg_renumber[regno];

    if (r < 0)
{
 /* reload_combine uses the information from DF_LIVE_IN,
    which might still contain registers that have not
    actually been allocated since they have an
    equivalence.  */
 gcc_assert (ira_conflicts_p || reload_completed)((void)(!(ira_conflicts_p || reload_completed) ? fancy_abort (
"/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 510, __FUNCTION__), 0 : 0));
}
    else
add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno)((machine_mode) (regno_reg_rtx[regno])->mode), r);
  }
515}

517/* Replace all pseudos found in LOC with their corresponding
 equivalences.  */

520static void
521replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage)
522{
rtx x = *loc;
enum rtx_code code;
const char *fmt;
int i, j;

if (! x)
  return;

code = GET_CODE (x)((enum rtx_code) (x)->code);
if (code == REG)
  {
    unsigned int regno = REGNO (x)(rhs_regno(x));

    if (regno < FIRST_PSEUDO_REGISTER76)
return;

    x = eliminate_regs_1 (x, mem_mode, usage, true, false);
    if (x != *loc)
{
 *loc = x;
 replace_pseudos_in (loc, mem_mode, usage);
 return;
}

    if (reg_equiv_constant (regno)(*reg_equivs)[(regno)].constant)
*loc = reg_equiv_constant (regno)(*reg_equivs)[(regno)].constant;
    else if (reg_equiv_invariant (regno)(*reg_equivs)[(regno)].invariant)
*loc = reg_equiv_invariant (regno)(*reg_equivs)[(regno)].invariant;
    else if (reg_equiv_mem (regno)(*reg_equivs)[(regno)].mem)
*loc = reg_equiv_mem (regno)(*reg_equivs)[(regno)].mem;
    else if (reg_equiv_address (regno)(*reg_equivs)[(regno)].address)
*loc = gen_rtx_MEM (GET_MODE (x)((machine_mode) (x)->mode), reg_equiv_address (regno)(*reg_equivs)[(regno)].address);
    else
{
 gcc_assert (!REG_P (regno_reg_rtx[regno])((void)(!(!(((enum rtx_code) (regno_reg_rtx[regno])->code)
 == REG) || (rhs_regno(regno_reg_rtx[regno])) != regno) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 558, __FUNCTION__), 0 : 0))
      || REGNO (regno_reg_rtx[regno]) != regno)((void)(!(!(((enum rtx_code) (regno_reg_rtx[regno])->code)
 == REG) || (rhs_regno(regno_reg_rtx[regno])) != regno) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 558, __FUNCTION__), 0 : 0));
 *loc = regno_reg_rtx[regno];
}

    return;
  }
else if (code == MEM)
  {
    replace_pseudos_in (& XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), GET_MODE (x)((machine_mode) (x)->mode), usage);
    return;
  }

/* Process each of our operands recursively.  */
fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = 0; i < GET_RTX_LENGTH (code)(rtx_length[(int) (code)]); i++, fmt++)
  if (*fmt == 'e')
    replace_pseudos_in (&XEXP (x, i)(((x)->u.fld[i]).rt_rtx), mem_mode, usage);
  else if (*fmt == 'E')
    for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
replace_pseudos_in (& XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), mem_mode, usage);
578}

580/* Determine if the current function has an exception receiver block
 that reaches the exit block via non-exceptional edges  */

583static bool
584has_nonexceptional_receiver (void)
585{
edge e;
edge_iterator ei;
basic_block *tos, *worklist, bb;

/* If we're not optimizing, then just err on the safe side.  */
if (!optimizeglobal_options.x_optimize)
  return true;

/* First determine which blocks can reach exit via normal paths.  */
tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1)((basic_block *) xmalloc (sizeof (basic_block) * ((((cfun + 0
))->cfg->x_n_basic_blocks) + 1)));

FOR_EACH_BB_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_entry_block_ptr->next_bb
; bb != ((cfun + 0))->cfg->x_exit_block_ptr; bb = bb->
next_bb)
  bb->flags &= ~BB_REACHABLE;

/* Place the exit block on our worklist.  */
EXIT_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_exit_block_ptr)->flags |= BB_REACHABLE;
*tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_exit_block_ptr);

/* Iterate: find everything reachable from what we've already seen.  */
while (tos != worklist)
  {
    bb = *--tos;

    FOR_EACH_EDGE (e, ei, bb->preds)for ((ei) = ei_start_1 (&((bb->preds))); ei_cond ((ei)
, &(e)); ei_next (&(ei)))
if (!(e->flags & EDGE_ABNORMAL))
 {
   basic_block src = e->src;

   if (!(src->flags & BB_REACHABLE))
     {
src->flags |= BB_REACHABLE;
*tos++ = src;
     }
 }
  }
free (worklist);

/* Now see if there's a reachable block with an exceptional incoming
   edge.  */
FOR_EACH_BB_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_entry_block_ptr->next_bb
; bb != ((cfun + 0))->cfg->x_exit_block_ptr; bb = bb->
next_bb)
  if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
    return true;

/* No exceptional block reached exit unexceptionally.  */
return false;
631}

633/* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
 zero elements) to MAX_REG_NUM elements.

 Initialize all new fields to NULL and update REG_EQUIVS_SIZE.  */
637void
638grow_reg_equivs (void)
639{
int old_size = vec_safe_length (reg_equivs);
int max_regno = max_reg_num ();
int i;
reg_equivs_t ze;

memset (&ze, 0, sizeof (reg_equivs_t));
vec_safe_reserve (reg_equivs, max_regno);
for (i = old_size; i < max_regno; i++)
  reg_equivs->quick_insert (i, ze);
649}

651
652/* Global variables used by reload and its subroutines.  */

654/* The current basic block while in calculate_elim_costs_all_insns.  */
655static basic_block elim_bb;

657/* Set during calculate_needs if an insn needs register elimination.  */
658static int something_needs_elimination;
659/* Set during calculate_needs if an insn needs an operand changed.  */
660static int something_needs_operands_changed;
661/* Set by alter_regs if we spilled a register to the stack.  */
662static bool something_was_spilled;

664/* Nonzero means we couldn't get enough spill regs.  */
665static int failure;

667/* Temporary array of pseudo-register number.  */
668static int *temp_pseudo_reg_arr;

670/* If a pseudo has no hard reg, delete the insns that made the equivalence.
 If that insn didn't set the register (i.e., it copied the register to
 memory), just delete that insn instead of the equivalencing insn plus
 anything now dead.  If we call delete_dead_insn on that insn, we may
 delete the insn that actually sets the register if the register dies
 there and that is incorrect.  */
676static void
677remove_init_insns ()
678{
for (int i = FIRST_PSEUDO_REGISTER76; i < max_regno; i++)
  {
    if (reg_renumber[i] < 0 && reg_equiv_init (i)(*reg_equivs)[(i)].init != 0)
{
 rtx list;
 for (list = reg_equiv_init (i)(*reg_equivs)[(i)].init; list; list = XEXP (list, 1)(((list)->u.fld[1]).rt_rtx))
   {
     rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0)(((list)->u.fld[0]).rt_rtx));

     /* If we already deleted the insn or if it may trap, we can't
 delete it.  The latter case shouldn't happen, but can
 if an insn has a variable address, gets a REG_EH_REGION
 note added to it, and then gets converted into a load
 from a constant address.  */
     if (NOTE_P (equiv_insn)(((enum rtx_code) (equiv_insn)->code) == NOTE)
  || can_throw_internal (equiv_insn))
;
     else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
delete_dead_insn (equiv_insn);
     else
SET_INSN_DELETED (equiv_insn)set_insn_deleted (equiv_insn);;
   }
}
  }
703}

705/* Return true if remove_init_insns will delete INSN.  */
706static bool
707will_delete_init_insn_p (rtx_insn *insn)
708{
rtx set = single_set (insn);
if (!set || !REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 REG))
  return false;
unsigned regno = REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx)));

if (can_throw_internal (insn))
  return false;

if (regno < FIRST_PSEUDO_REGISTER76 || reg_renumber[regno] >= 0)
  return false;

for (rtx list = reg_equiv_init (regno)(*reg_equivs)[(regno)].init; list; list = XEXP (list, 1)(((list)->u.fld[1]).rt_rtx))
  {
    rtx equiv_insn = XEXP (list, 0)(((list)->u.fld[0]).rt_rtx);
    if (equiv_insn == insn)
return true;
  }
return false;
727}

729/* Main entry point for the reload pass.

 FIRST is the first insn of the function being compiled.

 GLOBAL nonzero means we were called from global_alloc
 and should attempt to reallocate any pseudoregs that we
 displace from hard regs we will use for reloads.
 If GLOBAL is zero, we do not have enough information to do that,
 so any pseudo reg that is spilled must go to the stack.

 Return value is TRUE if reload likely left dead insns in the
 stream and a DCE pass should be run to elimiante them.  Else the
 return value is FALSE.  */

743bool
744reload (rtx_insn *first, int global)
745{
int i, n;
rtx_insn *insn;
struct elim_table *ep;
basic_block bb;
bool inserted;

/* Make sure even insns with volatile mem refs are recognizable.  */
init_recog ();

failure = 0;

reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0)((char *) __extension__ ({ struct obstack *__h = ((&reload_obstack
)); __extension__ ({ struct obstack *__o = (__h); size_t __len
 = (((0))); if (__extension__ ({ struct obstack const *__o1 =
 (__o); (size_t) (__o1->chunk_limit - __o1->next_free);
 }) < __len) _obstack_newchunk (__o, __len); ((void) ((__o
)->next_free += (__len))); }); __extension__ ({ struct obstack
 *__o1 = (__h); void *__value = (void *) __o1->object_base
; if (__o1->next_free == __value) __o1->maybe_empty_object
 = 1; __o1->next_free = (sizeof (ptrdiff_t) < sizeof (void
 *) ? ((__o1->object_base) + (((__o1->next_free) - (__o1
->object_base) + (__o1->alignment_mask)) & ~(__o1->
alignment_mask))) : (char *) (((ptrdiff_t) (__o1->next_free
) + (__o1->alignment_mask)) & ~(__o1->alignment_mask
))); if ((size_t) (__o1->next_free - (char *) __o1->chunk
) > (size_t) (__o1->chunk_limit - (char *) __o1->chunk
)) __o1->next_free = __o1->chunk_limit; __o1->object_base
 = __o1->next_free; __value; }); }));

/* Make sure that the last insn in the chain
   is not something that needs reloading.  */
emit_note (NOTE_INSN_DELETED);

/* Enable find_equiv_reg to distinguish insns made by reload.  */
reload_first_uid = get_max_uid ();

/* Initialize the secondary memory table.  */
clear_secondary_mem ();

/* We don't have a stack slot for any spill reg yet.  */
memset (spill_stack_slot, 0, sizeof spill_stack_slot);
memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);

/* Initialize the save area information for caller-save, in case some
   are needed.  */
init_save_areas ();

/* Compute which hard registers are now in use
   as homes for pseudo registers.
   This is done here rather than (eg) in global_alloc
   because this point is reached even if not optimizing.  */
for (i = FIRST_PSEUDO_REGISTER76; i < max_regno; i++)
  mark_home_live (i);

/* A function that has a nonlocal label that can reach the exit
   block via non-exceptional paths must save all call-saved
   registers.  */
if (cfun(cfun + 0)->has_nonlocal_label
    && has_nonexceptional_receiver ())
  crtl(&x_rtl)->saves_all_registers = 1;

if (crtl(&x_rtl)->saves_all_registers)
  for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
    if (! crtl(&x_rtl)->abi->clobbers_full_reg_p (i)
 && ! fixed_regs(this_target_hard_regs->x_fixed_regs)[i]
 && ! LOCAL_REGNO (i)0)
df_set_regs_ever_live (i, true);

/* Find all the pseudo registers that didn't get hard regs
   but do have known equivalent constants or memory slots.
   These include parameters (known equivalent to parameter slots)
   and cse'd or loop-moved constant memory addresses.

   Record constant equivalents in reg_equiv_constant
   so they will be substituted by find_reloads.
   Record memory equivalents in reg_mem_equiv so they can
   be substituted eventually by altering the REG-rtx's.  */

grow_reg_equivs ();
reg_old_renumber = XCNEWVEC (short, max_regno)((short *) xcalloc ((max_regno), sizeof (short)));
memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno)((HARD_REG_SET *) xmalloc (sizeof (HARD_REG_SET) * (max_regno
)));
pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno)((HARD_REG_SET *) xcalloc ((max_regno), sizeof (HARD_REG_SET)
));

CLEAR_HARD_REG_SET (bad_spill_regs_global);

init_eliminable_invariants (first, true);
init_elim_table ();

/* Alter each pseudo-reg rtx to contain its hard reg number.  Assign
   stack slots to the pseudos that lack hard regs or equivalents.
   Do not touch virtual registers.  */

temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1)((int *) xmalloc (sizeof (int) * (max_regno - (((76)) + 5) - 1
)));
for (n = 0, i = LAST_VIRTUAL_REGISTER(((76)) + 5) + 1; i < max_regno; i++)
  temp_pseudo_reg_arr[n++] = i;

if (ira_conflicts_p)
  /* Ask IRA to order pseudo-registers for better stack slot
     sharing.  */
  ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_mode);

for (i = 0; i < n; i++)
  alter_reg (temp_pseudo_reg_arr[i], -1, false);

/* If we have some registers we think can be eliminated, scan all insns to
   see if there is an insn that sets one of these registers to something
   other than itself plus a constant.  If so, the register cannot be
   eliminated.  Doing this scan here eliminates an extra pass through the
   main reload loop in the most common case where register elimination
   cannot be done.  */
for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
  if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
    note_pattern_stores (PATTERN (insn), mark_not_eliminable, NULLnullptr);

maybe_fix_stack_asms ();

insns_need_reload = 0;
something_needs_elimination = 0;

/* Initialize to -1, which means take the first spill register.  */
last_spill_reg = -1;

/* Spill any hard regs that we know we can't eliminate.  */
CLEAR_HARD_REG_SET (used_spill_regs);
/* There can be multiple ways to eliminate a register;
   they should be listed adjacently.
   Elimination for any register fails only if all possible ways fail.  */
for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; )
  {
    int from = ep->from;
    int can_eliminate = 0;
    do
{
        can_eliminate |= ep->can_eliminate;
        ep++;
}
    while (ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))] && ep->from == from);
    if (! can_eliminate)
spill_hard_reg (from, 1);
  }

if (!HARD_FRAME_POINTER_IS_FRAME_POINTER(6 == 19) && frame_pointer_needed((&x_rtl)->frame_pointer_needed))
  spill_hard_reg (HARD_FRAME_POINTER_REGNUM6, 1);

finish_spills (global);

/* From now on, we may need to generate moves differently.  We may also
   allow modifications of insns which cause them to not be recognized.
   Any such modifications will be cleaned up during reload itself.  */
reload_in_progress = 1;

/* This loop scans the entire function each go-round
   and repeats until one repetition spills no additional hard regs.  */
for (;;)
  {
    int something_changed;
    poly_int64 starting_frame_size;

    starting_frame_size = get_frame_size ();
    something_was_spilled = false;

    set_initial_elim_offsets ();
    set_initial_label_offsets ();

    /* For each pseudo register that has an equivalent location defined,
try to eliminate any eliminable registers (such as the frame pointer)
assuming initial offsets for the replacement register, which
is the normal case.

If the resulting location is directly addressable, substitute
the MEM we just got directly for the old REG.

If it is not addressable but is a constant or the sum of a hard reg
and constant, it is probably not addressable because the constant is
out of range, in that case record the address; we will generate
hairy code to compute the address in a register each time it is
needed.  Similarly if it is a hard register, but one that is not
valid as an address register.

If the location is not addressable, but does not have one of the
above forms, assign a stack slot.  We have to do this to avoid the
potential of producing lots of reloads if, e.g., a location involves
a pseudo that didn't get a hard register and has an equivalent memory
location that also involves a pseudo that didn't get a hard register.

Perhaps at some point we will improve reload_when_needed handling
so this problem goes away.  But that's very hairy.  */

    for (i = FIRST_PSEUDO_REGISTER76; i < max_regno; i++)
if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i)(*reg_equivs)[(i)].memory_loc)
 {
   rtx x = eliminate_regs (reg_equiv_memory_loc (i)(*reg_equivs)[(i)].memory_loc, VOIDmode((void) 0, E_VOIDmode),
		    NULL_RTX(rtx) 0);

   if (strict_memory_address_addr_space_p
  (GET_MODE (regno_reg_rtx[i])((machine_mode) (regno_reg_rtx[i])->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx),
   MEM_ADDR_SPACE (x)(get_mem_attrs (x)->addrspace)))
     reg_equiv_mem (i)(*reg_equivs)[(i)].mem = x, reg_equiv_address (i)(*reg_equivs)[(i)].address = 0;
   else if (CONSTANT_P (XEXP (x, 0))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
     || (REG_P (XEXP (x, 0))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
	 && REGNO (XEXP (x, 0))(rhs_regno((((x)->u.fld[0]).rt_rtx))) < FIRST_PSEUDO_REGISTER76)
     || (GET_CODE (XEXP (x, 0))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == PLUS
	 && REG_P (XEXP (XEXP (x, 0), 0))(((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[
0]).rt_rtx))->code) == REG)
	 && (REGNO (XEXP (XEXP (x, 0), 0))(rhs_regno(((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx
)))
	     < FIRST_PSEUDO_REGISTER76)
	 && CONSTANT_P (XEXP (XEXP (x, 0), 1))((rtx_class[(int) (((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx
))->u.fld[1]).rt_rtx))->code))]) == RTX_CONST_OBJ)))
     reg_equiv_address (i)(*reg_equivs)[(i)].address = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), reg_equiv_mem (i)(*reg_equivs)[(i)].mem = 0;
   else
     {
/* Make a new stack slot.  Then indicate that something
   changed so we go back and recompute offsets for
   eliminable registers because the allocation of memory
   below might change some offset.  reg_equiv_{mem,address}
   will be set up for this pseudo on the next pass around
   the loop.  */
reg_equiv_memory_loc (i)(*reg_equivs)[(i)].memory_loc = 0;
reg_equiv_init (i)(*reg_equivs)[(i)].init = 0;
alter_reg (i, -1, true);
     }
 }

    if (caller_save_needed)
setup_save_areas ();

    if (maybe_ne (starting_frame_size, 0) && crtl(&x_rtl)->stack_alignment_needed)
{
 /* If we have a stack frame, we must align it now.  The
    stack size may be a part of the offset computation for
    register elimination.  So if this changes the stack size,
    then repeat the elimination bookkeeping.  We don't
    realign when there is no stack, as that will cause a
    stack frame when none is needed should
    TARGET_STARTING_FRAME_OFFSET not be already aligned to
    STACK_BOUNDARY.  */
 assign_stack_local (BLKmode((void) 0, E_BLKmode), 0, crtl(&x_rtl)->stack_alignment_needed);
}
    /* If we allocated another stack slot, redo elimination bookkeeping.  */
    if (something_was_spilled
 || maybe_ne (starting_frame_size, get_frame_size ()))
{
 if (update_eliminables_and_spill ())
   finish_spills (0);
 continue;
}

    if (caller_save_needed)
{
 save_call_clobbered_regs ();
 /* That might have allocated new insn_chain structures.  */
 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0)((char *) __extension__ ({ struct obstack *__h = ((&reload_obstack
)); __extension__ ({ struct obstack *__o = (__h); size_t __len
 = (((0))); if (__extension__ ({ struct obstack const *__o1 =
 (__o); (size_t) (__o1->chunk_limit - __o1->next_free);
 }) < __len) _obstack_newchunk (__o, __len); ((void) ((__o
)->next_free += (__len))); }); __extension__ ({ struct obstack
 *__o1 = (__h); void *__value = (void *) __o1->object_base
; if (__o1->next_free == __value) __o1->maybe_empty_object
 = 1; __o1->next_free = (sizeof (ptrdiff_t) < sizeof (void
 *) ? ((__o1->object_base) + (((__o1->next_free) - (__o1
->object_base) + (__o1->alignment_mask)) & ~(__o1->
alignment_mask))) : (char *) (((ptrdiff_t) (__o1->next_free
) + (__o1->alignment_mask)) & ~(__o1->alignment_mask
))); if ((size_t) (__o1->next_free - (char *) __o1->chunk
) > (size_t) (__o1->chunk_limit - (char *) __o1->chunk
)) __o1->next_free = __o1->chunk_limit; __o1->object_base
 = __o1->next_free; __value; }); }));
}

    calculate_needs_all_insns (global);

    if (! ira_conflicts_p)
/* Don't do it for IRA.  We need this info because we don't
  change live_throughout and dead_or_set for chains when IRA
  is used.  */
CLEAR_REG_SET (&spilled_pseudos)bitmap_clear (&spilled_pseudos);

    something_changed = 0;

    /* If we allocated any new memory locations, make another pass
since it might have changed elimination offsets.  */
    if (something_was_spilled
 || maybe_ne (starting_frame_size, get_frame_size ()))
something_changed = 1;

    /* Even if the frame size remained the same, we might still have
changed elimination offsets, e.g. if find_reloads called
force_const_mem requiring the back end to allocate a constant
pool base register that needs to be saved on the stack.  */
    else if (!verify_initial_elim_offsets ())
something_changed = 1;

    if (update_eliminables_and_spill ())
{
 finish_spills (0);
 something_changed = 1;
}
    else
{
 select_reload_regs ();
 if (failure)
   goto failed;
 if (insns_need_reload)
   something_changed |= finish_spills (global);
}

    if (! something_changed)
break;

    if (caller_save_needed)
delete_caller_save_insns ();

    obstack_free (&reload_obstack, reload_firstobj)__extension__ ({ struct obstack *__o = (&reload_obstack);
 void *__obj = (void *) (reload_firstobj); if (__obj > (void
 *) __o->chunk && __obj < (void *) __o->chunk_limit
) __o->next_free = __o->object_base = (char *) __obj; else
 _obstack_free (__o, __obj); });
  }

/* If global-alloc was run, notify it of any register eliminations we have
   done.  */
if (global)
  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
    if (ep->can_eliminate)
mark_elimination (ep->from, ep->to);

remove_init_insns ();

/* Use the reload registers where necessary
   by generating move instructions to move the must-be-register
   values into or out of the reload registers.  */

if (insns_need_reload != 0 || something_needs_elimination
    || something_needs_operands_changed)
  {
    poly_int64 old_frame_size = get_frame_size ();

    reload_as_needed (global);

    gcc_assert (known_eq (old_frame_size, get_frame_size ()))((void)(!((!maybe_ne (old_frame_size, get_frame_size ()))) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1049, __FUNCTION__), 0 : 0));

    gcc_assert (verify_initial_elim_offsets ())((void)(!(verify_initial_elim_offsets ()) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1051, __FUNCTION__), 0 : 0));
  }

/* If we were able to eliminate the frame pointer, show that it is no
   longer live at the start of any basic block.  If it ls live by
   virtue of being in a pseudo, that pseudo will be marked live
   and hence the frame pointer will be known to be live via that
   pseudo.  */

if (! frame_pointer_needed((&x_rtl)->frame_pointer_needed))
  FOR_EACH_BB_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_entry_block_ptr->next_bb
; bb != ((cfun + 0))->cfg->x_exit_block_ptr; bb = bb->
next_bb)
    bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM6);

/* Come here (with failure set nonzero) if we can't get enough spill
   regs.  */
failed:

CLEAR_REG_SET (&changed_allocation_pseudos)bitmap_clear (&changed_allocation_pseudos);
CLEAR_REG_SET (&spilled_pseudos)bitmap_clear (&spilled_pseudos);
reload_in_progress = 0;

/* Now eliminate all pseudo regs by modifying them into
   their equivalent memory references.
   The REG-rtx's for the pseudos are modified in place,
   so all insns that used to refer to them now refer to memory.

   For a reg that has a reg_equiv_address, all those insns
   were changed by reloading so that no insns refer to it any longer;
   but the DECL_RTL of a variable decl may refer to it,
   and if so this causes the debugging info to mention the variable.  */

for (i = FIRST_PSEUDO_REGISTER76; i < max_regno; i++)
  {
    rtx addr = 0;

    if (reg_equiv_mem (i)(*reg_equivs)[(i)].mem)
addr = XEXP (reg_equiv_mem (i), 0)((((*reg_equivs)[(i)].mem)->u.fld[0]).rt_rtx);

    if (reg_equiv_address (i)(*reg_equivs)[(i)].address)
addr = reg_equiv_address (i)(*reg_equivs)[(i)].address;

    if (addr)
{
 if (reg_renumber[i] < 0)
   {
     rtx reg = regno_reg_rtx[i];

     REG_USERVAR_P (reg)(__extension__ ({ __typeof ((reg)) const _rtx = ((reg)); if (
((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
 ("REG_USERVAR_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1098, __FUNCTION__); _rtx; })->volatil) = 0;
     PUT_CODE (reg, MEM)((reg)->code = (MEM));
     XEXP (reg, 0)(((reg)->u.fld[0]).rt_rtx) = addr;
     if (reg_equiv_memory_loc (i)(*reg_equivs)[(i)].memory_loc)
MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i))((__extension__ ({ __typeof ((reg)) const _rtx = ((reg)); if (
((enum rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1102, __FUNCTION__); _rtx; })->volatil) = (__extension__
 ({ __typeof (((*reg_equivs)[(i)].memory_loc)) const _rtx = (
((*reg_equivs)[(i)].memory_loc)); if (((enum rtx_code) (_rtx)
->code) != MEM && ((enum rtx_code) (_rtx)->code
) != ASM_OPERANDS && ((enum rtx_code) (_rtx)->code
) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P", _rtx
, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1102, __FUNCTION__); _rtx; })->volatil), (__extension__ (
{ __typeof ((reg)) const _rtx = ((reg)); if (((enum rtx_code)
 (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_NOTRAP_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1102, __FUNCTION__); _rtx; })->call) = (__extension__ ({
 __typeof (((*reg_equivs)[(i)].memory_loc)) const _rtx = (((*
reg_equivs)[(i)].memory_loc)); if (((enum rtx_code) (_rtx)->
code) != MEM) rtl_check_failed_flag ("MEM_NOTRAP_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1102, __FUNCTION__); _rtx; })->call), (__extension__ ({ __typeof
 ((reg)) const _rtx = ((reg)); if (((enum rtx_code) (_rtx)->
code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1102, __FUNCTION__); _rtx; })->unchanging) = (__extension__
 ({ __typeof (((*reg_equivs)[(i)].memory_loc)) const _rtx = (
((*reg_equivs)[(i)].memory_loc)); if (((enum rtx_code) (_rtx)
->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P", _rtx
, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1102, __FUNCTION__); _rtx; })->unchanging), (__extension__
 ({ __typeof ((reg)) const _rtx = ((reg)); if (((enum rtx_code
) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_KEEP_ALIAS_SET_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1102, __FUNCTION__); _rtx; })->jump) = (__extension__ ({
 __typeof (((*reg_equivs)[(i)].memory_loc)) const _rtx = (((*
reg_equivs)[(i)].memory_loc)); if (((enum rtx_code) (_rtx)->
code) != MEM) rtl_check_failed_flag ("MEM_KEEP_ALIAS_SET_P", _rtx
, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1102, __FUNCTION__); _rtx; })->jump), (__extension__ ({ __typeof
 ((reg)) const _rtx = ((reg)); if (((enum rtx_code) (_rtx)->
code) != MEM) rtl_check_failed_flag ("MEM_POINTER", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1102, __FUNCTION__); _rtx; })->frame_related) = (__extension__
 ({ __typeof (((*reg_equivs)[(i)].memory_loc)) const _rtx = (
((*reg_equivs)[(i)].memory_loc)); if (((enum rtx_code) (_rtx)
->code) != MEM) rtl_check_failed_flag ("MEM_POINTER", _rtx
, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1102, __FUNCTION__); _rtx; })->frame_related), (((reg)->
u.fld[1]).rt_mem) = ((((*reg_equivs)[(i)].memory_loc)->u.fld
[1]).rt_mem));
     else
MEM_ATTRS (reg)(((reg)->u.fld[1]).rt_mem) = 0;
     MEM_NOTRAP_P (reg)(__extension__ ({ __typeof ((reg)) const _rtx = ((reg)); if (
((enum rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag
 ("MEM_NOTRAP_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1105, __FUNCTION__); _rtx; })->call) = 1;
   }
 else if (reg_equiv_mem (i)(*reg_equivs)[(i)].mem)
   XEXP (reg_equiv_mem (i), 0)((((*reg_equivs)[(i)].mem)->u.fld[0]).rt_rtx) = addr;
}

    /* We don't want complex addressing modes in debug insns
if simpler ones will do, so delegitimize equivalences
in debug insns.  */
    if (MAY_HAVE_DEBUG_BIND_INSNSglobal_options.x_flag_var_tracking_assignments && reg_renumber[i] < 0)
{
 rtx reg = regno_reg_rtx[i];
 rtx equiv = 0;
 df_ref use, next;

 if (reg_equiv_constant (i)(*reg_equivs)[(i)].constant)
   equiv = reg_equiv_constant (i)(*reg_equivs)[(i)].constant;
 else if (reg_equiv_invariant (i)(*reg_equivs)[(i)].invariant)
   equiv = reg_equiv_invariant (i)(*reg_equivs)[(i)].invariant;
 else if (reg && MEM_P (reg)(((enum rtx_code) (reg)->code) == MEM))
   equiv = targetm.delegitimize_address (reg);
 else if (reg && REG_P (reg)(((enum rtx_code) (reg)->code) == REG) && (int)REGNO (reg)(rhs_regno(reg)) != i)
   equiv = reg;

 if (equiv == reg)
   continue;

 for (use = DF_REG_USE_CHAIN (i)(df->use_regs[(i)]->reg_chain); use; use = next)
   {
     insn = DF_REF_INSN (use)((use)->base.insn_info->insn);

     /* Make sure the next ref is for a different instruction,
 so that we're not affected by the rescan.  */
     next = DF_REF_NEXT_REG (use)((use)->base.next_reg);
     while (next && DF_REF_INSN (next)((next)->base.insn_info->insn) == insn)
next = DF_REF_NEXT_REG (next)((next)->base.next_reg);

     if (DEBUG_BIND_INSN_P (insn)((((enum rtx_code) (insn)->code) == DEBUG_INSN) &&
 (((enum rtx_code) (PATTERN (insn))->code) == VAR_LOCATION
)))
{
  if (!equiv)
    {
      INSN_VAR_LOCATION_LOC (insn)((((((__extension__ ({ __typeof (PATTERN (insn)) const _rtx =
 (PATTERN (insn)); if (((enum rtx_code) (_rtx)->code) != VAR_LOCATION
) rtl_check_failed_flag ("INSN_VAR_LOCATION", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1146, __FUNCTION__); _rtx; }))))->u.fld[1]).rt_rtx)) = gen_rtx_UNKNOWN_VAR_LOC ()(gen_rtx_fmt_e_stat ((CLOBBER), ((((void) 0, E_VOIDmode))), (
((const_int_rtx[64]))) ));
      df_insn_rescan_debug_internal (insn);
    }
  else
    INSN_VAR_LOCATION_LOC (insn)((((((__extension__ ({ __typeof (PATTERN (insn)) const _rtx =
 (PATTERN (insn)); if (((enum rtx_code) (_rtx)->code) != VAR_LOCATION
) rtl_check_failed_flag ("INSN_VAR_LOCATION", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1150, __FUNCTION__); _rtx; }))))->u.fld[1]).rt_rtx))
      = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn)((((((__extension__ ({ __typeof (PATTERN (insn)) const _rtx =
 (PATTERN (insn)); if (((enum rtx_code) (_rtx)->code) != VAR_LOCATION
) rtl_check_failed_flag ("INSN_VAR_LOCATION", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1151, __FUNCTION__); _rtx; }))))->u.fld[1]).rt_rtx)),
			      reg, equiv);
}
   }
}
  }

/* We must set reload_completed now since the cleanup_subreg_operands call
   below will re-recognize each insn and reload may have generated insns
   which are only valid during and after reload.  */
reload_completed = 1;

/* Make a pass over all the insns and delete all USEs which we inserted
   only to tag a REG_EQUAL note on them.  Remove all REG_DEAD and REG_UNUSED
   notes.  Delete all CLOBBER insns, except those that refer to the return
   value and the special mem:BLK CLOBBERs added to prevent the scheduler
   from misarranging variable-array code, and simplify (subreg (reg))
   operands.  Strip and regenerate REG_INC notes that may have been moved
   around.  */

for (insn = first; insn; insn = NEXT_INSN (insn))
  if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
    {
rtx *pnote;

if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx),
	      VOIDmode((void) 0, E_VOIDmode), CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx));

if ((GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == USE
    /* We mark with QImode USEs introduced by reload itself.  */
    && (GET_MODE (insn)((machine_mode) (insn)->mode) == QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode))
 || find_reg_note (insn, REG_EQUAL, NULL_RTX(rtx) 0)))
   || (GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == CLOBBER
&& (!MEM_P (XEXP (PATTERN (insn), 0))(((enum rtx_code) ((((PATTERN (insn))->u.fld[0]).rt_rtx))->
code) == MEM)
    || GET_MODE (XEXP (PATTERN (insn), 0))((machine_mode) ((((PATTERN (insn))->u.fld[0]).rt_rtx))->
mode) != BLKmode((void) 0, E_BLKmode)
    || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0))((enum rtx_code) (((((((PATTERN (insn))->u.fld[0]).rt_rtx)
)->u.fld[0]).rt_rtx))->code) != SCRATCH
	&& XEXP (XEXP (PATTERN (insn), 0), 0)((((((PATTERN (insn))->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx
)
		!= stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])))
&& (!REG_P (XEXP (PATTERN (insn), 0))(((enum rtx_code) ((((PATTERN (insn))->u.fld[0]).rt_rtx))->
code) == REG)
    || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))(__extension__ ({ __typeof (((((PATTERN (insn))->u.fld[0])
.rt_rtx))) const _rtx = (((((PATTERN (insn))->u.fld[0]).rt_rtx
))); if (((enum rtx_code) (_rtx)->code) != REG && (
(enum rtx_code) (_rtx)->code) != PARALLEL) rtl_check_failed_flag
 ("REG_FUNCTION_VALUE_P",_rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1191, __FUNCTION__); _rtx; })->return_val))))
 {
   delete_insn (insn);
   continue;
 }

/* Some CLOBBERs may survive until here and still reference unassigned
  pseudos with const equivalent, which may in turn cause ICE in later
  passes if the reference remains in place.  */
if (GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == CLOBBER)
 replace_pseudos_in (& XEXP (PATTERN (insn), 0)(((PATTERN (insn))->u.fld[0]).rt_rtx),
	      VOIDmode((void) 0, E_VOIDmode), PATTERN (insn));

/* Discard obvious no-ops, even without -O.  This optimization
  is fast and doesn't interfere with debugging.  */
if (NONJUMP_INSN_P (insn)(((enum rtx_code) (insn)->code) == INSN)
   && GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == SET
   && REG_P (SET_SRC (PATTERN (insn)))(((enum rtx_code) ((((PATTERN (insn))->u.fld[1]).rt_rtx))->
code) == REG)
   && REG_P (SET_DEST (PATTERN (insn)))(((enum rtx_code) ((((PATTERN (insn))->u.fld[0]).rt_rtx))->
code) == REG)
   && (REGNO (SET_SRC (PATTERN (insn)))(rhs_regno((((PATTERN (insn))->u.fld[1]).rt_rtx)))
== REGNO (SET_DEST (PATTERN (insn)))(rhs_regno((((PATTERN (insn))->u.fld[0]).rt_rtx)))))
 {
   delete_insn (insn);
   continue;
 }

pnote = &REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx);
while (*pnote != 0)
 {
   if (REG_NOTE_KIND (*pnote)((enum reg_note) ((machine_mode) (*pnote)->mode)) == REG_DEAD
|| REG_NOTE_KIND (*pnote)((enum reg_note) ((machine_mode) (*pnote)->mode)) == REG_UNUSED
|| REG_NOTE_KIND (*pnote)((enum reg_note) ((machine_mode) (*pnote)->mode)) == REG_INC)
     *pnote = XEXP (*pnote, 1)(((*pnote)->u.fld[1]).rt_rtx);
   else
     pnote = &XEXP (*pnote, 1)(((*pnote)->u.fld[1]).rt_rtx);
 }

if (AUTO_INC_DEC0)
 add_auto_inc_notes (insn, PATTERN (insn));

/* Simplify (subreg (reg)) if it appears as an operand.  */
cleanup_subreg_operands (insn);

/* Clean up invalid ASMs so that they don't confuse later passes.
  See PR 21299.  */
if (asm_noperands (PATTERN (insn)) >= 0)
 {
   extract_insn (insn);
   if (!constrain_operands (1, get_enabled_alternatives (insn)))
     {
error_for_asm (insn,
	       "%<asm%> operand has impossible constraints");
delete_insn (insn);
continue;
     }
 }
    }

free (temp_pseudo_reg_arr);

/* Indicate that we no longer have known memory locations or constants.  */
free_reg_equiv ();

free (reg_max_ref_mode);
free (reg_old_renumber);
free (pseudo_previous_regs);
free (pseudo_forbidden_regs);

CLEAR_HARD_REG_SET (used_spill_regs);
for (i = 0; i < n_spills; i++)
  SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);

/* Free all the insn_chain structures at once.  */
obstack_free (&reload_obstack, reload_startobj)__extension__ ({ struct obstack *__o = (&reload_obstack);
 void *__obj = (void *) (reload_startobj); if (__obj > (void
 *) __o->chunk && __obj < (void *) __o->chunk_limit
) __o->next_free = __o->object_base = (char *) __obj; else
 _obstack_free (__o, __obj); });
unused_insn_chains = 0;

inserted = fixup_abnormal_edges ();

/* We've possibly turned single trapping insn into multiple ones.  */
if (cfun(cfun + 0)->can_throw_non_call_exceptions)
  {
    auto_sbitmap blocks (last_basic_block_for_fn (cfun)(((cfun + 0))->cfg->x_last_basic_block));
    bitmap_ones (blocks);
    find_many_sub_basic_blocks (blocks);
  }

if (inserted)
  commit_edge_insertions ();

/* Replacing pseudos with their memory equivalents might have
   created shared rtx.  Subsequent passes would get confused
   by this, so unshare everything here.  */
unshare_all_rtl_again (first);

1285#ifdef STACK_BOUNDARY((((global_options.x_ix86_isa_flags & (1UL << 1)) !=
 0) && ix86_cfun_abi () == MS_ABI) ? 128 : ((8) * (((
global_options.x_ix86_isa_flags & (1UL << 1)) != 0)
 ? 8 : 4)))
/* init_emit has set the alignment of the hard frame pointer
   to STACK_BOUNDARY.  It is very likely no longer valid if
   the hard frame pointer was used for register allocation.  */
if (!frame_pointer_needed((&x_rtl)->frame_pointer_needed))
  REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM)((&x_rtl)->emit.regno_pointer_align[6]) = BITS_PER_UNIT(8);
1291#endif

substitute_stack.release ();

gcc_assert (bitmap_empty_p (&spilled_pseudos))((void)(!(bitmap_empty_p (&spilled_pseudos)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1295, __FUNCTION__), 0 : 0));

reload_completed = !failure;

return need_dce;
1300}

1302/* Yet another special case.  Unfortunately, reg-stack forces people to
 write incorrect clobbers in asm statements.  These clobbers must not
 cause the register to appear in bad_spill_regs, otherwise we'll call
 fatal_insn later.  We clear the corresponding regnos in the live
 register sets to avoid this.
 The whole thing is rather sick, I'm afraid.  */

1309static void
1310maybe_fix_stack_asms (void)
1311{
1312#ifdef STACK_REGS
const char *constraints[MAX_RECOG_OPERANDS30];
machine_mode operand_mode[MAX_RECOG_OPERANDS30];
class insn_chain *chain;

for (chain = reload_insn_chain; chain != 0; chain = chain->next)
  {
    int i, noperands;
    HARD_REG_SET clobbered, allowed;
    rtx pat;

    if (! INSN_P (chain->insn)(((((enum rtx_code) (chain->insn)->code) == INSN) || ((
(enum rtx_code) (chain->insn)->code) == JUMP_INSN) || (
((enum rtx_code) (chain->insn)->code) == CALL_INSN)) ||
 (((enum rtx_code) (chain->insn)->code) == DEBUG_INSN))
 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
continue;
    pat = PATTERN (chain->insn);
    if (GET_CODE (pat)((enum rtx_code) (pat)->code) != PARALLEL)
continue;

    CLEAR_HARD_REG_SET (clobbered);
    CLEAR_HARD_REG_SET (allowed);

    /* First, make a mask of all stack regs that are clobbered.  */
    for (i = 0; i < XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
{
 rtx t = XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]);
 if (GET_CODE (t)((enum rtx_code) (t)->code) == CLOBBER && STACK_REG_P (XEXP (t, 0))((((enum rtx_code) ((((t)->u.fld[0]).rt_rtx))->code) ==
 REG) && ((unsigned long) (((rhs_regno((((t)->u.fld
[0]).rt_rtx))))) - (unsigned long) (8) <= (unsigned long) (
15) - (unsigned long) (8))))
   SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))(rhs_regno((((t)->u.fld[0]).rt_rtx))));
}

    /* Get the operand values and constraints out of the insn.  */
    decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
	   constraints, operand_mode, NULLnullptr);

    /* For every operand, see what registers are allowed.  */
    for (i = 0; i < noperands; i++)
{
 const char *p = constraints[i];
 /* For every alternative, we compute the class of registers allowed
    for reloading in CLS, and merge its contents into the reg set
    ALLOWED.  */
 int cls = (int) NO_REGS;

 for (;;)
   {
     char c = *p;

     if (c == '\0' || c == ',' || c == '#')
{
  /* End of one alternative - mark the regs in the current
     class, and reset the class.  */
  allowed |= reg_class_contents(this_target_hard_regs->x_reg_class_contents)[cls];
  cls = NO_REGS;
  p++;
  if (c == '#')
    do {
      c = *p++;
    } while (c != '\0' && c != ',');
  if (c == '\0')
    break;
  continue;
}

     switch (c)
{
case 'g':
  cls = (int) reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[cls][(int) GENERAL_REGS];
  break;

default:
  enum constraint_num cn = lookup_constraint (p);
  if (insn_extra_address_constraint (cn))
    cls = (int) reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[cls]
      [(int) base_reg_class (VOIDmode((void) 0, E_VOIDmode), ADDR_SPACE_GENERIC0,
			     ADDRESS, SCRATCH)];
  else
    cls = (int) reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[cls]
      [reg_class_for_constraint (cn)];
  break;
}
     p += CONSTRAINT_LEN (c, p)insn_constraint_len (c,p);
   }
}
    /* Those of the registers which are clobbered, but allowed by the
constraints, must be usable as reload registers.  So clear them
out of the life information.  */
    allowed &= clobbered;
    for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
if (TEST_HARD_REG_BIT (allowed, i))
 {
   CLEAR_REGNO_REG_SET (&chain->live_throughout, i)bitmap_clear_bit (&chain->live_throughout, i);
   CLEAR_REGNO_REG_SET (&chain->dead_or_set, i)bitmap_clear_bit (&chain->dead_or_set, i);
 }
  }

1406#endif
1407}
1408
1409/* Copy the global variables n_reloads and rld into the corresponding elts
 of CHAIN.  */
1411static void
1412copy_reloads (class insn_chain *chain)
1413{
chain->n_reloads = n_reloads;
chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads)((struct reload *) __extension__ ({ struct obstack *__h = ((&
reload_obstack)); __extension__ ({ struct obstack *__o = (__h
); size_t __len = ((sizeof (struct reload) * (n_reloads))); if
 (__extension__ ({ struct obstack const *__o1 = (__o); (size_t
) (__o1->chunk_limit - __o1->next_free); }) < __len)
 _obstack_newchunk (__o, __len); ((void) ((__o)->next_free
 += (__len))); }); __extension__ ({ struct obstack *__o1 = (__h
); void *__value = (void *) __o1->object_base; if (__o1->
next_free == __value) __o1->maybe_empty_object = 1; __o1->
next_free = (sizeof (ptrdiff_t) < sizeof (void *) ? ((__o1
->object_base) + (((__o1->next_free) - (__o1->object_base
) + (__o1->alignment_mask)) & ~(__o1->alignment_mask
))) : (char *) (((ptrdiff_t) (__o1->next_free) + (__o1->
alignment_mask)) & ~(__o1->alignment_mask))); if ((size_t
) (__o1->next_free - (char *) __o1->chunk) > (size_t
) (__o1->chunk_limit - (char *) __o1->chunk)) __o1->
next_free = __o1->chunk_limit; __o1->object_base = __o1
->next_free; __value; }); }));
memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0)((char *) __extension__ ({ struct obstack *__h = ((&reload_obstack
)); __extension__ ({ struct obstack *__o = (__h); size_t __len
 = (((0))); if (__extension__ ({ struct obstack const *__o1 =
 (__o); (size_t) (__o1->chunk_limit - __o1->next_free);
 }) < __len) _obstack_newchunk (__o, __len); ((void) ((__o
)->next_free += (__len))); }); __extension__ ({ struct obstack
 *__o1 = (__h); void *__value = (void *) __o1->object_base
; if (__o1->next_free == __value) __o1->maybe_empty_object
 = 1; __o1->next_free = (sizeof (ptrdiff_t) < sizeof (void
 *) ? ((__o1->object_base) + (((__o1->next_free) - (__o1
->object_base) + (__o1->alignment_mask)) & ~(__o1->
alignment_mask))) : (char *) (((ptrdiff_t) (__o1->next_free
) + (__o1->alignment_mask)) & ~(__o1->alignment_mask
))); if ((size_t) (__o1->next_free - (char *) __o1->chunk
) > (size_t) (__o1->chunk_limit - (char *) __o1->chunk
)) __o1->next_free = __o1->chunk_limit; __o1->object_base
 = __o1->next_free; __value; }); }));
1418}

1420/* Walk the chain of insns, and determine for each whether it needs reloads
 and/or eliminations.  Build the corresponding insns_need_reload list, and
 set something_needs_elimination as appropriate.  */
1423static void
1424calculate_needs_all_insns (int global)
1425{
class insn_chain **pprev_reload = &insns_need_reload;
class insn_chain *chain, *next = 0;

something_needs_elimination = 0;

reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0)((char *) __extension__ ({ struct obstack *__h = ((&reload_obstack
)); __extension__ ({ struct obstack *__o = (__h); size_t __len
 = (((0))); if (__extension__ ({ struct obstack const *__o1 =
 (__o); (size_t) (__o1->chunk_limit - __o1->next_free);
 }) < __len) _obstack_newchunk (__o, __len); ((void) ((__o
)->next_free += (__len))); }); __extension__ ({ struct obstack
 *__o1 = (__h); void *__value = (void *) __o1->object_base
; if (__o1->next_free == __value) __o1->maybe_empty_object
 = 1; __o1->next_free = (sizeof (ptrdiff_t) < sizeof (void
 *) ? ((__o1->object_base) + (((__o1->next_free) - (__o1
->object_base) + (__o1->alignment_mask)) & ~(__o1->
alignment_mask))) : (char *) (((ptrdiff_t) (__o1->next_free
) + (__o1->alignment_mask)) & ~(__o1->alignment_mask
))); if ((size_t) (__o1->next_free - (char *) __o1->chunk
) > (size_t) (__o1->chunk_limit - (char *) __o1->chunk
)) __o1->next_free = __o1->chunk_limit; __o1->object_base
 = __o1->next_free; __value; }); }));
for (chain = reload_insn_chain; chain != 0; chain = next)
  {
    rtx_insn *insn = chain->insn;

    next = chain->next;

    /* Clear out the shortcuts.  */
    chain->n_reloads = 0;
    chain->need_elim = 0;
    chain->need_reload = 0;
    chain->need_operand_change = 0;

    /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
what effects this has on the known offsets at labels.  */

    if (LABEL_P (insn)(((enum rtx_code) (insn)->code) == CODE_LABEL) || JUMP_P (insn)(((enum rtx_code) (insn)->code) == JUMP_INSN) || JUMP_TABLE_DATA_P (insn)(((enum rtx_code) (insn)->code) == JUMP_TABLE_DATA)
 || (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)) && REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) != 0))
set_label_offsets (insn, insn, 0);

    if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
{
 rtx old_body = PATTERN (insn);
 int old_code = INSN_CODE (insn)(((insn)->u.fld[5]).rt_int);
 rtx old_notes = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx);
 int did_elimination = 0;
 int operands_changed = 0;

 /* Skip insns that only set an equivalence.  */
 if (will_delete_init_insn_p (insn))
   continue;

 /* If needed, eliminate any eliminable registers.  */
 if (num_eliminable || num_eliminable_invariants)
   did_elimination = eliminate_regs_in_insn (insn, 0);

 /* Analyze the instruction.  */
 operands_changed = find_reloads (insn, 0, spill_indirect_levels(this_target_reload->x_spill_indirect_levels),
			   global, spill_reg_order);

 /* If a no-op set needs more than one reload, this is likely
    to be something that needs input address reloads.  We
    can't get rid of this cleanly later, and it is of no use
    anyway, so discard it now.
    We only do this when expensive_optimizations is enabled,
    since this complements reload inheritance / output
    reload deletion, and it can make debugging harder.  */
 if (flag_expensive_optimizationsglobal_options.x_flag_expensive_optimizations && n_reloads > 1)
   {
     rtx set = single_set (insn);
     if (set
  &&
  ((SET_SRC (set)(((set)->u.fld[1]).rt_rtx) == SET_DEST (set)(((set)->u.fld[0]).rt_rtx)
    && REG_P (SET_SRC (set))(((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) ==
 REG)
    && REGNO (SET_SRC (set))(rhs_regno((((set)->u.fld[1]).rt_rtx))) >= FIRST_PSEUDO_REGISTER76)
   || (REG_P (SET_SRC (set))(((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) ==
 REG) && REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 REG)
       && reg_renumber[REGNO (SET_SRC (set))(rhs_regno((((set)->u.fld[1]).rt_rtx)))] < 0
       && reg_renumber[REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx)))] < 0
       && reg_equiv_memory_loc (REGNO (SET_SRC (set)))(*reg_equivs)[((rhs_regno((((set)->u.fld[1]).rt_rtx))))].memory_loc != NULLnullptr
       && reg_equiv_memory_loc (REGNO (SET_DEST (set)))(*reg_equivs)[((rhs_regno((((set)->u.fld[0]).rt_rtx))))].memory_loc != NULLnullptr
       && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set)))(*reg_equivs)[((rhs_regno((((set)->u.fld[1]).rt_rtx))))].memory_loc,
		       reg_equiv_memory_loc (REGNO (SET_DEST (set)))(*reg_equivs)[((rhs_regno((((set)->u.fld[0]).rt_rtx))))].memory_loc))))
{
  if (ira_conflicts_p)
    /* Inform IRA about the insn deletion.  */
    ira_mark_memory_move_deletion (REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx))),
				   REGNO (SET_SRC (set))(rhs_regno((((set)->u.fld[1]).rt_rtx))));
  delete_insn (insn);
  /* Delete it from the reload chain.  */
  if (chain->prev)
    chain->prev->next = next;
  else
    reload_insn_chain = next;
  if (next)
    next->prev = chain->prev;
  chain->next = unused_insn_chains;
  unused_insn_chains = chain;
  continue;
}
   }
 if (num_eliminable)
   update_eliminable_offsets ();

 /* Remember for later shortcuts which insns had any reloads or
    register eliminations.  */
 chain->need_elim = did_elimination;
 chain->need_reload = n_reloads > 0;
 chain->need_operand_change = operands_changed;

 /* Discard any register replacements done.  */
 if (did_elimination)
   {
     obstack_free (&reload_obstack, reload_insn_firstobj)__extension__ ({ struct obstack *__o = (&reload_obstack);
 void *__obj = (void *) (reload_insn_firstobj); if (__obj >
 (void *) __o->chunk && __obj < (void *) __o->
chunk_limit) __o->next_free = __o->object_base = (char *
) __obj; else _obstack_free (__o, __obj); });
     PATTERN (insn) = old_body;
     INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) = old_code;
     REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) = old_notes;
     something_needs_elimination = 1;
   }

 something_needs_operands_changed |= operands_changed;

 if (n_reloads != 0)
   {
     copy_reloads (chain);
     *pprev_reload = chain;
     pprev_reload = &chain->next_need_reload;
   }
}
  }
*pprev_reload = 0;
1542}
1543
1544/* This function is called from the register allocator to set up estimates
 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
 an invariant.  The structure is similar to calculate_needs_all_insns.  */

1548void
1549calculate_elim_costs_all_insns (void)
1550{
int *reg_equiv_init_cost;
basic_block bb;
int i;

reg_equiv_init_cost = XCNEWVEC (int, max_regno)((int *) xcalloc ((max_regno), sizeof (int)));
init_elim_table ();
init_eliminable_invariants (get_insns (), false);

set_initial_elim_offsets ();
set_initial_label_offsets ();

FOR_EACH_BB_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_entry_block_ptr->next_bb
; bb != ((cfun + 0))->cfg->x_exit_block_ptr; bb = bb->
next_bb)
  {
    rtx_insn *insn;
    elim_bb = bb;

    FOR_BB_INSNS (bb, insn)for ((insn) = (bb)->il.x.head_; (insn) && (insn) !=
 NEXT_INSN ((bb)->il.x.rtl->end_); (insn) = NEXT_INSN (
insn))
{
 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
    include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
    what effects this has on the known offsets at labels.  */

 if (LABEL_P (insn)(((enum rtx_code) (insn)->code) == CODE_LABEL) || JUMP_P (insn)(((enum rtx_code) (insn)->code) == JUMP_INSN) || JUMP_TABLE_DATA_P (insn)(((enum rtx_code) (insn)->code) == JUMP_TABLE_DATA)
     || (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)) && REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) != 0))
   set_label_offsets (insn, insn, 0);

 if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
   {
     rtx set = single_set (insn);

     /* Skip insns that only set an equivalence.  */
     if (set && REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 REG)
  && reg_renumber[REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx)))] < 0
  && (reg_equiv_constant (REGNO (SET_DEST (set)))(*reg_equivs)[((rhs_regno((((set)->u.fld[0]).rt_rtx))))].constant
      || reg_equiv_invariant (REGNO (SET_DEST (set)))(*reg_equivs)[((rhs_regno((((set)->u.fld[0]).rt_rtx))))].invariant))
{
  unsigned regno = REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx)));
  rtx_insn_list *init = reg_equiv_init (regno)(*reg_equivs)[(regno)].init;
  if (init)
    {
      rtx t = eliminate_regs_1 (SET_SRC (set)(((set)->u.fld[1]).rt_rtx), VOIDmode((void) 0, E_VOIDmode), insn,
				false, true);
      machine_mode mode = GET_MODE (SET_DEST (set))((machine_mode) ((((set)->u.fld[0]).rt_rtx))->mode);
      int cost = set_src_cost (t, mode,
			       optimize_bb_for_speed_p (bb));
      int freq = REG_FREQ_FROM_BB (bb)((optimize_function_for_size_p ((cfun + 0)) || !(cfun + 0)->
cfg->count_max.initialized_p ()) ? 1000 : ((bb)->count.
to_frequency ((cfun + 0)) * 1000 / 10000) ? ((bb)->count.to_frequency
 ((cfun + 0)) * 1000 / 10000) : 1);

      reg_equiv_init_cost[regno] = cost * freq;
      continue;
    }
}
     /* If needed, eliminate any eliminable registers.  */
     if (num_eliminable || num_eliminable_invariants)
elimination_costs_in_insn (insn);

     if (num_eliminable)
update_eliminable_offsets ();
   }
}
  }
for (i = FIRST_PSEUDO_REGISTER76; i < max_regno; i++)
  {
    if (reg_equiv_invariant (i)(*reg_equivs)[(i)].invariant)
{
 if (reg_equiv_init (i)(*reg_equivs)[(i)].init)
   {
     int cost = reg_equiv_init_cost[i];
     if (dump_file)
fprintf (dump_file,
	 "Reg %d has equivalence, initial gains %d\n", i, cost);
     if (cost != 0)
ira_adjust_equiv_reg_cost (i, cost);
   }
 else
   {
     if (dump_file)
fprintf (dump_file,
	 "Reg %d had equivalence, but can't be eliminated\n",
	 i);
     ira_adjust_equiv_reg_cost (i, 0);
   }
}
  }

free (reg_equiv_init_cost);
free (offsets_known_at);
free (offsets_at);
offsets_at = NULLnullptr;
offsets_known_at = NULLnullptr;
1640}
1641
1642/* Comparison function for qsort to decide which of two reloads
 should be handled first.  *P1 and *P2 are the reload numbers.  */

1645static int
1646reload_reg_class_lower (const void *r1p, const void *r2p)
1647{
int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
int t;

/* Consider required reloads before optional ones.  */
t = rld[r1].optional - rld[r2].optional;
if (t != 0)
  return t;

/* Count all solitary classes before non-solitary ones.  */
t = ((reg_class_size(this_target_hard_regs->x_reg_class_size)[(int) rld[r2].rclass] == 1)
     - (reg_class_size(this_target_hard_regs->x_reg_class_size)[(int) rld[r1].rclass] == 1));
if (t != 0)
  return t;

/* Aside from solitaires, consider all multi-reg groups first.  */
t = rld[r2].nregs - rld[r1].nregs;
if (t != 0)
  return t;

/* Consider reloads in order of increasing reg-class number.  */
t = (int) rld[r1].rclass - (int) rld[r2].rclass;
if (t != 0)
  return t;

/* If reloads are equally urgent, sort by reload number,
   so that the results of qsort leave nothing to chance.  */
return r1 - r2;
1675}
1676
1677/* The cost of spilling each hard reg.  */
1678static int spill_cost[FIRST_PSEUDO_REGISTER76];

1680/* When spilling multiple hard registers, we use SPILL_COST for the first
 spilled hard reg and SPILL_ADD_COST for subsequent regs.  SPILL_ADD_COST
 only the first hard reg for a multi-reg pseudo.  */
1683static int spill_add_cost[FIRST_PSEUDO_REGISTER76];

1685/* Map of hard regno to pseudo regno currently occupying the hard
 reg.  */
1687static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER76];

1689/* Update the spill cost arrays, considering that pseudo REG is live.  */

1691static void
1692count_pseudo (int reg)
1693{
int freq = REG_FREQ (reg)(reg_info_p[reg].freq);
int r = reg_renumber[reg];
int nregs;

/* Ignore spilled pseudo-registers which can be here only if IRA is used.  */
if (ira_conflicts_p && r < 0)
  return;

if (REGNO_REG_SET_P (&pseudos_counted, reg)bitmap_bit_p (&pseudos_counted, reg)
    || REGNO_REG_SET_P (&spilled_pseudos, reg)bitmap_bit_p (&spilled_pseudos, reg))
  return;

SET_REGNO_REG_SET (&pseudos_counted, reg)bitmap_set_bit (&pseudos_counted, reg);

gcc_assert (r >= 0)((void)(!(r >= 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1708, __FUNCTION__), 0 : 0));

spill_add_cost[r] += freq;
nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg)((machine_mode) (regno_reg_rtx[reg])->mode));
while (nregs-- > 0)
  {
    hard_regno_to_pseudo_regno[r + nregs] = reg;
    spill_cost[r + nregs] += freq;
  }
1717}

1719/* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
 contents of BAD_SPILL_REGS for the insn described by CHAIN.  */

1722static void
1723order_regs_for_reload (class insn_chain *chain)
1724{
unsigned i;
HARD_REG_SET used_by_pseudos;
HARD_REG_SET used_by_pseudos2;
reg_set_iterator rsi;

bad_spill_regs = fixed_reg_set(this_target_hard_regs->x_fixed_reg_set);

memset (spill_cost, 0, sizeof spill_cost);
memset (spill_add_cost, 0, sizeof spill_add_cost);
for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
  hard_regno_to_pseudo_regno[i] = -1;

/* Count number of uses of each hard reg by pseudo regs allocated to it
   and then order them by decreasing use.  First exclude hard registers
   that are live in or across this insn.  */

REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout)do { CLEAR_HARD_REG_SET (used_by_pseudos); reg_set_to_hard_reg_set
 (&used_by_pseudos, &chain->live_throughout); } while
 (0);
REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set)do { CLEAR_HARD_REG_SET (used_by_pseudos2); reg_set_to_hard_reg_set
 (&used_by_pseudos2, &chain->dead_or_set); } while
 (0);
bad_spill_regs |= used_by_pseudos;
bad_spill_regs |= used_by_pseudos2;

/* Now find out which pseudos are allocated to it, and update
   hard_reg_n_uses.  */
CLEAR_REG_SET (&pseudos_counted)bitmap_clear (&pseudos_counted);

EXECUTE_IF_SET_IN_REG_SETfor (bmp_iter_set_init (&(rsi), (&chain->live_throughout
), (76), &(i)); bmp_iter_set (&(rsi), &(i)); bmp_iter_next
 (&(rsi), &(i)))
  (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)for (bmp_iter_set_init (&(rsi), (&chain->live_throughout
), (76), &(i)); bmp_iter_set (&(rsi), &(i)); bmp_iter_next
 (&(rsi), &(i)))
  {
    count_pseudo (i);
  }
EXECUTE_IF_SET_IN_REG_SETfor (bmp_iter_set_init (&(rsi), (&chain->dead_or_set
), (76), &(i)); bmp_iter_set (&(rsi), &(i)); bmp_iter_next
 (&(rsi), &(i)))
  (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)for (bmp_iter_set_init (&(rsi), (&chain->dead_or_set
), (76), &(i)); bmp_iter_set (&(rsi), &(i)); bmp_iter_next
 (&(rsi), &(i)))
  {
    count_pseudo (i);
  }
CLEAR_REG_SET (&pseudos_counted)bitmap_clear (&pseudos_counted);
1761}
1762
1763/* Vector of reload-numbers showing the order in which the reloads should
 be processed.  */
1765static short reload_order[MAX_RELOADS(2 * 30 * (2 + 1))];

1767/* This is used to keep track of the spill regs used in one insn.  */
1768static HARD_REG_SET used_spill_regs_local;

1770/* We decided to spill hard register SPILLED, which has a size of
 SPILLED_NREGS.  Determine how pseudo REG, which is live during the insn,
 is affected.  We will add it to SPILLED_PSEUDOS if necessary, and we will
 update SPILL_COST/SPILL_ADD_COST.  */

1775static void
1776count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1777{
int freq = REG_FREQ (reg)(reg_info_p[reg].freq);
int r = reg_renumber[reg];
int nregs;

/* Ignore spilled pseudo-registers which can be here only if IRA is used.  */
if (ira_conflicts_p && r < 0)
  return;

gcc_assert (r >= 0)((void)(!(r >= 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1786, __FUNCTION__), 0 : 0));

nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg)((machine_mode) (regno_reg_rtx[reg])->mode));

if (REGNO_REG_SET_P (&spilled_pseudos, reg)bitmap_bit_p (&spilled_pseudos, reg)
    || spilled + spilled_nregs <= r || r + nregs <= spilled)
  return;

SET_REGNO_REG_SET (&spilled_pseudos, reg)bitmap_set_bit (&spilled_pseudos, reg);

spill_add_cost[r] -= freq;
while (nregs-- > 0)
  {
    hard_regno_to_pseudo_regno[r + nregs] = -1;
    spill_cost[r + nregs] -= freq;
  }
1802}

1804/* Find reload register to use for reload number ORDER.  */

1806static int
1807find_reg (class insn_chain *chain, int order)
1808{
int rnum = reload_order[order];
struct reload *rl = rld + rnum;
int best_cost = INT_MAX2147483647;
int best_reg = -1;
unsigned int i, j, n;
int k;
HARD_REG_SET not_usable;
HARD_REG_SET used_by_other_reload;
reg_set_iterator rsi;
static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER76];
static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER76];

not_usable = (bad_spill_regs
| bad_spill_regs_global
| ~reg_class_contents(this_target_hard_regs->x_reg_class_contents)[rl->rclass]);

CLEAR_HARD_REG_SET (used_by_other_reload);
for (k = 0; k < order; k++)
  {
    int other = reload_order[k];

    if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
for (j = 0; j < rld[other].nregs; j++)
 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
  }

for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
  {
1837#ifdef REG_ALLOC_ORDER{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17
, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48
, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 }
    unsigned int regno = reg_alloc_order(this_target_hard_regs->x_reg_alloc_order)[i];
1839#else
    unsigned int regno = i;
1841#endif

    if (! TEST_HARD_REG_BIT (not_usable, regno)
 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
 && targetm.hard_regno_mode_ok (regno, rl->mode))
{
 int this_cost = spill_cost[regno];
 int ok = 1;
 unsigned int this_nregs = hard_regno_nregs (regno, rl->mode);

 for (j = 1; j < this_nregs; j++)
   {
     this_cost += spill_add_cost[regno + j];
     if ((TEST_HARD_REG_BIT (not_usable, regno + j))
  || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
ok = 0;
   }
 if (! ok)
   continue;

 if (ira_conflicts_p)
   {
     /* Ask IRA to find a better pseudo-register for
 spilling.  */
     for (n = j = 0; j < this_nregs; j++)
{
  int r = hard_regno_to_pseudo_regno[regno + j];

  if (r < 0)
    continue;
  if (n == 0 || regno_pseudo_regs[n - 1] != r)
    regno_pseudo_regs[n++] = r;
}
     regno_pseudo_regs[n++] = -1;
     if (best_reg < 0
  || ira_better_spill_reload_regno_p (regno_pseudo_regs,
				      best_regno_pseudo_regs,
				      rl->in, rl->out,
				      chain->insn))
{
  best_reg = regno;
  for (j = 0;; j++)
    {
      best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
      if (regno_pseudo_regs[j] < 0)
	break;
    }
}
     continue;
   }

 if (rl->in && REG_P (rl->in)(((enum rtx_code) (rl->in)->code) == REG) && REGNO (rl->in)(rhs_regno(rl->in)) == regno)
   this_cost--;
 if (rl->out && REG_P (rl->out)(((enum rtx_code) (rl->out)->code) == REG) && REGNO (rl->out)(rhs_regno(rl->out)) == regno)
   this_cost--;
 if (this_cost < best_cost
     /* Among registers with equal cost, prefer caller-saved ones, or
 use REG_ALLOC_ORDER if it is defined.  */
     || (this_cost == best_cost
1900#ifdef REG_ALLOC_ORDER{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17
, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48
, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 }
  && (inv_reg_alloc_order(this_target_hard_regs->x_inv_reg_alloc_order)[regno]
      < inv_reg_alloc_order(this_target_hard_regs->x_inv_reg_alloc_order)[best_reg])
1903#else
  && crtl(&x_rtl)->abi->clobbers_full_reg_p (regno)
  && !crtl(&x_rtl)->abi->clobbers_full_reg_p (best_reg)
1906#endif
  ))
   {
     best_reg = regno;
     best_cost = this_cost;
   }
}
  }
if (best_reg == -1)
  return 0;

if (dump_file)
  fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);

rl->nregs = hard_regno_nregs (best_reg, rl->mode);
rl->regno = best_reg;

EXECUTE_IF_SET_IN_REG_SETfor (bmp_iter_set_init (&(rsi), (&chain->live_throughout
), (76), &(j)); bmp_iter_set (&(rsi), &(j)); bmp_iter_next
 (&(rsi), &(j)))
  (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)for (bmp_iter_set_init (&(rsi), (&chain->live_throughout
), (76), &(j)); bmp_iter_set (&(rsi), &(j)); bmp_iter_next
 (&(rsi), &(j)))
  {
    count_spilled_pseudo (best_reg, rl->nregs, j);
  }

EXECUTE_IF_SET_IN_REG_SETfor (bmp_iter_set_init (&(rsi), (&chain->dead_or_set
), (76), &(j)); bmp_iter_set (&(rsi), &(j)); bmp_iter_next
 (&(rsi), &(j)))
  (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)for (bmp_iter_set_init (&(rsi), (&chain->dead_or_set
), (76), &(j)); bmp_iter_set (&(rsi), &(j)); bmp_iter_next
 (&(rsi), &(j)))
  {
    count_spilled_pseudo (best_reg, rl->nregs, j);
  }

for (i = 0; i < rl->nregs; i++)
  {
    gcc_assert (spill_cost[best_reg + i] == 0)((void)(!(spill_cost[best_reg + i] == 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1937, __FUNCTION__), 0 : 0));
    gcc_assert (spill_add_cost[best_reg + i] == 0)((void)(!(spill_add_cost[best_reg + i] == 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1938, __FUNCTION__), 0 : 0));
    gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1)((void)(!(hard_regno_to_pseudo_regno[best_reg + i] == -1) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 1939, __FUNCTION__), 0 : 0));
    SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
  }
return 1;
1943}

1945/* Find more reload regs to satisfy the remaining need of an insn, which
 is given by CHAIN.
 Do it by ascending class number, since otherwise a reg
 might be spilled for a big class and might fail to count
 for a smaller class even though it belongs to that class.  */

1951static void
1952find_reload_regs (class insn_chain *chain)
1953{
int i;

/* In order to be certain of getting the registers we need,
   we must sort the reloads into order of increasing register class.
   Then our grabbing of reload registers will parallel the process
   that provided the reload registers.  */
for (i = 0; i < chain->n_reloads; i++)
  {
    /* Show whether this reload already has a hard reg.  */
    if (chain->rld[i].reg_rtx)
{
 chain->rld[i].regno = REGNO (chain->rld[i].reg_rtx)(rhs_regno(chain->rld[i].reg_rtx));
 chain->rld[i].nregs = REG_NREGS (chain->rld[i].reg_rtx)((&(chain->rld[i].reg_rtx)->u.reg)->nregs);
}
    else
chain->rld[i].regno = -1;
    reload_order[i] = i;
  }

n_reloads = chain->n_reloads;
memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));

CLEAR_HARD_REG_SET (used_spill_regs_local);

if (dump_file)
  fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));

qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower)gcc_qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower
);

/* Compute the order of preference for hard registers to spill.  */

order_regs_for_reload (chain);

for (i = 0; i < n_reloads; i++)
  {
    int r = reload_order[i];

    /* Ignore reloads that got marked inoperative.  */
    if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
 && ! rld[r].optional
 && rld[r].regno == -1)
if (! find_reg (chain, i))
 {
   if (dump_file)
     fprintf (dump_file, "reload failure for reload %d\n", r);
   spill_failure (chain->insn, rld[r].rclass);
   failure = 1;
   return;
 }
  }

chain->used_spill_regs = used_spill_regs_local;
used_spill_regs |= used_spill_regs_local;

memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2009}

2011static void
2012select_reload_regs (void)
2013{
class insn_chain *chain;

/* Try to satisfy the needs for each insn.  */
for (chain = insns_need_reload; chain != 0;
     chain = chain->next_need_reload)
  find_reload_regs (chain);
2020}
2021
2022/* Delete all insns that were inserted by emit_caller_save_insns during
 this iteration.  */
2024static void
2025delete_caller_save_insns (void)
2026{
class insn_chain *c = reload_insn_chain;

while (c != 0)
  {
    while (c != 0 && c->is_caller_save_insn)
{
 class insn_chain *next = c->next;
 rtx_insn *insn = c->insn;

 if (c == reload_insn_chain)
   reload_insn_chain = next;
 delete_insn (insn);

 if (next)
   next->prev = c->prev;
 if (c->prev)
   c->prev->next = next;
 c->next = unused_insn_chains;
 unused_insn_chains = c;
 c = next;
}
    if (c != 0)
c = c->next;
  }
2051}
2052
2053/* Handle the failure to find a register to spill.
 INSN should be one of the insns which needed this particular spill reg.  */

2056static void
2057spill_failure (rtx_insn *insn, enum reg_class rclass)
2058{
if (asm_noperands (PATTERN (insn)) >= 0)
  error_for_asm (insn, "cannot find a register in class %qs while "
   "reloading %<asm%>",
   reg_class_names[rclass]);
else
  {
    error ("unable to find a register to spill in class %qs",
    reg_class_names[rclass]);

    if (dump_file)
{
 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
 debug_reload_to_stream (dump_file);
}
    fatal_insn ("this is the insn:", insn)_fatal_insn ("this is the insn:", insn, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 2073, __FUNCTION__);
  }
2075}
2076
2077/* Delete an unneeded INSN and any previous insns who sole purpose is loading
 data that is dead in INSN.  */

2080static void
2081delete_dead_insn (rtx_insn *insn)
2082{
rtx_insn *prev = prev_active_insn (insn);
rtx prev_dest;

/* If the previous insn sets a register that dies in our insn make
   a note that we want to run DCE immediately after reload.

   We used to delete the previous insn & recurse, but that's wrong for
   block local equivalences.  Instead of trying to figure out the exact
   circumstances where we can delete the potentially dead insns, just
   let DCE do the job.  */
if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
    && GET_CODE (PATTERN (prev))((enum rtx_code) (PATTERN (prev))->code) == SET
    && (prev_dest = SET_DEST (PATTERN (prev))(((PATTERN (prev))->u.fld[0]).rt_rtx), REG_P (prev_dest)(((enum rtx_code) (prev_dest)->code) == REG))
    && reg_mentioned_p (prev_dest, PATTERN (insn))
    && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)(rhs_regno(prev_dest)))
    && ! side_effects_p (SET_SRC (PATTERN (prev))(((PATTERN (prev))->u.fld[1]).rt_rtx)))
  need_dce = 1;

SET_INSN_DELETED (insn)set_insn_deleted (insn);;
2102}

2104/* Modify the home of pseudo-reg I.
 The new home is present in reg_renumber[I].

 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
 or it may be -1, meaning there is none or it is not relevant.
 This is used so that all pseudos spilled from a given hard reg
 can share one stack slot.  */

2112static void
2113alter_reg (int i, int from_reg, bool dont_share_p)
2114{
/* When outputting an inline function, this can happen
   for a reg that isn't actually used.  */
if (regno_reg_rtx[i] == 0)
  return;

/* If the reg got changed to a MEM at rtl-generation time,
   ignore it.  */
if (!REG_P (regno_reg_rtx[i])(((enum rtx_code) (regno_reg_rtx[i])->code) == REG))
  return;

/* Modify the reg-rtx to contain the new hard reg
   number or else to contain its pseudo reg number.  */
SET_REGNO (regno_reg_rtx[i],(df_ref_change_reg_with_loc (regno_reg_rtx[i], reg_renumber[i
] >= 0 ? reg_renumber[i] : i))
    reg_renumber[i] >= 0 ? reg_renumber[i] : i)(df_ref_change_reg_with_loc (regno_reg_rtx[i], reg_renumber[i
] >= 0 ? reg_renumber[i] : i));

/* If we have a pseudo that is needed but has no hard reg or equivalent,
   allocate a stack slot for it.  */

if (reg_renumber[i] < 0
    && REG_N_REFS (i) > 0
    && reg_equiv_constant (i)(*reg_equivs)[(i)].constant == 0
    && (reg_equiv_invariant (i)(*reg_equivs)[(i)].invariant == 0
 || reg_equiv_init (i)(*reg_equivs)[(i)].init == 0)
    && reg_equiv_memory_loc (i)(*reg_equivs)[(i)].memory_loc == 0)
  {
    rtx x = NULL_RTX(rtx) 0;
    machine_mode mode = GET_MODE (regno_reg_rtx[i])((machine_mode) (regno_reg_rtx[i])->mode);
    poly_uint64 inherent_size = GET_MODE_SIZE (mode);
    unsigned int inherent_align = GET_MODE_ALIGNMENT (mode)get_mode_alignment (mode);
    machine_mode wider_mode = wider_subreg_mode (mode, reg_max_ref_mode[i]);
    poly_uint64 total_size = GET_MODE_SIZE (wider_mode);
    /* ??? Seems strange to derive the minimum alignment from the size,
but that's the traditional behavior.  For polynomial-size modes,
the natural extension is to use the minimum possible size.  */
    unsigned int min_align
= constant_lower_bound (GET_MODE_BITSIZE (reg_max_ref_mode[i]));
    poly_int64 adjust = 0;

    something_was_spilled = true;

    if (ira_conflicts_p)
{
 /* Mark the spill for IRA.  */
 SET_REGNO_REG_SET (&spilled_pseudos, i)bitmap_set_bit (&spilled_pseudos, i);
 if (!dont_share_p)
   x = ira_reuse_stack_slot (i, inherent_size, total_size);
}

    if (x)
;

    /* Each pseudo reg has an inherent size which comes from its own mode,
and a total size which provides room for paradoxical subregs
which refer to the pseudo reg in wider modes.

We can use a slot already allocated if it provides both
enough inherent space and enough total space.
Otherwise, we allocate a new slot, making sure that it has no less
inherent space, and no less total space, then the previous slot.  */
    else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
{
 rtx stack_slot;

 /* The sizes are taken from a subreg operation, which guarantees
    that they're ordered.  */
 gcc_checking_assert (ordered_p (total_size, inherent_size))((void)(!(ordered_p (total_size, inherent_size)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 2180, __FUNCTION__), 0 : 0));

 /* No known place to spill from => no slot to reuse.  */
 x = assign_stack_local (mode, total_size,
		  min_align > inherent_align
		  || maybe_gt (total_size, inherent_size)maybe_lt (inherent_size, total_size)
		  ? -1 : 0);

 stack_slot = x;

 /* Cancel the big-endian correction done in assign_stack_local.
    Get the address of the beginning of the slot.  This is so we
    can do a big-endian correction unconditionally below.  */
 if (BYTES_BIG_ENDIAN0)
   {
     adjust = inherent_size - total_size;
     if (maybe_ne (adjust, 0))
{
  poly_uint64 total_bits = total_size * BITS_PER_UNIT(8);
  machine_mode mem_mode
    = int_mode_for_size (total_bits, 1).else_blk ();
  stack_slot = adjust_address_nv (x, mem_mode, adjust)adjust_address_1 (x, mem_mode, adjust, 0, 1, 0, 0);
}
   }

 if (! dont_share_p && ira_conflicts_p)
   /* Inform IRA about allocation a new stack slot.  */
   ira_mark_new_stack_slot (stack_slot, i, total_size);
}

    /* Reuse a stack slot if possible.  */
    else if (spill_stack_slot[from_reg] != 0
      && known_ge (spill_stack_slot_width[from_reg], total_size)(!maybe_lt (spill_stack_slot_width[from_reg], total_size))
      && known_ge (GET_MODE_SIZE(!maybe_lt (GET_MODE_SIZE (((machine_mode) (spill_stack_slot[
from_reg])->mode)), inherent_size))
	    (GET_MODE (spill_stack_slot[from_reg])),(!maybe_lt (GET_MODE_SIZE (((machine_mode) (spill_stack_slot[
from_reg])->mode)), inherent_size))
	    inherent_size)(!maybe_lt (GET_MODE_SIZE (((machine_mode) (spill_stack_slot[
from_reg])->mode)), inherent_size))
      && MEM_ALIGN (spill_stack_slot[from_reg])(get_mem_attrs (spill_stack_slot[from_reg])->align) >= min_align)
x = spill_stack_slot[from_reg];

    /* Allocate a bigger slot.  */
    else
{
 /* Compute maximum size needed, both for inherent size
    and for total size.  */
 rtx stack_slot;

 if (spill_stack_slot[from_reg])
   {
     if (partial_subreg_p (mode,
		    GET_MODE (spill_stack_slot[from_reg])((machine_mode) (spill_stack_slot[from_reg])->mode)))
mode = GET_MODE (spill_stack_slot[from_reg])((machine_mode) (spill_stack_slot[from_reg])->mode);
     total_size = ordered_max (total_size,
			spill_stack_slot_width[from_reg]);
     if (MEM_ALIGN (spill_stack_slot[from_reg])(get_mem_attrs (spill_stack_slot[from_reg])->align) > min_align)
min_align = MEM_ALIGN (spill_stack_slot[from_reg])(get_mem_attrs (spill_stack_slot[from_reg])->align);
   }

 /* The sizes are taken from a subreg operation, which guarantees
    that they're ordered.  */
 gcc_checking_assert (ordered_p (total_size, inherent_size))((void)(!(ordered_p (total_size, inherent_size)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 2239, __FUNCTION__), 0 : 0));

 /* Make a slot with that size.  */
 x = assign_stack_local (mode, total_size,
		  min_align > inherent_align
		  || maybe_gt (total_size, inherent_size)maybe_lt (inherent_size, total_size)
		  ? -1 : 0);
 stack_slot = x;

 /* Cancel the  big-endian correction done in assign_stack_local.
    Get the address of the beginning of the slot.  This is so we
    can do a big-endian correction unconditionally below.  */
 if (BYTES_BIG_ENDIAN0)
   {
     adjust = GET_MODE_SIZE (mode) - total_size;
     if (maybe_ne (adjust, 0))
{
  poly_uint64 total_bits = total_size * BITS_PER_UNIT(8);
  machine_mode mem_mode
    = int_mode_for_size (total_bits, 1).else_blk ();
  stack_slot = adjust_address_nv (x, mem_mode, adjust)adjust_address_1 (x, mem_mode, adjust, 0, 1, 0, 0);
}
   }

 spill_stack_slot[from_reg] = stack_slot;
 spill_stack_slot_width[from_reg] = total_size;
}

    /* On a big endian machine, the "address" of the slot
is the address of the low part that fits its inherent mode.  */
    adjust += subreg_size_lowpart_offset (inherent_size, total_size);

    /* If we have any adjustment to make, or if the stack slot is the
wrong mode, make a new stack slot.  */
    x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust)adjust_address_1 (x, ((machine_mode) (regno_reg_rtx[i])->mode
), adjust, 0, 1, 0, 0);

    /* Set all of the memory attributes as appropriate for a spill.  */
    set_mem_attrs_for_spill (x);

    /* Save the stack slot for later.  */
    reg_equiv_memory_loc (i)(*reg_equivs)[(i)].memory_loc = x;
  }
2281}

2283/* Mark the slots in regs_ever_live for the hard regs used by
 pseudo-reg number REGNO, accessed in MODE.  */

2286static void
2287mark_home_live_1 (int regno, machine_mode mode)
2288{
int i, lim;

i = reg_renumber[regno];
if (i < 0)
  return;
lim = end_hard_regno (mode, i);
while (i < lim)
  df_set_regs_ever_live (i++, true);
2297}

2299/* Mark the slots in regs_ever_live for the hard regs
 used by pseudo-reg number REGNO.  */

2302void
2303mark_home_live (int regno)
2304{
if (reg_renumber[regno] >= 0)
  mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno)((machine_mode) (regno_reg_rtx[regno])->mode));
2307}
2308
2309/* This function handles the tracking of elimination offsets around branches.

 X is a piece of RTL being scanned.

 INSN is the insn that it came from, if any.

 INITIAL_P is nonzero if we are to set the offset to be the initial
 offset and zero if we are setting the offset of the label to be the
 current offset.  */

2319static void
2320set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
2321{
enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
rtx tem;
unsigned int i;
struct elim_table *p;

switch (code)
  {
  case LABEL_REF:
    if (LABEL_REF_NONLOCAL_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != LABEL_REF) rtl_check_failed_flag
 ("LABEL_REF_NONLOCAL_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 2330, __FUNCTION__); _rtx; })->volatil))
return;

    x = label_ref_label (x);

    /* fall through */

  case CODE_LABEL:
    /* If we know nothing about this label, set the desired offsets.  Note
that this sets the offset at a label to be the offset before a label
if we don't know anything about the label.  This is not correct for
the label after a BARRIER, but is the best guess we can make.  If
we guessed wrong, we will suppress an elimination that might have
been possible had we been able to guess correctly.  */

    if (! offsets_known_at[CODE_LABEL_NUMBER (x)(((x)->u.fld[5]).rt_int) - first_label_num])
{
 for (i = 0; i < NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0])); i++)
   offsets_at[CODE_LABEL_NUMBER (x)(((x)->u.fld[5]).rt_int) - first_label_num][i]
     = (initial_p ? reg_eliminate[i].initial_offset
 : reg_eliminate[i].offset);
 offsets_known_at[CODE_LABEL_NUMBER (x)(((x)->u.fld[5]).rt_int) - first_label_num] = 1;
}

    /* Otherwise, if this is the definition of a label and it is
preceded by a BARRIER, set our offsets to the known offset of
that label.  */

    else if (x == insn
      && (tem = prev_nonnote_insn (insn)) != 0
      && BARRIER_P (tem)(((enum rtx_code) (tem)->code) == BARRIER))
set_offsets_for_label (insn);
    else
/* If neither of the above cases is true, compare each offset
  with those previously recorded and suppress any eliminations
  where the offsets disagree.  */

for (i = 0; i < NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0])); i++)
 if (maybe_ne (offsets_at[CODE_LABEL_NUMBER (x)(((x)->u.fld[5]).rt_int) - first_label_num][i],
	(initial_p ? reg_eliminate[i].initial_offset
	 : reg_eliminate[i].offset)))
   reg_eliminate[i].can_eliminate = 0;

    return;

  case JUMP_TABLE_DATA:
    set_label_offsets (PATTERN (insn), insn, initial_p);
    return;

  case JUMP_INSN:
    set_label_offsets (PATTERN (insn), insn, initial_p);

    /* fall through */

  case INSN:
  case CALL_INSN:
    /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
to indirectly and hence must have all eliminations at their
initial offsets.  */
    for (tem = REG_NOTES (x)(((x)->u.fld[6]).rt_rtx); tem; tem = XEXP (tem, 1)(((tem)->u.fld[1]).rt_rtx))
if (REG_NOTE_KIND (tem)((enum reg_note) ((machine_mode) (tem)->mode)) == REG_LABEL_OPERAND)
 set_label_offsets (XEXP (tem, 0)(((tem)->u.fld[0]).rt_rtx), insn, 1);
    return;

  case PARALLEL:
  case ADDR_VEC:
  case ADDR_DIFF_VEC:
    /* Each of the labels in the parallel or address vector must be
at their initial offsets.  We want the first field for PARALLEL
and ADDR_VEC and the second field for ADDR_DIFF_VEC.  */

    for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC)(((((x)->u.fld[code == ADDR_DIFF_VEC]).rt_rtvec))->num_elem
); i++)
set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i)(((((x)->u.fld[code == ADDR_DIFF_VEC]).rt_rtvec))->elem
[i]),
	   insn, initial_p);
    return;

  case SET:
    /* We only care about setting PC.  If the source is not RETURN,
IF_THEN_ELSE, or a label, disable any eliminations not at
their initial offsets.  Similarly if any arm of the IF_THEN_ELSE
isn't one of those possibilities.  For branches to a label,
call ourselves recursively.

Note that this can disable elimination unnecessarily when we have
a non-local goto since it will look like a non-constant jump to
someplace in the current function.  This isn't a significant
problem since such jumps will normally be when all elimination
pairs are back to their initial offsets.  */

    if (SET_DEST (x)(((x)->u.fld[0]).rt_rtx) != pc_rtx)
return;

    switch (GET_CODE (SET_SRC (x))((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code))
{
case PC:
case RETURN:
 return;

case LABEL_REF:
 set_label_offsets (SET_SRC (x)(((x)->u.fld[1]).rt_rtx), insn, initial_p);
 return;

case IF_THEN_ELSE:
 tem = XEXP (SET_SRC (x), 1)((((((x)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx);
 if (GET_CODE (tem)((enum rtx_code) (tem)->code) == LABEL_REF)
   set_label_offsets (label_ref_label (tem), insn, initial_p);
 else if (GET_CODE (tem)((enum rtx_code) (tem)->code) != PC && GET_CODE (tem)((enum rtx_code) (tem)->code) != RETURN)
   break;

 tem = XEXP (SET_SRC (x), 2)((((((x)->u.fld[1]).rt_rtx))->u.fld[2]).rt_rtx);
 if (GET_CODE (tem)((enum rtx_code) (tem)->code) == LABEL_REF)
   set_label_offsets (label_ref_label (tem), insn, initial_p);
 else if (GET_CODE (tem)((enum rtx_code) (tem)->code) != PC && GET_CODE (tem)((enum rtx_code) (tem)->code) != RETURN)
   break;
 return;

default:
 break;
}

    /* If we reach here, all eliminations must be at their initial
offset because we are doing a jump to a variable address.  */
    for (p = reg_eliminate; p < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; p++)
if (maybe_ne (p->offset, p->initial_offset))
 p->can_eliminate = 0;
    break;

  default:
    break;
  }
2460}
2461
2462/* This function examines every reg that occurs in X and adjusts the
 costs for its elimination which are gathered by IRA.  INSN is the
 insn in which X occurs.  We do not recurse into MEM expressions.  */

2466static void
2467note_reg_elim_costly (const_rtx x, rtx insn)
2468{
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, NONCONST)for (subrtx_iterator iter (array, x, rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
  {
    const_rtx x = *iter;
    if (MEM_P (x)(((enum rtx_code) (x)->code) == MEM))
iter.skip_subrtxes ();
    else if (REG_P (x)(((enum rtx_code) (x)->code) == REG)
      && REGNO (x)(rhs_regno(x)) >= FIRST_PSEUDO_REGISTER76
      && reg_equiv_init (REGNO (x))(*reg_equivs)[((rhs_regno(x)))].init
      && reg_equiv_invariant (REGNO (x))(*reg_equivs)[((rhs_regno(x)))].invariant)
{
 rtx t = reg_equiv_invariant (REGNO (x))(*reg_equivs)[((rhs_regno(x)))].invariant;
 rtx new_rtx = eliminate_regs_1 (t, Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), insn, true, true);
 int cost = set_src_cost (new_rtx, Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))),
		   optimize_bb_for_speed_p (elim_bb));
 int freq = REG_FREQ_FROM_BB (elim_bb)((optimize_function_for_size_p ((cfun + 0)) || !(cfun + 0)->
cfg->count_max.initialized_p ()) ? 1000 : ((elim_bb)->count
.to_frequency ((cfun + 0)) * 1000 / 10000) ? ((elim_bb)->count
.to_frequency ((cfun + 0)) * 1000 / 10000) : 1);

 if (cost != 0)
   ira_adjust_equiv_reg_cost (REGNO (x)(rhs_regno(x)), -cost * freq);
}
  }
2490}

2492/* Scan X and replace any eliminable registers (such as fp) with a
 replacement (such as sp), plus an offset.

 MEM_MODE is the mode of an enclosing MEM.  We need this to know how
 much to adjust a register for, e.g., PRE_DEC.  Also, if we are inside a
 MEM, we are allowed to replace a sum of a register and the constant zero
 with the register, which we cannot do outside a MEM.  In addition, we need
 to record the fact that a register is referenced outside a MEM.

 If INSN is an insn, it is the insn containing X.  If we replace a REG
 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
 the REG is being modified.

 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
 That's used when we eliminate in expressions stored in notes.
 This means, do not set ref_outside_mem even if the reference
 is outside of MEMs.

 If FOR_COSTS is true, we are being called before reload in order to
 estimate the costs of keeping registers with an equivalence unallocated.

 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
 replacements done assuming all offsets are at their initial values.  If
 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
 encounter, return the actual location so that find_reloads will do
 the proper thing.  */

2520static rtx
2521eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
  bool may_use_invariant, bool for_costs)
2523{
enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
struct elim_table *ep;
int regno;
rtx new_rtx;
int i, j;
const char *fmt;
int copied = 0;

if (! current_function_decl)
  return x;

switch (code)
  {
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case CONST:
  case SYMBOL_REF:
  case CODE_LABEL:
  case PC:
  case ASM_INPUT:
  case ADDR_VEC:
  case ADDR_DIFF_VEC:
  case RETURN:
    return x;

  case REG:
    regno = REGNO (x)(rhs_regno(x));

    /* First handle the case where we encounter a bare register that
is eliminable.  Replace it with a PLUS.  */
    if (regno < FIRST_PSEUDO_REGISTER76)
{
 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))];
      ep++)
   if (ep->from_rtx == x && ep->can_eliminate)
     return plus_constant (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), ep->to_rtx, ep->previous_offset);

}
    else if (reg_renumber && reg_renumber[regno] < 0
      && reg_equivs
      && reg_equiv_invariant (regno)(*reg_equivs)[(regno)].invariant)
{
 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN)))
   return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)(*reg_equivs)[(regno)].invariant),
	             mem_mode, insn, true, for_costs);
 /* There exists at least one use of REGNO that cannot be
    eliminated.  Prevent the defining insn from being deleted.  */
 reg_equiv_init (regno)(*reg_equivs)[(regno)].init = NULLnullptr;
 if (!for_costs)
   alter_reg (regno, -1, true);
}
    return x;

  /* You might think handling MINUS in a manner similar to PLUS is a
     good idea.  It is not.  It has been tried multiple times and every
     time the change has had to have been reverted.

     Other parts of reload know a PLUS is special (gen_reload for example)
     and require special code to handle code a reloaded PLUS operand.

     Also consider backends where the flags register is clobbered by a
     MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
     lea instruction comes to mind).  If we try to reload a MINUS, we
     may kill the flags register that was holding a useful value.

     So, please before trying to handle MINUS, consider reload as a
     whole instead of this little section as well as the backend issues.  */
  case PLUS:
    /* If this is the sum of an eliminable register and a constant, rework
the sum.  */
    if (REG_P (XEXP (x, 0))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
 && REGNO (XEXP (x, 0))(rhs_regno((((x)->u.fld[0]).rt_rtx))) < FIRST_PSEUDO_REGISTER76
 && CONSTANT_P (XEXP (x, 1))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
{
 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))];
      ep++)
   if (ep->from_rtx == XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) && ep->can_eliminate)
     {
/* The only time we want to replace a PLUS with a REG (this
   occurs when the constant operand of the PLUS is the negative
   of the offset) is when we are inside a MEM.  We won't want
   to do so at other times because that would change the
   structure of the insn in a way that reload can't handle.
   We special-case the commonest situation in
   eliminate_regs_in_insn, so just replace a PLUS with a
   PLUS here, unless inside a MEM.  In DEBUG_INSNs, it is
   always ok to replace a PLUS with just a REG.  */
if ((mem_mode != 0 || (insn && DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN)))
    && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
    && known_eq (INTVAL (XEXP (x, 1)), -ep->previous_offset)(!maybe_ne ((((((x)->u.fld[1]).rt_rtx))->u.hwint[0]), -
ep->previous_offset)))
  return ep->to_rtx;
else
  return gen_rtx_PLUS (Pmode, ep->to_rtx,gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((ep->to_rtx)), ((plus_constant ((global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
), (((x)->u.fld[1]).rt_rtx), ep->previous_offset))) )
		       plus_constant (Pmode, XEXP (x, 1),gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((ep->to_rtx)), ((plus_constant ((global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
), (((x)->u.fld[1]).rt_rtx), ep->previous_offset))) )
				      ep->previous_offset))gen_rtx_fmt_ee_stat ((PLUS), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((ep->to_rtx)), ((plus_constant ((global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
), (((x)->u.fld[1]).rt_rtx), ep->previous_offset))) );
     }

 /* If the register is not eliminable, we are done since the other
    operand is a constant.  */
 return x;
}

    /* If this is part of an address, we want to bring any constant to the
outermost PLUS.  We will do this by doing register replacement in
our operands and seeing if a constant shows up in one of them.

Note that there is no risk of modifying the structure of the insn,
since we only get called for its operands, thus we are either
modifying the address inside a MEM, or something like an address
operand of a load-address insn.  */

    {
rtx new0 = eliminate_regs_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mem_mode, insn, true,
		     for_costs);
rtx new1 = eliminate_regs_1 (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mem_mode, insn, true,
		     for_costs);

if (reg_renumber && (new0 != XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) || new1 != XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
 {
   /* If one side is a PLUS and the other side is a pseudo that
      didn't get a hard register but has a reg_equiv_constant,
      we must replace the constant here since it may no longer
      be in the position of any operand.  */
   if (GET_CODE (new0)((enum rtx_code) (new0)->code) == PLUS && REG_P (new1)(((enum rtx_code) (new1)->code) == REG)
&& REGNO (new1)(rhs_regno(new1)) >= FIRST_PSEUDO_REGISTER76
&& reg_renumber[REGNO (new1)(rhs_regno(new1))] < 0
&& reg_equivs
&& reg_equiv_constant (REGNO (new1))(*reg_equivs)[((rhs_regno(new1)))].constant != 0)
     new1 = reg_equiv_constant (REGNO (new1))(*reg_equivs)[((rhs_regno(new1)))].constant;
   else if (GET_CODE (new1)((enum rtx_code) (new1)->code) == PLUS && REG_P (new0)(((enum rtx_code) (new0)->code) == REG)
     && REGNO (new0)(rhs_regno(new0)) >= FIRST_PSEUDO_REGISTER76
     && reg_renumber[REGNO (new0)(rhs_regno(new0))] < 0
     && reg_equiv_constant (REGNO (new0))(*reg_equivs)[((rhs_regno(new0)))].constant != 0)
     new0 = reg_equiv_constant (REGNO (new0))(*reg_equivs)[((rhs_regno(new0)))].constant;

   new_rtx = form_sum (GET_MODE (x)((machine_mode) (x)->mode), new0, new1);

   /* As above, if we are not inside a MEM we do not want to
      turn a PLUS into something else.  We might try to do so here
      for an addition of 0 if we aren't optimizing.  */
   if (! mem_mode && GET_CODE (new_rtx)((enum rtx_code) (new_rtx)->code) != PLUS)
     return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx)gen_rtx_fmt_ee_stat ((PLUS), ((((machine_mode) (x)->mode))
), ((new_rtx)), (((const_int_rtx[64]))) );
   else
     return new_rtx;
 }
    }
    return x;

  case MULT:
    /* If this is the product of an eliminable register and a
constant, apply the distribute law and move the constant out
so that we have (plus (mult ..) ..).  This is needed in order
to keep load-address insns valid.   This case is pathological.
We ignore the possibility of overflow here.  */
    if (REG_P (XEXP (x, 0))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
 && REGNO (XEXP (x, 0))(rhs_regno((((x)->u.fld[0]).rt_rtx))) < FIRST_PSEUDO_REGISTER76
 && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
))
for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))];
    ep++)
 if (ep->from_rtx == XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) && ep->can_eliminate)
   {
     if (! mem_mode
  /* Refs inside notes or in DEBUG_INSNs don't count for
     this purpose.  */
  && ! (insn != 0 && (GET_CODE (insn)((enum rtx_code) (insn)->code) == EXPR_LIST
		      || GET_CODE (insn)((enum rtx_code) (insn)->code) == INSN_LIST
		      || DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN))))
ep->ref_outside_mem = 1;

     return
plus_constant (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))),
	       gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1))gen_rtx_fmt_ee_stat ((MULT), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((ep->to_rtx)), (((((x)->u.fld[1]).rt_rtx))) ),
	       ep->previous_offset * INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]));
   }

    /* fall through */

  case CALL:
  case COMPARE:
  /* See comments before PLUS about handling MINUS.  */
  case MINUS:
  case DIV:      case UDIV:
  case MOD:      case UMOD:
  case AND:      case IOR:      case XOR:
  case ROTATERT: case ROTATE:
  case ASHIFTRT: case LSHIFTRT: case ASHIFT:
  case NE:       case EQ:
  case GE:       case GT:       case GEU:    case GTU:
  case LE:       case LT:       case LEU:    case LTU:
    {
rtx new0 = eliminate_regs_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mem_mode, insn, false,
		     for_costs);
rtx new1 = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)
 ? eliminate_regs_1 (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mem_mode, insn, false,
	      for_costs) : 0;

if (new0 != XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) || new1 != XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1)gen_rtx_fmt_ee_stat ((code), (((machine_mode) (x)->mode)),
 (new0), (new1) );
    }
    return x;

  case EXPR_LIST:
    /* If we have something in XEXP (x, 0), the usual case, eliminate it.  */
    if (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
{
 new_rtx = eliminate_regs_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mem_mode, insn, true,
		      for_costs);
 if (new_rtx != XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
   {
     /* If this is a REG_DEAD note, it is not valid anymore.
 Using the eliminated version could result in creating a
 REG_DEAD note for the stack or frame pointer.  */
     if (REG_NOTE_KIND (x)((enum reg_note) ((machine_mode) (x)->mode)) == REG_DEAD)
return (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)
	? eliminate_regs_1 (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mem_mode, insn, true,
			    for_costs)
	: NULL_RTX(rtx) 0);

     x = alloc_reg_note (REG_NOTE_KIND (x)((enum reg_note) ((machine_mode) (x)->mode)), new_rtx, XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));
   }
}

    /* fall through */

  case INSN_LIST:
  case INT_LIST:
    /* Now do eliminations in the rest of the chain.  If this was
an EXPR_LIST, this might result in allocating more memory than is
strictly needed, but it simplifies the code.  */
    if (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
{
 new_rtx = eliminate_regs_1 (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mem_mode, insn, true,
		      for_costs);
 if (new_rtx != XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
   return
     gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx)gen_rtx_fmt_ee_stat ((((enum rtx_code) (x)->code)), (((machine_mode
) (x)->mode)), ((((x)->u.fld[0]).rt_rtx)), (new_rtx) );
}
    return x;

  case PRE_INC:
  case POST_INC:
  case PRE_DEC:
  case POST_DEC:
    /* We do not support elimination of a register that is modified.
elimination_effects has already make sure that this does not
happen.  */
    return x;

  case PRE_MODIFY:
  case POST_MODIFY:
    /* We do not support elimination of a register that is modified.
elimination_effects has already make sure that this does not
happen.  The only remaining case we need to consider here is
that the increment value may be an eliminable register.  */
    if (GET_CODE (XEXP (x, 1))((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == PLUS
 && XEXP (XEXP (x, 1), 0)((((((x)->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx) == XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
{
 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1)((((((x)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx), mem_mode,
			  insn, true, for_costs);

 if (new_rtx != XEXP (XEXP (x, 1), 1)((((((x)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx))
   return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),gen_rtx_fmt_ee_stat ((code), (((machine_mode) (x)->mode)),
 ((((x)->u.fld[0]).rt_rtx)), (gen_rtx_fmt_ee_stat ((PLUS),
 ((((machine_mode) (x)->mode))), (((((x)->u.fld[0]).rt_rtx
))), ((new_rtx)) )) )
		   gen_rtx_PLUS (GET_MODE (x),gen_rtx_fmt_ee_stat ((code), (((machine_mode) (x)->mode)),
 ((((x)->u.fld[0]).rt_rtx)), (gen_rtx_fmt_ee_stat ((PLUS),
 ((((machine_mode) (x)->mode))), (((((x)->u.fld[0]).rt_rtx
))), ((new_rtx)) )) )
				 XEXP (x, 0), new_rtx))gen_rtx_fmt_ee_stat ((code), (((machine_mode) (x)->mode)),
 ((((x)->u.fld[0]).rt_rtx)), (gen_rtx_fmt_ee_stat ((PLUS),
 ((((machine_mode) (x)->mode))), (((((x)->u.fld[0]).rt_rtx
))), ((new_rtx)) )) );
}
    return x;

  case STRICT_LOW_PART:
  case NEG:          case NOT:
  case SIGN_EXTEND:  case ZERO_EXTEND:
  case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
  case FLOAT:        case FIX:
  case UNSIGNED_FIX: case UNSIGNED_FLOAT:
  case ABS:
  case SQRT:
  case FFS:
  case CLZ:
  case CTZ:
  case POPCOUNT:
  case PARITY:
  case BSWAP:
    new_rtx = eliminate_regs_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mem_mode, insn, false,
		  for_costs);
    if (new_rtx != XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx)gen_rtx_fmt_e_stat ((code), (((machine_mode) (x)->mode)), (
new_rtx) );
    return x;

  case SUBREG:
    /* Similar to above processing, but preserve SUBREG_BYTE.
Convert (subreg (mem)) to (mem) if not paradoxical.
Also, if we have a non-paradoxical (subreg (pseudo)) and the
pseudo didn't get a hard reg, we must replace this with the
eliminated version of the memory location because push_reload
may do the replacement in certain circumstances.  */
    if (REG_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
 && !paradoxical_subreg_p (x)
 && reg_equivs
 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x)))(*reg_equivs)[((rhs_regno((((x)->u.fld[0]).rt_rtx))))].memory_loc != 0)
{
 new_rtx = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
}
    else
new_rtx = eliminate_regs_1 (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), mem_mode, insn, false, for_costs);

    if (new_rtx != SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx))
{
 poly_int64 x_size = GET_MODE_SIZE (GET_MODE (x)((machine_mode) (x)->mode));
 poly_int64 new_size = GET_MODE_SIZE (GET_MODE (new_rtx)((machine_mode) (new_rtx)->mode));

 if (MEM_P (new_rtx)(((enum rtx_code) (new_rtx)->code) == MEM)
     && ((partial_subreg_p (GET_MODE (x)((machine_mode) (x)->mode), GET_MODE (new_rtx)((machine_mode) (new_rtx)->mode))
   /* On RISC machines, combine can create rtl of the form
      (set (subreg:m1 (reg:m2 R) 0) ...)
      where m1 < m2, and expects something interesting to
      happen to the entire word.  Moreover, it will use the
      (reg:m2 R) later, expecting all bits to be preserved.
      So if the number of words is the same, preserve the
      subreg so that push_reload can see it.  */
   && !(WORD_REGISTER_OPERATIONS0
	&& known_equal_after_align_down (x_size - 1,
					 new_size - 1,
					 UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
 0) ? 8 : 4))))
  || known_eq (x_size, new_size)(!maybe_ne (x_size, new_size)))
     )
   return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x))adjust_address_1 (new_rtx, ((machine_mode) (x)->mode), (((
x)->u.fld[1]).rt_subreg), 0, 1, 0, 0);
 else if (insn && GET_CODE (insn)((enum rtx_code) (insn)->code) == DEBUG_INSN)
   return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x))gen_rtx_fmt_ep_stat ((SUBREG), ((((machine_mode) (x)->mode
))), ((new_rtx)), (((((x)->u.fld[1]).rt_subreg))) );
 else
   return gen_rtx_SUBREG (GET_MODE (x)((machine_mode) (x)->mode), new_rtx, SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg));
}

    return x;

  case MEM:
    /* Our only special processing is to pass the mode of the MEM to our
recursive call and copy the flags.  While we are here, handle this
case more efficiently.  */

    new_rtx = eliminate_regs_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), GET_MODE (x)((machine_mode) (x)->mode), insn, true,
		  for_costs);
    if (for_costs
 && memory_address_p (GET_MODE (x), XEXP (x, 0))memory_address_addr_space_p ((((machine_mode) (x)->mode)),
 ((((x)->u.fld[0]).rt_rtx)), 0)
 && !memory_address_p (GET_MODE (x), new_rtx)memory_address_addr_space_p ((((machine_mode) (x)->mode)),
 (new_rtx), 0))
note_reg_elim_costly (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), insn);

    return replace_equiv_address_nv (x, new_rtx);

  case USE:
    /* Handle insn_list USE that a call to a pure function may generate.  */
    new_rtx = eliminate_regs_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), VOIDmode((void) 0, E_VOIDmode), insn, false,
		  for_costs);
    if (new_rtx != XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
return gen_rtx_USE (GET_MODE (x), new_rtx)gen_rtx_fmt_e_stat ((USE), ((((machine_mode) (x)->mode))),
 ((new_rtx)) );
    return x;

  case CLOBBER:
  case ASM_OPERANDS:
    gcc_assert (insn && DEBUG_INSN_P (insn))((void)(!(insn && (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 2880, __FUNCTION__), 0 : 0));
    break;

  case SET:
    gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 2884, __FUNCTION__));

  default:
    break;
  }

/* Process each of our operands recursively.  If any have changed, make a
   copy of the rtx.  */
fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = 0; i < GET_RTX_LENGTH (code)(rtx_length[(int) (code)]); i++, fmt++)
  {
    if (*fmt == 'e')
{
 new_rtx = eliminate_regs_1 (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), mem_mode, insn, false,
		      for_costs);
 if (new_rtx != XEXP (x, i)(((x)->u.fld[i]).rt_rtx) && ! copied)
   {
     x = shallow_copy_rtx (x);
     copied = 1;
   }
 XEXP (x, i)(((x)->u.fld[i]).rt_rtx) = new_rtx;
}
    else if (*fmt == 'E')
{
 int copied_vec = 0;
 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
   {
     new_rtx = eliminate_regs_1 (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), mem_mode, insn, false,
			  for_costs);
     if (new_rtx != XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]) && ! copied_vec)
{
  rtvec new_v = gen_rtvec_v (XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem),
			     XVEC (x, i)(((x)->u.fld[i]).rt_rtvec)->elem);
  if (! copied)
    {
      x = shallow_copy_rtx (x);
      copied = 1;
    }
  XVEC (x, i)(((x)->u.fld[i]).rt_rtvec) = new_v;
  copied_vec = 1;
}
     XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]) = new_rtx;
   }
}
  }

return x;
2931}

2933rtx
2934eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
2935{
if (reg_eliminate == NULLnullptr)
  {
    gcc_assert (targetm.no_register_allocation)((void)(!(targetm.no_register_allocation) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 2938, __FUNCTION__), 0 : 0));
    return x;
  }
return eliminate_regs_1 (x, mem_mode, insn, false, false);
2942}

2944/* Scan rtx X for modifications of elimination target registers.  Update
 the table of eliminables to reflect the changed state.  MEM_MODE is
 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM.  */

2948static void
2949elimination_effects (rtx x, machine_mode mem_mode)
2950{
enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
struct elim_table *ep;
int regno;
int i, j;
const char *fmt;

switch (code)
  {
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case CONST:
  case SYMBOL_REF:
  case CODE_LABEL:
  case PC:
  case ASM_INPUT:
  case ADDR_VEC:
  case ADDR_DIFF_VEC:
  case RETURN:
    return;

  case REG:
    regno = REGNO (x)(rhs_regno(x));

    /* First handle the case where we encounter a bare register that
is eliminable.  Replace it with a PLUS.  */
    if (regno < FIRST_PSEUDO_REGISTER76)
{
 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))];
      ep++)
   if (ep->from_rtx == x && ep->can_eliminate)
     {
if (! mem_mode)
  ep->ref_outside_mem = 1;
return;
     }

}
    else if (reg_renumber[regno] < 0
      && reg_equivs
      && reg_equiv_constant (regno)(*reg_equivs)[(regno)].constant
      && ! function_invariant_p (reg_equiv_constant (regno)(*reg_equivs)[(regno)].constant))
elimination_effects (reg_equiv_constant (regno)(*reg_equivs)[(regno)].constant, mem_mode);
    return;

  case PRE_INC:
  case POST_INC:
  case PRE_DEC:
  case POST_DEC:
  case POST_MODIFY:
  case PRE_MODIFY:
    /* If we modify the source of an elimination rule, disable it.  */
    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
if (ep->from_rtx == XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
 ep->can_eliminate = 0;

    /* If we modify the target of an elimination rule by adding a constant,
update its offset.  If we modify the target in any other way, we'll
have to disable the rule as well.  */
    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
if (ep->to_rtx == XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
 {
   poly_int64 size = GET_MODE_SIZE (mem_mode);

   /* If more bytes than MEM_MODE are pushed, account for them.  */
3014#ifdef PUSH_ROUNDING
   if (ep->to_rtx == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
     size = PUSH_ROUNDING (size)ix86_push_rounding (size);
3017#endif
   if (code == PRE_DEC || code == POST_DEC)
     ep->offset += size;
   else if (code == PRE_INC || code == POST_INC)
     ep->offset -= size;
   else if (code == PRE_MODIFY || code == POST_MODIFY)
     {
if (GET_CODE (XEXP (x, 1))((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == PLUS
    && XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) == XEXP (XEXP (x, 1), 0)((((((x)->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx)
    && CONST_INT_P (XEXP (XEXP (x, 1), 1))(((enum rtx_code) (((((((x)->u.fld[1]).rt_rtx))->u.fld[
1]).rt_rtx))->code) == CONST_INT))
  ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1))((((((((x)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx))->
u.hwint[0]);
else
  ep->can_eliminate = 0;
     }
 }

    /* These two aren't unary operators.  */
    if (code == POST_MODIFY || code == PRE_MODIFY)
break;

    /* Fall through to generic unary operation case.  */
    gcc_fallthrough ();
  case STRICT_LOW_PART:
  case NEG:          case NOT:
  case SIGN_EXTEND:  case ZERO_EXTEND:
  case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
  case FLOAT:        case FIX:
  case UNSIGNED_FIX: case UNSIGNED_FLOAT:
  case ABS:
  case SQRT:
  case FFS:
  case CLZ:
  case CTZ:
  case POPCOUNT:
  case PARITY:
  case BSWAP:
    elimination_effects (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mem_mode);
    return;

  case SUBREG:
    if (REG_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
 && !paradoxical_subreg_p (x)
 && reg_equivs
 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x)))(*reg_equivs)[((rhs_regno((((x)->u.fld[0]).rt_rtx))))].memory_loc != 0)
return;

    elimination_effects (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), mem_mode);
    return;

  case USE:
    /* If using a register that is the source of an eliminate we still
think can be performed, note it cannot be performed since we don't
know how this register is used.  */
    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
if (ep->from_rtx == XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
 ep->can_eliminate = 0;

    elimination_effects (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mem_mode);
    return;

  case CLOBBER:
    /* If clobbering a register that is the replacement register for an
elimination we still think can be performed, note that it cannot
be performed.  Otherwise, we need not be concerned about it.  */
    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
if (ep->to_rtx == XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
 ep->can_eliminate = 0;

    elimination_effects (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mem_mode);
    return;

  case SET:
    /* Check for setting a register that we know about.  */
    if (REG_P (SET_DEST (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
))
{
 /* See if this is setting the replacement register for an
    elimination.

    If DEST is the hard frame pointer, we do nothing because we
    assume that all assignments to the frame pointer are for
    non-local gotos and are being done at a time when they are valid
    and do not disturb anything else.  Some machines want to
    eliminate a fake argument pointer (or even a fake frame pointer)
    with either the real frame or the stack pointer.  Assignments to
    the hard frame pointer must not prevent this elimination.  */

 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))];
      ep++)
   if (ep->to_rtx == SET_DEST (x)(((x)->u.fld[0]).rt_rtx)
&& SET_DEST (x)(((x)->u.fld[0]).rt_rtx) != hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER]))
     {
/* If it is being incremented, adjust the offset.  Otherwise,
   this elimination can't be done.  */
rtx src = SET_SRC (x)(((x)->u.fld[1]).rt_rtx);

if (GET_CODE (src)((enum rtx_code) (src)->code) == PLUS
    && XEXP (src, 0)(((src)->u.fld[0]).rt_rtx) == SET_DEST (x)(((x)->u.fld[0]).rt_rtx)
    && CONST_INT_P (XEXP (src, 1))(((enum rtx_code) ((((src)->u.fld[1]).rt_rtx))->code) ==
 CONST_INT))
  ep->offset -= INTVAL (XEXP (src, 1))(((((src)->u.fld[1]).rt_rtx))->u.hwint[0]);
else
  ep->can_eliminate = 0;
     }
}

    elimination_effects (SET_DEST (x)(((x)->u.fld[0]).rt_rtx), VOIDmode((void) 0, E_VOIDmode));
    elimination_effects (SET_SRC (x)(((x)->u.fld[1]).rt_rtx), VOIDmode((void) 0, E_VOIDmode));
    return;

  case MEM:
    /* Our only special processing is to pass the mode of the MEM to our
recursive call.  */
    elimination_effects (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), GET_MODE (x)((machine_mode) (x)->mode));
    return;

  default:
    break;
  }

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = 0; i < GET_RTX_LENGTH (code)(rtx_length[(int) (code)]); i++, fmt++)
  {
    if (*fmt == 'e')
elimination_effects (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), mem_mode);
    else if (*fmt == 'E')
for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
 elimination_effects (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), mem_mode);
  }
3144}

3146/* Descend through rtx X and verify that no references to eliminable registers
 remain.  If any do remain, mark the involved register as not
 eliminable.  */

3150static void
3151check_eliminable_occurrences (rtx x)
3152{
const char *fmt;
int i;
enum rtx_code code;

if (x == 0)
  return;

code = GET_CODE (x)((enum rtx_code) (x)->code);

if (code == REG && REGNO (x)(rhs_regno(x)) < FIRST_PSEUDO_REGISTER76)
  {
    struct elim_table *ep;

    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
if (ep->from_rtx == x)
 ep->can_eliminate = 0;
    return;
  }

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = 0; i < GET_RTX_LENGTH (code)(rtx_length[(int) (code)]); i++, fmt++)
  {
    if (*fmt == 'e')
check_eliminable_occurrences (XEXP (x, i)(((x)->u.fld[i]).rt_rtx));
    else if (*fmt == 'E')
{
 int j;
 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
   check_eliminable_occurrences (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]));
}
  }
3184}
3185
3186/* Scan INSN and eliminate all eliminable registers in it.

 If REPLACE is nonzero, do the replacement destructively.  Also
 delete the insn as dead it if it is setting an eliminable register.

 If REPLACE is zero, do all our allocations in reload_obstack.

 If no eliminations were done and this insn doesn't require any elimination
 processing (these are not identical conditions: it might be updating sp,
 but not referencing fp; this needs to be seen during reload_as_needed so
 that the offset between fp and sp can be taken into consideration), zero
 is returned.  Otherwise, 1 is returned.  */

3199static int
3200eliminate_regs_in_insn (rtx_insn *insn, int replace)
3201{
int icode = recog_memoized (insn);
rtx old_body = PATTERN (insn);
int insn_is_asm = asm_noperands (old_body) >= 0;
1
Assuming the condition is false→
rtx old_set = single_set (insn);
rtx new_body;
int val = 0;
int i;
rtx substed_operand[MAX_RECOG_OPERANDS30];
rtx orig_operand[MAX_RECOG_OPERANDS30];
struct elim_table *ep;
rtx plus_src, plus_cst_src;

if (! insn_is_asm1.1
'insn_is_asm' is 0
 && icode1.2
'icode' is >= 0
 < 0)
2
←
Taking false branch→
  {
    gcc_assert (DEBUG_INSN_P (insn)((void)(!((((enum rtx_code) (insn)->code) == DEBUG_INSN) ||
 ((enum rtx_code) (PATTERN (insn))->code) == USE || ((enum
 rtx_code) (PATTERN (insn))->code) == CLOBBER || ((enum rtx_code
) (PATTERN (insn))->code) == ASM_INPUT) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 3219, __FUNCTION__), 0 : 0))
  || GET_CODE (PATTERN (insn)) == USE((void)(!((((enum rtx_code) (insn)->code) == DEBUG_INSN) ||
 ((enum rtx_code) (PATTERN (insn))->code) == USE || ((enum
 rtx_code) (PATTERN (insn))->code) == CLOBBER || ((enum rtx_code
) (PATTERN (insn))->code) == ASM_INPUT) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 3219, __FUNCTION__), 0 : 0))
  || GET_CODE (PATTERN (insn)) == CLOBBER((void)(!((((enum rtx_code) (insn)->code) == DEBUG_INSN) ||
 ((enum rtx_code) (PATTERN (insn))->code) == USE || ((enum
 rtx_code) (PATTERN (insn))->code) == CLOBBER || ((enum rtx_code
) (PATTERN (insn))->code) == ASM_INPUT) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 3219, __FUNCTION__), 0 : 0))
  || GET_CODE (PATTERN (insn)) == ASM_INPUT)((void)(!((((enum rtx_code) (insn)->code) == DEBUG_INSN) ||
 ((enum rtx_code) (PATTERN (insn))->code) == USE || ((enum
 rtx_code) (PATTERN (insn))->code) == CLOBBER || ((enum rtx_code
) (PATTERN (insn))->code) == ASM_INPUT) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 3219, __FUNCTION__), 0 : 0));
    if (DEBUG_BIND_INSN_P (insn)((((enum rtx_code) (insn)->code) == DEBUG_INSN) &&
 (((enum rtx_code) (PATTERN (insn))->code) == VAR_LOCATION
)))
INSN_VAR_LOCATION_LOC (insn)((((((__extension__ ({ __typeof (PATTERN (insn)) const _rtx =
 (PATTERN (insn)); if (((enum rtx_code) (_rtx)->code) != VAR_LOCATION
) rtl_check_failed_flag ("INSN_VAR_LOCATION", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 3221, __FUNCTION__); _rtx; }))))->u.fld[1]).rt_rtx))
 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn)((((((__extension__ ({ __typeof (PATTERN (insn)) const _rtx =
 (PATTERN (insn)); if (((enum rtx_code) (_rtx)->code) != VAR_LOCATION
) rtl_check_failed_flag ("INSN_VAR_LOCATION", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 3222, __FUNCTION__); _rtx; }))))->u.fld[1]).rt_rtx)), VOIDmode((void) 0, E_VOIDmode), insn);
    return 0;
  }

/* We allow one special case which happens to work on all machines we
   currently support: a single set with the source or a REG_EQUAL
   note being a PLUS of an eliminable register and a constant.  */
plus_src = plus_cst_src = 0;
if (old_set2.1
'old_set' is null
 && REG_P (SET_DEST (old_set))(((enum rtx_code) ((((old_set)->u.fld[0]).rt_rtx))->code
) == REG))
  {
    if (GET_CODE (SET_SRC (old_set))((enum rtx_code) ((((old_set)->u.fld[1]).rt_rtx))->code
) == PLUS)
plus_src = SET_SRC (old_set)(((old_set)->u.fld[1]).rt_rtx);
    /* First see if the source is of the form (plus (...) CST).  */
    if (plus_src
 && CONST_INT_P (XEXP (plus_src, 1))(((enum rtx_code) ((((plus_src)->u.fld[1]).rt_rtx))->code
) == CONST_INT))
plus_cst_src = plus_src;
    else if (REG_P (SET_SRC (old_set))(((enum rtx_code) ((((old_set)->u.fld[1]).rt_rtx))->code
) == REG)
      || plus_src)
{
 /* Otherwise, see if we have a REG_EQUAL note of the form
    (plus (...) CST).  */
 rtx links;
 for (links = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); links; links = XEXP (links, 1)(((links)->u.fld[1]).rt_rtx))
   {
     if ((REG_NOTE_KIND (links)((enum reg_note) ((machine_mode) (links)->mode)) == REG_EQUAL
   || REG_NOTE_KIND (links)((enum reg_note) ((machine_mode) (links)->mode)) == REG_EQUIV)
  && GET_CODE (XEXP (links, 0))((enum rtx_code) ((((links)->u.fld[0]).rt_rtx))->code) == PLUS
  && CONST_INT_P (XEXP (XEXP (links, 0), 1))(((enum rtx_code) (((((((links)->u.fld[0]).rt_rtx))->u.
fld[1]).rt_rtx))->code) == CONST_INT))
{
  plus_cst_src = XEXP (links, 0)(((links)->u.fld[0]).rt_rtx);
  break;
}
   }
}

    /* Check that the first operand of the PLUS is a hard reg or
the lowpart subreg of one.  */
    if (plus_cst_src)
{
 rtx reg = XEXP (plus_cst_src, 0)(((plus_cst_src)->u.fld[0]).rt_rtx);
 if (GET_CODE (reg)((enum rtx_code) (reg)->code) == SUBREG && subreg_lowpart_p (reg))
   reg = SUBREG_REG (reg)(((reg)->u.fld[0]).rt_rtx);

 if (!REG_P (reg)(((enum rtx_code) (reg)->code) == REG) || REGNO (reg)(rhs_regno(reg)) >= FIRST_PSEUDO_REGISTER76)
   plus_cst_src = 0;
}
  }
if (plus_cst_src2.2
'plus_cst_src' is null
)
3
←
Taking false branch→
  {
    rtx reg = XEXP (plus_cst_src, 0)(((plus_cst_src)->u.fld[0]).rt_rtx);
    poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1))(((((plus_cst_src)->u.fld[1]).rt_rtx))->u.hwint[0]);

    if (GET_CODE (reg)((enum rtx_code) (reg)->code) == SUBREG)
reg = SUBREG_REG (reg)(((reg)->u.fld[0]).rt_rtx);

    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
if (ep->from_rtx == reg && ep->can_eliminate)
 {
   rtx to_rtx = ep->to_rtx;
   offset += ep->offset;
   offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src)((machine_mode) (plus_cst_src)->mode));

   if (GET_CODE (XEXP (plus_cst_src, 0))((enum rtx_code) ((((plus_cst_src)->u.fld[0]).rt_rtx))->
code) == SUBREG)
     to_rtx = gen_lowpartrtl_hooks.gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0))((machine_mode) ((((plus_cst_src)->u.fld[0]).rt_rtx))->
mode),
		    to_rtx);
   /* If we have a nonzero offset, and the source is already
      a simple REG, the following transformation would
      increase the cost of the insn by replacing a simple REG
      with (plus (reg sp) CST).  So try only when we already
      had a PLUS before.  */
   if (known_eq (offset, 0)(!maybe_ne (offset, 0)) || plus_src)
     {
rtx new_src = plus_constant (GET_MODE (to_rtx)((machine_mode) (to_rtx)->mode),
			     to_rtx, offset);

new_body = old_body;
if (! replace)
  {
    new_body = copy_insn (old_body);
    if (REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx))
      REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) = copy_insn_1 (REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx));
  }
PATTERN (insn) = new_body;
old_set = single_set (insn);

/* First see if this insn remains valid when we make the
   change.  If not, try to replace the whole pattern with
   a simple set (this may help if the original insn was a
   PARALLEL that was only recognized as single_set due to
   REG_UNUSED notes).  If this isn't valid either, keep
   the INSN_CODE the same and let reload fix it up.  */
if (!validate_change (insn, &SET_SRC (old_set)(((old_set)->u.fld[1]).rt_rtx), new_src, 0))
  {
    rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), (((((old_set
)->u.fld[0]).rt_rtx))), ((new_src)) );

    if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
      SET_SRC (old_set)(((old_set)->u.fld[1]).rt_rtx) = new_src;
  }
     }
   else
     break;

   val = 1;
   /* This can't have an effect on elimination offsets, so skip right
      to the end.  */
   goto done;
 }
  }

/* Determine the effects of this insn on elimination offsets.  */
elimination_effects (old_body, VOIDmode((void) 0, E_VOIDmode));

/* Eliminate all eliminable registers occurring in operands that
   can be handled by reload.  */
extract_insn (insn);
for (i = 0; i < recog_data.n_operands; i++)
4
←
Assuming 'i' is >= field 'n_operands'→
5
←
Loop condition is false. Execution continues on line 3393→
  {
    orig_operand[i] = recog_data.operand[i];
    substed_operand[i] = recog_data.operand[i];

    /* For an asm statement, every operand is eliminable.  */
    if (insn_is_asm || insn_data[icode].operand[i].eliminable)
{
 bool is_set_src, in_plus;

 /* Check for setting a register that we know about.  */
 if (recog_data.operand_type[i] != OP_IN
     && REG_P (orig_operand[i])(((enum rtx_code) (orig_operand[i])->code) == REG))
   {
     /* If we are assigning to a register that can be eliminated, it
 must be as part of a PARALLEL, since the code above handles
 single SETs.  We must indicate that we can no longer
 eliminate this reg.  */
     for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))];
   ep++)
if (ep->from_rtx == orig_operand[i])
  ep->can_eliminate = 0;
   }

 /* Companion to the above plus substitution, we can allow
    invariants as the source of a plain move.  */
 is_set_src = false;
 if (old_set
     && recog_data.operand_loc[i] == &SET_SRC (old_set)(((old_set)->u.fld[1]).rt_rtx))
   is_set_src = true;
 in_plus = false;
 if (plus_src
     && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)(((plus_src)->u.fld[0]).rt_rtx)
  || recog_data.operand_loc[i] == &XEXP (plus_src, 1)(((plus_src)->u.fld[1]).rt_rtx)))
   in_plus = true;

 substed_operand[i]
   = eliminate_regs_1 (recog_data.operand[i], VOIDmode((void) 0, E_VOIDmode),
	        replace ? insn : NULL_RTX(rtx) 0,
		is_set_src || in_plus, false);
 if (substed_operand[i] != orig_operand[i])
   val = 1;
 /* Terminate the search in check_eliminable_occurrences at
    this point.  */
 *recog_data.operand_loc[i] = 0;

 /* If an output operand changed from a REG to a MEM and INSN is an
    insn, write a CLOBBER insn.  */
 if (recog_data.operand_type[i] != OP_IN
     && REG_P (orig_operand[i])(((enum rtx_code) (orig_operand[i])->code) == REG)
     && MEM_P (substed_operand[i])(((enum rtx_code) (substed_operand[i])->code) == MEM)
     && replace)
   emit_insn_after (gen_clobber (orig_operand[i]), insn);
}
  }

for (i = 0; i < recog_data.n_dups; i++)
6
←
Assuming 'i' is >= field 'n_dups'→
7
←
Loop condition is false. Execution continues on line 3398→
  *recog_data.dup_loc[i]
    = *recog_data.operand_loc[(int) recog_data.dup_num[i]];

/* If any eliminable remain, they aren't eliminable anymore.  */
check_eliminable_occurrences (old_body);

/* Substitute the operands; the new values are in the substed_operand
   array.  */
for (i = 0; i < recog_data.n_operands; i++)
8
←
The value 0 is assigned to 'i'→
9
←
Assuming 'i' is < field 'n_operands'→
10
←
Loop condition is true.  Entering loop body→
  *recog_data.operand_loc[i] = substed_operand[i];
11
←
Assigned value is garbage or undefined
for (i = 0; i < recog_data.n_dups; i++)
  *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];

/* If we are replacing a body that was a (set X (plus Y Z)), try to
   re-recognize the insn.  We do this in case we had a simple addition
   but now can do this as a load-address.  This saves an insn in this
   common case.
   If re-recognition fails, the old insn code number will still be used,
   and some register operands may have changed into PLUS expressions.
   These will be handled by find_reloads by loading them into a register
   again.  */

if (val)
  {
    /* If we aren't replacing things permanently and we changed something,
make another copy to ensure that all the RTL is new.  Otherwise
things can go wrong if find_reload swaps commutative operands
and one is inside RTL that has been copied while the other is not.  */
    new_body = old_body;
    if (! replace)
{
 new_body = copy_insn (old_body);
 if (REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx))
   REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) = copy_insn_1 (REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx));
}
    PATTERN (insn) = new_body;

    /* If we had a move insn but now we don't, rerecognize it.  This will
cause spurious re-recognition if the old move had a PARALLEL since
the new one still will, but we can't call single_set without
having put NEW_BODY into the insn and the re-recognition won't
hurt in this rare case.  */
    /* ??? Why this huge if statement - why don't we just rerecognize the
thing always?  */
    if (! insn_is_asm
 && old_set != 0
 && ((REG_P (SET_SRC (old_set))(((enum rtx_code) ((((old_set)->u.fld[1]).rt_rtx))->code
) == REG)
      && (GET_CODE (new_body)((enum rtx_code) (new_body)->code) != SET
   || !REG_P (SET_SRC (new_body))(((enum rtx_code) ((((new_body)->u.fld[1]).rt_rtx))->code
) == REG)))
     /* If this was a load from or store to memory, compare
 the MEM in recog_data.operand to the one in the insn.
 If they are not equal, then rerecognize the insn.  */
     || (old_set != 0
  && ((MEM_P (SET_SRC (old_set))(((enum rtx_code) ((((old_set)->u.fld[1]).rt_rtx))->code
) == MEM)
       && SET_SRC (old_set)(((old_set)->u.fld[1]).rt_rtx) != recog_data.operand[1])
      || (MEM_P (SET_DEST (old_set))(((enum rtx_code) ((((old_set)->u.fld[0]).rt_rtx))->code
) == MEM)
	  && SET_DEST (old_set)(((old_set)->u.fld[0]).rt_rtx) != recog_data.operand[0])))
     /* If this was an add insn before, rerecognize.  */
     || GET_CODE (SET_SRC (old_set))((enum rtx_code) ((((old_set)->u.fld[1]).rt_rtx))->code
) == PLUS))
{
 int new_icode = recog (PATTERN (insn), insn, 0);
 if (new_icode >= 0)
   INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) = new_icode;
}
  }

/* Restore the old body.  If there were any changes to it, we made a copy
   of it while the changes were still in place, so we'll correctly return
   a modified insn below.  */
if (! replace)
  {
    /* Restore the old body.  */
    for (i = 0; i < recog_data.n_operands; i++)
/* Restoring a top-level match_parallel would clobber the new_body
  we installed in the insn.  */
if (recog_data.operand_loc[i] != &PATTERN (insn))
 *recog_data.operand_loc[i] = orig_operand[i];
    for (i = 0; i < recog_data.n_dups; i++)
*recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
  }

/* Update all elimination pairs to reflect the status after the current
   insn.  The changes we make were determined by the earlier call to
   elimination_effects.

   We also detect cases where register elimination cannot be done,
   namely, if a register would be both changed and referenced outside a MEM
   in the resulting insn since such an insn is often undefined and, even if
   not, we cannot know what meaning will be given to it.  Note that it is
   valid to have a register used in an address in an insn that changes it
   (presumably with a pre- or post-increment or decrement).

   If anything changes, return nonzero.  */

for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
  {
    if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
ep->can_eliminate = 0;

    ep->ref_outside_mem = 0;

    if (maybe_ne (ep->previous_offset, ep->offset))
val = 1;
  }

done:
/* If we changed something, perform elimination in REG_NOTES.  This is
   needed even when REPLACE is zero because a REG_DEAD note might refer
   to a register that we eliminate and could cause a different number
   of spill registers to be needed in the final reload pass than in
   the pre-passes.  */
if (val && REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) != 0)
  REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx)
    = eliminate_regs_1 (REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx), VOIDmode((void) 0, E_VOIDmode), REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx), true,
	  false);

return val;
3511}

3513/* Like eliminate_regs_in_insn, but only estimate costs for the use of the
 register allocator.  INSN is the instruction we need to examine, we perform
 eliminations in its operands and record cases where eliminating a reg with
 an invariant equivalence would add extra cost.  */

3518#pragma GCC diagnostic push
3519#pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3520static void
3521elimination_costs_in_insn (rtx_insn *insn)
3522{
int icode = recog_memoized (insn);
rtx old_body = PATTERN (insn);
int insn_is_asm = asm_noperands (old_body) >= 0;
rtx old_set = single_set (insn);
int i;
rtx orig_operand[MAX_RECOG_OPERANDS30];
rtx orig_dup[MAX_RECOG_OPERANDS30];
struct elim_table *ep;
rtx plus_src, plus_cst_src;
bool sets_reg_p;

if (! insn_is_asm && icode < 0)
  {
    gcc_assert (DEBUG_INSN_P (insn)((void)(!((((enum rtx_code) (insn)->code) == DEBUG_INSN) ||
 ((enum rtx_code) (PATTERN (insn))->code) == USE || ((enum
 rtx_code) (PATTERN (insn))->code) == CLOBBER || ((enum rtx_code
) (PATTERN (insn))->code) == ASM_INPUT) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 3539, __FUNCTION__), 0 : 0))
  || GET_CODE (PATTERN (insn)) == USE((void)(!((((enum rtx_code) (insn)->code) == DEBUG_INSN) ||
 ((enum rtx_code) (PATTERN (insn))->code) == USE || ((enum
 rtx_code) (PATTERN (insn))->code) == CLOBBER || ((enum rtx_code
) (PATTERN (insn))->code) == ASM_INPUT) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 3539, __FUNCTION__), 0 : 0))
  || GET_CODE (PATTERN (insn)) == CLOBBER((void)(!((((enum rtx_code) (insn)->code) == DEBUG_INSN) ||
 ((enum rtx_code) (PATTERN (insn))->code) == USE || ((enum
 rtx_code) (PATTERN (insn))->code) == CLOBBER || ((enum rtx_code
) (PATTERN (insn))->code) == ASM_INPUT) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 3539, __FUNCTION__), 0 : 0))
  || GET_CODE (PATTERN (insn)) == ASM_INPUT)((void)(!((((enum rtx_code) (insn)->code) == DEBUG_INSN) ||
 ((enum rtx_code) (PATTERN (insn))->code) == USE || ((enum
 rtx_code) (PATTERN (insn))->code) == CLOBBER || ((enum rtx_code
) (PATTERN (insn))->code) == ASM_INPUT) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 3539, __FUNCTION__), 0 : 0));
    return;
  }

if (old_set != 0 && REG_P (SET_DEST (old_set))(((enum rtx_code) ((((old_set)->u.fld[0]).rt_rtx))->code
) == REG)
    && REGNO (SET_DEST (old_set))(rhs_regno((((old_set)->u.fld[0]).rt_rtx))) < FIRST_PSEUDO_REGISTER76)
  {
    /* Check for setting an eliminable register.  */
    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
if (ep->from_rtx == SET_DEST (old_set)(((old_set)->u.fld[0]).rt_rtx) && ep->can_eliminate)
 return;
  }

/* We allow one special case which happens to work on all machines we
   currently support: a single set with the source or a REG_EQUAL
   note being a PLUS of an eliminable register and a constant.  */
plus_src = plus_cst_src = 0;
sets_reg_p = false;
if (old_set && REG_P (SET_DEST (old_set))(((enum rtx_code) ((((old_set)->u.fld[0]).rt_rtx))->code
) == REG))
  {
    sets_reg_p = true;
    if (GET_CODE (SET_SRC (old_set))((enum rtx_code) ((((old_set)->u.fld[1]).rt_rtx))->code
) == PLUS)
plus_src = SET_SRC (old_set)(((old_set)->u.fld[1]).rt_rtx);
    /* First see if the source is of the form (plus (...) CST).  */
    if (plus_src
 && CONST_INT_P (XEXP (plus_src, 1))(((enum rtx_code) ((((plus_src)->u.fld[1]).rt_rtx))->code
) == CONST_INT))
plus_cst_src = plus_src;
    else if (REG_P (SET_SRC (old_set))(((enum rtx_code) ((((old_set)->u.fld[1]).rt_rtx))->code
) == REG)
      || plus_src)
{
 /* Otherwise, see if we have a REG_EQUAL note of the form
    (plus (...) CST).  */
 rtx links;
 for (links = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); links; links = XEXP (links, 1)(((links)->u.fld[1]).rt_rtx))
   {
     if ((REG_NOTE_KIND (links)((enum reg_note) ((machine_mode) (links)->mode)) == REG_EQUAL
   || REG_NOTE_KIND (links)((enum reg_note) ((machine_mode) (links)->mode)) == REG_EQUIV)
  && GET_CODE (XEXP (links, 0))((enum rtx_code) ((((links)->u.fld[0]).rt_rtx))->code) == PLUS
  && CONST_INT_P (XEXP (XEXP (links, 0), 1))(((enum rtx_code) (((((((links)->u.fld[0]).rt_rtx))->u.
fld[1]).rt_rtx))->code) == CONST_INT))
{
  plus_cst_src = XEXP (links, 0)(((links)->u.fld[0]).rt_rtx);
  break;
}
   }
}
  }

/* Determine the effects of this insn on elimination offsets.  */
elimination_effects (old_body, VOIDmode((void) 0, E_VOIDmode));

/* Eliminate all eliminable registers occurring in operands that
   can be handled by reload.  */
extract_insn (insn);
int n_dups = recog_data.n_dups;
for (i = 0; i < n_dups; i++)
  orig_dup[i] = *recog_data.dup_loc[i];

int n_operands = recog_data.n_operands;
for (i = 0; i < n_operands; i++)
  {
    orig_operand[i] = recog_data.operand[i];

    /* For an asm statement, every operand is eliminable.  */
    if (insn_is_asm || insn_data[icode].operand[i].eliminable)
{
 bool is_set_src, in_plus;

 /* Check for setting a register that we know about.  */
 if (recog_data.operand_type[i] != OP_IN
     && REG_P (orig_operand[i])(((enum rtx_code) (orig_operand[i])->code) == REG))
   {
     /* If we are assigning to a register that can be eliminated, it
 must be as part of a PARALLEL, since the code above handles
 single SETs.  We must indicate that we can no longer
 eliminate this reg.  */
     for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))];
   ep++)
if (ep->from_rtx == orig_operand[i])
  ep->can_eliminate = 0;
   }

 /* Companion to the above plus substitution, we can allow
    invariants as the source of a plain move.  */
 is_set_src = false;
 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)(((old_set)->u.fld[1]).rt_rtx))
   is_set_src = true;
 if (is_set_src && !sets_reg_p)
   note_reg_elim_costly (SET_SRC (old_set)(((old_set)->u.fld[1]).rt_rtx), insn);
 in_plus = false;
 if (plus_src && sets_reg_p
     && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)(((plus_src)->u.fld[0]).rt_rtx)
  || recog_data.operand_loc[i] == &XEXP (plus_src, 1)(((plus_src)->u.fld[1]).rt_rtx)))
   in_plus = true;

 eliminate_regs_1 (recog_data.operand[i], VOIDmode((void) 0, E_VOIDmode),
	    NULL_RTX(rtx) 0,
	    is_set_src || in_plus, true);
 /* Terminate the search in check_eliminable_occurrences at
    this point.  */
 *recog_data.operand_loc[i] = 0;
}
  }

for (i = 0; i < n_dups; i++)
  *recog_data.dup_loc[i]
    = *recog_data.operand_loc[(int) recog_data.dup_num[i]];

/* If any eliminable remain, they aren't eliminable anymore.  */
check_eliminable_occurrences (old_body);

/* Restore the old body.  */
for (i = 0; i < n_operands; i++)
  *recog_data.operand_loc[i] = orig_operand[i];
for (i = 0; i < n_dups; i++)
  *recog_data.dup_loc[i] = orig_dup[i];

/* Update all elimination pairs to reflect the status after the current
   insn.  The changes we make were determined by the earlier call to
   elimination_effects.  */

for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
  {
    if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
ep->can_eliminate = 0;

    ep->ref_outside_mem = 0;
  }

return;
3668}
3669#pragma GCC diagnostic pop

3671/* Loop through all elimination pairs.
 Recalculate the number not at initial offset.

 Compute the maximum offset (minimum offset if the stack does not
 grow downward) for each elimination pair.  */

3677static void
3678update_eliminable_offsets (void)
3679{
struct elim_table *ep;

num_not_at_initial_offset = 0;
for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
  {
    ep->previous_offset = ep->offset;
    if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
num_not_at_initial_offset++;
  }
3689}

3691/* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
 replacement we currently believe is valid, mark it as not eliminable if X
 modifies DEST in any way other than by adding a constant integer to it.

 If DEST is the frame pointer, we do nothing because we assume that
 all assignments to the hard frame pointer are nonlocal gotos and are being
 done at a time when they are valid and do not disturb anything else.
 Some machines want to eliminate a fake argument pointer with either the
 frame or stack pointer.  Assignments to the hard frame pointer must not
 prevent this elimination.

 Called via note_stores from reload before starting its passes to scan
 the insns of the function.  */

3705static void
3706mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED__attribute__ ((__unused__)))
3707{
unsigned int i;

/* A SUBREG of a hard register here is just changing its mode.  We should
   not see a SUBREG of an eliminable hard register, but check just in
   case.  */
if (GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG)
  dest = SUBREG_REG (dest)(((dest)->u.fld[0]).rt_rtx);

if (dest == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER]))
  return;

for (i = 0; i < NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0])); i++)
  if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
&& (GET_CODE (x)((enum rtx_code) (x)->code) != SET
   || GET_CODE (SET_SRC (x))((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) != PLUS
   || XEXP (SET_SRC (x), 0)((((((x)->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx) != dest
   || !CONST_INT_P (XEXP (SET_SRC (x), 1))(((enum rtx_code) (((((((x)->u.fld[1]).rt_rtx))->u.fld[
1]).rt_rtx))->code) == CONST_INT)))
    {
reg_eliminate[i].can_eliminate_previous
 = reg_eliminate[i].can_eliminate = 0;
num_eliminable--;
    }
3730}

3732/* Verify that the initial elimination offsets did not change since the
 last call to set_initial_elim_offsets.  This is used to catch cases
 where something illegal happened during reload_as_needed that could
 cause incorrect code to be generated if we did not check for it.  */

3737static bool
3738verify_initial_elim_offsets (void)
3739{
poly_int64 t;
struct elim_table *ep;

if (!num_eliminable)
  return true;

targetm.compute_frame_layout ();
for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
  {
    INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t)((t) = ix86_initial_elimination_offset ((ep->from), (ep->
to)));
    if (maybe_ne (t, ep->initial_offset))
return false;
  }

return true;
3755}

3757/* Reset all offsets on eliminable registers to their initial values.  */

3759static void
3760set_initial_elim_offsets (void)
3761{
struct elim_table *ep = reg_eliminate;

targetm.compute_frame_layout ();
for (; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
  {
    INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset)((ep->initial_offset) = ix86_initial_elimination_offset ((
ep->from), (ep->to)));
    ep->previous_offset = ep->offset = ep->initial_offset;
  }

num_not_at_initial_offset = 0;
3772}

3774/* Subroutine of set_initial_label_offsets called via for_each_eh_label.  */

3776static void
3777set_initial_eh_label_offset (rtx label)
3778{
set_label_offsets (label, NULLnullptr, 1);
3780}

3782/* Initialize the known label offsets.
 Set a known offset for each forced label to be at the initial offset
 of each elimination.  We do this because we assume that all
 computed jumps occur from a location where each elimination is
 at its initial offset.
 For all other labels, show that we don't know the offsets.  */

3789static void
3790set_initial_label_offsets (void)
3791{
memset (offsets_known_at, 0, num_labels);

unsigned int i;
rtx_insn *insn;
FOR_EACH_VEC_SAFE_ELT (forced_labels, i, insn)for (i = 0; vec_safe_iterate ((((&x_rtl)->expr.x_forced_labels
)), (i), &(insn)); ++(i))
  set_label_offsets (insn, NULLnullptr, 1);

for (rtx_insn_list *x = nonlocal_goto_handler_labels((&x_rtl)->x_nonlocal_goto_handler_labels); x; x = x->next ())
  if (x->insn ())
    set_label_offsets (x->insn (), NULLnullptr, 1);

for_each_eh_label (set_initial_eh_label_offset);
3804}

3806/* Set all elimination offsets to the known values for the code label given
 by INSN.  */

3809static void
3810set_offsets_for_label (rtx_insn *insn)
3811{
unsigned int i;
int label_nr = CODE_LABEL_NUMBER (insn)(((insn)->u.fld[5]).rt_int);
struct elim_table *ep;

num_not_at_initial_offset = 0;
for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0])); ep++, i++)
  {
    ep->offset = ep->previous_offset
 = offsets_at[label_nr - first_label_num][i];
    if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
num_not_at_initial_offset++;
  }
3824}

3826/* See if anything that happened changes which eliminations are valid.
 For example, on the SPARC, whether or not the frame pointer can
 be eliminated can depend on what registers have been used.  We need
 not check some conditions again (such as flag_omit_frame_pointer)
 since they can't have changed.  */

3832static void
3833update_eliminables (HARD_REG_SET *pset)
3834{
int previous_frame_pointer_needed = frame_pointer_needed((&x_rtl)->frame_pointer_needed);
struct elim_table *ep;

for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
  if ((ep->from == HARD_FRAME_POINTER_REGNUM6
       && targetm.frame_pointer_required ())
|| ! targetm.can_eliminate (ep->from, ep->to)
)
    ep->can_eliminate = 0;

/* Look for the case where we have discovered that we can't replace
   register A with register B and that means that we will now be
   trying to replace register A with register C.  This means we can
   no longer replace register C with register B and we need to disable
   such an elimination, if it exists.  This occurs often with A == ap,
   B == sp, and C == fp.  */

for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
  {
    struct elim_table *op;
    int new_to = -1;

    if (! ep->can_eliminate && ep->can_eliminate_previous)
{
 /* Find the current elimination for ep->from, if there is a
    new one.  */
 for (op = reg_eliminate;
      op < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; op++)
   if (op->from == ep->from && op->can_eliminate)
     {
new_to = op->to;
break;
     }

 /* See if there is an elimination of NEW_TO -> EP->TO.  If so,
    disable it.  */
 for (op = reg_eliminate;
      op < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; op++)
   if (op->from == new_to && op->to == ep->to)
     op->can_eliminate = 0;
}
  }

/* See if any registers that we thought we could eliminate the previous
   time are no longer eliminable.  If so, something has changed and we
   must spill the register.  Also, recompute the number of eliminable
   registers and see if the frame pointer is needed; it is if there is
   no elimination of the frame pointer that we can perform.  */

frame_pointer_needed((&x_rtl)->frame_pointer_needed) = 1;
for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
  {
    if (ep->can_eliminate
 && ep->from == FRAME_POINTER_REGNUM19
 && ep->to != HARD_FRAME_POINTER_REGNUM6
 && (! SUPPORTS_STACK_ALIGNMENT((((unsigned int) 1 << 28) * 8) > ((((global_options
.x_ix86_isa_flags & (1UL << 1)) != 0) && ix86_cfun_abi
 () == MS_ABI) ? 128 : ((8) * (((global_options.x_ix86_isa_flags
 & (1UL << 1)) != 0) ? 8 : 4))))
     || ! crtl(&x_rtl)->stack_realign_needed))
frame_pointer_needed((&x_rtl)->frame_pointer_needed) = 0;

    if (! ep->can_eliminate && ep->can_eliminate_previous)
{
 ep->can_eliminate_previous = 0;
 SET_HARD_REG_BIT (*pset, ep->from);
 num_eliminable--;
}
  }

/* If we didn't need a frame pointer last time, but we do now, spill
   the hard frame pointer.  */
if (frame_pointer_needed((&x_rtl)->frame_pointer_needed) && ! previous_frame_pointer_needed)
  SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM6);
3906}

3908/* Call update_eliminables an spill any registers we can't eliminate anymore.
 Return true iff a register was spilled.  */

3911static bool
3912update_eliminables_and_spill (void)
3913{
int i;
bool did_spill = false;
HARD_REG_SET to_spill;
CLEAR_HARD_REG_SET (to_spill);
update_eliminables (&to_spill);
used_spill_regs &= ~to_spill;

for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
  if (TEST_HARD_REG_BIT (to_spill, i))
    {
spill_hard_reg (i, 1);
did_spill = true;

/* Regardless of the state of spills, if we previously had
  a register that we thought we could eliminate, but now
  cannot eliminate, we must run another pass.

  Consider pseudos which have an entry in reg_equiv_* which
  reference an eliminable register.  We must make another pass
  to update reg_equiv_* so that we do not substitute in the
  old value from when we thought the elimination could be
  performed.  */
    }
return did_spill;
3938}

3940/* Return true if X is used as the target register of an elimination.  */

3942bool
3943elimination_target_reg_p (rtx x)
3944{
struct elim_table *ep;

for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
  if (ep->to_rtx == x && ep->can_eliminate)
    return true;

return false;
3952}

3954/* Initialize the table of registers to eliminate.
 Pre-condition: global flag frame_pointer_needed has been set before
 calling this function.  */

3958static void
3959init_elim_table (void)
3960{
struct elim_table *ep;
const struct elim_table_1 *ep1;

if (!reg_eliminate)
  reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS)((struct elim_table *) xcalloc (((sizeof (reg_eliminate_1) / sizeof
 ((reg_eliminate_1)[0]))), sizeof (struct elim_table)));

num_eliminable = 0;

for (ep = reg_eliminate, ep1 = reg_eliminate_1;
     ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++, ep1++)
  {
    ep->from = ep1->from;
    ep->to = ep1->to;
    ep->can_eliminate = ep->can_eliminate_previous
= (targetm.can_eliminate (ep->from, ep->to)
  && ! (ep->to == STACK_POINTER_REGNUM7
 && frame_pointer_needed((&x_rtl)->frame_pointer_needed)
 && (! SUPPORTS_STACK_ALIGNMENT((((unsigned int) 1 << 28) * 8) > ((((global_options
.x_ix86_isa_flags & (1UL << 1)) != 0) && ix86_cfun_abi
 () == MS_ABI) ? 128 : ((8) * (((global_options.x_ix86_isa_flags
 & (1UL << 1)) != 0) ? 8 : 4))))
     || ! stack_realign_fp((&x_rtl)->stack_realign_needed && !(&x_rtl
)->need_drap))));
  }

/* Count the number of eliminable registers and build the FROM and TO
   REG rtx's.  Note that code in gen_rtx_REG will cause, e.g.,
   gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
   We depend on this.  */
for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))]; ep++)
  {
    num_eliminable += ep->can_eliminate;
    ep->from_rtx = gen_rtx_REG (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), ep->from);
    ep->to_rtx = gen_rtx_REG (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), ep->to);
  }
3992}

3994/* Find all the pseudo registers that didn't get hard regs
 but do have known equivalent constants or memory slots.
 These include parameters (known equivalent to parameter slots)
 and cse'd or loop-moved constant memory addresses.

 Record constant equivalents in reg_equiv_constant
 so they will be substituted by find_reloads.
 Record memory equivalents in reg_mem_equiv so they can
 be substituted eventually by altering the REG-rtx's.  */

4004static void
4005init_eliminable_invariants (rtx_insn *first, bool do_subregs)
4006{
int i;
rtx_insn *insn;

grow_reg_equivs ();
if (do_subregs)
  reg_max_ref_mode = XCNEWVEC (machine_mode, max_regno)((machine_mode *) xcalloc ((max_regno), sizeof (machine_mode)
));
else
  reg_max_ref_mode = NULLnullptr;

num_eliminable_invariants = 0;

first_label_num = get_first_label_num ();
num_labels = max_label_num () - first_label_num;

/* Allocate the tables used to store offset information at labels.  */
offsets_known_at = XNEWVEC (char, num_labels)((char *) xmalloc (sizeof (char) * (num_labels)));
offsets_at = (poly_int64_pod (*)[NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0]))])
  xmalloc (num_labels * NUM_ELIMINABLE_REGS(sizeof (reg_eliminate_1) / sizeof ((reg_eliminate_1)[0])) * sizeof (poly_int64));

4026/* Look for REG_EQUIV notes; record what each pseudo is equivalent
 to.  If DO_SUBREGS is true, also find all paradoxical subregs and
 find largest such for each pseudo.  FIRST is the head of the insn
 list.  */

for (insn = first; insn; insn = NEXT_INSN (insn))
  {
    rtx set = single_set (insn);

    /* We may introduce USEs that we want to remove at the end, so
we'll mark them with QImode.  Make sure there are no
previously-marked insns left by say regmove.  */
    if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)) && GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == USE
 && GET_MODE (insn)((machine_mode) (insn)->mode) != VOIDmode((void) 0, E_VOIDmode))
PUT_MODE (insn, VOIDmode((void) 0, E_VOIDmode));

    if (do_subregs && NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)))
scan_paradoxical_subregs (PATTERN (insn));

    if (set != 0 && REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 REG))
{
 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX(rtx) 0);
 rtx x;

 if (! note)
   continue;

 i = REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx)));
 x = XEXP (note, 0)(((note)->u.fld[0]).rt_rtx);

 if (i <= LAST_VIRTUAL_REGISTER(((76)) + 5))
   continue;

 /* If flag_pic and we have constant, verify it's legitimate.  */
 if (!CONSTANT_P (x)((rtx_class[(int) (((enum rtx_code) (x)->code))]) == RTX_CONST_OBJ
)
     || !flag_picglobal_options.x_flag_pic || LEGITIMATE_PIC_OPERAND_P (x)legitimate_pic_operand_p (x))
   {
     /* It can happen that a REG_EQUIV note contains a MEM
 that is not a legitimate memory operand.  As later
 stages of reload assume that all addresses found
 in the reg_equiv_* arrays were originally legitimate,
 we ignore such REG_EQUIV notes.  */
     if (memory_operand (x, VOIDmode((void) 0, E_VOIDmode)))
{
  /* Always unshare the equivalence, so we can
     substitute into this insn without touching the
       equivalence.  */
  reg_equiv_memory_loc (i)(*reg_equivs)[(i)].memory_loc = copy_rtx (x);
}
     else if (function_invariant_p (x))
{
  machine_mode mode;

  mode = GET_MODE (SET_DEST (set))((machine_mode) ((((set)->u.fld[0]).rt_rtx))->mode);
  if (GET_CODE (x)((enum rtx_code) (x)->code) == PLUS)
    {
      /* This is PLUS of frame pointer and a constant,
	 and might be shared.  Unshare it.  */
      reg_equiv_invariant (i)(*reg_equivs)[(i)].invariant = copy_rtx (x);
      num_eliminable_invariants++;
    }
  else if (x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER]) || x == arg_pointer_rtx((this_target_rtl->x_global_rtl)[GR_ARG_POINTER]))
    {
      reg_equiv_invariant (i)(*reg_equivs)[(i)].invariant = x;
      num_eliminable_invariants++;
    }
  else if (targetm.legitimate_constant_p (mode, x))
    reg_equiv_constant (i)(*reg_equivs)[(i)].constant = x;
  else
    {
      reg_equiv_memory_loc (i)(*reg_equivs)[(i)].memory_loc = force_const_mem (mode, x);
      if (! reg_equiv_memory_loc (i)(*reg_equivs)[(i)].memory_loc)
	reg_equiv_init (i)(*reg_equivs)[(i)].init = NULLnullptr;
    }
}
     else
{
  reg_equiv_init (i)(*reg_equivs)[(i)].init = NULLnullptr;
  continue;
}
   }
 else
   reg_equiv_init (i)(*reg_equivs)[(i)].init = NULLnullptr;
}
  }

if (dump_file)
  for (i = FIRST_PSEUDO_REGISTER76; i < max_regno; i++)
    if (reg_equiv_init (i)(*reg_equivs)[(i)].init)
{
 fprintf (dump_file, "init_insns for %u: ", i);
 print_inline_rtx (dump_file, reg_equiv_init (i)(*reg_equivs)[(i)].init, 20);
 fprintf (dump_file, "\n");
}
4120}

4122/* Indicate that we no longer have known memory locations or constants.
 Free all data involved in tracking these.  */

4125static void
4126free_reg_equiv (void)
4127{
int i;

free (offsets_known_at);
free (offsets_at);
offsets_at = 0;
offsets_known_at = 0;

for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
  if (reg_equiv_alt_mem_list (i)(*reg_equivs)[(i)].alt_mem_list)
    free_EXPR_LIST_list (&reg_equiv_alt_mem_list (i)(*reg_equivs)[(i)].alt_mem_list);
vec_free (reg_equivs);
4139}
4140
4141/* Kick all pseudos out of hard register REGNO.

 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
 because we found we can't eliminate some register.  In the case, no pseudos
 are allowed to be in the register, even if they are only in a block that
 doesn't require spill registers, unlike the case when we are spilling this
 hard reg to produce another spill register.

 Return nonzero if any pseudos needed to be kicked out.  */

4151static void
4152spill_hard_reg (unsigned int regno, int cant_eliminate)
4153{
int i;

if (cant_eliminate)
  {
    SET_HARD_REG_BIT (bad_spill_regs_global, regno);
    df_set_regs_ever_live (regno, true);
  }

/* Spill every pseudo reg that was allocated to this reg
   or to something that overlaps this reg.  */

for (i = FIRST_PSEUDO_REGISTER76; i < max_regno; i++)
  if (reg_renumber[i] >= 0
&& (unsigned int) reg_renumber[i] <= regno
&& end_hard_regno (PSEUDO_REGNO_MODE (i)((machine_mode) (regno_reg_rtx[i])->mode), reg_renumber[i]) > regno)
    SET_REGNO_REG_SET (&spilled_pseudos, i)bitmap_set_bit (&spilled_pseudos, i);
4170}

4172/* After spill_hard_reg was called and/or find_reload_regs was run for all
 insns that need reloads, this function is used to actually spill pseudo
 registers and try to reallocate them.  It also sets up the spill_regs
 array for use by choose_reload_regs.

 GLOBAL nonzero means we should attempt to reallocate any pseudo registers
 that we displace from hard registers.  */

4180static int
4181finish_spills (int global)
4182{
class insn_chain *chain;
int something_changed = 0;
unsigned i;
reg_set_iterator rsi;

/* Build the spill_regs array for the function.  */
/* If there are some registers still to eliminate and one of the spill regs
   wasn't ever used before, additional stack space may have to be
   allocated to store this register.  Thus, we may have changed the offset
   between the stack and frame pointers, so mark that something has changed.

   One might think that we need only set VAL to 1 if this is a call-used
   register.  However, the set of registers that must be saved by the
   prologue is not identical to the call-used set.  For example, the
   register used by the call insn for the return PC is a call-used register,
   but must be saved by the prologue.  */

n_spills = 0;
for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
  if (TEST_HARD_REG_BIT (used_spill_regs, i))
    {
spill_reg_order[i] = n_spills;
spill_regs[n_spills++] = i;
if (num_eliminable && ! df_regs_ever_live_p (i))
 something_changed = 1;
df_set_regs_ever_live (i, true);
    }
  else
    spill_reg_order[i] = -1;

EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)for (bmp_iter_set_init (&(rsi), (&spilled_pseudos), (
76), &(i)); bmp_iter_set (&(rsi), &(i)); bmp_iter_next
 (&(rsi), &(i)))
  if (reg_renumber[i] >= 0)
    {
SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
/* Mark it as no longer having a hard register home.  */
reg_renumber[i] = -1;
if (ira_conflicts_p)
 /* Inform IRA about the change.  */
 ira_mark_allocation_change (i);
/* We will need to scan everything again.  */
something_changed = 1;
    }

/* Retry global register allocation if possible.  */
if (global && ira_conflicts_p)
  {
    unsigned int n;

    memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
    /* For every insn that needs reloads, set the registers used as spill
regs in pseudo_forbidden_regs for every pseudo live across the
insn.  */
    for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
{
 EXECUTE_IF_SET_IN_REG_SETfor (bmp_iter_set_init (&(rsi), (&chain->live_throughout
), (76), &(i)); bmp_iter_set (&(rsi), &(i)); bmp_iter_next
 (&(rsi), &(i)))
   (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)for (bmp_iter_set_init (&(rsi), (&chain->live_throughout
), (76), &(i)); bmp_iter_set (&(rsi), &(i)); bmp_iter_next
 (&(rsi), &(i)))
   {
     pseudo_forbidden_regs[i] |= chain->used_spill_regs;
   }
 EXECUTE_IF_SET_IN_REG_SETfor (bmp_iter_set_init (&(rsi), (&chain->dead_or_set
), (76), &(i)); bmp_iter_set (&(rsi), &(i)); bmp_iter_next
 (&(rsi), &(i)))
   (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)for (bmp_iter_set_init (&(rsi), (&chain->dead_or_set
), (76), &(i)); bmp_iter_set (&(rsi), &(i)); bmp_iter_next
 (&(rsi), &(i)))
   {
     pseudo_forbidden_regs[i] |= chain->used_spill_regs;
   }
}

    /* Retry allocating the pseudos spilled in IRA and the
reload.  For each reg, merge the various reg sets that
indicate which hard regs can't be used, and call
ira_reassign_pseudos.  */
    for (n = 0, i = FIRST_PSEUDO_REGISTER76; i < (unsigned) max_regno; i++)
if (reg_old_renumber[i] != reg_renumber[i])
 {
   if (reg_renumber[i] < 0)
     temp_pseudo_reg_arr[n++] = i;
   else
     CLEAR_REGNO_REG_SET (&spilled_pseudos, i)bitmap_clear_bit (&spilled_pseudos, i);
 }
    if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
		bad_spill_regs_global,
		pseudo_forbidden_regs, pseudo_previous_regs,
		&spilled_pseudos))
something_changed = 1;
  }
/* Fix up the register information in the insn chain.
   This involves deleting those of the spilled pseudos which did not get
   a new hard register home from the live_{before,after} sets.  */
for (chain = reload_insn_chain; chain; chain = chain->next)
  {
    HARD_REG_SET used_by_pseudos;
    HARD_REG_SET used_by_pseudos2;

    if (! ira_conflicts_p)
{
 /* Don't do it for IRA because IRA and the reload still can
    assign hard registers to the spilled pseudos on next
    reload iterations.  */
 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos)bitmap_and_compl_into (&chain->live_throughout, &spilled_pseudos
);
 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos)bitmap_and_compl_into (&chain->dead_or_set, &spilled_pseudos
);
}
    /* Mark any unallocated hard regs as available for spills.  That
makes inheritance work somewhat better.  */
    if (chain->need_reload)
{
 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout)do { CLEAR_HARD_REG_SET (used_by_pseudos); reg_set_to_hard_reg_set
 (&used_by_pseudos, &chain->live_throughout); } while
 (0);
 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set)do { CLEAR_HARD_REG_SET (used_by_pseudos2); reg_set_to_hard_reg_set
 (&used_by_pseudos2, &chain->dead_or_set); } while
 (0);
 used_by_pseudos |= used_by_pseudos2;

 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
 /* Value of chain->used_spill_regs from previous iteration
    may be not included in the value calculated here because
    of possible removing caller-saves insns (see function
    delete_caller_save_insns.  */
 chain->used_spill_regs = ~used_by_pseudos & used_spill_regs;
}
  }

CLEAR_REG_SET (&changed_allocation_pseudos)bitmap_clear (&changed_allocation_pseudos);
/* Let alter_reg modify the reg rtx's for the modified pseudos.  */
for (i = FIRST_PSEUDO_REGISTER76; i < (unsigned)max_regno; i++)
  {
    int regno = reg_renumber[i];
    if (reg_old_renumber[i] == regno)
continue;

    SET_REGNO_REG_SET (&changed_allocation_pseudos, i)bitmap_set_bit (&changed_allocation_pseudos, i);

    alter_reg (i, reg_old_renumber[i], false);
    reg_old_renumber[i] = regno;
    if (dump_file)
{
 if (regno == -1)
   fprintf (dump_file, " Register %d now on stack.\n\n", i);
 else
   fprintf (dump_file, " Register %d now in %d.\n\n",
     i, reg_renumber[i]);
}
  }

return something_changed;
4324}
4325
4326/* Find all paradoxical subregs within X and update reg_max_ref_mode.  */

4328static void
4329scan_paradoxical_subregs (rtx x)
4330{
int i;
const char *fmt;
enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);

switch (code)
  {
  case REG:
  case CONST:
  case SYMBOL_REF:
  case LABEL_REF:
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case PC:
  case USE:
  case CLOBBER:
    return;

  case SUBREG:
    if (REG_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
))
{
 unsigned int regno = REGNO (SUBREG_REG (x))(rhs_regno((((x)->u.fld[0]).rt_rtx)));
 if (partial_subreg_p (reg_max_ref_mode[regno], GET_MODE (x)((machine_mode) (x)->mode)))
   {
     reg_max_ref_mode[regno] = GET_MODE (x)((machine_mode) (x)->mode);
     mark_home_live_1 (regno, GET_MODE (x)((machine_mode) (x)->mode));
   }
}
    return;

  default:
    break;
  }

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'e')
scan_paradoxical_subregs (XEXP (x, i)(((x)->u.fld[i]).rt_rtx));
    else if (fmt[i] == 'E')
{
 int j;
 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
   scan_paradoxical_subregs (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]));
}
  }
4375}

4377/* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
 If *OP_PTR is a paradoxical subreg, try to remove that subreg
 and apply the corresponding narrowing subreg to *OTHER_PTR.
 Return true if the operands were changed, false otherwise.  */

4382static bool
4383strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4384{
rtx op, inner, other, tem;

op = *op_ptr;
if (!paradoxical_subreg_p (op))
  return false;
inner = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);

other = *other_ptr;
tem = gen_lowpart_common (GET_MODE (inner)((machine_mode) (inner)->mode), other);
if (!tem)
  return false;

/* If the lowpart operation turned a hard register into a subreg,
   rather than simplifying it to another hard register, then the
   mode change cannot be properly represented.  For example, OTHER
   might be valid in its current mode, but not in the new one.  */
if (GET_CODE (tem)((enum rtx_code) (tem)->code) == SUBREG
    && REG_P (other)(((enum rtx_code) (other)->code) == REG)
    && HARD_REGISTER_P (other)((((rhs_regno(other))) < 76)))
  return false;

*op_ptr = inner;
*other_ptr = tem;
return true;
4409}
4410
4411/* A subroutine of reload_as_needed.  If INSN has a REG_EH_REGION note,
 examine all of the reload insns between PREV and NEXT exclusive, and
 annotate all that may trap.  */

4415static void
4416fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4417{
rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX(rtx) 0);
if (note == NULLnullptr)
  return;
if (!insn_could_throw_p (insn))
  remove_note (insn, note);
copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4424}

4426/* Reload pseudo-registers into hard regs around each insn as needed.
 Additional register load insns are output before the insn that needs it
 and perhaps store insns after insns that modify the reloaded pseudo reg.

 reg_last_reload_reg and reg_reloaded_contents keep track of
 which registers are already available in reload registers.
 We update these for the reloads that we perform,
 as the insns are scanned.  */

4435static void
4436reload_as_needed (int live_known)
4437{
class insn_chain *chain;
4439#if AUTO_INC_DEC0
int i;
4441#endif
rtx_note *marker;

memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
memset (spill_reg_store, 0, sizeof spill_reg_store);
reg_last_reload_reg = XCNEWVEC (rtx, max_regno)((rtx *) xcalloc ((max_regno), sizeof (rtx)));
INIT_REG_SET (&reg_has_output_reload)bitmap_initialize (&reg_has_output_reload, &reg_obstack
);
CLEAR_HARD_REG_SET (reg_reloaded_valid);

set_initial_elim_offsets ();

/* Generate a marker insn that we will move around.  */
marker = emit_note (NOTE_INSN_DELETED);
unlink_insn_chain (marker, marker);

for (chain = reload_insn_chain; chain; chain = chain->next)
  {
    rtx_insn *prev = 0;
    rtx_insn *insn = chain->insn;
    rtx_insn *old_next = NEXT_INSN (insn);
4461#if AUTO_INC_DEC0
    rtx_insn *old_prev = PREV_INSN (insn);
4463#endif

    if (will_delete_init_insn_p (insn))
continue;

    /* If we pass a label, copy the offsets from the label information
into the current offsets of each elimination.  */
    if (LABEL_P (insn)(((enum rtx_code) (insn)->code) == CODE_LABEL))
set_offsets_for_label (insn);

    else if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
{
 regset_head regs_to_forget;
 INIT_REG_SET (&regs_to_forget)bitmap_initialize (&regs_to_forget, &reg_obstack);
 note_stores (insn, forget_old_reloads_1, &regs_to_forget);

 /* If this is a USE and CLOBBER of a MEM, ensure that any
    references to eliminable registers have been removed.  */

 if ((GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == USE
      || GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == CLOBBER)
     && MEM_P (XEXP (PATTERN (insn), 0))(((enum rtx_code) ((((PATTERN (insn))->u.fld[0]).rt_rtx))->
code) == MEM))
   XEXP (XEXP (PATTERN (insn), 0), 0)((((((PATTERN (insn))->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx
)
     = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0)((((((PATTERN (insn))->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx
),
		GET_MODE (XEXP (PATTERN (insn), 0))((machine_mode) ((((PATTERN (insn))->u.fld[0]).rt_rtx))->
mode),
		NULL_RTX(rtx) 0);

 /* If we need to do register elimination processing, do so.
    This might delete the insn, in which case we are done.  */
 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
   {
     eliminate_regs_in_insn (insn, 1);
     if (NOTE_P (insn)(((enum rtx_code) (insn)->code) == NOTE))
{
  update_eliminable_offsets ();
  CLEAR_REG_SET (&regs_to_forget)bitmap_clear (&regs_to_forget);
  continue;
}
   }

 /* If need_elim is nonzero but need_reload is zero, one might think
    that we could simply set n_reloads to 0.  However, find_reloads
    could have done some manipulation of the insn (such as swapping
    commutative operands), and these manipulations are lost during
    the first pass for every insn that needs register elimination.
    So the actions of find_reloads must be redone here.  */

 if (! chain->need_elim && ! chain->need_reload
     && ! chain->need_operand_change)
   n_reloads = 0;
 /* First find the pseudo regs that must be reloaded for this insn.
    This info is returned in the tables reload_... (see reload.h).
    Also modify the body of INSN by substituting RELOAD
    rtx's for those pseudo regs.  */
 else
   {
     CLEAR_REG_SET (&reg_has_output_reload)bitmap_clear (&reg_has_output_reload);
     CLEAR_HARD_REG_SET (reg_is_output_reload);

     find_reloads (insn, 1, spill_indirect_levels(this_target_reload->x_spill_indirect_levels), live_known,
	    spill_reg_order);
   }

 if (n_reloads > 0)
   {
     rtx_insn *next = NEXT_INSN (insn);

     /* ??? PREV can get deleted by reload inheritance.
 Work around this by emitting a marker note.  */
     prev = PREV_INSN (insn);
     reorder_insns_nobb (marker, marker, prev);

     /* Now compute which reload regs to reload them into.  Perhaps
 reusing reload regs from previous insns, or else output
 load insns to reload them.  Maybe output store insns too.
 Record the choices of reload reg in reload_reg_rtx.  */
     choose_reload_regs (chain);

     /* Generate the insns to reload operands into or out of
 their reload regs.  */
     emit_reload_insns (chain);

     /* Substitute the chosen reload regs from reload_reg_rtx
 into the insn's body (or perhaps into the bodies of other
 load and store insn that we just made for reloading
 and that we moved the structure into).  */
     subst_reloads (insn);

     prev = PREV_INSN (marker);
     unlink_insn_chain (marker, marker);

     /* Adjust the exception region notes for loads and stores.  */
     if (cfun(cfun + 0)->can_throw_non_call_exceptions && !CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
fixup_eh_region_note (insn, prev, next);

     /* Adjust the location of REG_ARGS_SIZE.  */
     rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX(rtx) 0);
     if (p)
{
  remove_note (insn, p);
  fixup_args_size_notes (prev, PREV_INSN (next),
			 get_args_size (p));
}

     /* If this was an ASM, make sure that all the reload insns
 we have generated are valid.  If not, give an error
 and delete them.  */
     if (asm_noperands (PATTERN (insn)) >= 0)
for (rtx_insn *p = NEXT_INSN (prev);
     p != next;
     p = NEXT_INSN (p))
  if (p != insn && INSN_P (p)(((((enum rtx_code) (p)->code) == INSN) || (((enum rtx_code
) (p)->code) == JUMP_INSN) || (((enum rtx_code) (p)->code
) == CALL_INSN)) || (((enum rtx_code) (p)->code) == DEBUG_INSN
))
      && GET_CODE (PATTERN (p))((enum rtx_code) (PATTERN (p))->code) != USE
      && (recog_memoized (p) < 0
	  || (extract_insn (p),
	      !(constrain_operands (1,
		  get_enabled_alternatives (p))))))
    {
      error_for_asm (insn,
		     "%<asm%> operand requires "
		     "impossible reload");
      delete_insn (p);
    }
   }

 if (num_eliminable && chain->need_elim)
   update_eliminable_offsets ();

 /* Any previously reloaded spilled pseudo reg, stored in this insn,
    is no longer validly lying around to save a future reload.
    Note that this does not detect pseudos that were reloaded
    for this insn in order to be stored in
    (obeying register constraints).  That is correct; such reload
    registers ARE still valid.  */
 forget_marked_reloads (&regs_to_forget);
 CLEAR_REG_SET (&regs_to_forget)bitmap_clear (&regs_to_forget);

 /* There may have been CLOBBER insns placed after INSN.  So scan
    between INSN and NEXT and use them to forget old reloads.  */
 for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
   if (NONJUMP_INSN_P (x)(((enum rtx_code) (x)->code) == INSN) && GET_CODE (PATTERN (x))((enum rtx_code) (PATTERN (x))->code) == CLOBBER)
     note_stores (x, forget_old_reloads_1, NULLnullptr);

4606#if AUTO_INC_DEC0
 /* Likewise for regs altered by auto-increment in this insn.
    REG_INC notes have been changed by reloading:
    find_reloads_address_1 records substitutions for them,
    which have been performed by subst_reloads above.  */
 for (i = n_reloads - 1; i >= 0; i--)
   {
     rtx in_reg = rld[i].in_reg;
     if (in_reg)
{
  enum rtx_code code = GET_CODE (in_reg)((enum rtx_code) (in_reg)->code);
  /* PRE_INC / PRE_DEC will have the reload register ending up
     with the same value as the stack slot, but that doesn't
     hold true for POST_INC / POST_DEC.  Either we have to
     convert the memory access to a true POST_INC / POST_DEC,
     or we can't use the reload register for inheritance.  */
  if ((code == POST_INC || code == POST_DEC)
      && TEST_HARD_REG_BIT (reg_reloaded_valid,
			    REGNO (rld[i].reg_rtx)(rhs_regno(rld[i].reg_rtx)))
      /* Make sure it is the inc/dec pseudo, and not
	 some other (e.g. output operand) pseudo.  */
      && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)(rhs_regno(rld[i].reg_rtx))]
	  == REGNO (XEXP (in_reg, 0))(rhs_regno((((in_reg)->u.fld[0]).rt_rtx)))))

    {
      rtx reload_reg = rld[i].reg_rtx;
      machine_mode mode = GET_MODE (reload_reg)((machine_mode) (reload_reg)->mode);
      int n = 0;
      rtx_insn *p;

      for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
	{
	  /* We really want to ignore REG_INC notes here, so
	     use PATTERN (p) as argument to reg_set_p .  */
	  if (reg_set_p (reload_reg, PATTERN (p)))
	    break;
	  n = count_occurrences (PATTERN (p), reload_reg, 0);
	  if (! n)
	    continue;
	  if (n == 1)
	    {
	      rtx replace_reg
		= gen_rtx_fmt_e (code, mode, reload_reg)gen_rtx_fmt_e_stat ((code), (mode), (reload_reg) );

	      validate_replace_rtx_group (reload_reg,
					  replace_reg, p);
	      n = verify_changes (0);

	      /* We must also verify that the constraints
		 are met after the replacement.  Make sure
		 extract_insn is only called for an insn
		 where the replacements were found to be
		 valid so far. */
	      if (n)
		{
		  extract_insn (p);
		  n = constrain_operands (1,
		    get_enabled_alternatives (p));
		}

	      /* If the constraints were not met, then
		 undo the replacement, else confirm it.  */
	      if (!n)
		cancel_changes (0);
	      else
		confirm_change_group ();
	    }
	  break;
	}
      if (n == 1)
	{
	  add_reg_note (p, REG_INC, reload_reg);
	  /* Mark this as having an output reload so that the
	     REG_INC processing code below won't invalidate
	     the reload for inheritance.  */
	  SET_HARD_REG_BIT (reg_is_output_reload,
			    REGNO (reload_reg)(rhs_regno(reload_reg)));
	  SET_REGNO_REG_SET (&reg_has_output_reload,bitmap_set_bit (&reg_has_output_reload, (rhs_regno((((in_reg
)->u.fld[0]).rt_rtx))))
			     REGNO (XEXP (in_reg, 0)))bitmap_set_bit (&reg_has_output_reload, (rhs_regno((((in_reg
)->u.fld[0]).rt_rtx))));
	}
      else
	forget_old_reloads_1 (XEXP (in_reg, 0)(((in_reg)->u.fld[0]).rt_rtx), NULL_RTX(rtx) 0,
			      NULLnullptr);
    }
  else if ((code == PRE_INC || code == PRE_DEC)
	   && TEST_HARD_REG_BIT (reg_reloaded_valid,
				 REGNO (rld[i].reg_rtx)(rhs_regno(rld[i].reg_rtx)))
	   /* Make sure it is the inc/dec pseudo, and not
	      some other (e.g. output operand) pseudo.  */
	   && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)(rhs_regno(rld[i].reg_rtx))]
	       == REGNO (XEXP (in_reg, 0))(rhs_regno((((in_reg)->u.fld[0]).rt_rtx)))))
    {
      SET_HARD_REG_BIT (reg_is_output_reload,
			REGNO (rld[i].reg_rtx)(rhs_regno(rld[i].reg_rtx)));
      SET_REGNO_REG_SET (&reg_has_output_reload,bitmap_set_bit (&reg_has_output_reload, (rhs_regno((((in_reg
)->u.fld[0]).rt_rtx))))
			 REGNO (XEXP (in_reg, 0)))bitmap_set_bit (&reg_has_output_reload, (rhs_regno((((in_reg
)->u.fld[0]).rt_rtx))));
    }
  else if (code == PRE_INC || code == PRE_DEC
	   || code == POST_INC || code == POST_DEC)
    {
      int in_regno = REGNO (XEXP (in_reg, 0))(rhs_regno((((in_reg)->u.fld[0]).rt_rtx)));

      if (reg_last_reload_reg[in_regno] != NULL_RTX(rtx) 0)
	{
	  int in_hard_regno;
	  bool forget_p = true;

	  in_hard_regno = REGNO (reg_last_reload_reg[in_regno])(rhs_regno(reg_last_reload_reg[in_regno]));
	  if (TEST_HARD_REG_BIT (reg_reloaded_valid,
				 in_hard_regno))
	    {
	      for (rtx_insn *x = (old_prev ?
				  NEXT_INSN (old_prev) : insn);
		   x != old_next;
		   x = NEXT_INSN (x))
		if (x == reg_reloaded_insn[in_hard_regno])
		  {
		    forget_p = false;
		    break;
		  }
	    }
	  /* If for some reasons, we didn't set up
	     reg_last_reload_reg in this insn,
	     invalidate inheritance from previous
	     insns for the incremented/decremented
	     register.  Such registers will be not in
	     reg_has_output_reload.  Invalidate it
	     also if the corresponding element in
	     reg_reloaded_insn is also
	     invalidated.  */
	  if (forget_p)
	    forget_old_reloads_1 (XEXP (in_reg, 0)(((in_reg)->u.fld[0]).rt_rtx),
				  NULL_RTX(rtx) 0, NULLnullptr);
	}
    }
}
   }
 /* If a pseudo that got a hard register is auto-incremented,
    we must purge records of copying it into pseudos without
    hard registers.  */
 for (rtx x = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); x; x = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
   if (REG_NOTE_KIND (x)((enum reg_note) ((machine_mode) (x)->mode)) == REG_INC)
     {
/* See if this pseudo reg was reloaded in this insn.
   If so, its last-reload info is still valid
   because it is based on this insn's reload.  */
for (i = 0; i < n_reloads; i++)
  if (rld[i].out == XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
    break;

if (i == n_reloads)
  forget_old_reloads_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), NULL_RTX(rtx) 0, NULLnullptr);
     }
4759#endif
}
    /* A reload reg's contents are unknown after a label.  */
    if (LABEL_P (insn)(((enum rtx_code) (insn)->code) == CODE_LABEL))
CLEAR_HARD_REG_SET (reg_reloaded_valid);

    /* Don't assume a reload reg is still good after a call insn
if it is a call-used reg, or if it contains a value that will
       be partially clobbered by the call.  */
    else if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
{
 reg_reloaded_valid
   &= ~insn_callee_abi (insn).full_and_partial_reg_clobbers ();

 /* If this is a call to a setjmp-type function, we must not
    reuse any reload reg contents across the call; that will
    just be clobbered by other uses of the register in later
    code, before the longjmp.  */
 if (find_reg_note (insn, REG_SETJMP, NULL_RTX(rtx) 0))
   CLEAR_HARD_REG_SET (reg_reloaded_valid);
}
  }

/* Clean up.  */
free (reg_last_reload_reg);
CLEAR_REG_SET (&reg_has_output_reload)bitmap_clear (&reg_has_output_reload);
4785}

4787/* Discard all record of any value reloaded from X,
 or reloaded in X from someplace else;
 unless X is an output reload reg of the current insn.

 X may be a hard reg (the reload reg)
 or it may be a pseudo reg that was reloaded from.

 When DATA is non-NULL just mark the registers in regset
 to be forgotten later.  */

4797static void
4798forget_old_reloads_1 (rtx x, const_rtx, void *data)
4799{
unsigned int regno;
unsigned int nr;
regset regs = (regset) data;

/* note_stores does give us subregs of hard regs,
   subreg_regno_offset requires a hard reg.  */
while (GET_CODE (x)((enum rtx_code) (x)->code) == SUBREG)
  {
    /* We ignore the subreg offset when calculating the regno,
because we are using the entire underlying hard register
below.  */
    x = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
  }

if (!REG_P (x)(((enum rtx_code) (x)->code) == REG))
  return;

regno = REGNO (x)(rhs_regno(x));

if (regno >= FIRST_PSEUDO_REGISTER76)
  nr = 1;
else
  {
    unsigned int i;

    nr = REG_NREGS (x)((&(x)->u.reg)->nregs);
    /* Storing into a spilled-reg invalidates its contents.
This can happen if a block-local pseudo is allocated to that reg
and it wasn't spilled because this block's total need is 0.
Then some insn might have an optional reload and use this reg.  */
    if (!regs)
for (i = 0; i < nr; i++)
 /* But don't do this if the reg actually serves as an output
    reload reg in the current instruction.  */
 if (n_reloads == 0
     || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
   {
     CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
     spill_reg_store[regno + i] = 0;
   }
  }

if (regs)
  while (nr-- > 0)
    SET_REGNO_REG_SET (regs, regno + nr)bitmap_set_bit (regs, regno + nr);
else
  {
    /* Since value of X has changed,
forget any value previously copied from it.  */

    while (nr-- > 0)
/* But don't forget a copy if this is the output reload
  that establishes the copy's validity.  */
if (n_reloads == 0
   || !REGNO_REG_SET_P (&reg_has_output_reload, regno + nr)bitmap_bit_p (&reg_has_output_reload, regno + nr))
 reg_last_reload_reg[regno + nr] = 0;
   }
4857}

4859/* Forget the reloads marked in regset by previous function.  */
4860static void
4861forget_marked_reloads (regset regs)
4862{
unsigned int reg;
reg_set_iterator rsi;
EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)for (bmp_iter_set_init (&(rsi), (regs), (0), &(reg));
 bmp_iter_set (&(rsi), &(reg)); bmp_iter_next (&(
rsi), &(reg)))
  {
    if (reg < FIRST_PSEUDO_REGISTER76
 /* But don't do this if the reg actually serves as an output
    reload reg in the current instruction.  */
 && (n_reloads == 0
     || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
 {
   CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
   spill_reg_store[reg] = 0;
 }
    if (n_reloads == 0
 || !REGNO_REG_SET_P (&reg_has_output_reload, reg)bitmap_bit_p (&reg_has_output_reload, reg))
reg_last_reload_reg[reg] = 0;
  }
4880}
4881
4882/* The following HARD_REG_SETs indicate when each hard register is
 used for a reload of various parts of the current insn.  */

4885/* If reg is unavailable for all reloads.  */
4886static HARD_REG_SET reload_reg_unavailable;
4887/* If reg is in use as a reload reg for a RELOAD_OTHER reload.  */
4888static HARD_REG_SET reload_reg_used;
4889/* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I.  */
4890static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS30];
4891/* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I.  */
4892static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS30];
4893/* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I.  */
4894static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS30];
4895/* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I.  */
4896static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS30];
4897/* If reg is in use for a RELOAD_FOR_INPUT reload for operand I.  */
4898static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS30];
4899/* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I.  */
4900static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS30];
4901/* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload.  */
4902static HARD_REG_SET reload_reg_used_in_op_addr;
4903/* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload.  */
4904static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4905/* If reg is in use for a RELOAD_FOR_INSN reload.  */
4906static HARD_REG_SET reload_reg_used_in_insn;
4907/* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload.  */
4908static HARD_REG_SET reload_reg_used_in_other_addr;

4910/* If reg is in use as a reload reg for any sort of reload.  */
4911static HARD_REG_SET reload_reg_used_at_all;

4913/* If reg is use as an inherited reload.  We just mark the first register
 in the group.  */
4915static HARD_REG_SET reload_reg_used_for_inherit;

4917/* Records which hard regs are used in any way, either as explicit use or
 by being allocated to a pseudo during any point of the current insn.  */
4919static HARD_REG_SET reg_used_in_insn;

4921/* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
 TYPE. MODE is used to indicate how many consecutive regs are
 actually used.  */

4925static void
4926mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
	machine_mode mode)
4928{
switch (type)
  {
  case RELOAD_OTHER:
    add_to_hard_reg_set (&reload_reg_used, mode, regno);
    break;

  case RELOAD_FOR_INPUT_ADDRESS:
    add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
    break;

  case RELOAD_FOR_INPADDR_ADDRESS:
    add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
    break;

  case RELOAD_FOR_OUTPUT_ADDRESS:
    add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
    break;

  case RELOAD_FOR_OUTADDR_ADDRESS:
    add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
    break;

  case RELOAD_FOR_OPERAND_ADDRESS:
    add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
    break;

  case RELOAD_FOR_OPADDR_ADDR:
    add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
    break;

  case RELOAD_FOR_OTHER_ADDRESS:
    add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
    break;

  case RELOAD_FOR_INPUT:
    add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
    break;

  case RELOAD_FOR_OUTPUT:
    add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
    break;

  case RELOAD_FOR_INSN:
    add_to_hard_reg_set (&reload_reg_used_in_insn,  mode, regno);
    break;
  }

add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
4977}

4979/* Similarly, but show REGNO is no longer in use for a reload.  */

4981static void
4982clear_reload_reg_in_use (unsigned int regno, int opnum,
	 enum reload_type type, machine_mode mode)
4984{
unsigned int nregs = hard_regno_nregs (regno, mode);
unsigned int start_regno, end_regno, r;
int i;
/* A complication is that for some reload types, inheritance might
   allow multiple reloads of the same types to share a reload register.
   We set check_opnum if we have to check only reloads with the same
   operand number, and check_any if we have to check all reloads.  */
int check_opnum = 0;
int check_any = 0;
HARD_REG_SET *used_in_set;

switch (type)
  {
  case RELOAD_OTHER:
    used_in_set = &reload_reg_used;
    break;

  case RELOAD_FOR_INPUT_ADDRESS:
    used_in_set = &reload_reg_used_in_input_addr[opnum];
    break;

  case RELOAD_FOR_INPADDR_ADDRESS:
    check_opnum = 1;
    used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
    break;

  case RELOAD_FOR_OUTPUT_ADDRESS:
    used_in_set = &reload_reg_used_in_output_addr[opnum];
    break;

  case RELOAD_FOR_OUTADDR_ADDRESS:
    check_opnum = 1;
    used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
    break;

  case RELOAD_FOR_OPERAND_ADDRESS:
    used_in_set = &reload_reg_used_in_op_addr;
    break;

  case RELOAD_FOR_OPADDR_ADDR:
    check_any = 1;
    used_in_set = &reload_reg_used_in_op_addr_reload;
    break;

  case RELOAD_FOR_OTHER_ADDRESS:
    used_in_set = &reload_reg_used_in_other_addr;
    check_any = 1;
    break;

  case RELOAD_FOR_INPUT:
    used_in_set = &reload_reg_used_in_input[opnum];
    break;

  case RELOAD_FOR_OUTPUT:
    used_in_set = &reload_reg_used_in_output[opnum];
    break;

  case RELOAD_FOR_INSN:
    used_in_set = &reload_reg_used_in_insn;
    break;
  default:
    gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 5046, __FUNCTION__));
  }
/* We resolve conflicts with remaining reloads of the same type by
   excluding the intervals of reload registers by them from the
   interval of freed reload registers.  Since we only keep track of
   one set of interval bounds, we might have to exclude somewhat
   more than what would be necessary if we used a HARD_REG_SET here.
   But this should only happen very infrequently, so there should
   be no reason to worry about it.  */

start_regno = regno;
end_regno = regno + nregs;
if (check_opnum || check_any)
  {
    for (i = n_reloads - 1; i >= 0; i--)
{
 if (rld[i].when_needed == type
     && (check_any || rld[i].opnum == opnum)
     && rld[i].reg_rtx)
   {
     unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
     unsigned int conflict_end
= end_hard_regno (rld[i].mode, conflict_start);

     /* If there is an overlap with the first to-be-freed register,
 adjust the interval start.  */
     if (conflict_start <= start_regno && conflict_end > start_regno)
start_regno = conflict_end;
     /* Otherwise, if there is a conflict with one of the other
 to-be-freed registers, adjust the interval end.  */
     if (conflict_start > start_regno && conflict_start < end_regno)
end_regno = conflict_start;
   }
}
  }

for (r = start_regno; r < end_regno; r++)
  CLEAR_HARD_REG_BIT (*used_in_set, r);
5084}

5086/* 1 if reg REGNO is free as a reload reg for a reload of the sort
 specified by OPNUM and TYPE.  */

5089static int
5090reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5091{
int i;

/* In use for a RELOAD_OTHER means it's not available for anything.  */
if (TEST_HARD_REG_BIT (reload_reg_used, regno)
    || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
  return 0;

switch (type)
  {
  case RELOAD_OTHER:
    /* In use for anything means we can't use it for RELOAD_OTHER.  */
    if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
return 0;

    for (i = 0; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
 return 0;

    return 1;

  case RELOAD_FOR_INPUT:
    if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
return 0;

    if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
return 0;

    /* If it is used for some other input, can't use it.  */
    for (i = 0; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
 return 0;

    /* If it is used in a later operand's address, can't use it.  */
    for (i = opnum + 1; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
 return 0;

    return 1;

  case RELOAD_FOR_INPUT_ADDRESS:
    /* Can't use a register if it is used for an input address for this
operand or used as an input in an earlier one.  */
    if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
return 0;

    for (i = 0; i < opnum; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
 return 0;

    return 1;

  case RELOAD_FOR_INPADDR_ADDRESS:
    /* Can't use a register if it is used for an input address
for this operand or used as an input in an earlier
one.  */
    if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
return 0;

    for (i = 0; i < opnum; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
 return 0;

    return 1;

  case RELOAD_FOR_OUTPUT_ADDRESS:
    /* Can't use a register if it is used for an output address for this
operand or used as an output in this or a later operand.  Note
that multiple output operands are emitted in reverse order, so
the conflicting ones are those with lower indices.  */
    if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
return 0;

    for (i = 0; i <= opnum; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
 return 0;

    return 1;

  case RELOAD_FOR_OUTADDR_ADDRESS:
    /* Can't use a register if it is used for an output address
for this operand or used as an output in this or a
later operand.  Note that multiple output operands are
emitted in reverse order, so the conflicting ones are
those with lower indices.  */
    if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
return 0;

    for (i = 0; i <= opnum; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
 return 0;

    return 1;

  case RELOAD_FOR_OPERAND_ADDRESS:
    for (i = 0; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
 return 0;

    return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
     && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));

  case RELOAD_FOR_OPADDR_ADDR:
    for (i = 0; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
 return 0;

    return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));

  case RELOAD_FOR_OUTPUT:
    /* This cannot share a register with RELOAD_FOR_INSN reloads, other
outputs, or an operand address for this or an earlier output.
Note that multiple output operands are emitted in reverse order,
so the conflicting ones are those with higher indices.  */
    if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
return 0;

    for (i = 0; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
 return 0;

    for (i = opnum; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
 return 0;

    return 1;

  case RELOAD_FOR_INSN:
    for (i = 0; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
 return 0;

    return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
     && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));

  case RELOAD_FOR_OTHER_ADDRESS:
    return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);

  default:
    gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 5243, __FUNCTION__));
  }
5245}

5247/* Return 1 if the value in reload reg REGNO, as used by the reload with
 the number RELOADNUM, is still available in REGNO at the end of the insn.

 We can assume that the reload reg was already tested for availability
 at the time it is needed, and we should not check this again,
 in case the reg has already been marked in use.  */

5254static int
5255reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5256{
int opnum = rld[reloadnum].opnum;
enum reload_type type = rld[reloadnum].when_needed;
int i;

/* See if there is a reload with the same type for this operand, using
   the same register. This case is not handled by the code below.  */
for (i = reloadnum + 1; i < n_reloads; i++)
  {
    rtx reg;

    if (rld[i].opnum != opnum || rld[i].when_needed != type)
continue;
    reg = rld[i].reg_rtx;
    if (reg == NULL_RTX(rtx) 0)
continue;
    if (regno >= REGNO (reg)(rhs_regno(reg)) && regno < END_REGNO (reg))
return 0;
  }

switch (type)
  {
  case RELOAD_OTHER:
    /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
its value must reach the end.  */
    return 1;

    /* If this use is for part of the insn,
its value reaches if no subsequent part uses the same register.
Just like the above function, don't try to do this with lots
of fallthroughs.  */

  case RELOAD_FOR_OTHER_ADDRESS:
    /* Here we check for everything else, since these don't conflict
with anything else and everything comes later.  */

    for (i = 0; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
 return 0;

    return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
     && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
     && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
     && ! TEST_HARD_REG_BIT (reload_reg_used, regno));

  case RELOAD_FOR_INPUT_ADDRESS:
  case RELOAD_FOR_INPADDR_ADDRESS:
    /* Similar, except that we check only for this and subsequent inputs
and the address of only subsequent inputs and we do not need
to check for RELOAD_OTHER objects since they are known not to
conflict.  */

    for (i = opnum; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
 return 0;

    /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
could be killed if the register is also used by reload with type
RELOAD_FOR_INPUT_ADDRESS, so check it.  */
    if (type == RELOAD_FOR_INPADDR_ADDRESS
 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
return 0;

    for (i = opnum + 1; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
 return 0;

    for (i = 0; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
 return 0;

    if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
return 0;

    return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
     && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
     && !TEST_HARD_REG_BIT (reload_reg_used, regno));

  case RELOAD_FOR_INPUT:
    /* Similar to input address, except we start at the next operand for
both input and input address and we do not check for
RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
would conflict.  */

    for (i = opnum + 1; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
 return 0;

    /* ... fall through ...  */

  case RELOAD_FOR_OPERAND_ADDRESS:
    /* Check outputs and their addresses.  */

    for (i = 0; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
 return 0;

    return (!TEST_HARD_REG_BIT (reload_reg_used, regno));

  case RELOAD_FOR_OPADDR_ADDR:
    for (i = 0; i < reload_n_operands; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
 return 0;

    return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
     && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
     && !TEST_HARD_REG_BIT (reload_reg_used, regno));

  case RELOAD_FOR_INSN:
    /* These conflict with other outputs with RELOAD_OTHER.  So
we need only check for output addresses.  */

    opnum = reload_n_operands;

    /* fall through */

  case RELOAD_FOR_OUTPUT:
  case RELOAD_FOR_OUTPUT_ADDRESS:
  case RELOAD_FOR_OUTADDR_ADDRESS:
    /* We already know these can't conflict with a later output.  So the
only thing to check are later output addresses.
Note that multiple output operands are emitted in reverse order,
so the conflicting ones are those with lower indices.  */
    for (i = 0; i < opnum; i++)
if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
   || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
 return 0;

    /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
could be killed if the register is also used by reload with type
RELOAD_FOR_OUTPUT_ADDRESS, so check it.  */
    if (type == RELOAD_FOR_OUTADDR_ADDRESS
 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
return 0;

    return 1;

  default:
    gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 5408, __FUNCTION__));
  }
5410}

5412/* Like reload_reg_reaches_end_p, but check that the condition holds for
 every register in REG.  */

5415static bool
5416reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5417{
unsigned int i;

for (i = REGNO (reg)(rhs_regno(reg)); i < END_REGNO (reg); i++)
  if (!reload_reg_reaches_end_p (i, reloadnum))
    return false;
return true;
5424}
5425

5427/*  Returns whether R1 and R2 are uniquely chained: the value of one
  is used by the other, and that value is not used by any other
  reload for this insn.  This is used to partially undo the decision
  made in find_reloads when in the case of multiple
  RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
  RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
  reloads.  This code tries to avoid the conflict created by that
  change.  It might be cleaner to explicitly keep track of which
  RELOAD_FOR_OPADDR_ADDR reload is associated with which
  RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
  this after the fact. */
5438static bool
5439reloads_unique_chain_p (int r1, int r2)
5440{
int i;

/* We only check input reloads.  */
if (! rld[r1].in || ! rld[r2].in)
  return false;

/* Avoid anything with output reloads.  */
if (rld[r1].out || rld[r2].out)
  return false;

/* "chained" means one reload is a component of the other reload,
   not the same as the other reload.  */
if (rld[r1].opnum != rld[r2].opnum
    || rtx_equal_p (rld[r1].in, rld[r2].in)
    || rld[r1].optional || rld[r2].optional
    || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
   || reg_mentioned_p (rld[r2].in, rld[r1].in)))
  return false;

/* The following loop assumes that r1 is the reload that feeds r2.  */
if (r1 > r2)
  std::swap (r1, r2);

for (i = 0; i < n_reloads; i ++)
  /* Look for input reloads that aren't our two */
  if (i != r1 && i != r2 && rld[i].in)
    {
/* If our reload is mentioned at all, it isn't a simple chain.  */
if (reg_mentioned_p (rld[r1].in, rld[i].in))
 return false;
    }
return true;
5473}

5475/* The recursive function change all occurrences of WHAT in *WHERE
 to REPL.  */
5477static void
5478substitute (rtx *where, const_rtx what, rtx repl)
5479{
const char *fmt;
int i;
enum rtx_code code;

if (*where == 0)
  return;

if (*where == what || rtx_equal_p (*where, what))
  {
    /* Record the location of the changed rtx.  */
    substitute_stack.safe_push (where);
    *where = repl;
    return;
  }

code = GET_CODE (*where)((enum rtx_code) (*where)->code);
fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'E')
{
 int j;

 for (j = XVECLEN (*where, i)(((((*where)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
   substitute (&XVECEXP (*where, i, j)(((((*where)->u.fld[i]).rt_rtvec))->elem[j]), what, repl);
}
    else if (fmt[i] == 'e')
substitute (&XEXP (*where, i)(((*where)->u.fld[i]).rt_rtx), what, repl);
  }
5509}

5511/* The function returns TRUE if chain of reload R1 and R2 (in any
 order) can be evaluated without usage of intermediate register for
 the reload containing another reload.  It is important to see
 gen_reload to understand what the function is trying to do.  As an
 example, let us have reload chain

    r2: const
    r1: <something> + const

 and reload R2 got reload reg HR.  The function returns true if
 there is a correct insn HR = HR + <something>.  Otherwise,
 gen_reload will use intermediate register (and this is the reload
 reg for R1) to reload <something>.

 We need this function to find a conflict for chain reloads.  In our
 example, if HR = HR + <something> is incorrect insn, then we cannot
 use HR as a reload register for R2.  If we do use it then we get a
 wrong code:

    HR = const
    HR = <something>
    HR = HR + HR

5534*/
5535static bool
5536gen_reload_chain_without_interm_reg_p (int r1, int r2)
5537{
/* Assume other cases in gen_reload are not possible for
   chain reloads or do need an intermediate hard registers.  */
bool result = true;
int regno, code;
rtx out, in;
rtx_insn *insn;
rtx_insn *last = get_last_insn ();

/* Make r2 a component of r1.  */
if (reg_mentioned_p (rld[r1].in, rld[r2].in))
  std::swap (r1, r2);

gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in))((void)(!(reg_mentioned_p (rld[r2].in, rld[r1].in)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 5550, __FUNCTION__), 0 : 0));
regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
gcc_assert (regno >= 0)((void)(!(regno >= 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/reload1.cc"
, 5552, __FUNCTION__), 0 : 0));
out = gen_rtx_REG (rld[r1].mode, regno);
in = rld[r1].in;
substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));

/* If IN is a paradoxical SUBREG, remove it and try to put the
   opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
strip_paradoxical_subreg (&in, &out);

if (GET_CODE (in)((enum rtx_code) (in)->code) == PLUS
    && (REG_P (XEXP (in, 0))(((enum rtx_code) ((((in)->u.fld[0]).rt_rtx))->code) ==
 REG)
 || GET_CODE (XEXP (in, 0))((enum rtx_code) ((((in)->u.fld[0]).rt_rtx))->code) == SUBREG
 || MEM_P (XEXP (in, 0))(((enum rtx_code) ((((in)->u.fld[0]).rt_rtx))->code) ==
 MEM))
    && (REG_P (XEXP (in, 1))(((enum rtx_code) ((((in)->u.fld[1]).rt_rtx))->code) ==
 REG)
 || GET_CODE (XEXP (in, 1))((enum rtx_code) ((((in)->u.fld[1]).rt_rtx))->code) == SUBREG
 || CONSTANT_P (XEXP (in, 1))((rtx_class[(int) (((enum rtx_code) ((((in)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
 || MEM_P (XEXP (in, 1))(((enum rtx_code) ((((in)->u.fld[1]).rt_rtx))->code) ==
 MEM)))
  {
    insn = emit_insn (gen_rtx_SET (out, in)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((out))
, ((in)) ));
    code = recog_memoized (insn);
    result = false;

    if (code >= 0)
{
 extract_insn (insn);
 /* We want constrain operands to treat this insn strictly in
    its validity determination, i.e., the way it would after
    reload has completed.  */
 result = constrain_operands (1, get_enabled_alternatives (insn));
}

    delete_insns_since (last);
  }

/* Restore the original value at each changed address within R1.  */
while (!substitute_stack.is_empty ())
  {
    rtx *where = substitute_stack.pop ();
    *where = rld[r2].in;
  }

return result;
5594}

5596/* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
 Return 0 otherwise.

 This function uses the same algorithm as reload_reg_free_p above.  */

5601static int
5602reloads_conflict (int r1, int r2)
5603{
enum reload_type r1_type = rld[r1].when_needed;
enum reload_type r2_type = rld[r2].when_needed;
int r1_opnum = rld[r1].opnum;
int r2_opnum = rld[r2].opnum;

/* RELOAD_OTHER conflicts with everything.  */
if (r2_type == RELOAD_OTHER)
  return 1;

/* Otherwise, check conflicts differently for each type.  */

switch (r1_type)
  {
  case RELOAD_FOR_INPUT:
    return (r2_type == RELOAD_FOR_INSN
     || r2_type == RELOAD_FOR_OPERAND_ADDRESS
     || r2_type == RELOAD_FOR_OPADDR_ADDR
     || r2_type == RELOAD_FOR_INPUT
     || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
   || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
  && r2_opnum > r1_opnum));

  case RELOAD_FOR_INPUT_ADDRESS:
    return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
     || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));

  case RELOAD_FOR_INPADDR_ADDRESS:
    return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
     || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));

  case RELOAD_FOR_OUTPUT_ADDRESS:
    return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS &am