Bug Summary

File:build/gcc/recog.c
Warning:line 2248, column 4
Value stored to 'incdec_ok' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-unknown-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name recog.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -resource-dir /usr/lib64/clang/13.0.0 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../include/c++/11 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../include/c++/11/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../include/c++/11/backward -internal-isystem /usr/lib64/clang/13.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../x86_64-suse-linux/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-error=format-diag -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir=/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2021-11-20-133755-20252-1/report-KWKuKi.plist -x c++ /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c
1/* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2021 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8Software Foundation; either version 3, or (at your option) any later
9version.
10
11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14for more details.
15
16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
19
20
21#include "config.h"
22#include "system.h"
23#include "coretypes.h"
24#include "backend.h"
25#include "target.h"
26#include "rtl.h"
27#include "tree.h"
28#include "cfghooks.h"
29#include "df.h"
30#include "memmodel.h"
31#include "tm_p.h"
32#include "insn-config.h"
33#include "regs.h"
34#include "emit-rtl.h"
35#include "recog.h"
36#include "insn-attr.h"
37#include "addresses.h"
38#include "cfgrtl.h"
39#include "cfgbuild.h"
40#include "cfgcleanup.h"
41#include "reload.h"
42#include "tree-pass.h"
43#include "function-abi.h"
44
45#ifndef STACK_POP_CODEPOST_INC
46#if STACK_GROWS_DOWNWARD1
47#define STACK_POP_CODEPOST_INC POST_INC
48#else
49#define STACK_POP_CODEPOST_INC POST_DEC
50#endif
51#endif
52
53static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx_insn *, bool);
54static void validate_replace_src_1 (rtx *, void *);
55static rtx_insn *split_insn (rtx_insn *);
56
57struct target_recog default_target_recog;
58#if SWITCHABLE_TARGET1
59struct target_recog *this_target_recog = &default_target_recog;
60#endif
61
62/* Nonzero means allow operands to be volatile.
63 This should be 0 if you are generating rtl, such as if you are calling
64 the functions in optabs.c and expmed.c (most of the time).
65 This should be 1 if all valid insns need to be recognized,
66 such as in reginfo.c and final.c and reload.c.
67
68 init_recog and init_recog_no_volatile are responsible for setting this. */
69
70int volatile_ok;
71
72struct recog_data_d recog_data;
73
74/* Contains a vector of operand_alternative structures, such that
75 operand OP of alternative A is at index A * n_operands + OP.
76 Set up by preprocess_constraints. */
77const operand_alternative *recog_op_alt;
78
79/* Used to provide recog_op_alt for asms. */
80static operand_alternative asm_op_alt[MAX_RECOG_OPERANDS30
81 * MAX_RECOG_ALTERNATIVES35];
82
83/* On return from `constrain_operands', indicate which alternative
84 was satisfied. */
85
86int which_alternative;
87
88/* Nonzero after end of reload pass.
89 Set to 1 or 0 by toplev.c.
90 Controls the significance of (SUBREG (MEM)). */
91
92int reload_completed;
93
94/* Nonzero after thread_prologue_and_epilogue_insns has run. */
95int epilogue_completed;
96
97/* Initialize data used by the function `recog'.
98 This must be called once in the compilation of a function
99 before any insn recognition may be done in the function. */
100
101void
102init_recog_no_volatile (void)
103{
104 volatile_ok = 0;
105}
106
107void
108init_recog (void)
109{
110 volatile_ok = 1;
111}
112
113
114/* Return true if labels in asm operands BODY are LABEL_REFs. */
115
116static bool
117asm_labels_ok (rtx body)
118{
119 rtx asmop;
120 int i;
121
122 asmop = extract_asm_operands (body);
123 if (asmop == NULL_RTX(rtx) 0)
124 return true;
125
126 for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop)(((((asmop)->u.fld[5]).rt_rtvec))->num_elem); i++)
127 if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i))((enum rtx_code) ((((((asmop)->u.fld[5]).rt_rtvec))->elem
[i]))->code)
!= LABEL_REF)
128 return false;
129
130 return true;
131}
132
133/* Check that X is an insn-body for an `asm' with operands
134 and that the operands mentioned in it are legitimate. */
135
136int
137check_asm_operands (rtx x)
138{
139 int noperands;
140 rtx *operands;
141 const char **constraints;
142 int i;
143
144 if (!asm_labels_ok (x))
145 return 0;
146
147 /* Post-reload, be more strict with things. */
148 if (reload_completed)
149 {
150 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
151 rtx_insn *insn = make_insn_raw (x);
152 extract_insn (insn);
153 constrain_operands (1, get_enabled_alternatives (insn));
154 return which_alternative >= 0;
155 }
156
157 noperands = asm_noperands (x);
158 if (noperands < 0)
159 return 0;
160 if (noperands == 0)
161 return 1;
162
163 operands = XALLOCAVEC (rtx, noperands)((rtx *) __builtin_alloca(sizeof (rtx) * (noperands)));
164 constraints = XALLOCAVEC (const char *, noperands)((const char * *) __builtin_alloca(sizeof (const char *) * (noperands
)))
;
165
166 decode_asm_operands (x, operands, NULLnullptr, constraints, NULLnullptr, NULLnullptr);
167
168 for (i = 0; i < noperands; i++)
169 {
170 const char *c = constraints[i];
171 if (c[0] == '%')
172 c++;
173 if (! asm_operand_ok (operands[i], c, constraints))
174 return 0;
175 }
176
177 return 1;
178}
179
180/* Static data for the next two routines. */
181
182struct change_t
183{
184 rtx object;
185 int old_code;
186 int old_len;
187 bool unshare;
188 rtx *loc;
189 rtx old;
190};
191
192static change_t *changes;
193static int changes_allocated;
194
195static int num_changes = 0;
196static int temporarily_undone_changes = 0;
197
198/* Validate a proposed change to OBJECT. LOC is the location in the rtl
199 at which NEW_RTX will be placed. If NEW_LEN is >= 0, XVECLEN (NEW_RTX, 0)
200 will also be changed to NEW_LEN, which is no greater than the current
201 XVECLEN. If OBJECT is zero, no validation is done, the change is
202 simply made.
203
204 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
205 will be called with the address and mode as parameters. If OBJECT is
206 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
207 the change in place.
208
209 IN_GROUP is nonzero if this is part of a group of changes that must be
210 performed as a group. In that case, the changes will be stored. The
211 function `apply_change_group' will validate and apply the changes.
212
213 If IN_GROUP is zero, this is a single change. Try to recognize the insn
214 or validate the memory reference with the change applied. If the result
215 is not valid for the machine, suppress the change and return zero.
216 Otherwise, perform the change and return 1. */
217
218static bool
219validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group,
220 bool unshare, int new_len = -1)
221{
222 gcc_assert (temporarily_undone_changes == 0)((void)(!(temporarily_undone_changes == 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 222, __FUNCTION__), 0 : 0))
;
223 rtx old = *loc;
224
225 /* Single-element parallels aren't valid and won't match anything.
226 Replace them with the single element. */
227 if (new_len == 1 && GET_CODE (new_rtx)((enum rtx_code) (new_rtx)->code) == PARALLEL)
228 {
229 new_rtx = XVECEXP (new_rtx, 0, 0)(((((new_rtx)->u.fld[0]).rt_rtvec))->elem[0]);
230 new_len = -1;
231 }
232
233 if ((old == new_rtx || rtx_equal_p (old, new_rtx))
234 && (new_len < 0 || XVECLEN (new_rtx, 0)(((((new_rtx)->u.fld[0]).rt_rtvec))->num_elem) == new_len))
235 return 1;
236
237 gcc_assert ((in_group != 0 || num_changes == 0)((void)(!((in_group != 0 || num_changes == 0) && (new_len
< 0 || new_rtx == *loc)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 238, __FUNCTION__), 0 : 0))
238 && (new_len < 0 || new_rtx == *loc))((void)(!((in_group != 0 || num_changes == 0) && (new_len
< 0 || new_rtx == *loc)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 238, __FUNCTION__), 0 : 0))
;
239
240 *loc = new_rtx;
241
242 /* Save the information describing this change. */
243 if (num_changes >= changes_allocated)
244 {
245 if (changes_allocated == 0)
246 /* This value allows for repeated substitutions inside complex
247 indexed addresses, or changes in up to 5 insns. */
248 changes_allocated = MAX_RECOG_OPERANDS30 * 5;
249 else
250 changes_allocated *= 2;
251
252 changes = XRESIZEVEC (change_t, changes, changes_allocated)((change_t *) xrealloc ((void *) (changes), sizeof (change_t)
* (changes_allocated)))
;
253 }
254
255 changes[num_changes].object = object;
256 changes[num_changes].loc = loc;
257 changes[num_changes].old = old;
258 changes[num_changes].old_len = (new_len >= 0 ? XVECLEN (new_rtx, 0)(((((new_rtx)->u.fld[0]).rt_rtvec))->num_elem) : -1);
259 changes[num_changes].unshare = unshare;
260
261 if (new_len >= 0)
262 XVECLEN (new_rtx, 0)(((((new_rtx)->u.fld[0]).rt_rtvec))->num_elem) = new_len;
263
264 if (object && !MEM_P (object)(((enum rtx_code) (object)->code) == MEM))
265 {
266 /* Set INSN_CODE to force rerecognition of insn. Save old code in
267 case invalid. */
268 changes[num_changes].old_code = INSN_CODE (object)(((object)->u.fld[5]).rt_int);
269 INSN_CODE (object)(((object)->u.fld[5]).rt_int) = -1;
270 }
271
272 num_changes++;
273
274 /* If we are making a group of changes, return 1. Otherwise, validate the
275 change group we made. */
276
277 if (in_group)
278 return 1;
279 else
280 return apply_change_group ();
281}
282
283/* Wrapper for validate_change_1 without the UNSHARE argument defaulting
284 UNSHARE to false. */
285
286bool
287validate_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
288{
289 return validate_change_1 (object, loc, new_rtx, in_group, false);
290}
291
292/* Wrapper for validate_change_1 without the UNSHARE argument defaulting
293 UNSHARE to true. */
294
295bool
296validate_unshare_change (rtx object, rtx *loc, rtx new_rtx, bool in_group)
297{
298 return validate_change_1 (object, loc, new_rtx, in_group, true);
299}
300
301/* Change XVECLEN (*LOC, 0) to NEW_LEN. OBJECT, IN_GROUP and the return
302 value are as for validate_change_1. */
303
304bool
305validate_change_xveclen (rtx object, rtx *loc, int new_len, bool in_group)
306{
307 return validate_change_1 (object, loc, *loc, in_group, false, new_len);
308}
309
310/* Keep X canonicalized if some changes have made it non-canonical; only
311 modifies the operands of X, not (for example) its code. Simplifications
312 are not the job of this routine.
313
314 Return true if anything was changed. */
315bool
316canonicalize_change_group (rtx_insn *insn, rtx x)
317{
318 if (COMMUTATIVE_P (x)(((rtx_class[(int) (((enum rtx_code) (x)->code))]) & (
~2)) == (RTX_COMM_COMPARE & (~2)))
319 && swap_commutative_operands_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
320 {
321 /* Oops, the caller has made X no longer canonical.
322 Let's redo the changes in the correct order. */
323 rtx tem = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
324 validate_unshare_change (insn, &XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), 1);
325 validate_unshare_change (insn, &XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), tem, 1);
326 return true;
327 }
328 else
329 return false;
330}
331
332
333/* This subroutine of apply_change_group verifies whether the changes to INSN
334 were valid; i.e. whether INSN can still be recognized.
335
336 If IN_GROUP is true clobbers which have to be added in order to
337 match the instructions will be added to the current change group.
338 Otherwise the changes will take effect immediately. */
339
340int
341insn_invalid_p (rtx_insn *insn, bool in_group)
342{
343 rtx pat = PATTERN (insn);
344 int num_clobbers = 0;
345 /* If we are before reload and the pattern is a SET, see if we can add
346 clobbers. */
347 int icode = recog (pat, insn,
348 (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET
349 && ! reload_completed
350 && ! reload_in_progress)
351 ? &num_clobbers : 0);
352 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
353
354
355 /* If this is an asm and the operand aren't legal, then fail. Likewise if
356 this is not an asm and the insn wasn't recognized. */
357 if ((is_asm && ! check_asm_operands (PATTERN (insn)))
358 || (!is_asm && icode < 0))
359 return 1;
360
361 /* If we have to add CLOBBERs, fail if we have to add ones that reference
362 hard registers since our callers can't know if they are live or not.
363 Otherwise, add them. */
364 if (num_clobbers > 0)
365 {
366 rtx newpat;
367
368 if (added_clobbers_hard_reg_p (icode))
369 return 1;
370
371 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(rtvec_alloc (num_clobbers + 1))) )
;
372 XVECEXP (newpat, 0, 0)(((((newpat)->u.fld[0]).rt_rtvec))->elem[0]) = pat;
373 add_clobbers (newpat, icode);
374 if (in_group)
375 validate_change (insn, &PATTERN (insn), newpat, 1);
376 else
377 PATTERN (insn) = pat = newpat;
378 }
379
380 /* After reload, verify that all constraints are satisfied. */
381 if (reload_completed)
382 {
383 extract_insn (insn);
384
385 if (! constrain_operands (1, get_preferred_alternatives (insn)))
386 return 1;
387 }
388
389 INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) = icode;
390 return 0;
391}
392
393/* Return number of changes made and not validated yet. */
394int
395num_changes_pending (void)
396{
397 return num_changes;
398}
399
400/* Tentatively apply the changes numbered NUM and up.
401 Return 1 if all changes are valid, zero otherwise. */
402
403int
404verify_changes (int num)
405{
406 int i;
407 rtx last_validated = NULL_RTX(rtx) 0;
408
409 /* The changes have been applied and all INSN_CODEs have been reset to force
410 rerecognition.
411
412 The changes are valid if we aren't given an object, or if we are
413 given a MEM and it still is a valid address, or if this is in insn
414 and it is recognized. In the latter case, if reload has completed,
415 we also require that the operands meet the constraints for
416 the insn. */
417
418 for (i = num; i < num_changes; i++)
419 {
420 rtx object = changes[i].object;
421
422 /* If there is no object to test or if it is the same as the one we
423 already tested, ignore it. */
424 if (object == 0 || object == last_validated)
425 continue;
426
427 if (MEM_P (object)(((enum rtx_code) (object)->code) == MEM))
428 {
429 if (! memory_address_addr_space_p (GET_MODE (object)((machine_mode) (object)->mode),
430 XEXP (object, 0)(((object)->u.fld[0]).rt_rtx),
431 MEM_ADDR_SPACE (object)(get_mem_attrs (object)->addrspace)))
432 break;
433 }
434 else if (/* changes[i].old might be zero, e.g. when putting a
435 REG_FRAME_RELATED_EXPR into a previously empty list. */
436 changes[i].old
437 && REG_P (changes[i].old)(((enum rtx_code) (changes[i].old)->code) == REG)
438 && asm_noperands (PATTERN (object)) > 0
439 && register_asm_p (changes[i].old))
440 {
441 /* Don't allow changes of hard register operands to inline
442 assemblies if they have been defined as register asm ("x"). */
443 break;
444 }
445 else if (DEBUG_INSN_P (object)(((enum rtx_code) (object)->code) == DEBUG_INSN))
446 continue;
447 else if (insn_invalid_p (as_a <rtx_insn *> (object), true))
448 {
449 rtx pat = PATTERN (object);
450
451 /* Perhaps we couldn't recognize the insn because there were
452 extra CLOBBERs at the end. If so, try to re-recognize
453 without the last CLOBBER (later iterations will cause each of
454 them to be eliminated, in turn). But don't do this if we
455 have an ASM_OPERAND. */
456 if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL
457 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1))((enum rtx_code) ((((((pat)->u.fld[0]).rt_rtvec))->elem
[(((((pat)->u.fld[0]).rt_rtvec))->num_elem) - 1]))->
code)
== CLOBBER
458 && asm_noperands (PATTERN (object)) < 0)
459 {
460 rtx newpat;
461
462 if (XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem) == 2)
463 newpat = XVECEXP (pat, 0, 0)(((((pat)->u.fld[0]).rt_rtvec))->elem[0]);
464 else
465 {
466 int j;
467
468 newpat
469 = gen_rtx_PARALLEL (VOIDmode,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(rtvec_alloc ((((((pat)->u.fld[0]).rt_rtvec))->num_elem
) - 1))) )
470 rtvec_alloc (XVECLEN (pat, 0) - 1))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(rtvec_alloc ((((((pat)->u.fld[0]).rt_rtvec))->num_elem
) - 1))) )
;
471 for (j = 0; j < XVECLEN (newpat, 0)(((((newpat)->u.fld[0]).rt_rtvec))->num_elem); j++)
472 XVECEXP (newpat, 0, j)(((((newpat)->u.fld[0]).rt_rtvec))->elem[j]) = XVECEXP (pat, 0, j)(((((pat)->u.fld[0]).rt_rtvec))->elem[j]);
473 }
474
475 /* Add a new change to this group to replace the pattern
476 with this new pattern. Then consider this change
477 as having succeeded. The change we added will
478 cause the entire call to fail if things remain invalid.
479
480 Note that this can lose if a later change than the one
481 we are processing specified &XVECEXP (PATTERN (object), 0, X)
482 but this shouldn't occur. */
483
484 validate_change (object, &PATTERN (object), newpat, 1);
485 continue;
486 }
487 else if (GET_CODE (pat)((enum rtx_code) (pat)->code) == USE || GET_CODE (pat)((enum rtx_code) (pat)->code) == CLOBBER
488 || GET_CODE (pat)((enum rtx_code) (pat)->code) == VAR_LOCATION)
489 /* If this insn is a CLOBBER or USE, it is always valid, but is
490 never recognized. */
491 continue;
492 else
493 break;
494 }
495 last_validated = object;
496 }
497
498 return (i == num_changes);
499}
500
501/* A group of changes has previously been issued with validate_change
502 and verified with verify_changes. Call df_insn_rescan for each of
503 the insn changed and clear num_changes. */
504
505void
506confirm_change_group (void)
507{
508 int i;
509 rtx last_object = NULLnullptr;
510
511 gcc_assert (temporarily_undone_changes == 0)((void)(!(temporarily_undone_changes == 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 511, __FUNCTION__), 0 : 0))
;
512 for (i = 0; i < num_changes; i++)
513 {
514 rtx object = changes[i].object;
515
516 if (changes[i].unshare)
517 *changes[i].loc = copy_rtx (*changes[i].loc);
518
519 /* Avoid unnecessary rescanning when multiple changes to same instruction
520 are made. */
521 if (object)
522 {
523 if (object != last_object && last_object && INSN_P (last_object)(((((enum rtx_code) (last_object)->code) == INSN) || (((enum
rtx_code) (last_object)->code) == JUMP_INSN) || (((enum rtx_code
) (last_object)->code) == CALL_INSN)) || (((enum rtx_code)
(last_object)->code) == DEBUG_INSN))
)
524 df_insn_rescan (as_a <rtx_insn *> (last_object));
525 last_object = object;
526 }
527 }
528
529 if (last_object && INSN_P (last_object)(((((enum rtx_code) (last_object)->code) == INSN) || (((enum
rtx_code) (last_object)->code) == JUMP_INSN) || (((enum rtx_code
) (last_object)->code) == CALL_INSN)) || (((enum rtx_code)
(last_object)->code) == DEBUG_INSN))
)
530 df_insn_rescan (as_a <rtx_insn *> (last_object));
531 num_changes = 0;
532}
533
534/* Apply a group of changes previously issued with `validate_change'.
535 If all changes are valid, call confirm_change_group and return 1,
536 otherwise, call cancel_changes and return 0. */
537
538int
539apply_change_group (void)
540{
541 if (verify_changes (0))
542 {
543 confirm_change_group ();
544 return 1;
545 }
546 else
547 {
548 cancel_changes (0);
549 return 0;
550 }
551}
552
553
554/* Return the number of changes so far in the current group. */
555
556int
557num_validated_changes (void)
558{
559 return num_changes;
560}
561
562/* Retract the changes numbered NUM and up. */
563
564void
565cancel_changes (int num)
566{
567 gcc_assert (temporarily_undone_changes == 0)((void)(!(temporarily_undone_changes == 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 567, __FUNCTION__), 0 : 0))
;
568 int i;
569
570 /* Back out all the changes. Do this in the opposite order in which
571 they were made. */
572 for (i = num_changes - 1; i >= num; i--)
573 {
574 if (changes[i].old_len >= 0)
575 XVECLEN (*changes[i].loc, 0)(((((*changes[i].loc)->u.fld[0]).rt_rtvec))->num_elem) = changes[i].old_len;
576 else
577 *changes[i].loc = changes[i].old;
578 if (changes[i].object && !MEM_P (changes[i].object)(((enum rtx_code) (changes[i].object)->code) == MEM))
579 INSN_CODE (changes[i].object)(((changes[i].object)->u.fld[5]).rt_int) = changes[i].old_code;
580 }
581 num_changes = num;
582}
583
584/* Swap the status of change NUM from being applied to not being applied,
585 or vice versa. */
586
587static void
588swap_change (int num)
589{
590 if (changes[num].old_len >= 0)
591 std::swap (XVECLEN (*changes[num].loc, 0)(((((*changes[num].loc)->u.fld[0]).rt_rtvec))->num_elem
)
, changes[num].old_len);
592 else
593 std::swap (*changes[num].loc, changes[num].old);
594 if (changes[num].object && !MEM_P (changes[num].object)(((enum rtx_code) (changes[num].object)->code) == MEM))
595 std::swap (INSN_CODE (changes[num].object)(((changes[num].object)->u.fld[5]).rt_int), changes[num].old_code);
596}
597
598/* Temporarily undo all the changes numbered NUM and up, with a view
599 to reapplying them later. The next call to the changes machinery
600 must be:
601
602 redo_changes (NUM)
603
604 otherwise things will end up in an invalid state. */
605
606void
607temporarily_undo_changes (int num)
608{
609 gcc_assert (temporarily_undone_changes == 0 && num <= num_changes)((void)(!(temporarily_undone_changes == 0 && num <=
num_changes) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 609, __FUNCTION__), 0 : 0))
;
610 for (int i = num_changes - 1; i >= num; i--)
611 swap_change (i);
612 temporarily_undone_changes = num_changes - num;
613}
614
615/* Redo the changes that were temporarily undone by:
616
617 temporarily_undo_changes (NUM). */
618
619void
620redo_changes (int num)
621{
622 gcc_assert (temporarily_undone_changes == num_changes - num)((void)(!(temporarily_undone_changes == num_changes - num) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 622, __FUNCTION__), 0 : 0))
;
623 for (int i = num; i < num_changes; ++i)
624 swap_change (i);
625 temporarily_undone_changes = 0;
626}
627
628/* Reduce conditional compilation elsewhere. */
629/* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
630 rtx. */
631
632static void
633simplify_while_replacing (rtx *loc, rtx to, rtx_insn *object,
634 machine_mode op0_mode)
635{
636 rtx x = *loc;
637 enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
638 rtx new_rtx = NULL_RTX(rtx) 0;
639 scalar_int_mode is_mode;
640
641 if (SWAPPABLE_OPERANDS_P (x)((1 << (rtx_class[(int) (((enum rtx_code) (x)->code)
)])) & ((1 << RTX_COMM_ARITH) | (1 << RTX_COMM_COMPARE
) | (1 << RTX_COMPARE)))
642 && swap_commutative_operands_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
643 {
644 validate_unshare_change (object, loc,
645 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x) ? codegen_rtx_fmt_ee_stat ((((rtx_class[(int) (((enum rtx_code) (x)
->code))]) == RTX_COMM_ARITH) ? code : swap_condition (code
)), (((machine_mode) (x)->mode)), ((((x)->u.fld[1]).rt_rtx
)), ((((x)->u.fld[0]).rt_rtx)) )
646 : swap_condition (code),gen_rtx_fmt_ee_stat ((((rtx_class[(int) (((enum rtx_code) (x)
->code))]) == RTX_COMM_ARITH) ? code : swap_condition (code
)), (((machine_mode) (x)->mode)), ((((x)->u.fld[1]).rt_rtx
)), ((((x)->u.fld[0]).rt_rtx)) )
647 GET_MODE (x), XEXP (x, 1),gen_rtx_fmt_ee_stat ((((rtx_class[(int) (((enum rtx_code) (x)
->code))]) == RTX_COMM_ARITH) ? code : swap_condition (code
)), (((machine_mode) (x)->mode)), ((((x)->u.fld[1]).rt_rtx
)), ((((x)->u.fld[0]).rt_rtx)) )
648 XEXP (x, 0))gen_rtx_fmt_ee_stat ((((rtx_class[(int) (((enum rtx_code) (x)
->code))]) == RTX_COMM_ARITH) ? code : swap_condition (code
)), (((machine_mode) (x)->mode)), ((((x)->u.fld[1]).rt_rtx
)), ((((x)->u.fld[0]).rt_rtx)) )
, 1);
649 x = *loc;
650 code = GET_CODE (x)((enum rtx_code) (x)->code);
651 }
652
653 /* Canonicalize arithmetics with all constant operands. */
654 switch (GET_RTX_CLASS (code)(rtx_class[(int) (code)]))
655 {
656 case RTX_UNARY:
657 if (CONSTANT_P (XEXP (x, 0))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
)
658 new_rtx = simplify_unary_operation (code, GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx),
659 op0_mode);
660 break;
661 case RTX_COMM_ARITH:
662 case RTX_BIN_ARITH:
663 if (CONSTANT_P (XEXP (x, 0))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
&& CONSTANT_P (XEXP (x, 1))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
)
664 new_rtx = simplify_binary_operation (code, GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx),
665 XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));
666 break;
667 case RTX_COMPARE:
668 case RTX_COMM_COMPARE:
669 if (CONSTANT_P (XEXP (x, 0))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
&& CONSTANT_P (XEXP (x, 1))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
)
670 new_rtx = simplify_relational_operation (code, GET_MODE (x)((machine_mode) (x)->mode), op0_mode,
671 XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));
672 break;
673 default:
674 break;
675 }
676 if (new_rtx)
677 {
678 validate_change (object, loc, new_rtx, 1);
679 return;
680 }
681
682 switch (code)
683 {
684 case PLUS:
685 /* If we have a PLUS whose second operand is now a CONST_INT, use
686 simplify_gen_binary to try to simplify it.
687 ??? We may want later to remove this, once simplification is
688 separated from this function. */
689 if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
&& XEXP (x, 1)(((x)->u.fld[1]).rt_rtx) == to)
690 validate_change (object, loc,
691 simplify_gen_binary
692 (PLUS, GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)), 1);
693 break;
694 case MINUS:
695 if (CONST_SCALAR_INT_P (XEXP (x, 1))((((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) ==
CONST_INT) || (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx)
)->code) == CONST_WIDE_INT))
)
696 validate_change (object, loc,
697 simplify_gen_binary
698 (PLUS, GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx),
699 simplify_gen_unary (NEG,
700 GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx),
701 GET_MODE (x)((machine_mode) (x)->mode))), 1);
702 break;
703 case ZERO_EXTEND:
704 case SIGN_EXTEND:
705 if (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) == VOIDmode((void) 0, E_VOIDmode))
706 {
707 new_rtx = simplify_gen_unary (code, GET_MODE (x)((machine_mode) (x)->mode), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx),
708 op0_mode);
709 /* If any of the above failed, substitute in something that
710 we know won't be recognized. */
711 if (!new_rtx)
712 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx)gen_rtx_fmt_e_stat ((CLOBBER), ((((machine_mode) (x)->mode
))), (((const_int_rtx[64]))) )
;
713 validate_change (object, loc, new_rtx, 1);
714 }
715 break;
716 case SUBREG:
717 /* All subregs possible to simplify should be simplified. */
718 new_rtx = simplify_subreg (GET_MODE (x)((machine_mode) (x)->mode), SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), op0_mode,
719 SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg));
720
721 /* Subregs of VOIDmode operands are incorrect. */
722 if (!new_rtx && GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) == VOIDmode((void) 0, E_VOIDmode))
723 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx)gen_rtx_fmt_e_stat ((CLOBBER), ((((machine_mode) (x)->mode
))), (((const_int_rtx[64]))) )
;
724 if (new_rtx)
725 validate_change (object, loc, new_rtx, 1);
726 break;
727 case ZERO_EXTRACT:
728 case SIGN_EXTRACT:
729 /* If we are replacing a register with memory, try to change the memory
730 to be the mode required for memory in extract operations (this isn't
731 likely to be an insertion operation; if it was, nothing bad will
732 happen, we might just fail in some cases). */
733
734 if (MEM_P (XEXP (x, 0))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == MEM
)
735 && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode), &is_mode)
736 && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
737 && CONST_INT_P (XEXP (x, 2))(((enum rtx_code) ((((x)->u.fld[2]).rt_rtx))->code) == CONST_INT
)
738 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0)((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx),
739 MEM_ADDR_SPACE (XEXP (x, 0))(get_mem_attrs ((((x)->u.fld[0]).rt_rtx))->addrspace))
740 && !MEM_VOLATILE_P (XEXP (x, 0))(__extension__ ({ __typeof (((((x)->u.fld[0]).rt_rtx))) const
_rtx = (((((x)->u.fld[0]).rt_rtx))); if (((enum rtx_code)
(_rtx)->code) != MEM && ((enum rtx_code) (_rtx)->
code) != ASM_OPERANDS && ((enum rtx_code) (_rtx)->
code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P", _rtx
, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 740, __FUNCTION__); _rtx; })->volatil)
)
741 {
742 int pos = INTVAL (XEXP (x, 2))(((((x)->u.fld[2]).rt_rtx))->u.hwint[0]);
743 machine_mode new_mode = is_mode;
744 if (GET_CODE (x)((enum rtx_code) (x)->code) == ZERO_EXTRACT && targetm.have_extzv ())
745 new_mode = insn_data[targetm.code_for_extzv].operand[1].mode;
746 else if (GET_CODE (x)((enum rtx_code) (x)->code) == SIGN_EXTRACT && targetm.have_extv ())
747 new_mode = insn_data[targetm.code_for_extv].operand[1].mode;
748 scalar_int_mode wanted_mode = (new_mode == VOIDmode((void) 0, E_VOIDmode)
749 ? word_mode
750 : as_a <scalar_int_mode> (new_mode));
751
752 /* If we have a narrower mode, we can do something. */
753 if (GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
754 {
755 int offset = pos / BITS_PER_UNIT(8);
756 rtx newmem;
757
758 /* If the bytes and bits are counted differently, we
759 must adjust the offset. */
760 if (BYTES_BIG_ENDIAN0 != BITS_BIG_ENDIAN0)
761 offset =
762 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) -
763 offset);
764
765 gcc_assert (GET_MODE_PRECISION (wanted_mode)((void)(!(GET_MODE_PRECISION (wanted_mode) == GET_MODE_BITSIZE
(wanted_mode)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 766, __FUNCTION__), 0 : 0))
766 == GET_MODE_BITSIZE (wanted_mode))((void)(!(GET_MODE_PRECISION (wanted_mode) == GET_MODE_BITSIZE
(wanted_mode)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 766, __FUNCTION__), 0 : 0))
;
767 pos %= GET_MODE_BITSIZE (wanted_mode);
768
769 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset)adjust_address_1 ((((x)->u.fld[0]).rt_rtx), wanted_mode, offset
, 0, 1, 0, 0)
;
770
771 validate_change (object, &XEXP (x, 2)(((x)->u.fld[2]).rt_rtx), GEN_INT (pos)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (pos)), 1);
772 validate_change (object, &XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), newmem, 1);
773 }
774 }
775
776 break;
777
778 default:
779 break;
780 }
781}
782
783/* Replace every occurrence of FROM in X with TO. Mark each change with
784 validate_change passing OBJECT. */
785
786static void
787validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx_insn *object,
788 bool simplify)
789{
790 int i, j;
791 const char *fmt;
792 rtx x = *loc;
793 enum rtx_code code;
794 machine_mode op0_mode = VOIDmode((void) 0, E_VOIDmode);
795 int prev_changes = num_changes;
796
797 if (!x)
798 return;
799
800 code = GET_CODE (x)((enum rtx_code) (x)->code);
801 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
802 if (fmt[0] == 'e')
803 op0_mode = GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
804
805 /* X matches FROM if it is the same rtx or they are both referring to the
806 same register in the same mode. Avoid calling rtx_equal_p unless the
807 operands look similar. */
808
809 if (x == from
810 || (REG_P (x)(((enum rtx_code) (x)->code) == REG) && REG_P (from)(((enum rtx_code) (from)->code) == REG)
811 && GET_MODE (x)((machine_mode) (x)->mode) == GET_MODE (from)((machine_mode) (from)->mode)
812 && REGNO (x)(rhs_regno(x)) == REGNO (from)(rhs_regno(from)))
813 || (GET_CODE (x)((enum rtx_code) (x)->code) == GET_CODE (from)((enum rtx_code) (from)->code) && GET_MODE (x)((machine_mode) (x)->mode) == GET_MODE (from)((machine_mode) (from)->mode)
814 && rtx_equal_p (x, from)))
815 {
816 validate_unshare_change (object, loc, to, 1);
817 return;
818 }
819
820 /* Call ourself recursively to perform the replacements.
821 We must not replace inside already replaced expression, otherwise we
822 get infinite recursion for replacements like (reg X)->(subreg (reg X))
823 so we must special case shared ASM_OPERANDS. */
824
825 if (GET_CODE (x)((enum rtx_code) (x)->code) == PARALLEL)
826 {
827 for (j = XVECLEN (x, 0)(((((x)->u.fld[0]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
828 {
829 if (j && GET_CODE (XVECEXP (x, 0, j))((enum rtx_code) ((((((x)->u.fld[0]).rt_rtvec))->elem[j
]))->code)
== SET
830 && GET_CODE (SET_SRC (XVECEXP (x, 0, j)))((enum rtx_code) (((((((((x)->u.fld[0]).rt_rtvec))->elem
[j]))->u.fld[1]).rt_rtx))->code)
== ASM_OPERANDS)
831 {
832 /* Verify that operands are really shared. */
833 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, 0)))((void)(!((((((((((((x)->u.fld[0]).rt_rtvec))->elem[0])
)->u.fld[1]).rt_rtx))->u.fld[3]).rt_rtvec) == (((((((((
((x)->u.fld[0]).rt_rtvec))->elem[j]))->u.fld[1]).rt_rtx
))->u.fld[3]).rt_rtvec)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 835, __FUNCTION__), 0 : 0))
834 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP((void)(!((((((((((((x)->u.fld[0]).rt_rtvec))->elem[0])
)->u.fld[1]).rt_rtx))->u.fld[3]).rt_rtvec) == (((((((((
((x)->u.fld[0]).rt_rtvec))->elem[j]))->u.fld[1]).rt_rtx
))->u.fld[3]).rt_rtvec)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 835, __FUNCTION__), 0 : 0))
835 (x, 0, j))))((void)(!((((((((((((x)->u.fld[0]).rt_rtvec))->elem[0])
)->u.fld[1]).rt_rtx))->u.fld[3]).rt_rtvec) == (((((((((
((x)->u.fld[0]).rt_rtvec))->elem[j]))->u.fld[1]).rt_rtx
))->u.fld[3]).rt_rtvec)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 835, __FUNCTION__), 0 : 0))
;
836 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x, 0, j))((((((((x)->u.fld[0]).rt_rtvec))->elem[j]))->u.fld[0
]).rt_rtx)
,
837 from, to, object, simplify);
838 }
839 else
840 validate_replace_rtx_1 (&XVECEXP (x, 0, j)(((((x)->u.fld[0]).rt_rtvec))->elem[j]), from, to, object,
841 simplify);
842 }
843 }
844 else
845 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
846 {
847 if (fmt[i] == 'e')
848 validate_replace_rtx_1 (&XEXP (x, i)(((x)->u.fld[i]).rt_rtx), from, to, object, simplify);
849 else if (fmt[i] == 'E')
850 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
851 validate_replace_rtx_1 (&XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), from, to, object,
852 simplify);
853 }
854
855 /* If we didn't substitute, there is nothing more to do. */
856 if (num_changes == prev_changes)
857 return;
858
859 /* ??? The regmove is no more, so is this aberration still necessary? */
860 /* Allow substituted expression to have different mode. This is used by
861 regmove to change mode of pseudo register. */
862 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) != VOIDmode((void) 0, E_VOIDmode))
863 op0_mode = GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
864
865 /* Do changes needed to keep rtx consistent. Don't do any other
866 simplifications, as it is not our job. */
867 if (simplify)
868 simplify_while_replacing (loc, to, object, op0_mode);
869}
870
871/* Try replacing every occurrence of FROM in subexpression LOC of INSN
872 with TO. After all changes have been made, validate by seeing
873 if INSN is still valid. */
874
875int
876validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc)
877{
878 validate_replace_rtx_1 (loc, from, to, insn, true);
879 return apply_change_group ();
880}
881
882/* Try replacing every occurrence of FROM in INSN with TO. After all
883 changes have been made, validate by seeing if INSN is still valid. */
884
885int
886validate_replace_rtx (rtx from, rtx to, rtx_insn *insn)
887{
888 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
889 return apply_change_group ();
890}
891
892/* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
893 is a part of INSN. After all changes have been made, validate by seeing if
894 INSN is still valid.
895 validate_replace_rtx (from, to, insn) is equivalent to
896 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
897
898int
899validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn)
900{
901 validate_replace_rtx_1 (where, from, to, insn, true);
902 return apply_change_group ();
903}
904
905/* Same as above, but do not simplify rtx afterwards. */
906int
907validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where,
908 rtx_insn *insn)
909{
910 validate_replace_rtx_1 (where, from, to, insn, false);
911 return apply_change_group ();
912
913}
914
915/* Try replacing every occurrence of FROM in INSN with TO. This also
916 will replace in REG_EQUAL and REG_EQUIV notes. */
917
918void
919validate_replace_rtx_group (rtx from, rtx to, rtx_insn *insn)
920{
921 rtx note;
922 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
923 for (note = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); note; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
924 if (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_EQUAL
925 || REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_EQUIV)
926 validate_replace_rtx_1 (&XEXP (note, 0)(((note)->u.fld[0]).rt_rtx), from, to, insn, true);
927}
928
929/* Function called by note_uses to replace used subexpressions. */
930struct validate_replace_src_data
931{
932 rtx from; /* Old RTX */
933 rtx to; /* New RTX */
934 rtx_insn *insn; /* Insn in which substitution is occurring. */
935};
936
937static void
938validate_replace_src_1 (rtx *x, void *data)
939{
940 struct validate_replace_src_data *d
941 = (struct validate_replace_src_data *) data;
942
943 validate_replace_rtx_1 (x, d->from, d->to, d->insn, true);
944}
945
946/* Try replacing every occurrence of FROM in INSN with TO, avoiding
947 SET_DESTs. */
948
949void
950validate_replace_src_group (rtx from, rtx to, rtx_insn *insn)
951{
952 struct validate_replace_src_data d;
953
954 d.from = from;
955 d.to = to;
956 d.insn = insn;
957 note_uses (&PATTERN (insn), validate_replace_src_1, &d);
958}
959
960/* Try simplify INSN.
961 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
962 pattern and return true if something was simplified. */
963
964bool
965validate_simplify_insn (rtx_insn *insn)
966{
967 int i;
968 rtx pat = NULLnullptr;
969 rtx newpat = NULLnullptr;
970
971 pat = PATTERN (insn);
972
973 if (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET)
974 {
975 newpat = simplify_rtx (SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx));
976 if (newpat && !rtx_equal_p (SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx), newpat))
977 validate_change (insn, &SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx), newpat, 1);
978 newpat = simplify_rtx (SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx));
979 if (newpat && !rtx_equal_p (SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx), newpat))
980 validate_change (insn, &SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx), newpat, 1);
981 }
982 else if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
983 for (i = 0; i < XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
984 {
985 rtx s = XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]);
986
987 if (GET_CODE (XVECEXP (pat, 0, i))((enum rtx_code) ((((((pat)->u.fld[0]).rt_rtvec))->elem
[i]))->code)
== SET)
988 {
989 newpat = simplify_rtx (SET_SRC (s)(((s)->u.fld[1]).rt_rtx));
990 if (newpat && !rtx_equal_p (SET_SRC (s)(((s)->u.fld[1]).rt_rtx), newpat))
991 validate_change (insn, &SET_SRC (s)(((s)->u.fld[1]).rt_rtx), newpat, 1);
992 newpat = simplify_rtx (SET_DEST (s)(((s)->u.fld[0]).rt_rtx));
993 if (newpat && !rtx_equal_p (SET_DEST (s)(((s)->u.fld[0]).rt_rtx), newpat))
994 validate_change (insn, &SET_DEST (s)(((s)->u.fld[0]).rt_rtx), newpat, 1);
995 }
996 }
997 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
998}
999
1000/* Try to process the address of memory expression MEM. Return true on
1001 success; leave the caller to clean up on failure. */
1002
1003bool
1004insn_propagation::apply_to_mem_1 (rtx mem)
1005{
1006 auto old_num_changes = num_validated_changes ();
1007 mem_depth += 1;
1008 bool res = apply_to_rvalue_1 (&XEXP (mem, 0)(((mem)->u.fld[0]).rt_rtx));
1009 mem_depth -= 1;
1010 if (!res)
1011 return false;
1012
1013 if (old_num_changes != num_validated_changes ()
1014 && should_check_mems
1015 && !check_mem (old_num_changes, mem))
1016 return false;
1017
1018 return true;
1019}
1020
1021/* Try to process the rvalue expression at *LOC. Return true on success;
1022 leave the caller to clean up on failure. */
1023
1024bool
1025insn_propagation::apply_to_rvalue_1 (rtx *loc)
1026{
1027 rtx x = *loc;
1028 enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
1029 machine_mode mode = GET_MODE (x)((machine_mode) (x)->mode);
1030
1031 auto old_num_changes = num_validated_changes ();
1032 if (from && GET_CODE (x)((enum rtx_code) (x)->code) == GET_CODE (from)((enum rtx_code) (from)->code) && rtx_equal_p (x, from))
1033 {
1034 /* Don't replace register asms in asm statements; we mustn't
1035 change the user's register allocation. */
1036 if (REG_P (x)(((enum rtx_code) (x)->code) == REG)
1037 && HARD_REGISTER_P (x)((((rhs_regno(x))) < 76))
1038 && register_asm_p (x)
1039 && asm_noperands (PATTERN (insn)) > 0)
1040 return false;
1041
1042 if (should_unshare)
1043 validate_unshare_change (insn, loc, to, 1);
1044 else
1045 validate_change (insn, loc, to, 1);
1046 if (mem_depth && !REG_P (to)(((enum rtx_code) (to)->code) == REG) && !CONSTANT_P (to)((rtx_class[(int) (((enum rtx_code) (to)->code))]) == RTX_CONST_OBJ
)
)
1047 {
1048 /* We're substituting into an address, but TO will have the
1049 form expected outside an address. Canonicalize it if
1050 necessary. */
1051 insn_propagation subprop (insn);
1052 subprop.mem_depth += 1;
1053 if (!subprop.apply_to_rvalue (loc))
1054 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 1054, __FUNCTION__))
;
1055 if (should_unshare
1056 && num_validated_changes () != old_num_changes + 1)
1057 {
1058 /* TO is owned by someone else, so create a copy and
1059 return TO to its original form. */
1060 rtx to = copy_rtx (*loc);
1061 cancel_changes (old_num_changes);
1062 validate_change (insn, loc, to, 1);
1063 }
1064 }
1065 num_replacements += 1;
1066 should_unshare = true;
1067 result_flags |= UNSIMPLIFIED;
1068 return true;
1069 }
1070
1071 /* Recursively apply the substitution and see if we can simplify
1072 the result. This specifically shouldn't use simplify_gen_* for
1073 speculative simplifications, since we want to avoid generating new
1074 expressions where possible. */
1075 auto old_result_flags = result_flags;
1076 rtx newx = NULL_RTX(rtx) 0;
1077 bool recurse_p = false;
1078 switch (GET_RTX_CLASS (code)(rtx_class[(int) (code)]))
1079 {
1080 case RTX_UNARY:
1081 {
1082 machine_mode op0_mode = GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
1083 if (!apply_to_rvalue_1 (&XEXP (x, 0)(((x)->u.fld[0]).rt_rtx)))
1084 return false;
1085 if (from && old_num_changes == num_validated_changes ())
1086 return true;
1087
1088 newx = simplify_unary_operation (code, mode, XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), op0_mode);
1089 break;
1090 }
1091
1092 case RTX_BIN_ARITH:
1093 case RTX_COMM_ARITH:
1094 {
1095 if (!apply_to_rvalue_1 (&XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
1096 || !apply_to_rvalue_1 (&XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
1097 return false;
1098 if (from && old_num_changes == num_validated_changes ())
1099 return true;
1100
1101 if (GET_RTX_CLASS (code)(rtx_class[(int) (code)]) == RTX_COMM_ARITH
1102 && swap_commutative_operands_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
1103 newx = simplify_gen_binary (code, mode, XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));
1104 else
1105 newx = simplify_binary_operation (code, mode,
1106 XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));
1107 break;
1108 }
1109
1110 case RTX_COMPARE:
1111 case RTX_COMM_COMPARE:
1112 {
1113 machine_mode op_mode = (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) != VOIDmode((void) 0, E_VOIDmode)
1114 ? GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode)
1115 : GET_MODE (XEXP (x, 1))((machine_mode) ((((x)->u.fld[1]).rt_rtx))->mode));
1116 if (!apply_to_rvalue_1 (&XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
1117 || !apply_to_rvalue_1 (&XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
1118 return false;
1119 if (from && old_num_changes == num_validated_changes ())
1120 return true;
1121
1122 newx = simplify_relational_operation (code, mode, op_mode,
1123 XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));
1124 break;
1125 }
1126
1127 case RTX_TERNARY:
1128 case RTX_BITFIELD_OPS:
1129 {
1130 machine_mode op0_mode = GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
1131 if (!apply_to_rvalue_1 (&XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
1132 || !apply_to_rvalue_1 (&XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
1133 || !apply_to_rvalue_1 (&XEXP (x, 2)(((x)->u.fld[2]).rt_rtx)))
1134 return false;
1135 if (from && old_num_changes == num_validated_changes ())
1136 return true;
1137
1138 newx = simplify_ternary_operation (code, mode, op0_mode,
1139 XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), XEXP (x, 1)(((x)->u.fld[1]).rt_rtx),
1140 XEXP (x, 2)(((x)->u.fld[2]).rt_rtx));
1141 break;
1142 }
1143
1144 case RTX_EXTRA:
1145 if (code == SUBREG)
1146 {
1147 machine_mode inner_mode = GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
1148 if (!apply_to_rvalue_1 (&SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx)))
1149 return false;
1150 if (from && old_num_changes == num_validated_changes ())
1151 return true;
1152
1153 rtx inner = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
1154 newx = simplify_subreg (mode, inner, inner_mode, SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg));
1155 /* Reject the same cases that simplify_gen_subreg would. */
1156 if (!newx
1157 && (GET_CODE (inner)((enum rtx_code) (inner)->code) == SUBREG
1158 || GET_CODE (inner)((enum rtx_code) (inner)->code) == CONCAT
1159 || GET_MODE (inner)((machine_mode) (inner)->mode) == VOIDmode((void) 0, E_VOIDmode)
1160 || !validate_subreg (mode, inner_mode,
1161 inner, SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg))))
1162 {
1163 failure_reason = "would create an invalid subreg";
1164 return false;
1165 }
1166 break;
1167 }
1168 else
1169 recurse_p = true;
1170 break;
1171
1172 case RTX_OBJ:
1173 if (code == LO_SUM)
1174 {
1175 if (!apply_to_rvalue_1 (&XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
1176 || !apply_to_rvalue_1 (&XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
1177 return false;
1178 if (from && old_num_changes == num_validated_changes ())
1179 return true;
1180
1181 /* (lo_sum (high x) y) -> y where x and y have the same base. */
1182 rtx op0 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
1183 rtx op1 = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);
1184 if (GET_CODE (op0)((enum rtx_code) (op0)->code) == HIGH)
1185 {
1186 rtx base0, base1, offset0, offset1;
1187 split_const (XEXP (op0, 0)(((op0)->u.fld[0]).rt_rtx), &base0, &offset0);
1188 split_const (op1, &base1, &offset1);
1189 if (rtx_equal_p (base0, base1))
1190 newx = op1;
1191 }
1192 }
1193 else if (code == REG)
1194 {
1195 if (from && REG_P (from)(((enum rtx_code) (from)->code) == REG) && reg_overlap_mentioned_p (x, from))
1196 {
1197 failure_reason = "inexact register overlap";
1198 return false;
1199 }
1200 }
1201 else if (code == MEM)
1202 return apply_to_mem_1 (x);
1203 else
1204 recurse_p = true;
1205 break;
1206
1207 case RTX_CONST_OBJ:
1208 break;
1209
1210 case RTX_AUTOINC:
1211 if (from && reg_overlap_mentioned_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), from))
1212 {
1213 failure_reason = "is subject to autoinc";
1214 return false;
1215 }
1216 recurse_p = true;
1217 break;
1218
1219 case RTX_MATCH:
1220 case RTX_INSN:
1221 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 1221, __FUNCTION__))
;
1222 }
1223
1224 if (recurse_p)
1225 {
1226 const char *fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
1227 for (int i = 0; fmt[i]; i++)
1228 switch (fmt[i])
1229 {
1230 case 'E':
1231 for (int j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
1232 if (!apply_to_rvalue_1 (&XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
1233 return false;
1234 break;
1235
1236 case 'e':
1237 if (XEXP (x, i)(((x)->u.fld[i]).rt_rtx) && !apply_to_rvalue_1 (&XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
1238 return false;
1239 break;
1240 }
1241 }
1242 else if (newx && !rtx_equal_p (x, newx))
1243 {
1244 /* All substitutions made by OLD_NUM_CHANGES onwards have been
1245 simplified. */
1246 result_flags = ((result_flags & ~UNSIMPLIFIED)
1247 | (old_result_flags & UNSIMPLIFIED));
1248
1249 if (should_note_simplifications)
1250 note_simplification (old_num_changes, old_result_flags, x, newx);
1251
1252 /* There's no longer any point unsharing the substitutions made
1253 for subexpressions, since we'll just copy this one instead. */
1254 bool unshare = false;
1255 for (int i = old_num_changes; i < num_changes; ++i)
1256 {
1257 unshare |= changes[i].unshare;
1258 changes[i].unshare = false;
1259 }
1260 if (unshare)
1261 validate_unshare_change (insn, loc, newx, 1);
1262 else
1263 validate_change (insn, loc, newx, 1);
1264 }
1265
1266 return true;
1267}
1268
1269/* Try to process the lvalue expression at *LOC. Return true on success;
1270 leave the caller to clean up on failure. */
1271
1272bool
1273insn_propagation::apply_to_lvalue_1 (rtx dest)
1274{
1275 rtx old_dest = dest;
1276 while (GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG
1277 || GET_CODE (dest)((enum rtx_code) (dest)->code) == ZERO_EXTRACT
1278 || GET_CODE (dest)((enum rtx_code) (dest)->code) == STRICT_LOW_PART)
1279 {
1280 if (GET_CODE (dest)((enum rtx_code) (dest)->code) == ZERO_EXTRACT
1281 && (!apply_to_rvalue_1 (&XEXP (dest, 1)(((dest)->u.fld[1]).rt_rtx))
1282 || !apply_to_rvalue_1 (&XEXP (dest, 2)(((dest)->u.fld[2]).rt_rtx))))
1283 return false;
1284 dest = XEXP (dest, 0)(((dest)->u.fld[0]).rt_rtx);
1285 }
1286
1287 if (MEM_P (dest)(((enum rtx_code) (dest)->code) == MEM))
1288 return apply_to_mem_1 (dest);
1289
1290 /* Check whether the substitution is safe in the presence of this lvalue. */
1291 if (!from
1292 || dest == old_dest
1293 || !REG_P (dest)(((enum rtx_code) (dest)->code) == REG)
1294 || !reg_overlap_mentioned_p (dest, from))
1295 return true;
1296
1297 if (SUBREG_P (old_dest)(((enum rtx_code) (old_dest)->code) == SUBREG)
1298 && SUBREG_REG (old_dest)(((old_dest)->u.fld[0]).rt_rtx) == dest
1299 && !read_modify_subreg_p (old_dest))
1300 return true;
1301
1302 failure_reason = "is part of a read-write destination";
1303 return false;
1304}
1305
1306/* Try to process the instruction pattern at *LOC. Return true on success;
1307 leave the caller to clean up on failure. */
1308
1309bool
1310insn_propagation::apply_to_pattern_1 (rtx *loc)
1311{
1312 rtx body = *loc;
1313 switch (GET_CODE (body)((enum rtx_code) (body)->code))
1314 {
1315 case COND_EXEC:
1316 return (apply_to_rvalue_1 (&COND_EXEC_TEST (body)(((body)->u.fld[0]).rt_rtx))
1317 && apply_to_pattern_1 (&COND_EXEC_CODE (body)(((body)->u.fld[1]).rt_rtx)));
1318
1319 case PARALLEL:
1320 {
1321 int last = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1;
1322 for (int i = 0; i < last; ++i)
1323 if (!apply_to_pattern_1 (&XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i])))
1324 return false;
1325 return apply_to_pattern_1 (&XVECEXP (body, 0, last)(((((body)->u.fld[0]).rt_rtvec))->elem[last]));
1326 }
1327
1328 case ASM_OPERANDS:
1329 for (int i = 0, len = ASM_OPERANDS_INPUT_LENGTH (body)(((((body)->u.fld[3]).rt_rtvec))->num_elem); i < len; ++i)
1330 if (!apply_to_rvalue_1 (&ASM_OPERANDS_INPUT (body, i)(((((body)->u.fld[3]).rt_rtvec))->elem[i])))
1331 return false;
1332 return true;
1333
1334 case CLOBBER:
1335 return apply_to_lvalue_1 (XEXP (body, 0)(((body)->u.fld[0]).rt_rtx));
1336
1337 case SET:
1338 return (apply_to_lvalue_1 (SET_DEST (body)(((body)->u.fld[0]).rt_rtx))
1339 && apply_to_rvalue_1 (&SET_SRC (body)(((body)->u.fld[1]).rt_rtx)));
1340
1341 default:
1342 /* All the other possibilities never store and can use a normal
1343 rtx walk. This includes:
1344
1345 - USE
1346 - TRAP_IF
1347 - PREFETCH
1348 - UNSPEC
1349 - UNSPEC_VOLATILE. */
1350 return apply_to_rvalue_1 (loc);
1351 }
1352}
1353
1354/* Apply this insn_propagation object's simplification or substitution
1355 to the instruction pattern at LOC. */
1356
1357bool
1358insn_propagation::apply_to_pattern (rtx *loc)
1359{
1360 unsigned int num_changes = num_validated_changes ();
1361 bool res = apply_to_pattern_1 (loc);
1362 if (!res)
1363 cancel_changes (num_changes);
1364 return res;
1365}
1366
1367/* Apply this insn_propagation object's simplification or substitution
1368 to the rvalue expression at LOC. */
1369
1370bool
1371insn_propagation::apply_to_rvalue (rtx *loc)
1372{
1373 unsigned int num_changes = num_validated_changes ();
1374 bool res = apply_to_rvalue_1 (loc);
1375 if (!res)
1376 cancel_changes (num_changes);
1377 return res;
1378}
1379
1380/* Check whether INSN matches a specific alternative of an .md pattern. */
1381
1382bool
1383valid_insn_p (rtx_insn *insn)
1384{
1385 recog_memoized (insn);
1386 if (INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) < 0)
1387 return false;
1388 extract_insn (insn);
1389 /* We don't know whether the insn will be in code that is optimized
1390 for size or speed, so consider all enabled alternatives. */
1391 if (!constrain_operands (1, get_enabled_alternatives (insn)))
1392 return false;
1393 return true;
1394}
1395
1396/* Return true if OP is a valid general operand for machine mode MODE.
1397 This is either a register reference, a memory reference,
1398 or a constant. In the case of a memory reference, the address
1399 is checked for general validity for the target machine.
1400
1401 Register and memory references must have mode MODE in order to be valid,
1402 but some constants have no machine mode and are valid for any mode.
1403
1404 If MODE is VOIDmode, OP is checked for validity for whatever mode
1405 it has.
1406
1407 The main use of this function is as a predicate in match_operand
1408 expressions in the machine description. */
1409
1410bool
1411general_operand (rtx op, machine_mode mode)
1412{
1413 enum rtx_code code = GET_CODE (op)((enum rtx_code) (op)->code);
1414
1415 if (mode == VOIDmode((void) 0, E_VOIDmode))
1416 mode = GET_MODE (op)((machine_mode) (op)->mode);
1417
1418 /* Don't accept CONST_INT or anything similar
1419 if the caller wants something floating. */
1420 if (GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode) && mode != VOIDmode((void) 0, E_VOIDmode)
1421 && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_INT
1422 && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_PARTIAL_INT)
1423 return false;
1424
1425 if (CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT)
1426 && mode != VOIDmode((void) 0, E_VOIDmode)
1427 && trunc_int_for_mode (INTVAL (op)((op)->u.hwint[0]), mode) != INTVAL (op)((op)->u.hwint[0]))
1428 return false;
1429
1430 if (CONSTANT_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ
)
)
1431 return ((GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode) || GET_MODE (op)((machine_mode) (op)->mode) == mode
1432 || mode == VOIDmode((void) 0, E_VOIDmode))
1433 && (! flag_picglobal_options.x_flag_pic || LEGITIMATE_PIC_OPERAND_P (op)legitimate_pic_operand_p (op))
1434 && targetm.legitimate_constant_p (mode == VOIDmode((void) 0, E_VOIDmode)
1435 ? GET_MODE (op)((machine_mode) (op)->mode)
1436 : mode, op));
1437
1438 /* Except for certain constants with VOIDmode, already checked for,
1439 OP's mode must match MODE if MODE specifies a mode. */
1440
1441 if (GET_MODE (op)((machine_mode) (op)->mode) != mode)
1442 return false;
1443
1444 if (code == SUBREG)
1445 {
1446 rtx sub = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);
1447
1448#ifdef INSN_SCHEDULING
1449 /* On machines that have insn scheduling, we want all memory
1450 reference to be explicit, so outlaw paradoxical SUBREGs.
1451 However, we must allow them after reload so that they can
1452 get cleaned up by cleanup_subreg_operands. */
1453 if (!reload_completed && MEM_P (sub)(((enum rtx_code) (sub)->code) == MEM)
1454 && paradoxical_subreg_p (op))
1455 return false;
1456#endif
1457 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1458 may result in incorrect reference. We should simplify all valid
1459 subregs of MEM anyway. But allow this after reload because we
1460 might be called from cleanup_subreg_operands.
1461
1462 ??? This is a kludge. */
1463 if (!reload_completed
1464 && maybe_ne (SUBREG_BYTE (op)(((op)->u.fld[1]).rt_subreg), 0)
1465 && MEM_P (sub)(((enum rtx_code) (sub)->code) == MEM))
1466 return false;
1467
1468 if (REG_P (sub)(((enum rtx_code) (sub)->code) == REG)
1469 && REGNO (sub)(rhs_regno(sub)) < FIRST_PSEUDO_REGISTER76
1470 && !REG_CAN_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode)(targetm.can_change_mode_class (((machine_mode) (sub)->mode
), mode, (regclass_map[((rhs_regno(sub)))])))
1471 && GET_MODE_CLASS (GET_MODE (sub))((enum mode_class) mode_class[((machine_mode) (sub)->mode)
])
!= MODE_COMPLEX_INT
1472 && GET_MODE_CLASS (GET_MODE (sub))((enum mode_class) mode_class[((machine_mode) (sub)->mode)
])
!= MODE_COMPLEX_FLOAT
1473 /* LRA can generate some invalid SUBREGS just for matched
1474 operand reload presentation. LRA needs to treat them as
1475 valid. */
1476 && ! LRA_SUBREG_P (op)(__extension__ ({ __typeof ((op)) const _rtx = ((op)); if (((
enum rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag
("LRA_SUBREG_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 1476, __FUNCTION__); _rtx; })->jump)
)
1477 return false;
1478
1479 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1480 create such rtl, and we must reject it. */
1481 if (SCALAR_FLOAT_MODE_P (GET_MODE (op))(((enum mode_class) mode_class[((machine_mode) (op)->mode)
]) == MODE_FLOAT || ((enum mode_class) mode_class[((machine_mode
) (op)->mode)]) == MODE_DECIMAL_FLOAT)
1482 /* LRA can use subreg to store a floating point value in an
1483 integer mode. Although the floating point and the
1484 integer modes need the same number of hard registers, the
1485 size of floating point mode can be less than the integer
1486 mode. */
1487 && ! lra_in_progress
1488 && paradoxical_subreg_p (op))
1489 return false;
1490
1491 op = sub;
1492 code = GET_CODE (op)((enum rtx_code) (op)->code);
1493 }
1494
1495 if (code == REG)
1496 return (REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76
1497 || in_hard_reg_set_p (operand_reg_set(this_target_hard_regs->x_operand_reg_set), GET_MODE (op)((machine_mode) (op)->mode), REGNO (op)(rhs_regno(op))));
1498
1499 if (code == MEM)
1500 {
1501 rtx y = XEXP (op, 0)(((op)->u.fld[0]).rt_rtx);
1502
1503 if (! volatile_ok && MEM_VOLATILE_P (op)(__extension__ ({ __typeof ((op)) const _rtx = ((op)); if (((
enum rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 1503, __FUNCTION__); _rtx; })->volatil)
)
1504 return false;
1505
1506 /* Use the mem's mode, since it will be reloaded thus. LRA can
1507 generate move insn with invalid addresses which is made valid
1508 and efficiently calculated by LRA through further numerous
1509 transformations. */
1510 if (lra_in_progress
1511 || memory_address_addr_space_p (GET_MODE (op)((machine_mode) (op)->mode), y, MEM_ADDR_SPACE (op)(get_mem_attrs (op)->addrspace)))
1512 return true;
1513 }
1514
1515 return false;
1516}
1517
1518/* Return true if OP is a valid memory address for a memory reference
1519 of mode MODE.
1520
1521 The main use of this function is as a predicate in match_operand
1522 expressions in the machine description. */
1523
1524bool
1525address_operand (rtx op, machine_mode mode)
1526{
1527 /* Wrong mode for an address expr. */
1528 if (GET_MODE (op)((machine_mode) (op)->mode) != VOIDmode((void) 0, E_VOIDmode)
1529 && ! SCALAR_INT_MODE_P (GET_MODE (op))(((enum mode_class) mode_class[((machine_mode) (op)->mode)
]) == MODE_INT || ((enum mode_class) mode_class[((machine_mode
) (op)->mode)]) == MODE_PARTIAL_INT)
)
1530 return false;
1531
1532 return memory_address_p (mode, op)memory_address_addr_space_p ((mode), (op), 0);
1533}
1534
1535/* Return true if OP is a register reference of mode MODE.
1536 If MODE is VOIDmode, accept a register in any mode.
1537
1538 The main use of this function is as a predicate in match_operand
1539 expressions in the machine description. */
1540
1541bool
1542register_operand (rtx op, machine_mode mode)
1543{
1544 if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG)
1545 {
1546 rtx sub = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);
1547
1548 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1549 because it is guaranteed to be reloaded into one.
1550 Just make sure the MEM is valid in itself.
1551 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1552 but currently it does result from (SUBREG (REG)...) where the
1553 reg went on the stack.) */
1554 if (!REG_P (sub)(((enum rtx_code) (sub)->code) == REG) && (reload_completed || !MEM_P (sub)(((enum rtx_code) (sub)->code) == MEM)))
1555 return false;
1556 }
1557 else if (!REG_P (op)(((enum rtx_code) (op)->code) == REG))
1558 return false;
1559 return general_operand (op, mode);
1560}
1561
1562/* Return true for a register in Pmode; ignore the tested mode. */
1563
1564bool
1565pmode_register_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED__attribute__ ((__unused__)))
1566{
1567 return register_operand (op, Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
);
1568}
1569
1570/* Return true if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1571 or a hard register. */
1572
1573bool
1574scratch_operand (rtx op, machine_mode mode)
1575{
1576 if (GET_MODE (op)((machine_mode) (op)->mode) != mode && mode != VOIDmode((void) 0, E_VOIDmode))
1577 return false;
1578
1579 return (GET_CODE (op)((enum rtx_code) (op)->code) == SCRATCH
1580 || (REG_P (op)(((enum rtx_code) (op)->code) == REG)
1581 && (lra_in_progress
1582 || (REGNO (op)(rhs_regno(op)) < FIRST_PSEUDO_REGISTER76
1583 && REGNO_REG_CLASS (REGNO (op))(regclass_map[((rhs_regno(op)))]) != NO_REGS))));
1584}
1585
1586/* Return true if OP is a valid immediate operand for mode MODE.
1587
1588 The main use of this function is as a predicate in match_operand
1589 expressions in the machine description. */
1590
1591bool
1592immediate_operand (rtx op, machine_mode mode)
1593{
1594 /* Don't accept CONST_INT or anything similar
1595 if the caller wants something floating. */
1596 if (GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode) && mode != VOIDmode((void) 0, E_VOIDmode)
1597 && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_INT
1598 && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_PARTIAL_INT)
1599 return false;
1600
1601 if (CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT)
1602 && mode != VOIDmode((void) 0, E_VOIDmode)
1603 && trunc_int_for_mode (INTVAL (op)((op)->u.hwint[0]), mode) != INTVAL (op)((op)->u.hwint[0]))
1604 return false;
1605
1606 return (CONSTANT_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ
)
1607 && (GET_MODE (op)((machine_mode) (op)->mode) == mode || mode == VOIDmode((void) 0, E_VOIDmode)
1608 || GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode))
1609 && (! flag_picglobal_options.x_flag_pic || LEGITIMATE_PIC_OPERAND_P (op)legitimate_pic_operand_p (op))
1610 && targetm.legitimate_constant_p (mode == VOIDmode((void) 0, E_VOIDmode)
1611 ? GET_MODE (op)((machine_mode) (op)->mode)
1612 : mode, op));
1613}
1614
1615/* Return true if OP is an operand that is a CONST_INT of mode MODE. */
1616
1617bool
1618const_int_operand (rtx op, machine_mode mode)
1619{
1620 if (!CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT))
1621 return false;
1622
1623 if (mode != VOIDmode((void) 0, E_VOIDmode)
1624 && trunc_int_for_mode (INTVAL (op)((op)->u.hwint[0]), mode) != INTVAL (op)((op)->u.hwint[0]))
1625 return false;
1626
1627 return true;
1628}
1629
1630#if TARGET_SUPPORTS_WIDE_INT1
1631/* Return true if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1632 of mode MODE. */
1633bool
1634const_scalar_int_operand (rtx op, machine_mode mode)
1635{
1636 if (!CONST_SCALAR_INT_P (op)((((enum rtx_code) (op)->code) == CONST_INT) || (((enum rtx_code
) (op)->code) == CONST_WIDE_INT))
)
1637 return false;
1638
1639 if (CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT))
1640 return const_int_operand (op, mode);
1641
1642 if (mode != VOIDmode((void) 0, E_VOIDmode))
1643 {
1644 scalar_int_mode int_mode = as_a <scalar_int_mode> (mode);
1645 int prec = GET_MODE_PRECISION (int_mode);
1646 int bitsize = GET_MODE_BITSIZE (int_mode);
1647
1648 if (CONST_WIDE_INT_NUNITS (op)((int)__extension__ ({ __typeof ((op)) const _rtx = ((op)); if
(((enum rtx_code) (_rtx)->code) != CONST_WIDE_INT) rtl_check_failed_flag
("CWI_GET_NUM_ELEM", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 1648, __FUNCTION__); _rtx; })->u2.num_elem)
* HOST_BITS_PER_WIDE_INT64 > bitsize)
1649 return false;
1650
1651 if (prec == bitsize)
1652 return true;
1653 else
1654 {
1655 /* Multiword partial int. */
1656 HOST_WIDE_INTlong x
1657 = CONST_WIDE_INT_ELT (op, CONST_WIDE_INT_NUNITS (op) - 1)((op)->u.hwiv.elem[((int)__extension__ ({ __typeof ((op)) const
_rtx = ((op)); if (((enum rtx_code) (_rtx)->code) != CONST_WIDE_INT
) rtl_check_failed_flag ("CWI_GET_NUM_ELEM", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 1657, __FUNCTION__); _rtx; })->u2.num_elem) - 1])
;
1658 return (sext_hwi (x, prec & (HOST_BITS_PER_WIDE_INT64 - 1)) == x);
1659 }
1660 }
1661 return true;
1662}
1663
1664/* Return true if OP is an operand that is a constant integer or constant
1665 floating-point number of MODE. */
1666
1667bool
1668const_double_operand (rtx op, machine_mode mode)
1669{
1670 return (GET_CODE (op)((enum rtx_code) (op)->code) == CONST_DOUBLE)
1671 && (GET_MODE (op)((machine_mode) (op)->mode) == mode || mode == VOIDmode((void) 0, E_VOIDmode));
1672}
1673#else
1674/* Return true if OP is an operand that is a constant integer or constant
1675 floating-point number of MODE. */
1676
1677bool
1678const_double_operand (rtx op, machine_mode mode)
1679{
1680 /* Don't accept CONST_INT or anything similar
1681 if the caller wants something floating. */
1682 if (GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode) && mode != VOIDmode((void) 0, E_VOIDmode)
1683 && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_INT
1684 && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_PARTIAL_INT)
1685 return false;
1686
1687 return ((CONST_DOUBLE_P (op)(((enum rtx_code) (op)->code) == CONST_DOUBLE) || CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT))
1688 && (mode == VOIDmode((void) 0, E_VOIDmode) || GET_MODE (op)((machine_mode) (op)->mode) == mode
1689 || GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode)));
1690}
1691#endif
1692/* Return true if OP is a general operand that is not an immediate
1693 operand of mode MODE. */
1694
1695bool
1696nonimmediate_operand (rtx op, machine_mode mode)
1697{
1698 return (general_operand (op, mode) && ! CONSTANT_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ
)
);
1699}
1700
1701/* Return true if OP is a register reference or
1702 immediate value of mode MODE. */
1703
1704bool
1705nonmemory_operand (rtx op, machine_mode mode)
1706{
1707 if (CONSTANT_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ
)
)
1708 return immediate_operand (op, mode);
1709 return register_operand (op, mode);
1710}
1711
1712/* Return true if OP is a valid operand that stands for pushing a
1713 value of mode MODE onto the stack.
1714
1715 The main use of this function is as a predicate in match_operand
1716 expressions in the machine description. */
1717
1718bool
1719push_operand (rtx op, machine_mode mode)
1720{
1721 if (!MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
1722 return false;
1723
1724 if (mode != VOIDmode((void) 0, E_VOIDmode) && GET_MODE (op)((machine_mode) (op)->mode) != mode)
1725 return false;
1726
1727 poly_int64 rounded_size = GET_MODE_SIZE (mode);
1728
1729#ifdef PUSH_ROUNDING
1730 rounded_size = PUSH_ROUNDING (MACRO_INT (rounded_size))ix86_push_rounding (((rounded_size).to_constant ()));
1731#endif
1732
1733 op = XEXP (op, 0)(((op)->u.fld[0]).rt_rtx);
1734
1735 if (known_eq (rounded_size, GET_MODE_SIZE (mode))(!maybe_ne (rounded_size, GET_MODE_SIZE (mode))))
1736 {
1737 if (GET_CODE (op)((enum rtx_code) (op)->code) != STACK_PUSH_CODEPRE_DEC)
1738 return false;
1739 }
1740 else
1741 {
1742 poly_int64 offset;
1743 if (GET_CODE (op)((enum rtx_code) (op)->code) != PRE_MODIFY
1744 || GET_CODE (XEXP (op, 1))((enum rtx_code) ((((op)->u.fld[1]).rt_rtx))->code) != PLUS
1745 || XEXP (XEXP (op, 1), 0)((((((op)->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx) != XEXP (op, 0)(((op)->u.fld[0]).rt_rtx)
1746 || !poly_int_rtx_p (XEXP (XEXP (op, 1), 1)((((((op)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx), &offset)
1747 || (STACK_GROWS_DOWNWARD1
1748 ? maybe_ne (offset, -rounded_size)
1749 : maybe_ne (offset, rounded_size)))
1750 return false;
1751 }
1752
1753 return XEXP (op, 0)(((op)->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]);
1754}
1755
1756/* Return true if OP is a valid operand that stands for popping a
1757 value of mode MODE off the stack.
1758
1759 The main use of this function is as a predicate in match_operand
1760 expressions in the machine description. */
1761
1762bool
1763pop_operand (rtx op, machine_mode mode)
1764{
1765 if (!MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
1766 return false;
1767
1768 if (mode != VOIDmode((void) 0, E_VOIDmode) && GET_MODE (op)((machine_mode) (op)->mode) != mode)
1769 return false;
1770
1771 op = XEXP (op, 0)(((op)->u.fld[0]).rt_rtx);
1772
1773 if (GET_CODE (op)((enum rtx_code) (op)->code) != STACK_POP_CODEPOST_INC)
1774 return false;
1775
1776 return XEXP (op, 0)(((op)->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]);
1777}
1778
1779/* Return true if ADDR is a valid memory address
1780 for mode MODE in address space AS. */
1781
1782bool
1783memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED__attribute__ ((__unused__)),
1784 rtx addr, addr_space_t as)
1785{
1786#ifdef GO_IF_LEGITIMATE_ADDRESS
1787 gcc_assert (ADDR_SPACE_GENERIC_P (as))((void)(!(((as) == 0)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 1787, __FUNCTION__), 0 : 0))
;
1788 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1789 return false;
1790
1791 win:
1792 return true;
1793#else
1794 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
1795#endif
1796}
1797
1798/* Return true if OP is a valid memory reference with mode MODE,
1799 including a valid address.
1800
1801 The main use of this function is as a predicate in match_operand
1802 expressions in the machine description. */
1803
1804bool
1805memory_operand (rtx op, machine_mode mode)
1806{
1807 rtx inner;
1808
1809 if (! reload_completed)
1810 /* Note that no SUBREG is a memory operand before end of reload pass,
1811 because (SUBREG (MEM...)) forces reloading into a register. */
1812 return MEM_P (op)(((enum rtx_code) (op)->code) == MEM) && general_operand (op, mode);
1813
1814 if (mode != VOIDmode((void) 0, E_VOIDmode) && GET_MODE (op)((machine_mode) (op)->mode) != mode)
1815 return false;
1816
1817 inner = op;
1818 if (GET_CODE (inner)((enum rtx_code) (inner)->code) == SUBREG)
1819 inner = SUBREG_REG (inner)(((inner)->u.fld[0]).rt_rtx);
1820
1821 return (MEM_P (inner)(((enum rtx_code) (inner)->code) == MEM) && general_operand (op, mode));
1822}
1823
1824/* Return true if OP is a valid indirect memory reference with mode MODE;
1825 that is, a memory reference whose address is a general_operand. */
1826
1827bool
1828indirect_operand (rtx op, machine_mode mode)
1829{
1830 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1831 if (! reload_completed
1832 && GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG && MEM_P (SUBREG_REG (op))(((enum rtx_code) ((((op)->u.fld[0]).rt_rtx))->code) ==
MEM)
)
1833 {
1834 if (mode != VOIDmode((void) 0, E_VOIDmode) && GET_MODE (op)((machine_mode) (op)->mode) != mode)
1835 return false;
1836
1837 /* The only way that we can have a general_operand as the resulting
1838 address is if OFFSET is zero and the address already is an operand
1839 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1840 operand. */
1841 poly_int64 offset;
1842 rtx addr = strip_offset (XEXP (SUBREG_REG (op), 0)((((((op)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx), &offset);
1843 return (known_eq (offset + SUBREG_BYTE (op), 0)(!maybe_ne (offset + (((op)->u.fld[1]).rt_subreg), 0))
1844 && general_operand (addr, Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
));
1845 }
1846
1847 return (MEM_P (op)(((enum rtx_code) (op)->code) == MEM)
1848 && memory_operand (op, mode)
1849 && general_operand (XEXP (op, 0)(((op)->u.fld[0]).rt_rtx), Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
));
1850}
1851
1852/* Return true if this is an ordered comparison operator (not including
1853 ORDERED and UNORDERED). */
1854
1855bool
1856ordered_comparison_operator (rtx op, machine_mode mode)
1857{
1858 if (mode != VOIDmode((void) 0, E_VOIDmode) && GET_MODE (op)((machine_mode) (op)->mode) != mode)
1859 return false;
1860 switch (GET_CODE (op)((enum rtx_code) (op)->code))
1861 {
1862 case EQ:
1863 case NE:
1864 case LT:
1865 case LTU:
1866 case LE:
1867 case LEU:
1868 case GT:
1869 case GTU:
1870 case GE:
1871 case GEU:
1872 return true;
1873 default:
1874 return false;
1875 }
1876}
1877
1878/* Return true if this is a comparison operator. This allows the use of
1879 MATCH_OPERATOR to recognize all the branch insns. */
1880
1881bool
1882comparison_operator (rtx op, machine_mode mode)
1883{
1884 return ((mode == VOIDmode((void) 0, E_VOIDmode) || GET_MODE (op)((machine_mode) (op)->mode) == mode)
1885 && COMPARISON_P (op)(((rtx_class[(int) (((enum rtx_code) (op)->code))]) & (
~1)) == (RTX_COMPARE & (~1)))
);
1886}
1887
1888/* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1889
1890rtx
1891extract_asm_operands (rtx body)
1892{
1893 rtx tmp;
1894 switch (GET_CODE (body)((enum rtx_code) (body)->code))
1895 {
1896 case ASM_OPERANDS:
1897 return body;
1898
1899 case SET:
1900 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1901 tmp = SET_SRC (body)(((body)->u.fld[1]).rt_rtx);
1902 if (GET_CODE (tmp)((enum rtx_code) (tmp)->code) == ASM_OPERANDS)
1903 return tmp;
1904 break;
1905
1906 case PARALLEL:
1907 tmp = XVECEXP (body, 0, 0)(((((body)->u.fld[0]).rt_rtvec))->elem[0]);
1908 if (GET_CODE (tmp)((enum rtx_code) (tmp)->code) == ASM_OPERANDS)
1909 return tmp;
1910 if (GET_CODE (tmp)((enum rtx_code) (tmp)->code) == SET)
1911 {
1912 tmp = SET_SRC (tmp)(((tmp)->u.fld[1]).rt_rtx);
1913 if (GET_CODE (tmp)((enum rtx_code) (tmp)->code) == ASM_OPERANDS)
1914 return tmp;
1915 }
1916 break;
1917
1918 default:
1919 break;
1920 }
1921 return NULLnullptr;
1922}
1923
1924/* If BODY is an insn body that uses ASM_OPERANDS,
1925 return the number of operands (both input and output) in the insn.
1926 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
1927 return 0.
1928 Otherwise return -1. */
1929
1930int
1931asm_noperands (const_rtx body)
1932{
1933 rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body)(const_cast<struct rtx_def *> (((body)))));
1934 int i, n_sets = 0;
1935
1936 if (asm_op == NULLnullptr)
1937 {
1938 if (GET_CODE (body)((enum rtx_code) (body)->code) == PARALLEL && XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) >= 2
1939 && GET_CODE (XVECEXP (body, 0, 0))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[0]))->code)
== ASM_INPUT)
1940 {
1941 /* body is [(asm_input ...) (clobber (reg ...))...]. */
1942 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i > 0; i--)
1943 if (GET_CODE (XVECEXP (body, 0, i))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[i]))->code)
!= CLOBBER)
1944 return -1;
1945 return 0;
1946 }
1947 return -1;
1948 }
1949
1950 if (GET_CODE (body)((enum rtx_code) (body)->code) == SET)
1951 n_sets = 1;
1952 else if (GET_CODE (body)((enum rtx_code) (body)->code) == PARALLEL)
1953 {
1954 if (GET_CODE (XVECEXP (body, 0, 0))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[0]))->code)
== SET)
1955 {
1956 /* Multiple output operands, or 1 output plus some clobbers:
1957 body is
1958 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1959 /* Count backwards through CLOBBERs to determine number of SETs. */
1960 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem); i > 0; i--)
1961 {
1962 if (GET_CODE (XVECEXP (body, 0, i - 1))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[i - 1]))->code)
== SET)
1963 break;
1964 if (GET_CODE (XVECEXP (body, 0, i - 1))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[i - 1]))->code)
!= CLOBBER)
1965 return -1;
1966 }
1967
1968 /* N_SETS is now number of output operands. */
1969 n_sets = i;
1970
1971 /* Verify that all the SETs we have
1972 came from a single original asm_operands insn
1973 (so that invalid combinations are blocked). */
1974 for (i = 0; i < n_sets; i++)
1975 {
1976 rtx elt = XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i]);
1977 if (GET_CODE (elt)((enum rtx_code) (elt)->code) != SET)
1978 return -1;
1979 if (GET_CODE (SET_SRC (elt))((enum rtx_code) ((((elt)->u.fld[1]).rt_rtx))->code) != ASM_OPERANDS)
1980 return -1;
1981 /* If these ASM_OPERANDS rtx's came from different original insns
1982 then they aren't allowed together. */
1983 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))((((((elt)->u.fld[1]).rt_rtx))->u.fld[3]).rt_rtvec)
1984 != ASM_OPERANDS_INPUT_VEC (asm_op)(((asm_op)->u.fld[3]).rt_rtvec))
1985 return -1;
1986 }
1987 }
1988 else
1989 {
1990 /* 0 outputs, but some clobbers:
1991 body is [(asm_operands ...) (clobber (reg ...))...]. */
1992 /* Make sure all the other parallel things really are clobbers. */
1993 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i > 0; i--)
1994 if (GET_CODE (XVECEXP (body, 0, i))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[i]))->code)
!= CLOBBER)
1995 return -1;
1996 }
1997 }
1998
1999 return (ASM_OPERANDS_INPUT_LENGTH (asm_op)(((((asm_op)->u.fld[3]).rt_rtvec))->num_elem)
2000 + ASM_OPERANDS_LABEL_LENGTH (asm_op)(((((asm_op)->u.fld[5]).rt_rtvec))->num_elem) + n_sets);
2001}
2002
2003/* Assuming BODY is an insn body that uses ASM_OPERANDS,
2004 copy its operands (both input and output) into the vector OPERANDS,
2005 the locations of the operands within the insn into the vector OPERAND_LOCS,
2006 and the constraints for the operands into CONSTRAINTS.
2007 Write the modes of the operands into MODES.
2008 Write the location info into LOC.
2009 Return the assembler-template.
2010 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL,
2011 return the basic assembly string.
2012
2013 If LOC, MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
2014 we don't store that info. */
2015
2016const char *
2017decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs,
2018 const char **constraints, machine_mode *modes,
2019 location_t *loc)
2020{
2021 int nbase = 0, n, i;
2022 rtx asmop;
2023
2024 switch (GET_CODE (body)((enum rtx_code) (body)->code))
2025 {
2026 case ASM_OPERANDS:
2027 /* Zero output asm: BODY is (asm_operands ...). */
2028 asmop = body;
2029 break;
2030
2031 case SET:
2032 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
2033 asmop = SET_SRC (body)(((body)->u.fld[1]).rt_rtx);
2034
2035 /* The output is in the SET.
2036 Its constraint is in the ASM_OPERANDS itself. */
2037 if (operands)
2038 operands[0] = SET_DEST (body)(((body)->u.fld[0]).rt_rtx);
2039 if (operand_locs)
2040 operand_locs[0] = &SET_DEST (body)(((body)->u.fld[0]).rt_rtx);
2041 if (constraints)
2042 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop)(((asmop)->u.fld[1]).rt_str);
2043 if (modes)
2044 modes[0] = GET_MODE (SET_DEST (body))((machine_mode) ((((body)->u.fld[0]).rt_rtx))->mode);
2045 nbase = 1;
2046 break;
2047
2048 case PARALLEL:
2049 {
2050 int nparallel = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem); /* Includes CLOBBERs. */
2051
2052 asmop = XVECEXP (body, 0, 0)(((((body)->u.fld[0]).rt_rtvec))->elem[0]);
2053 if (GET_CODE (asmop)((enum rtx_code) (asmop)->code) == SET)
2054 {
2055 asmop = SET_SRC (asmop)(((asmop)->u.fld[1]).rt_rtx);
2056
2057 /* At least one output, plus some CLOBBERs. The outputs are in
2058 the SETs. Their constraints are in the ASM_OPERANDS itself. */
2059 for (i = 0; i < nparallel; i++)
2060 {
2061 if (GET_CODE (XVECEXP (body, 0, i))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[i]))->code)
== CLOBBER)
2062 break; /* Past last SET */
2063 gcc_assert (GET_CODE (XVECEXP (body, 0, i)) == SET)((void)(!(((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec
))->elem[i]))->code) == SET) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2063, __FUNCTION__), 0 : 0))
;
2064 if (operands)
2065 operands[i] = SET_DEST (XVECEXP (body, 0, i))((((((((body)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx)
;
2066 if (operand_locs)
2067 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i))((((((((body)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx)
;
2068 if (constraints)
2069 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1)(((((((((((body)->u.fld[0]).rt_rtvec))->elem[i]))->u
.fld[1]).rt_rtx))->u.fld[1]).rt_str)
;
2070 if (modes)
2071 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)))((machine_mode) (((((((((body)->u.fld[0]).rt_rtvec))->elem
[i]))->u.fld[0]).rt_rtx))->mode)
;
2072 }
2073 nbase = i;
2074 }
2075 else if (GET_CODE (asmop)((enum rtx_code) (asmop)->code) == ASM_INPUT)
2076 {
2077 if (loc)
2078 *loc = ASM_INPUT_SOURCE_LOCATION (asmop)(((asmop)->u.fld[1]).rt_uint);
2079 return XSTR (asmop, 0)(((asmop)->u.fld[0]).rt_str);
2080 }
2081 break;
2082 }
2083
2084 default:
2085 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2085, __FUNCTION__))
;
2086 }
2087
2088 n = ASM_OPERANDS_INPUT_LENGTH (asmop)(((((asmop)->u.fld[3]).rt_rtvec))->num_elem);
2089 for (i = 0; i < n; i++)
2090 {
2091 if (operand_locs)
2092 operand_locs[nbase + i] = &ASM_OPERANDS_INPUT (asmop, i)(((((asmop)->u.fld[3]).rt_rtvec))->elem[i]);
2093 if (operands)
2094 operands[nbase + i] = ASM_OPERANDS_INPUT (asmop, i)(((((asmop)->u.fld[3]).rt_rtvec))->elem[i]);
2095 if (constraints)
2096 constraints[nbase + i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i)((((((((asmop)->u.fld[4]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_str)
;
2097 if (modes)
2098 modes[nbase + i] = ASM_OPERANDS_INPUT_MODE (asmop, i)((machine_mode) ((((((asmop)->u.fld[4]).rt_rtvec))->elem
[i]))->mode)
;
2099 }
2100 nbase += n;
2101
2102 n = ASM_OPERANDS_LABEL_LENGTH (asmop)(((((asmop)->u.fld[5]).rt_rtvec))->num_elem);
2103 for (i = 0; i < n; i++)
2104 {
2105 if (operand_locs)
2106 operand_locs[nbase + i] = &ASM_OPERANDS_LABEL (asmop, i)(((((asmop)->u.fld[5]).rt_rtvec))->elem[i]);
2107 if (operands)
2108 operands[nbase + i] = ASM_OPERANDS_LABEL (asmop, i)(((((asmop)->u.fld[5]).rt_rtvec))->elem[i]);
2109 if (constraints)
2110 constraints[nbase + i] = "";
2111 if (modes)
2112 modes[nbase + i] = Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
;
2113 }
2114
2115 if (loc)
2116 *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop)(((asmop)->u.fld[6]).rt_uint);
2117
2118 return ASM_OPERANDS_TEMPLATE (asmop)(((asmop)->u.fld[0]).rt_str);
2119}
2120
2121/* Parse inline assembly string STRING and determine which operands are
2122 referenced by % markers. For the first NOPERANDS operands, set USED[I]
2123 to true if operand I is referenced.
2124
2125 This is intended to distinguish barrier-like asms such as:
2126
2127 asm ("" : "=m" (...));
2128
2129 from real references such as:
2130
2131 asm ("sw\t$0, %0" : "=m" (...)); */
2132
2133void
2134get_referenced_operands (const char *string, bool *used,
2135 unsigned int noperands)
2136{
2137 memset (used, 0, sizeof (bool) * noperands);
2138 const char *p = string;
2139 while (*p)
2140 switch (*p)
2141 {
2142 case '%':
2143 p += 1;
2144 /* A letter followed by a digit indicates an operand number. */
2145 if (ISALPHA (p[0])(_sch_istable[(p[0]) & 0xff] & (unsigned short)(_sch_isalpha
))
&& ISDIGIT (p[1])(_sch_istable[(p[1]) & 0xff] & (unsigned short)(_sch_isdigit
))
)
2146 p += 1;
2147 if (ISDIGIT (*p)(_sch_istable[(*p) & 0xff] & (unsigned short)(_sch_isdigit
))
)
2148 {
2149 char *endptr;
2150 unsigned long opnum = strtoul (p, &endptr, 10);
2151 if (endptr != p && opnum < noperands)
2152 used[opnum] = true;
2153 p = endptr;
2154 }
2155 else
2156 p += 1;
2157 break;
2158
2159 default:
2160 p++;
2161 break;
2162 }
2163}
2164
2165/* Check if an asm_operand matches its constraints.
2166 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
2167
2168int
2169asm_operand_ok (rtx op, const char *constraint, const char **constraints)
2170{
2171 int result = 0;
2172 bool incdec_ok = false;
2173
2174 /* Use constrain_operands after reload. */
2175 gcc_assert (!reload_completed)((void)(!(!reload_completed) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2175, __FUNCTION__), 0 : 0))
;
2176
2177 /* Empty constraint string is the same as "X,...,X", i.e. X for as
2178 many alternatives as required to match the other operands. */
2179 if (*constraint == '\0')
2180 result = 1;
2181
2182 while (*constraint)
2183 {
2184 enum constraint_num cn;
2185 char c = *constraint;
2186 int len;
2187 switch (c)
2188 {
2189 case ',':
2190 constraint++;
2191 continue;
2192
2193 case '0': case '1': case '2': case '3': case '4':
2194 case '5': case '6': case '7': case '8': case '9':
2195 /* If caller provided constraints pointer, look up
2196 the matching constraint. Otherwise, our caller should have
2197 given us the proper matching constraint, but we can't
2198 actually fail the check if they didn't. Indicate that
2199 results are inconclusive. */
2200 if (constraints)
2201 {
2202 char *end;
2203 unsigned long match;
2204
2205 match = strtoul (constraint, &end, 10);
2206 if (!result)
2207 result = asm_operand_ok (op, constraints[match], NULLnullptr);
2208 constraint = (const char *) end;
2209 }
2210 else
2211 {
2212 do
2213 constraint++;
2214 while (ISDIGIT (*constraint)(_sch_istable[(*constraint) & 0xff] & (unsigned short
)(_sch_isdigit))
);
2215 if (! result)
2216 result = -1;
2217 }
2218 continue;
2219
2220 /* The rest of the compiler assumes that reloading the address
2221 of a MEM into a register will make it fit an 'o' constraint.
2222 That is, if it sees a MEM operand for an 'o' constraint,
2223 it assumes that (mem (base-reg)) will fit.
2224
2225 That assumption fails on targets that don't have offsettable
2226 addresses at all. We therefore need to treat 'o' asm
2227 constraints as a special case and only accept operands that
2228 are already offsettable, thus proving that at least one
2229 offsettable address exists. */
2230 case 'o': /* offsettable */
2231 if (offsettable_nonstrict_memref_p (op))
2232 result = 1;
2233 break;
2234
2235 case 'g':
2236 if (general_operand (op, VOIDmode((void) 0, E_VOIDmode)))
2237 result = 1;
2238 break;
2239
2240 case '<':
2241 case '>':
2242 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
2243 to exist, excepting those that expand_call created. Further,
2244 on some machines which do not have generalized auto inc/dec,
2245 an inc/dec is not a memory_operand.
2246
2247 Match any memory and hope things are resolved after reload. */
2248 incdec_ok = true;
Value stored to 'incdec_ok' is never read
2249 /* FALLTHRU */
2250 default:
2251 cn = lookup_constraint (constraint);
2252 rtx mem = NULLnullptr;
2253 switch (get_constraint_type (cn))
2254 {
2255 case CT_REGISTER:
2256 if (!result
2257 && reg_class_for_constraint (cn) != NO_REGS
2258 && GET_MODE (op)((machine_mode) (op)->mode) != BLKmode((void) 0, E_BLKmode)
2259 && register_operand (op, VOIDmode((void) 0, E_VOIDmode)))
2260 result = 1;
2261 break;
2262
2263 case CT_CONST_INT:
2264 if (!result
2265 && CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT)
2266 && insn_const_int_ok_for_constraint (INTVAL (op)((op)->u.hwint[0]), cn))
2267 result = 1;
2268 break;
2269
2270 case CT_MEMORY:
2271 case CT_RELAXED_MEMORY:
2272 mem = op;
2273 /* Fall through. */
2274 case CT_SPECIAL_MEMORY:
2275 /* Every memory operand can be reloaded to fit. */
2276 if (!mem)
2277 mem = extract_mem_from_operand (op);
2278 result = result || memory_operand (mem, VOIDmode((void) 0, E_VOIDmode));
2279 break;
2280
2281 case CT_ADDRESS:
2282 /* Every address operand can be reloaded to fit. */
2283 result = result || address_operand (op, VOIDmode((void) 0, E_VOIDmode));
2284 break;
2285
2286 case CT_FIXED_FORM:
2287 result = result || constraint_satisfied_p (op, cn);
2288 break;
2289 }
2290 break;
2291 }
2292 len = CONSTRAINT_LEN (c, constraint)insn_constraint_len (c,constraint);
2293 do
2294 constraint++;
2295 while (--len && *constraint && *constraint != ',');
2296 if (len)
2297 return 0;
2298 }
2299
2300 /* For operands without < or > constraints reject side-effects. */
2301 if (AUTO_INC_DEC0 && !incdec_ok && result && MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
2302 switch (GET_CODE (XEXP (op, 0))((enum rtx_code) ((((op)->u.fld[0]).rt_rtx))->code))
2303 {
2304 case PRE_INC:
2305 case POST_INC:
2306 case PRE_DEC:
2307 case POST_DEC:
2308 case PRE_MODIFY:
2309 case POST_MODIFY:
2310 return 0;
2311 default:
2312 break;
2313 }
2314
2315 return result;
2316}
2317
2318/* Given an rtx *P, if it is a sum containing an integer constant term,
2319 return the location (type rtx *) of the pointer to that constant term.
2320 Otherwise, return a null pointer. */
2321
2322rtx *
2323find_constant_term_loc (rtx *p)
2324{
2325 rtx *tem;
2326 enum rtx_code code = GET_CODE (*p)((enum rtx_code) (*p)->code);
2327
2328 /* If *P IS such a constant term, P is its location. */
2329
2330 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
2331 || code == CONST)
2332 return p;
2333
2334 /* Otherwise, if not a sum, it has no constant term. */
2335
2336 if (GET_CODE (*p)((enum rtx_code) (*p)->code) != PLUS)
2337 return 0;
2338
2339 /* If one of the summands is constant, return its location. */
2340
2341 if (XEXP (*p, 0)(((*p)->u.fld[0]).rt_rtx) && CONSTANT_P (XEXP (*p, 0))((rtx_class[(int) (((enum rtx_code) ((((*p)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
2342 && XEXP (*p, 1)(((*p)->u.fld[1]).rt_rtx) && CONSTANT_P (XEXP (*p, 1))((rtx_class[(int) (((enum rtx_code) ((((*p)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
)
2343 return p;
2344
2345 /* Otherwise, check each summand for containing a constant term. */
2346
2347 if (XEXP (*p, 0)(((*p)->u.fld[0]).rt_rtx) != 0)
2348 {
2349 tem = find_constant_term_loc (&XEXP (*p, 0)(((*p)->u.fld[0]).rt_rtx));
2350 if (tem != 0)
2351 return tem;
2352 }
2353
2354 if (XEXP (*p, 1)(((*p)->u.fld[1]).rt_rtx) != 0)
2355 {
2356 tem = find_constant_term_loc (&XEXP (*p, 1)(((*p)->u.fld[1]).rt_rtx));
2357 if (tem != 0)
2358 return tem;
2359 }
2360
2361 return 0;
2362}
2363
2364/* Return true if OP is a memory reference whose address contains
2365 no side effects and remains valid after the addition of a positive
2366 integer less than the size of the object being referenced.
2367
2368 We assume that the original address is valid and do not check it.
2369
2370 This uses strict_memory_address_p as a subroutine, so
2371 don't use it before reload. */
2372
2373bool
2374offsettable_memref_p (rtx op)
2375{
2376 return ((MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
2377 && offsettable_address_addr_space_p (1, GET_MODE (op)((machine_mode) (op)->mode), XEXP (op, 0)(((op)->u.fld[0]).rt_rtx),
2378 MEM_ADDR_SPACE (op)(get_mem_attrs (op)->addrspace)));
2379}
2380
2381/* Similar, but don't require a strictly valid mem ref:
2382 consider pseudo-regs valid as index or base regs. */
2383
2384bool
2385offsettable_nonstrict_memref_p (rtx op)
2386{
2387 return ((MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
2388 && offsettable_address_addr_space_p (0, GET_MODE (op)((machine_mode) (op)->mode), XEXP (op, 0)(((op)->u.fld[0]).rt_rtx),
2389 MEM_ADDR_SPACE (op)(get_mem_attrs (op)->addrspace)));
2390}
2391
2392/* Return true if Y is a memory address which contains no side effects
2393 and would remain valid for address space AS after the addition of
2394 a positive integer less than the size of that mode.
2395
2396 We assume that the original address is valid and do not check it.
2397 We do check that it is valid for narrower modes.
2398
2399 If STRICTP is nonzero, we require a strictly valid address,
2400 for the sake of use in reload.c. */
2401
2402bool
2403offsettable_address_addr_space_p (int strictp, machine_mode mode, rtx y,
2404 addr_space_t as)
2405{
2406 enum rtx_code ycode = GET_CODE (y)((enum rtx_code) (y)->code);
2407 rtx z;
2408 rtx y1 = y;
2409 rtx *y2;
2410 bool (*addressp) (machine_mode, rtx, addr_space_t) =
2411 (strictp ? strict_memory_address_addr_space_p
2412 : memory_address_addr_space_p);
2413 poly_int64 mode_sz = GET_MODE_SIZE (mode);
2414
2415 if (CONSTANT_ADDRESS_P (y)constant_address_p (y))
2416 return true;
2417
2418 /* Adjusting an offsettable address involves changing to a narrower mode.
2419 Make sure that's OK. */
2420
2421 if (mode_dependent_address_p (y, as))
2422 return false;
2423
2424 machine_mode address_mode = GET_MODE (y)((machine_mode) (y)->mode);
2425 if (address_mode == VOIDmode((void) 0, E_VOIDmode))
2426 address_mode = targetm.addr_space.address_mode (as);
2427#ifdef POINTERS_EXTEND_UNSIGNED1
2428 machine_mode pointer_mode = targetm.addr_space.pointer_mode (as);
2429#endif
2430
2431 /* ??? How much offset does an offsettable BLKmode reference need?
2432 Clearly that depends on the situation in which it's being used.
2433 However, the current situation in which we test 0xffffffff is
2434 less than ideal. Caveat user. */
2435 if (known_eq (mode_sz, 0)(!maybe_ne (mode_sz, 0)))
2436 mode_sz = BIGGEST_ALIGNMENT(((global_options.x_target_flags & (1U << 12)) != 0
) ? 32 : (((global_options.x_ix86_isa_flags & (1UL <<
15)) != 0) ? 512 : (((global_options.x_ix86_isa_flags & (
1UL << 8)) != 0) ? 256 : 128)))
/ BITS_PER_UNIT(8);
2437
2438 /* If the expression contains a constant term,
2439 see if it remains valid when max possible offset is added. */
2440
2441 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
2442 {
2443 bool good;
2444
2445 y1 = *y2;
2446 *y2 = plus_constant (address_mode, *y2, mode_sz - 1);
2447 /* Use QImode because an odd displacement may be automatically invalid
2448 for any wider mode. But it should be valid for a single byte. */
2449 good = (*addressp) (QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)), y, as);
2450
2451 /* In any case, restore old contents of memory. */
2452 *y2 = y1;
2453 return good;
2454 }
2455
2456 if (GET_RTX_CLASS (ycode)(rtx_class[(int) (ycode)]) == RTX_AUTOINC)
2457 return false;
2458
2459 /* The offset added here is chosen as the maximum offset that
2460 any instruction could need to add when operating on something
2461 of the specified mode. We assume that if Y and Y+c are
2462 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2463 go inside a LO_SUM here, so we do so as well. */
2464 if (GET_CODE (y)((enum rtx_code) (y)->code) == LO_SUM
2465 && mode != BLKmode((void) 0, E_BLKmode)
2466 && known_le (mode_sz, GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)(!maybe_lt (get_mode_alignment (mode) / (8), mode_sz)))
2467 z = gen_rtx_LO_SUM (address_mode, XEXP (y, 0),gen_rtx_fmt_ee_stat ((LO_SUM), ((address_mode)), (((((y)->
u.fld[0]).rt_rtx))), ((plus_constant (address_mode, (((y)->
u.fld[1]).rt_rtx), mode_sz - 1))) )
2468 plus_constant (address_mode, XEXP (y, 1),gen_rtx_fmt_ee_stat ((LO_SUM), ((address_mode)), (((((y)->
u.fld[0]).rt_rtx))), ((plus_constant (address_mode, (((y)->
u.fld[1]).rt_rtx), mode_sz - 1))) )
2469 mode_sz - 1))gen_rtx_fmt_ee_stat ((LO_SUM), ((address_mode)), (((((y)->
u.fld[0]).rt_rtx))), ((plus_constant (address_mode, (((y)->
u.fld[1]).rt_rtx), mode_sz - 1))) )
;
2470#ifdef POINTERS_EXTEND_UNSIGNED1
2471 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2472 else if (POINTERS_EXTEND_UNSIGNED1 > 0
2473 && GET_CODE (y)((enum rtx_code) (y)->code) == ZERO_EXTEND
2474 && GET_MODE (XEXP (y, 0))((machine_mode) ((((y)->u.fld[0]).rt_rtx))->mode) == pointer_mode)
2475 z = gen_rtx_ZERO_EXTEND (address_mode,gen_rtx_fmt_e_stat ((ZERO_EXTEND), ((address_mode)), ((plus_constant
(pointer_mode, (((y)->u.fld[0]).rt_rtx), mode_sz - 1))) )
2476 plus_constant (pointer_mode, XEXP (y, 0),gen_rtx_fmt_e_stat ((ZERO_EXTEND), ((address_mode)), ((plus_constant
(pointer_mode, (((y)->u.fld[0]).rt_rtx), mode_sz - 1))) )
2477 mode_sz - 1))gen_rtx_fmt_e_stat ((ZERO_EXTEND), ((address_mode)), ((plus_constant
(pointer_mode, (((y)->u.fld[0]).rt_rtx), mode_sz - 1))) )
;
2478#endif
2479 else
2480 z = plus_constant (address_mode, y, mode_sz - 1);
2481
2482 /* Use QImode because an odd displacement may be automatically invalid
2483 for any wider mode. But it should be valid for a single byte. */
2484 return (*addressp) (QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)), z, as);
2485}
2486
2487/* Return true if ADDR is an address-expression whose effect depends
2488 on the mode of the memory reference it is used in.
2489
2490 ADDRSPACE is the address space associated with the address.
2491
2492 Autoincrement addressing is a typical example of mode-dependence
2493 because the amount of the increment depends on the mode. */
2494
2495bool
2496mode_dependent_address_p (rtx addr, addr_space_t addrspace)
2497{
2498 /* Auto-increment addressing with anything other than post_modify
2499 or pre_modify always introduces a mode dependency. Catch such
2500 cases now instead of deferring to the target. */
2501 if (GET_CODE (addr)((enum rtx_code) (addr)->code) == PRE_INC
2502 || GET_CODE (addr)((enum rtx_code) (addr)->code) == POST_INC
2503 || GET_CODE (addr)((enum rtx_code) (addr)->code) == PRE_DEC
2504 || GET_CODE (addr)((enum rtx_code) (addr)->code) == POST_DEC)
2505 return true;
2506
2507 return targetm.mode_dependent_address_p (addr, addrspace);
2508}
2509
2510/* Return true if boolean attribute ATTR is supported. */
2511
2512static bool
2513have_bool_attr (bool_attr attr)
2514{
2515 switch (attr)
2516 {
2517 case BA_ENABLED:
2518 return HAVE_ATTR_enabled1;
2519 case BA_PREFERRED_FOR_SIZE:
2520 return HAVE_ATTR_enabled1 || HAVE_ATTR_preferred_for_size1;
2521 case BA_PREFERRED_FOR_SPEED:
2522 return HAVE_ATTR_enabled1 || HAVE_ATTR_preferred_for_speed1;
2523 }
2524 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2524, __FUNCTION__))
;
2525}
2526
2527/* Return the value of ATTR for instruction INSN. */
2528
2529static bool
2530get_bool_attr (rtx_insn *insn, bool_attr attr)
2531{
2532 switch (attr)
2533 {
2534 case BA_ENABLED:
2535 return get_attr_enabled (insn);
2536 case BA_PREFERRED_FOR_SIZE:
2537 return get_attr_enabled (insn) && get_attr_preferred_for_size (insn);
2538 case BA_PREFERRED_FOR_SPEED:
2539 return get_attr_enabled (insn) && get_attr_preferred_for_speed (insn);
2540 }
2541 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2541, __FUNCTION__))
;
2542}
2543
2544/* Like get_bool_attr_mask, but don't use the cache. */
2545
2546static alternative_mask
2547get_bool_attr_mask_uncached (rtx_insn *insn, bool_attr attr)
2548{
2549 /* Temporarily install enough information for get_attr_<foo> to assume
2550 that the insn operands are already cached. As above, the attribute
2551 mustn't depend on the values of operands, so we don't provide their
2552 real values here. */
2553 rtx_insn *old_insn = recog_data.insn;
2554 int old_alternative = which_alternative;
2555
2556 recog_data.insn = insn;
2557 alternative_mask mask = ALL_ALTERNATIVES((alternative_mask) -1);
2558 int n_alternatives = insn_data[INSN_CODE (insn)(((insn)->u.fld[5]).rt_int)].n_alternatives;
2559 for (int i = 0; i < n_alternatives; i++)
2560 {
2561 which_alternative = i;
2562 if (!get_bool_attr (insn, attr))
2563 mask &= ~ALTERNATIVE_BIT (i)((alternative_mask) 1 << (i));
2564 }
2565
2566 recog_data.insn = old_insn;
2567 which_alternative = old_alternative;
2568 return mask;
2569}
2570
2571/* Return the mask of operand alternatives that are allowed for INSN
2572 by boolean attribute ATTR. This mask depends only on INSN and on
2573 the current target; it does not depend on things like the values of
2574 operands. */
2575
2576static alternative_mask
2577get_bool_attr_mask (rtx_insn *insn, bool_attr attr)
2578{
2579 /* Quick exit for asms and for targets that don't use these attributes. */
2580 int code = INSN_CODE (insn)(((insn)->u.fld[5]).rt_int);
2581 if (code < 0 || !have_bool_attr (attr))
2582 return ALL_ALTERNATIVES((alternative_mask) -1);
2583
2584 /* Calling get_attr_<foo> can be expensive, so cache the mask
2585 for speed. */
2586 if (!this_target_recog->x_bool_attr_masks[code][attr])
2587 this_target_recog->x_bool_attr_masks[code][attr]
2588 = get_bool_attr_mask_uncached (insn, attr);
2589 return this_target_recog->x_bool_attr_masks[code][attr];
2590}
2591
2592/* Return the set of alternatives of INSN that are allowed by the current
2593 target. */
2594
2595alternative_mask
2596get_enabled_alternatives (rtx_insn *insn)
2597{
2598 return get_bool_attr_mask (insn, BA_ENABLED);
2599}
2600
2601/* Return the set of alternatives of INSN that are allowed by the current
2602 target and are preferred for the current size/speed optimization
2603 choice. */
2604
2605alternative_mask
2606get_preferred_alternatives (rtx_insn *insn)
2607{
2608 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))
2609 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2610 else
2611 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2612}
2613
2614/* Return the set of alternatives of INSN that are allowed by the current
2615 target and are preferred for the size/speed optimization choice
2616 associated with BB. Passing a separate BB is useful if INSN has not
2617 been emitted yet or if we are considering moving it to a different
2618 block. */
2619
2620alternative_mask
2621get_preferred_alternatives (rtx_insn *insn, basic_block bb)
2622{
2623 if (optimize_bb_for_speed_p (bb))
2624 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED);
2625 else
2626 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE);
2627}
2628
2629/* Assert that the cached boolean attributes for INSN are still accurate.
2630 The backend is required to define these attributes in a way that only
2631 depends on the current target (rather than operands, compiler phase,
2632 etc.). */
2633
2634bool
2635check_bool_attrs (rtx_insn *insn)
2636{
2637 int code = INSN_CODE (insn)(((insn)->u.fld[5]).rt_int);
2638 if (code >= 0)
2639 for (int i = 0; i <= BA_LAST; ++i)
2640 {
2641 enum bool_attr attr = (enum bool_attr) i;
2642 if (this_target_recog->x_bool_attr_masks[code][attr])
2643 gcc_assert (this_target_recog->x_bool_attr_masks[code][attr]((void)(!(this_target_recog->x_bool_attr_masks[code][attr]
== get_bool_attr_mask_uncached (insn, attr)) ? fancy_abort (
"/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2644, __FUNCTION__), 0 : 0))
2644 == get_bool_attr_mask_uncached (insn, attr))((void)(!(this_target_recog->x_bool_attr_masks[code][attr]
== get_bool_attr_mask_uncached (insn, attr)) ? fancy_abort (
"/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2644, __FUNCTION__), 0 : 0))
;
2645 }
2646 return true;
2647}
2648
2649/* Like extract_insn, but save insn extracted and don't extract again, when
2650 called again for the same insn expecting that recog_data still contain the
2651 valid information. This is used primary by gen_attr infrastructure that
2652 often does extract insn again and again. */
2653void
2654extract_insn_cached (rtx_insn *insn)
2655{
2656 if (recog_data.insn == insn && INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) >= 0)
2657 return;
2658 extract_insn (insn);
2659 recog_data.insn = insn;
2660}
2661
2662/* Do uncached extract_insn, constrain_operands and complain about failures.
2663 This should be used when extracting a pre-existing constrained instruction
2664 if the caller wants to know which alternative was chosen. */
2665void
2666extract_constrain_insn (rtx_insn *insn)
2667{
2668 extract_insn (insn);
2669 if (!constrain_operands (reload_completed, get_enabled_alternatives (insn)))
2670 fatal_insn_not_found (insn)_fatal_insn_not_found (insn, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2670, __FUNCTION__)
;
2671}
2672
2673/* Do cached extract_insn, constrain_operands and complain about failures.
2674 Used by insn_attrtab. */
2675void
2676extract_constrain_insn_cached (rtx_insn *insn)
2677{
2678 extract_insn_cached (insn);
2679 if (which_alternative == -1
2680 && !constrain_operands (reload_completed,
2681 get_enabled_alternatives (insn)))
2682 fatal_insn_not_found (insn)_fatal_insn_not_found (insn, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2682, __FUNCTION__)
;
2683}
2684
2685/* Do cached constrain_operands on INSN and complain about failures. */
2686int
2687constrain_operands_cached (rtx_insn *insn, int strict)
2688{
2689 if (which_alternative == -1)
2690 return constrain_operands (strict, get_enabled_alternatives (insn));
2691 else
2692 return 1;
2693}
2694
2695/* Analyze INSN and fill in recog_data. */
2696
2697void
2698extract_insn (rtx_insn *insn)
2699{
2700 int i;
2701 int icode;
2702 int noperands;
2703 rtx body = PATTERN (insn);
2704
2705 recog_data.n_operands = 0;
2706 recog_data.n_alternatives = 0;
2707 recog_data.n_dups = 0;
2708 recog_data.is_asm = false;
2709
2710 switch (GET_CODE (body)((enum rtx_code) (body)->code))
2711 {
2712 case USE:
2713 case CLOBBER:
2714 case ASM_INPUT:
2715 case ADDR_VEC:
2716 case ADDR_DIFF_VEC:
2717 case VAR_LOCATION:
2718 case DEBUG_MARKER:
2719 return;
2720
2721 case SET:
2722 if (GET_CODE (SET_SRC (body))((enum rtx_code) ((((body)->u.fld[1]).rt_rtx))->code) == ASM_OPERANDS)
2723 goto asm_insn;
2724 else
2725 goto normal_insn;
2726 case PARALLEL:
2727 if ((GET_CODE (XVECEXP (body, 0, 0))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[0]))->code)
== SET
2728 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0)))((enum rtx_code) (((((((((body)->u.fld[0]).rt_rtvec))->
elem[0]))->u.fld[1]).rt_rtx))->code)
== ASM_OPERANDS)
2729 || GET_CODE (XVECEXP (body, 0, 0))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[0]))->code)
== ASM_OPERANDS
2730 || GET_CODE (XVECEXP (body, 0, 0))((enum rtx_code) ((((((body)->u.fld[0]).rt_rtvec))->elem
[0]))->code)
== ASM_INPUT)
2731 goto asm_insn;
2732 else
2733 goto normal_insn;
2734 case ASM_OPERANDS:
2735 asm_insn:
2736 recog_data.n_operands = noperands = asm_noperands (body);
2737 if (noperands >= 0)
2738 {
2739 /* This insn is an `asm' with operands. */
2740
2741 /* expand_asm_operands makes sure there aren't too many operands. */
2742 gcc_assert (noperands <= MAX_RECOG_OPERANDS)((void)(!(noperands <= 30) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2742, __FUNCTION__), 0 : 0))
;
2743
2744 /* Now get the operand values and constraints out of the insn. */
2745 decode_asm_operands (body, recog_data.operand,
2746 recog_data.operand_loc,
2747 recog_data.constraints,
2748 recog_data.operand_mode, NULLnullptr);
2749 memset (recog_data.is_operator, 0, sizeof recog_data.is_operator);
2750 if (noperands > 0)
2751 {
2752 const char *p = recog_data.constraints[0];
2753 recog_data.n_alternatives = 1;
2754 while (*p)
2755 recog_data.n_alternatives += (*p++ == ',');
2756 }
2757 recog_data.is_asm = true;
2758 break;
2759 }
2760 fatal_insn_not_found (insn)_fatal_insn_not_found (insn, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2760, __FUNCTION__)
;
2761
2762 default:
2763 normal_insn:
2764 /* Ordinary insn: recognize it, get the operands via insn_extract
2765 and get the constraints. */
2766
2767 icode = recog_memoized (insn);
2768 if (icode < 0)
2769 fatal_insn_not_found (insn)_fatal_insn_not_found (insn, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2769, __FUNCTION__)
;
2770
2771 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2772 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2773 recog_data.n_dups = insn_data[icode].n_dups;
2774
2775 insn_extract (insn);
2776
2777 for (i = 0; i < noperands; i++)
2778 {
2779 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2780 recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator;
2781 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2782 /* VOIDmode match_operands gets mode from their real operand. */
2783 if (recog_data.operand_mode[i] == VOIDmode((void) 0, E_VOIDmode))
2784 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i])((machine_mode) (recog_data.operand[i])->mode);
2785 }
2786 }
2787 for (i = 0; i < noperands; i++)
2788 recog_data.operand_type[i]
2789 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2790 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2791 : OP_IN);
2792
2793 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES)((void)(!(recog_data.n_alternatives <= 35) ? fancy_abort (
"/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2793, __FUNCTION__), 0 : 0))
;
2794
2795 recog_data.insn = NULLnullptr;
2796 which_alternative = -1;
2797}
2798
2799/* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS
2800 operands, N_ALTERNATIVES alternatives and constraint strings
2801 CONSTRAINTS. OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries
2802 and CONSTRAINTS has N_OPERANDS entries. OPLOC should be passed in
2803 if the insn is an asm statement and preprocessing should take the
2804 asm operands into account, e.g. to determine whether they could be
2805 addresses in constraints that require addresses; it should then
2806 point to an array of pointers to each operand. */
2807
2808void
2809preprocess_constraints (int n_operands, int n_alternatives,
2810 const char **constraints,
2811 operand_alternative *op_alt_base,
2812 rtx **oploc)
2813{
2814 for (int i = 0; i < n_operands; i++)
2815 {
2816 int j;
2817 struct operand_alternative *op_alt;
2818 const char *p = constraints[i];
2819
2820 op_alt = op_alt_base;
2821
2822 for (j = 0; j < n_alternatives; j++, op_alt += n_operands)
2823 {
2824 op_alt[i].cl = NO_REGS;
2825 op_alt[i].constraint = p;
2826 op_alt[i].matches = -1;
2827 op_alt[i].matched = -1;
2828
2829 if (*p == '\0' || *p == ',')
2830 {
2831 op_alt[i].anything_ok = 1;
2832 continue;
2833 }
2834
2835 for (;;)
2836 {
2837 char c = *p;
2838 if (c == '#')
2839 do
2840 c = *++p;
2841 while (c != ',' && c != '\0');
2842 if (c == ',' || c == '\0')
2843 {
2844 p++;
2845 break;
2846 }
2847
2848 switch (c)
2849 {
2850 case '?':
2851 op_alt[i].reject += 6;
2852 break;
2853 case '!':
2854 op_alt[i].reject += 600;
2855 break;
2856 case '&':
2857 op_alt[i].earlyclobber = 1;
2858 break;
2859
2860 case '0': case '1': case '2': case '3': case '4':
2861 case '5': case '6': case '7': case '8': case '9':
2862 {
2863 char *end;
2864 op_alt[i].matches = strtoul (p, &end, 10);
2865 op_alt[op_alt[i].matches].matched = i;
2866 p = end;
2867 }
2868 continue;
2869
2870 case 'X':
2871 op_alt[i].anything_ok = 1;
2872 break;
2873
2874 case 'g':
2875 op_alt[i].cl =
2876 reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[(int) op_alt[i].cl][(int) GENERAL_REGS];
2877 break;
2878
2879 default:
2880 enum constraint_num cn = lookup_constraint (p);
2881 enum reg_class cl;
2882 switch (get_constraint_type (cn))
2883 {
2884 case CT_REGISTER:
2885 cl = reg_class_for_constraint (cn);
2886 if (cl != NO_REGS)
2887 op_alt[i].cl = reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[op_alt[i].cl][cl];
2888 break;
2889
2890 case CT_CONST_INT:
2891 break;
2892
2893 case CT_MEMORY:
2894 case CT_SPECIAL_MEMORY:
2895 case CT_RELAXED_MEMORY:
2896 op_alt[i].memory_ok = 1;
2897 break;
2898
2899 case CT_ADDRESS:
2900 if (oploc && !address_operand (*oploc[i], VOIDmode((void) 0, E_VOIDmode)))
2901 break;
2902
2903 op_alt[i].is_address = 1;
2904 op_alt[i].cl
2905 = (reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)
2906 [(int) op_alt[i].cl]
2907 [(int) base_reg_class (VOIDmode((void) 0, E_VOIDmode), ADDR_SPACE_GENERIC0,
2908 ADDRESS, SCRATCH)]);
2909 break;
2910
2911 case CT_FIXED_FORM:
2912 break;
2913 }
2914 break;
2915 }
2916 p += CONSTRAINT_LEN (c, p)insn_constraint_len (c,p);
2917 }
2918 }
2919 }
2920}
2921
2922/* Return an array of operand_alternative instructions for
2923 instruction ICODE. */
2924
2925const operand_alternative *
2926preprocess_insn_constraints (unsigned int icode)
2927{
2928 gcc_checking_assert (IN_RANGE (icode, 0, NUM_INSN_CODES - 1))((void)(!(((unsigned long) (icode) - (unsigned long) (0) <=
(unsigned long) (NUM_INSN_CODES - 1) - (unsigned long) (0)))
? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 2928, __FUNCTION__), 0 : 0))
;
2929 if (this_target_recog->x_op_alt[icode])
2930 return this_target_recog->x_op_alt[icode];
2931
2932 int n_operands = insn_data[icode].n_operands;
2933 if (n_operands == 0)
2934 return 0;
2935 /* Always provide at least one alternative so that which_op_alt ()
2936 works correctly. If the instruction has 0 alternatives (i.e. all
2937 constraint strings are empty) then each operand in this alternative
2938 will have anything_ok set. */
2939 int n_alternatives = MAX (insn_data[icode].n_alternatives, 1)((insn_data[icode].n_alternatives) > (1) ? (insn_data[icode
].n_alternatives) : (1))
;
2940 int n_entries = n_operands * n_alternatives;
2941
2942 operand_alternative *op_alt = XCNEWVEC (operand_alternative, n_entries)((operand_alternative *) xcalloc ((n_entries), sizeof (operand_alternative
)))
;
2943 const char **constraints = XALLOCAVEC (const char *, n_operands)((const char * *) __builtin_alloca(sizeof (const char *) * (n_operands
)))
;
2944
2945 for (int i = 0; i < n_operands; ++i)
2946 constraints[i] = insn_data[icode].operand[i].constraint;
2947 preprocess_constraints (n_operands, n_alternatives, constraints, op_alt,
2948 NULLnullptr);
2949
2950 this_target_recog->x_op_alt[icode] = op_alt;
2951 return op_alt;
2952}
2953
2954/* After calling extract_insn, you can use this function to extract some
2955 information from the constraint strings into a more usable form.
2956 The collected data is stored in recog_op_alt. */
2957
2958void
2959preprocess_constraints (rtx_insn *insn)
2960{
2961 int icode = INSN_CODE (insn)(((insn)->u.fld[5]).rt_int);
2962 if (icode >= 0)
2963 recog_op_alt = preprocess_insn_constraints (icode);
2964 else
2965 {
2966 int n_operands = recog_data.n_operands;
2967 int n_alternatives = recog_data.n_alternatives;
2968 int n_entries = n_operands * n_alternatives;
2969 memset (asm_op_alt, 0, n_entries * sizeof (operand_alternative));
2970 preprocess_constraints (n_operands, n_alternatives,
2971 recog_data.constraints, asm_op_alt,
2972 NULLnullptr);
2973 recog_op_alt = asm_op_alt;
2974 }
2975}
2976
2977/* Check the operands of an insn against the insn's operand constraints
2978 and return 1 if they match any of the alternatives in ALTERNATIVES.
2979
2980 The information about the insn's operands, constraints, operand modes
2981 etc. is obtained from the global variables set up by extract_insn.
2982
2983 WHICH_ALTERNATIVE is set to a number which indicates which
2984 alternative of constraints was matched: 0 for the first alternative,
2985 1 for the next, etc.
2986
2987 In addition, when two operands are required to match
2988 and it happens that the output operand is (reg) while the
2989 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2990 make the output operand look like the input.
2991 This is because the output operand is the one the template will print.
2992
2993 This is used in final, just before printing the assembler code and by
2994 the routines that determine an insn's attribute.
2995
2996 If STRICT is a positive nonzero value, it means that we have been
2997 called after reload has been completed. In that case, we must
2998 do all checks strictly. If it is zero, it means that we have been called
2999 before reload has completed. In that case, we first try to see if we can
3000 find an alternative that matches strictly. If not, we try again, this
3001 time assuming that reload will fix up the insn. This provides a "best
3002 guess" for the alternative and is used to compute attributes of insns prior
3003 to reload. A negative value of STRICT is used for this internal call. */
3004
3005struct funny_match
3006{
3007 int this_op, other;
3008};
3009
3010int
3011constrain_operands (int strict, alternative_mask alternatives)
3012{
3013 const char *constraints[MAX_RECOG_OPERANDS30];
3014 int matching_operands[MAX_RECOG_OPERANDS30];
3015 int earlyclobber[MAX_RECOG_OPERANDS30];
3016 int c;
3017
3018 struct funny_match funny_match[MAX_RECOG_OPERANDS30];
3019 int funny_match_index;
3020
3021 which_alternative = 0;
3022 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
3023 return 1;
3024
3025 for (c = 0; c < recog_data.n_operands; c++)
3026 constraints[c] = recog_data.constraints[c];
3027
3028 do
3029 {
3030 int seen_earlyclobber_at = -1;
3031 int opno;
3032 int lose = 0;
3033 funny_match_index = 0;
3034
3035 if (!TEST_BIT (alternatives, which_alternative)(((alternatives) >> (which_alternative)) & 1))
3036 {
3037 int i;
3038
3039 for (i = 0; i < recog_data.n_operands; i++)
3040 constraints[i] = skip_alternative (constraints[i]);
3041
3042 which_alternative++;
3043 continue;
3044 }
3045
3046 for (opno = 0; opno < recog_data.n_operands; opno++)
3047 matching_operands[opno] = -1;
3048
3049 for (opno = 0; opno < recog_data.n_operands; opno++)
3050 {
3051 rtx op = recog_data.operand[opno];
3052 machine_mode mode = GET_MODE (op)((machine_mode) (op)->mode);
3053 const char *p = constraints[opno];
3054 int offset = 0;
3055 int win = 0;
3056 int val;
3057 int len;
3058
3059 earlyclobber[opno] = 0;
3060
3061 /* A unary operator may be accepted by the predicate, but it
3062 is irrelevant for matching constraints. */
3063 /* For special_memory_operand, there could be a memory operand inside,
3064 and it would cause a mismatch for constraint_satisfied_p. */
3065 if (UNARY_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_UNARY
)
&& op == extract_mem_from_operand (op))
3066 op = XEXP (op, 0)(((op)->u.fld[0]).rt_rtx);
3067
3068 if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG)
3069 {
3070 if (REG_P (SUBREG_REG (op))(((enum rtx_code) ((((op)->u.fld[0]).rt_rtx))->code) ==
REG)
3071 && REGNO (SUBREG_REG (op))(rhs_regno((((op)->u.fld[0]).rt_rtx))) < FIRST_PSEUDO_REGISTER76)
3072 offset = subreg_regno_offset (REGNO (SUBREG_REG (op))(rhs_regno((((op)->u.fld[0]).rt_rtx))),
3073 GET_MODE (SUBREG_REG (op))((machine_mode) ((((op)->u.fld[0]).rt_rtx))->mode),
3074 SUBREG_BYTE (op)(((op)->u.fld[1]).rt_subreg),
3075 GET_MODE (op)((machine_mode) (op)->mode));
3076 op = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);
3077 }
3078
3079 /* An empty constraint or empty alternative
3080 allows anything which matched the pattern. */
3081 if (*p == 0 || *p == ',')
3082 win = 1;
3083
3084 do
3085 switch (c = *p, len = CONSTRAINT_LEN (c, p)insn_constraint_len (c,p), c)
3086 {
3087 case '\0':
3088 len = 0;
3089 break;
3090 case ',':
3091 c = '\0';
3092 break;
3093
3094 case '#':
3095 /* Ignore rest of this alternative as far as
3096 constraint checking is concerned. */
3097 do
3098 p++;
3099 while (*p && *p != ',');
3100 len = 0;
3101 break;
3102
3103 case '&':
3104 earlyclobber[opno] = 1;
3105 if (seen_earlyclobber_at < 0)
3106 seen_earlyclobber_at = opno;
3107 break;
3108
3109 case '0': case '1': case '2': case '3': case '4':
3110 case '5': case '6': case '7': case '8': case '9':
3111 {
3112 /* This operand must be the same as a previous one.
3113 This kind of constraint is used for instructions such
3114 as add when they take only two operands.
3115
3116 Note that the lower-numbered operand is passed first.
3117
3118 If we are not testing strictly, assume that this
3119 constraint will be satisfied. */
3120
3121 char *end;
3122 int match;
3123
3124 match = strtoul (p, &end, 10);
3125 p = end;
3126
3127 if (strict < 0)
3128 val = 1;
3129 else
3130 {
3131 rtx op1 = recog_data.operand[match];
3132 rtx op2 = recog_data.operand[opno];
3133
3134 /* A unary operator may be accepted by the predicate,
3135 but it is irrelevant for matching constraints. */
3136 if (UNARY_P (op1)((rtx_class[(int) (((enum rtx_code) (op1)->code))]) == RTX_UNARY
)
)
3137 op1 = XEXP (op1, 0)(((op1)->u.fld[0]).rt_rtx);
3138 if (UNARY_P (op2)((rtx_class[(int) (((enum rtx_code) (op2)->code))]) == RTX_UNARY
)
)
3139 op2 = XEXP (op2, 0)(((op2)->u.fld[0]).rt_rtx);
3140
3141 val = operands_match_p (op1, op2);
3142 }
3143
3144 matching_operands[opno] = match;
3145 matching_operands[match] = opno;
3146
3147 if (val != 0)
3148 win = 1;
3149
3150 /* If output is *x and input is *--x, arrange later
3151 to change the output to *--x as well, since the
3152 output op is the one that will be printed. */
3153 if (val == 2 && strict > 0)
3154 {
3155 funny_match[funny_match_index].this_op = opno;
3156 funny_match[funny_match_index++].other = match;
3157 }
3158 }
3159 len = 0;
3160 break;
3161
3162 case 'p':
3163 /* p is used for address_operands. When we are called by
3164 gen_reload, no one will have checked that the address is
3165 strictly valid, i.e., that all pseudos requiring hard regs
3166 have gotten them. We also want to make sure we have a
3167 valid mode. */
3168 if ((GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode)
3169 || SCALAR_INT_MODE_P (GET_MODE (op))(((enum mode_class) mode_class[((machine_mode) (op)->mode)
]) == MODE_INT || ((enum mode_class) mode_class[((machine_mode
) (op)->mode)]) == MODE_PARTIAL_INT)
)
3170 && (strict <= 0
3171 || (strict_memory_address_pstrict_memory_address_addr_space_p ((recog_data.operand_mode[
opno]), (op), 0)
3172 (recog_data.operand_mode[opno], op)strict_memory_address_addr_space_p ((recog_data.operand_mode[
opno]), (op), 0)
)))
3173 win = 1;
3174 break;
3175
3176 /* No need to check general_operand again;
3177 it was done in insn-recog.c. Well, except that reload
3178 doesn't check the validity of its replacements, but
3179 that should only matter when there's a bug. */
3180 case 'g':
3181 /* Anything goes unless it is a REG and really has a hard reg
3182 but the hard reg is not in the class GENERAL_REGS. */
3183 if (REG_P (op)(((enum rtx_code) (op)->code) == REG))
3184 {
3185 if (strict < 0
3186 || GENERAL_REGS == ALL_REGS
3187 || (reload_in_progress
3188 && REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76)
3189 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
3190 win = 1;
3191 }
3192 else if (strict < 0 || general_operand (op, mode))
3193 win = 1;
3194 break;
3195
3196 default:
3197 {
3198 enum constraint_num cn = lookup_constraint (p);
3199 enum reg_class cl = reg_class_for_constraint (cn);
3200 if (cl != NO_REGS)
3201 {
3202 if (strict < 0
3203 || (strict == 0
3204 && REG_P (op)(((enum rtx_code) (op)->code) == REG)
3205 && REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76)
3206 || (strict == 0 && GET_CODE (op)((enum rtx_code) (op)->code) == SCRATCH)
3207 || (REG_P (op)(((enum rtx_code) (op)->code) == REG)
3208 && reg_fits_class_p (op, cl, offset, mode)))
3209 win = 1;
3210 }
3211
3212 else if (constraint_satisfied_p (op, cn))
3213 win = 1;
3214
3215 else if (insn_extra_memory_constraint (cn)
3216 /* Every memory operand can be reloaded to fit. */
3217 && ((strict < 0 && MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
3218 /* Before reload, accept what reload can turn
3219 into a mem. */
3220 || (strict < 0 && CONSTANT_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ
)
)
3221 /* Before reload, accept a pseudo or hard register,
3222 since LRA can turn it into a mem. */
3223 || (strict < 0 && targetm.lra_p () && REG_P (op)(((enum rtx_code) (op)->code) == REG))
3224 /* During reload, accept a pseudo */
3225 || (reload_in_progress && REG_P (op)(((enum rtx_code) (op)->code) == REG)
3226 && REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76)))
3227 win = 1;
3228 else if (insn_extra_address_constraint (cn)
3229 /* Every address operand can be reloaded to fit. */
3230 && strict < 0)
3231 win = 1;
3232 /* Cater to architectures like IA-64 that define extra memory
3233 constraints without using define_memory_constraint. */
3234 else if (reload_in_progress
3235 && REG_P (op)(((enum rtx_code) (op)->code) == REG)
3236 && REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76
3237 && reg_renumber[REGNO (op)(rhs_regno(op))] < 0
3238 && reg_equiv_mem (REGNO (op))(*reg_equivs)[((rhs_regno(op)))].mem != 0
3239 && constraint_satisfied_p
3240 (reg_equiv_mem (REGNO (op))(*reg_equivs)[((rhs_regno(op)))].mem, cn))
3241 win = 1;
3242 break;
3243 }
3244 }
3245 while (p += len, c);
3246
3247 constraints[opno] = p;
3248 /* If this operand did not win somehow,
3249 this alternative loses. */
3250 if (! win)
3251 lose = 1;
3252 }
3253 /* This alternative won; the operands are ok.
3254 Change whichever operands this alternative says to change. */
3255 if (! lose)
3256 {
3257 int opno, eopno;
3258
3259 /* See if any earlyclobber operand conflicts with some other
3260 operand. */
3261
3262 if (strict > 0 && seen_earlyclobber_at >= 0)
3263 for (eopno = seen_earlyclobber_at;
3264 eopno < recog_data.n_operands;
3265 eopno++)
3266 /* Ignore earlyclobber operands now in memory,
3267 because we would often report failure when we have
3268 two memory operands, one of which was formerly a REG. */
3269 if (earlyclobber[eopno]
3270 && REG_P (recog_data.operand[eopno])(((enum rtx_code) (recog_data.operand[eopno])->code) == REG
)
)
3271 for (opno = 0; opno < recog_data.n_operands; opno++)
3272 if ((MEM_P (recog_data.operand[opno])(((enum rtx_code) (recog_data.operand[opno])->code) == MEM
)
3273 || recog_data.operand_type[opno] != OP_OUT)
3274 && opno != eopno
3275 /* Ignore things like match_operator operands. */
3276 && *recog_data.constraints[opno] != 0
3277 && ! (matching_operands[opno] == eopno
3278 && operands_match_p (recog_data.operand[opno],
3279 recog_data.operand[eopno]))
3280 && ! safe_from_earlyclobber (recog_data.operand[opno],
3281 recog_data.operand[eopno]))
3282 lose = 1;
3283
3284 if (! lose)
3285 {
3286 while (--funny_match_index >= 0)
3287 {
3288 recog_data.operand[funny_match[funny_match_index].other]
3289 = recog_data.operand[funny_match[funny_match_index].this_op];
3290 }
3291
3292 /* For operands without < or > constraints reject side-effects. */
3293 if (AUTO_INC_DEC0 && recog_data.is_asm)
3294 {
3295 for (opno = 0; opno < recog_data.n_operands; opno++)
3296 if (MEM_P (recog_data.operand[opno])(((enum rtx_code) (recog_data.operand[opno])->code) == MEM
)
)
3297 switch (GET_CODE (XEXP (recog_data.operand[opno], 0))((enum rtx_code) ((((recog_data.operand[opno])->u.fld[0]).
rt_rtx))->code)
)
3298 {
3299 case PRE_INC:
3300 case POST_INC:
3301 case PRE_DEC:
3302 case POST_DEC:
3303 case PRE_MODIFY:
3304 case POST_MODIFY:
3305 if (strchr (recog_data.constraints[opno], '<') == NULLnullptr
3306 && strchr (recog_data.constraints[opno], '>')
3307 == NULLnullptr)
3308 return 0;
3309 break;
3310 default:
3311 break;
3312 }
3313 }
3314
3315 return 1;
3316 }
3317 }
3318
3319 which_alternative++;
3320 }
3321 while (which_alternative < recog_data.n_alternatives);
3322
3323 which_alternative = -1;
3324 /* If we are about to reject this, but we are not to test strictly,
3325 try a very loose test. Only return failure if it fails also. */
3326 if (strict == 0)
3327 return constrain_operands (-1, alternatives);
3328 else
3329 return 0;
3330}
3331
3332/* Return true iff OPERAND (assumed to be a REG rtx)
3333 is a hard reg in class CLASS when its regno is offset by OFFSET
3334 and changed to mode MODE.
3335 If REG occupies multiple hard regs, all of them must be in CLASS. */
3336
3337bool
3338reg_fits_class_p (const_rtx operand, reg_class_t cl, int offset,
3339 machine_mode mode)
3340{
3341 unsigned int regno = REGNO (operand)(rhs_regno(operand));
3342
3343 if (cl == NO_REGS)
3344 return false;
3345
3346 /* Regno must not be a pseudo register. Offset may be negative. */
3347 return (HARD_REGISTER_NUM_P (regno)((regno) < 76)
3348 && HARD_REGISTER_NUM_P (regno + offset)((regno + offset) < 76)
3349 && in_hard_reg_set_p (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[(int) cl], mode,
3350 regno + offset));
3351}
3352
3353/* Split single instruction. Helper function for split_all_insns and
3354 split_all_insns_noflow. Return last insn in the sequence if successful,
3355 or NULL if unsuccessful. */
3356
3357static rtx_insn *
3358split_insn (rtx_insn *insn)
3359{
3360 /* Split insns here to get max fine-grain parallelism. */
3361 rtx_insn *first = PREV_INSN (insn);
3362 rtx_insn *last = try_split (PATTERN (insn), insn, 1);
3363 rtx insn_set, last_set, note;
3364
3365 if (last == insn)
3366 return NULLnullptr;
3367
3368 /* If the original instruction was a single set that was known to be
3369 equivalent to a constant, see if we can say the same about the last
3370 instruction in the split sequence. The two instructions must set
3371 the same destination. */
3372 insn_set = single_set (insn);
3373 if (insn_set)
3374 {
3375 last_set = single_set (last);
3376 if (last_set && rtx_equal_p (SET_DEST (last_set)(((last_set)->u.fld[0]).rt_rtx), SET_DEST (insn_set)(((insn_set)->u.fld[0]).rt_rtx)))
3377 {
3378 note = find_reg_equal_equiv_note (insn);
3379 if (note && CONSTANT_P (XEXP (note, 0))((rtx_class[(int) (((enum rtx_code) ((((note)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
)
3380 set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0)(((note)->u.fld[0]).rt_rtx));
3381 else if (CONSTANT_P (SET_SRC (insn_set))((rtx_class[(int) (((enum rtx_code) ((((insn_set)->u.fld[1
]).rt_rtx))->code))]) == RTX_CONST_OBJ)
)
3382 set_unique_reg_note (last, REG_EQUAL,
3383 copy_rtx (SET_SRC (insn_set)(((insn_set)->u.fld[1]).rt_rtx)));
3384 }
3385 }
3386
3387 /* try_split returns the NOTE that INSN became. */
3388 SET_INSN_DELETED (insn)set_insn_deleted (insn);;
3389
3390 /* ??? Coddle to md files that generate subregs in post-reload
3391 splitters instead of computing the proper hard register. */
3392 if (reload_completed && first != last)
3393 {
3394 first = NEXT_INSN (first);
3395 for (;;)
3396 {
3397 if (INSN_P (first)(((((enum rtx_code) (first)->code) == INSN) || (((enum rtx_code
) (first)->code) == JUMP_INSN) || (((enum rtx_code) (first
)->code) == CALL_INSN)) || (((enum rtx_code) (first)->code
) == DEBUG_INSN))
)
3398 cleanup_subreg_operands (first);
3399 if (first == last)
3400 break;
3401 first = NEXT_INSN (first);
3402 }
3403 }
3404
3405 return last;
3406}
3407
3408/* Split all insns in the function. If UPD_LIFE, update life info after. */
3409
3410void
3411split_all_insns (void)
3412{
3413 bool changed;
3414 bool need_cfg_cleanup = false;
3415 basic_block bb;
3416
3417 auto_sbitmap blocks (last_basic_block_for_fn (cfun)(((cfun + 0))->cfg->x_last_basic_block));
3418 bitmap_clear (blocks);
3419 changed = false;
3420
3421 FOR_EACH_BB_REVERSE_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_exit_block_ptr->prev_bb
; bb != ((cfun + 0))->cfg->x_entry_block_ptr; bb = bb->
prev_bb)
3422 {
3423 rtx_insn *insn, *next;
3424 bool finish = false;
3425
3426 rtl_profile_for_bb (bb);
3427 for (insn = BB_HEAD (bb)(bb)->il.x.head_; !finish ; insn = next)
3428 {
3429 /* Can't use `next_real_insn' because that might go across
3430 CODE_LABELS and short-out basic blocks. */
3431 next = NEXT_INSN (insn);
3432 finish = (insn == BB_END (bb)(bb)->il.x.rtl->end_);
3433
3434 /* If INSN has a REG_EH_REGION note and we split INSN, the
3435 resulting split may not have/need REG_EH_REGION notes.
3436
3437 If that happens and INSN was the last reference to the
3438 given EH region, then the EH region will become unreachable.
3439 We cannot leave the unreachable blocks in the CFG as that
3440 will trigger a checking failure.
3441
3442 So track if INSN has a REG_EH_REGION note. If so and we
3443 split INSN, then trigger a CFG cleanup. */
3444 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX(rtx) 0);
3445 if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
)
3446 {
3447 rtx set = single_set (insn);
3448
3449 /* Don't split no-op move insns. These should silently
3450 disappear later in final. Splitting such insns would
3451 break the code that handles LIBCALL blocks. */
3452 if (set && set_noop_p (set))
3453 {
3454 /* Nops get in the way while scheduling, so delete them
3455 now if register allocation has already been done. It
3456 is too risky to try to do this before register
3457 allocation, and there are unlikely to be very many
3458 nops then anyways. */
3459 if (reload_completed)
3460 delete_insn_and_edges (insn);
3461 if (note)
3462 need_cfg_cleanup = true;
3463 }
3464 else
3465 {
3466 if (split_insn (insn))
3467 {
3468 bitmap_set_bit (blocks, bb->index);
3469 changed = true;
3470 if (note)
3471 need_cfg_cleanup = true;
3472 }
3473 }
3474 }
3475 }
3476 }
3477
3478 default_rtl_profile ();
3479 if (changed)
3480 {
3481 find_many_sub_basic_blocks (blocks);
3482
3483 /* Splitting could drop an REG_EH_REGION if it potentially
3484 trapped in its original form, but does not in its split
3485 form. Consider a FLOAT_TRUNCATE which splits into a memory
3486 store/load pair and -fnon-call-exceptions. */
3487 if (need_cfg_cleanup)
3488 cleanup_cfg (0);
3489 }
3490
3491 checking_verify_flow_info ();
3492}
3493
3494/* Same as split_all_insns, but do not expect CFG to be available.
3495 Used by machine dependent reorg passes. */
3496
3497unsigned int
3498split_all_insns_noflow (void)
3499{
3500 rtx_insn *next, *insn;
3501
3502 for (insn = get_insns (); insn; insn = next)
3503 {
3504 next = NEXT_INSN (insn);
3505 if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
)
3506 {
3507 /* Don't split no-op move insns. These should silently
3508 disappear later in final. Splitting such insns would
3509 break the code that handles LIBCALL blocks. */
3510 rtx set = single_set (insn);
3511 if (set && set_noop_p (set))
3512 {
3513 /* Nops get in the way while scheduling, so delete them
3514 now if register allocation has already been done. It
3515 is too risky to try to do this before register
3516 allocation, and there are unlikely to be very many
3517 nops then anyways.
3518
3519 ??? Should we use delete_insn when the CFG isn't valid? */
3520 if (reload_completed)
3521 delete_insn_and_edges (insn);
3522 }
3523 else
3524 split_insn (insn);
3525 }
3526 }
3527 return 0;
3528}
3529
3530struct peep2_insn_data
3531{
3532 rtx_insn *insn;
3533 regset live_before;
3534};
3535
3536static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP25 + 1];
3537static int peep2_current;
3538
3539static bool peep2_do_rebuild_jump_labels;
3540static bool peep2_do_cleanup_cfg;
3541
3542/* The number of instructions available to match a peep2. */
3543int peep2_current_count;
3544
3545/* A marker indicating the last insn of the block. The live_before regset
3546 for this element is correct, indicating DF_LIVE_OUT for the block. */
3547#define PEEP2_EOBinvalid_insn_rtx invalid_insn_rtx
3548
3549/* Wrap N to fit into the peep2_insn_data buffer. */
3550
3551static int
3552peep2_buf_position (int n)
3553{
3554 if (n >= MAX_INSNS_PER_PEEP25 + 1)
3555 n -= MAX_INSNS_PER_PEEP25 + 1;
3556 return n;
3557}
3558
3559/* Return the Nth non-note insn after `current', or return NULL_RTX if it
3560 does not exist. Used by the recognizer to find the next insn to match
3561 in a multi-insn pattern. */
3562
3563rtx_insn *
3564peep2_next_insn (int n)
3565{
3566 gcc_assert (n <= peep2_current_count)((void)(!(n <= peep2_current_count) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3566, __FUNCTION__), 0 : 0))
;
3567
3568 n = peep2_buf_position (peep2_current + n);
3569
3570 return peep2_insn_data[n].insn;
3571}
3572
3573/* Return true if REGNO is dead before the Nth non-note insn
3574 after `current'. */
3575
3576int
3577peep2_regno_dead_p (int ofs, int regno)
3578{
3579 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1)((void)(!(ofs < 5 + 1) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3579, __FUNCTION__), 0 : 0))
;
3580
3581 ofs = peep2_buf_position (peep2_current + ofs);
3582
3583 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX)((void)(!(peep2_insn_data[ofs].insn != (rtx) 0) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3583, __FUNCTION__), 0 : 0))
;
3584
3585 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno)bitmap_bit_p (peep2_insn_data[ofs].live_before, regno);
3586}
3587
3588/* Similarly for a REG. */
3589
3590int
3591peep2_reg_dead_p (int ofs, rtx reg)
3592{
3593 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1)((void)(!(ofs < 5 + 1) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3593, __FUNCTION__), 0 : 0))
;
3594
3595 ofs = peep2_buf_position (peep2_current + ofs);
3596
3597 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX)((void)(!(peep2_insn_data[ofs].insn != (rtx) 0) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3597, __FUNCTION__), 0 : 0))
;
3598
3599 unsigned int end_regno = END_REGNO (reg);
3600 for (unsigned int regno = REGNO (reg)(rhs_regno(reg)); regno < end_regno; ++regno)
3601 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno)bitmap_bit_p (peep2_insn_data[ofs].live_before, regno))
3602 return 0;
3603 return 1;
3604}
3605
3606/* Regno offset to be used in the register search. */
3607static int search_ofs;
3608
3609/* Try to find a hard register of mode MODE, matching the register class in
3610 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3611 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3612 in which case the only condition is that the register must be available
3613 before CURRENT_INSN.
3614 Registers that already have bits set in REG_SET will not be considered.
3615
3616 If an appropriate register is available, it will be returned and the
3617 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3618 returned. */
3619
3620rtx
3621peep2_find_free_register (int from, int to, const char *class_str,
3622 machine_mode mode, HARD_REG_SET *reg_set)
3623{
3624 enum reg_class cl;
3625 HARD_REG_SET live;
3626 df_ref def;
3627 int i;
3628
3629 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1)((void)(!(from < 5 + 1) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3629, __FUNCTION__), 0 : 0))
;
3630 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1)((void)(!(to < 5 + 1) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3630, __FUNCTION__), 0 : 0))
;
3631
3632 from = peep2_buf_position (peep2_current + from);
3633 to = peep2_buf_position (peep2_current + to);
3634
3635 gcc_assert (peep2_insn_data[from].insn != NULL_RTX)((void)(!(peep2_insn_data[from].insn != (rtx) 0) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3635, __FUNCTION__), 0 : 0))
;
3636 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before)do { CLEAR_HARD_REG_SET (live); reg_set_to_hard_reg_set (&
live, peep2_insn_data[from].live_before); } while (0)
;
3637
3638 while (from != to)
3639 {
3640 gcc_assert (peep2_insn_data[from].insn != NULL_RTX)((void)(!(peep2_insn_data[from].insn != (rtx) 0) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3640, __FUNCTION__), 0 : 0))
;
3641
3642 /* Don't use registers set or clobbered by the insn. */
3643 FOR_EACH_INSN_DEF (def, peep2_insn_data[from].insn)for (def = (((df->insns[(INSN_UID (peep2_insn_data[from].insn
))]))->defs); def; def = ((def)->base.next_loc))
3644 SET_HARD_REG_BIT (live, DF_REF_REGNO (def)((def)->base.regno));
3645
3646 from = peep2_buf_position (from + 1);
3647 }
3648
3649 cl = reg_class_for_constraint (lookup_constraint (class_str));
3650
3651 for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
3652 {
3653 int raw_regno, regno, success, j;
3654
3655 /* Distribute the free registers as much as possible. */
3656 raw_regno = search_ofs + i;
3657 if (raw_regno >= FIRST_PSEUDO_REGISTER76)
3658 raw_regno -= FIRST_PSEUDO_REGISTER76;
3659#ifdef REG_ALLOC_ORDER{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17
, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48
, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 }
3660 regno = reg_alloc_order(this_target_hard_regs->x_reg_alloc_order)[raw_regno];
3661#else
3662 regno = raw_regno;
3663#endif
3664
3665 /* Can it support the mode we need? */
3666 if (!targetm.hard_regno_mode_ok (regno, mode))
3667 continue;
3668
3669 success = 1;
3670 for (j = 0; success && j < hard_regno_nregs (regno, mode); j++)
3671 {
3672 /* Don't allocate fixed registers. */
3673 if (fixed_regs(this_target_hard_regs->x_fixed_regs)[regno + j])
3674 {
3675 success = 0;
3676 break;
3677 }
3678 /* Don't allocate global registers. */
3679 if (global_regs[regno + j])
3680 {
3681 success = 0;
3682 break;
3683 }
3684 /* Make sure the register is of the right class. */
3685 if (! TEST_HARD_REG_BIT (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[cl], regno + j))
3686 {
3687 success = 0;
3688 break;
3689 }
3690 /* And that we don't create an extra save/restore. */
3691 if (! crtl(&x_rtl)->abi->clobbers_full_reg_p (regno + j)
3692 && ! df_regs_ever_live_p (regno + j))
3693 {
3694 success = 0;
3695 break;
3696 }
3697
3698 if (! targetm.hard_regno_scratch_ok (regno + j))
3699 {
3700 success = 0;
3701 break;
3702 }
3703
3704 /* And we don't clobber traceback for noreturn functions. */
3705 if ((regno + j == FRAME_POINTER_REGNUM19
3706 || regno + j == HARD_FRAME_POINTER_REGNUM6)
3707 && (! reload_completed || frame_pointer_needed((&x_rtl)->frame_pointer_needed)))
3708 {
3709 success = 0;
3710 break;
3711 }
3712
3713 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
3714 || TEST_HARD_REG_BIT (live, regno + j))
3715 {
3716 success = 0;
3717 break;
3718 }
3719 }
3720
3721 if (success)
3722 {
3723 add_to_hard_reg_set (reg_set, mode, regno);
3724
3725 /* Start the next search with the next register. */
3726 if (++raw_regno >= FIRST_PSEUDO_REGISTER76)
3727 raw_regno = 0;
3728 search_ofs = raw_regno;
3729
3730 return gen_rtx_REG (mode, regno);
3731 }
3732 }
3733
3734 search_ofs = 0;
3735 return NULL_RTX(rtx) 0;
3736}
3737
3738/* Forget all currently tracked instructions, only remember current
3739 LIVE regset. */
3740
3741static void
3742peep2_reinit_state (regset live)
3743{
3744 int i;
3745
3746 /* Indicate that all slots except the last holds invalid data. */
3747 for (i = 0; i < MAX_INSNS_PER_PEEP25; ++i)
3748 peep2_insn_data[i].insn = NULLnullptr;
3749 peep2_current_count = 0;
3750
3751 /* Indicate that the last slot contains live_after data. */
3752 peep2_insn_data[MAX_INSNS_PER_PEEP25].insn = PEEP2_EOBinvalid_insn_rtx;
3753 peep2_current = MAX_INSNS_PER_PEEP25;
3754
3755 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live)bitmap_copy (peep2_insn_data[5].live_before, live);
3756}
3757
3758/* Copies frame related info of an insn (OLD_INSN) to the single
3759 insn (NEW_INSN) that was obtained by splitting OLD_INSN. */
3760
3761void
3762copy_frame_info_to_split_insn (rtx_insn *old_insn, rtx_insn *new_insn)
3763{
3764 bool any_note = false;
3765 rtx note;
3766
3767 if (!RTX_FRAME_RELATED_P (old_insn)(__extension__ ({ __typeof ((old_insn)) const _rtx = ((old_insn
)); if (((enum rtx_code) (_rtx)->code) != DEBUG_INSN &&
((enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != CALL_INSN && ((enum rtx_code) (
_rtx)->code) != JUMP_INSN && ((enum rtx_code) (_rtx
)->code) != BARRIER && ((enum rtx_code) (_rtx)->
code) != SET) rtl_check_failed_flag ("RTX_FRAME_RELATED_P",_rtx
, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3767, __FUNCTION__); _rtx; })->frame_related)
)
3768 return;
3769
3770 RTX_FRAME_RELATED_P (new_insn)(__extension__ ({ __typeof ((new_insn)) const _rtx = ((new_insn
)); if (((enum rtx_code) (_rtx)->code) != DEBUG_INSN &&
((enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != CALL_INSN && ((enum rtx_code) (
_rtx)->code) != JUMP_INSN && ((enum rtx_code) (_rtx
)->code) != BARRIER && ((enum rtx_code) (_rtx)->
code) != SET) rtl_check_failed_flag ("RTX_FRAME_RELATED_P",_rtx
, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3770, __FUNCTION__); _rtx; })->frame_related)
= 1;
3771
3772 /* Allow the backend to fill in a note during the split. */
3773 for (note = REG_NOTES (new_insn)(((new_insn)->u.fld[6]).rt_rtx); note ; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
3774 switch (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)))
3775 {
3776 case REG_FRAME_RELATED_EXPR:
3777 case REG_CFA_DEF_CFA:
3778 case REG_CFA_ADJUST_CFA:
3779 case REG_CFA_OFFSET:
3780 case REG_CFA_REGISTER:
3781 case REG_CFA_EXPRESSION:
3782 case REG_CFA_RESTORE:
3783 case REG_CFA_SET_VDRAP:
3784 any_note = true;
3785 break;
3786 default:
3787 break;
3788 }
3789
3790 /* If the backend didn't supply a note, copy one over. */
3791 if (!any_note)
3792 for (note = REG_NOTES (old_insn)(((old_insn)->u.fld[6]).rt_rtx); note ; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
3793 switch (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)))
3794 {
3795 case REG_FRAME_RELATED_EXPR:
3796 case REG_CFA_DEF_CFA:
3797 case REG_CFA_ADJUST_CFA:
3798 case REG_CFA_OFFSET:
3799 case REG_CFA_REGISTER:
3800 case REG_CFA_EXPRESSION:
3801 case REG_CFA_RESTORE:
3802 case REG_CFA_SET_VDRAP:
3803 add_reg_note (new_insn, REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)), XEXP (note, 0)(((note)->u.fld[0]).rt_rtx));
3804 any_note = true;
3805 break;
3806 default:
3807 break;
3808 }
3809
3810 /* If there still isn't a note, make sure the unwind info sees the
3811 same expression as before the split. */
3812 if (!any_note)
3813 {
3814 rtx old_set, new_set;
3815
3816 /* The old insn had better have been simple, or annotated. */
3817 old_set = single_set (old_insn);
3818 gcc_assert (old_set != NULL)((void)(!(old_set != nullptr) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3818, __FUNCTION__), 0 : 0))
;
3819
3820 new_set = single_set (new_insn);
3821 if (!new_set || !rtx_equal_p (new_set, old_set))
3822 add_reg_note (new_insn, REG_FRAME_RELATED_EXPR, old_set);
3823 }
3824
3825 /* Copy prologue/epilogue status. This is required in order to keep
3826 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3827 maybe_copy_prologue_epilogue_insn (old_insn, new_insn);
3828}
3829
3830/* While scanning basic block BB, we found a match of length MATCH_LEN,
3831 starting at INSN. Perform the replacement, removing the old insns and
3832 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3833 if the replacement is rejected. */
3834
3835static rtx_insn *
3836peep2_attempt (basic_block bb, rtx_insn *insn, int match_len, rtx_insn *attempt)
3837{
3838 int i;
3839 rtx_insn *last, *before_try, *x;
3840 rtx eh_note, as_note;
3841 rtx_insn *old_insn;
3842 rtx_insn *new_insn;
3843 bool was_call = false;
3844
3845 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3846 match more than one insn, or to be split into more than one insn. */
3847 old_insn = peep2_insn_data[peep2_current].insn;
3848 if (RTX_FRAME_RELATED_P (old_insn)(__extension__ ({ __typeof ((old_insn)) const _rtx = ((old_insn
)); if (((enum rtx_code) (_rtx)->code) != DEBUG_INSN &&
((enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != CALL_INSN && ((enum rtx_code) (
_rtx)->code) != JUMP_INSN && ((enum rtx_code) (_rtx
)->code) != BARRIER && ((enum rtx_code) (_rtx)->
code) != SET) rtl_check_failed_flag ("RTX_FRAME_RELATED_P",_rtx
, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3848, __FUNCTION__); _rtx; })->frame_related)
)
3849 {
3850 if (match_len != 0)
3851 return NULLnullptr;
3852
3853 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3854 may be in the stream for the purpose of register allocation. */
3855 if (active_insn_p (attempt))
3856 new_insn = attempt;
3857 else
3858 new_insn = next_active_insn (attempt);
3859 if (next_active_insn (new_insn))
3860 return NULLnullptr;
3861
3862 /* We have a 1-1 replacement. Copy over any frame-related info. */
3863 copy_frame_info_to_split_insn (old_insn, new_insn);
3864 }
3865
3866 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3867 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3868 cfg-related call notes. */
3869 for (i = 0; i <= match_len; ++i)
3870 {
3871 int j;
3872 rtx note;
3873
3874 j = peep2_buf_position (peep2_current + i);
3875 old_insn = peep2_insn_data[j].insn;
3876 if (!CALL_P (old_insn)(((enum rtx_code) (old_insn)->code) == CALL_INSN))
3877 continue;
3878 was_call = true;
3879
3880 new_insn = attempt;
3881 while (new_insn != NULL_RTX(rtx) 0)
3882 {
3883 if (CALL_P (new_insn)(((enum rtx_code) (new_insn)->code) == CALL_INSN))
3884 break;
3885 new_insn = NEXT_INSN (new_insn);
3886 }
3887
3888 gcc_assert (new_insn != NULL_RTX)((void)(!(new_insn != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3888, __FUNCTION__), 0 : 0))
;
3889
3890 CALL_INSN_FUNCTION_USAGE (new_insn)(((new_insn)->u.fld[7]).rt_rtx)
3891 = CALL_INSN_FUNCTION_USAGE (old_insn)(((old_insn)->u.fld[7]).rt_rtx);
3892 SIBLING_CALL_P (new_insn)(__extension__ ({ __typeof ((new_insn)) const _rtx = ((new_insn
)); if (((enum rtx_code) (_rtx)->code) != CALL_INSN) rtl_check_failed_flag
("SIBLING_CALL_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3892, __FUNCTION__); _rtx; })->jump)
= SIBLING_CALL_P (old_insn)(__extension__ ({ __typeof ((old_insn)) const _rtx = ((old_insn
)); if (((enum rtx_code) (_rtx)->code) != CALL_INSN) rtl_check_failed_flag
("SIBLING_CALL_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3892, __FUNCTION__); _rtx; })->jump)
;
3893
3894 for (note = REG_NOTES (old_insn)(((old_insn)->u.fld[6]).rt_rtx);
3895 note;
3896 note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
3897 switch (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)))
3898 {
3899 case REG_NORETURN:
3900 case REG_SETJMP:
3901 case REG_TM:
3902 case REG_CALL_NOCF_CHECK:
3903 add_reg_note (new_insn, REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)),
3904 XEXP (note, 0)(((note)->u.fld[0]).rt_rtx));
3905 break;
3906 default:
3907 /* Discard all other reg notes. */
3908 break;
3909 }
3910
3911 /* Croak if there is another call in the sequence. */
3912 while (++i <= match_len)
3913 {
3914 j = peep2_buf_position (peep2_current + i);
3915 old_insn = peep2_insn_data[j].insn;
3916 gcc_assert (!CALL_P (old_insn))((void)(!(!(((enum rtx_code) (old_insn)->code) == CALL_INSN
)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3916, __FUNCTION__), 0 : 0))
;
3917 }
3918 break;
3919 }
3920
3921 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3922 move those notes over to the new sequence. */
3923 as_note = NULLnullptr;
3924 for (i = match_len; i >= 0; --i)
3925 {
3926 int j = peep2_buf_position (peep2_current + i);
3927 old_insn = peep2_insn_data[j].insn;
3928
3929 as_note = find_reg_note (old_insn, REG_ARGS_SIZE, NULLnullptr);
3930 if (as_note)
3931 break;
3932 }
3933
3934 i = peep2_buf_position (peep2_current + match_len);
3935 eh_note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX(rtx) 0);
3936
3937 /* Replace the old sequence with the new. */
3938 rtx_insn *peepinsn = peep2_insn_data[i].insn;
3939 last = emit_insn_after_setloc (attempt,
3940 peep2_insn_data[i].insn,
3941 INSN_LOCATION (peepinsn));
3942 if (JUMP_P (peepinsn)(((enum rtx_code) (peepinsn)->code) == JUMP_INSN) && JUMP_P (last)(((enum rtx_code) (last)->code) == JUMP_INSN))
3943 CROSSING_JUMP_P (last)(__extension__ ({ __typeof ((last)) const _rtx = ((last)); if
(((enum rtx_code) (_rtx)->code) != JUMP_INSN) rtl_check_failed_flag
("CROSSING_JUMP_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3943, __FUNCTION__); _rtx; })->jump)
= CROSSING_JUMP_P (peepinsn)(__extension__ ({ __typeof ((peepinsn)) const _rtx = ((peepinsn
)); if (((enum rtx_code) (_rtx)->code) != JUMP_INSN) rtl_check_failed_flag
("CROSSING_JUMP_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 3943, __FUNCTION__); _rtx; })->jump)
;
3944 before_try = PREV_INSN (insn);
3945 delete_insn_chain (insn, peep2_insn_data[i].insn, false);
3946
3947 /* Re-insert the EH_REGION notes. */
3948 if (eh_note || (was_call && nonlocal_goto_handler_labels((&x_rtl)->x_nonlocal_goto_handler_labels)))
3949 {
3950 edge eh_edge;
3951 edge_iterator ei;
3952
3953 FOR_EACH_EDGE (eh_edge, ei, bb->succs)for ((ei) = ei_start_1 (&((bb->succs))); ei_cond ((ei)
, &(eh_edge)); ei_next (&(ei)))
3954 if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL))
3955 break;
3956
3957 if (eh_note)
3958 copy_reg_eh_region_note_backward (eh_note, last, before_try);
3959
3960 if (eh_edge)
3961 for (x = last; x != before_try; x = PREV_INSN (x))
3962 if (x != BB_END (bb)(bb)->il.x.rtl->end_
3963 && (can_throw_internal (x)
3964 || can_nonlocal_goto (x)))
3965 {
3966 edge nfte, nehe;
3967 int flags;
3968
3969 nfte = split_block (bb, x);
3970 flags = (eh_edge->flags
3971 & (EDGE_EH | EDGE_ABNORMAL));
3972 if (CALL_P (x)(((enum rtx_code) (x)->code) == CALL_INSN))
3973 flags |= EDGE_ABNORMAL_CALL;
3974 nehe = make_edge (nfte->src, eh_edge->dest,
3975 flags);
3976
3977 nehe->probability = eh_edge->probability;
3978 nfte->probability = nehe->probability.invert ();
3979
3980 peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest);
3981 bb = nfte->src;
3982 eh_edge = nehe;
3983 }
3984
3985 /* Converting possibly trapping insn to non-trapping is
3986 possible. Zap dummy outgoing edges. */
3987 peep2_do_cleanup_cfg |= purge_dead_edges (bb);
3988 }
3989
3990 /* Re-insert the ARGS_SIZE notes. */
3991 if (as_note)
3992 fixup_args_size_notes (before_try, last, get_args_size (as_note));
3993
3994 /* Scan the new insns for embedded side effects and add appropriate
3995 REG_INC notes. */
3996 if (AUTO_INC_DEC0)
3997 for (x = last; x != before_try; x = PREV_INSN (x))
3998 if (NONDEBUG_INSN_P (x)((((enum rtx_code) (x)->code) == INSN) || (((enum rtx_code
) (x)->code) == JUMP_INSN) || (((enum rtx_code) (x)->code
) == CALL_INSN))
)
3999 add_auto_inc_notes (x, PATTERN (x));
4000
4001 /* If we generated a jump instruction, it won't have
4002 JUMP_LABEL set. Recompute after we're done. */
4003 for (x = last; x != before_try; x = PREV_INSN (x))
4004 if (JUMP_P (x)(((enum rtx_code) (x)->code) == JUMP_INSN))
4005 {
4006 peep2_do_rebuild_jump_labels = true;
4007 break;
4008 }
4009
4010 return last;
4011}
4012
4013/* After performing a replacement in basic block BB, fix up the life
4014 information in our buffer. LAST is the last of the insns that we
4015 emitted as a replacement. PREV is the insn before the start of
4016 the replacement. MATCH_LEN is the number of instructions that were
4017 matched, and which now need to be replaced in the buffer. */
4018
4019static void
4020peep2_update_life (basic_block bb, int match_len, rtx_insn *last,
4021 rtx_insn *prev)
4022{
4023 int i = peep2_buf_position (peep2_current + match_len + 1);
4024 rtx_insn *x;
4025 regset_head live;
4026
4027 INIT_REG_SET (&live)bitmap_initialize (&live, &reg_obstack);
4028 COPY_REG_SET (&live, peep2_insn_data[i].live_before)bitmap_copy (&live, peep2_insn_data[i].live_before);
4029
4030 gcc_assert (peep2_current_count >= match_len + 1)((void)(!(peep2_current_count >= match_len + 1) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 4030, __FUNCTION__), 0 : 0))
;
4031 peep2_current_count -= match_len + 1;
4032
4033 x = last;
4034 do
4035 {
4036 if (INSN_P (x)(((((enum rtx_code) (x)->code) == INSN) || (((enum rtx_code
) (x)->code) == JUMP_INSN) || (((enum rtx_code) (x)->code
) == CALL_INSN)) || (((enum rtx_code) (x)->code) == DEBUG_INSN
))
)
4037 {
4038 df_insn_rescan (x);
4039 if (peep2_current_count < MAX_INSNS_PER_PEEP25)
4040 {
4041 peep2_current_count++;
4042 if (--i < 0)
4043 i = MAX_INSNS_PER_PEEP25;
4044 peep2_insn_data[i].insn = x;
4045 df_simulate_one_insn_backwards (bb, x, &live);
4046 COPY_REG_SET (peep2_insn_data[i].live_before, &live)bitmap_copy (peep2_insn_data[i].live_before, &live);
4047 }
4048 }
4049 x = PREV_INSN (x);
4050 }
4051 while (x != prev);
4052 CLEAR_REG_SET (&live)bitmap_clear (&live);
4053
4054 peep2_current = i;
4055}
4056
4057/* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
4058 Return true if we added it, false otherwise. The caller will try to match
4059 peepholes against the buffer if we return false; otherwise it will try to
4060 add more instructions to the buffer. */
4061
4062static bool
4063peep2_fill_buffer (basic_block bb, rtx_insn *insn, regset live)
4064{
4065 int pos;
4066
4067 /* Once we have filled the maximum number of insns the buffer can hold,
4068 allow the caller to match the insns against peepholes. We wait until
4069 the buffer is full in case the target has similar peepholes of different
4070 length; we always want to match the longest if possible. */
4071 if (peep2_current_count == MAX_INSNS_PER_PEEP25)
4072 return false;
4073
4074 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
4075 any other pattern, lest it change the semantics of the frame info. */
4076 if (RTX_FRAME_RELATED_P (insn)(__extension__ ({ __typeof ((insn)) const _rtx = ((insn)); if
(((enum rtx_code) (_rtx)->code) != DEBUG_INSN && (
(enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != CALL_INSN && ((enum rtx_code) (
_rtx)->code) != JUMP_INSN && ((enum rtx_code) (_rtx
)->code) != BARRIER && ((enum rtx_code) (_rtx)->
code) != SET) rtl_check_failed_flag ("RTX_FRAME_RELATED_P",_rtx
, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 4076, __FUNCTION__); _rtx; })->frame_related)
)
4077 {
4078 /* Let the buffer drain first. */
4079 if (peep2_current_count > 0)
4080 return false;
4081 /* Now the insn will be the only thing in the buffer. */
4082 }
4083
4084 pos = peep2_buf_position (peep2_current + peep2_current_count);
4085 peep2_insn_data[pos].insn = insn;
4086 COPY_REG_SET (peep2_insn_data[pos].live_before, live)bitmap_copy (peep2_insn_data[pos].live_before, live);
4087 peep2_current_count++;
4088
4089 df_simulate_one_insn_forwards (bb, insn, live);
4090 return true;
4091}
4092
4093/* Perform the peephole2 optimization pass. */
4094
4095static void
4096peephole2_optimize (void)
4097{
4098 rtx_insn *insn;
4099 bitmap live;
4100 int i;
4101 basic_block bb;
4102
4103 peep2_do_cleanup_cfg = false;
4104 peep2_do_rebuild_jump_labels = false;
4105
4106 df_set_flags (DF_LR_RUN_DCE);
4107 df_note_add_problem ();
4108 df_analyze ();
4109
4110 /* Initialize the regsets we're going to use. */
4111 for (i = 0; i < MAX_INSNS_PER_PEEP25 + 1; ++i)
4112 peep2_insn_data[i].live_before = BITMAP_ALLOCbitmap_alloc (&reg_obstack);
4113 search_ofs = 0;
4114 live = BITMAP_ALLOCbitmap_alloc (&reg_obstack);
4115
4116 FOR_EACH_BB_REVERSE_FN (bb, cfun)for (bb = ((cfun + 0))->cfg->x_exit_block_ptr->prev_bb
; bb != ((cfun + 0))->cfg->x_entry_block_ptr; bb = bb->
prev_bb)
4117 {
4118 bool past_end = false;
4119 int pos;
4120
4121 rtl_profile_for_bb (bb);
4122
4123 /* Start up propagation. */
4124 bitmap_copy (live, DF_LR_IN (bb)(&(df_lr_get_bb_info ((bb)->index))->in));
4125 df_simulate_initialize_forwards (bb, live);
4126 peep2_reinit_state (live);
4127
4128 insn = BB_HEAD (bb)(bb)->il.x.head_;
4129 for (;;)
4130 {
4131 rtx_insn *attempt, *head;
4132 int match_len;
4133
4134 if (!past_end && !NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN))
)
4135 {
4136 next_insn:
4137 insn = NEXT_INSN (insn);
4138 if (insn == NEXT_INSN (BB_END (bb)(bb)->il.x.rtl->end_))
4139 past_end = true;
4140 continue;
4141 }
4142 if (!past_end && peep2_fill_buffer (bb, insn, live))
4143 goto next_insn;
4144
4145 /* If we did not fill an empty buffer, it signals the end of the
4146 block. */
4147 if (peep2_current_count == 0)
4148 break;
4149
4150 /* The buffer filled to the current maximum, so try to match. */
4151
4152 pos = peep2_buf_position (peep2_current + peep2_current_count);
4153 peep2_insn_data[pos].insn = PEEP2_EOBinvalid_insn_rtx;
4154 COPY_REG_SET (peep2_insn_data[pos].live_before, live)bitmap_copy (peep2_insn_data[pos].live_before, live);
4155
4156 /* Match the peephole. */
4157 head = peep2_insn_data[peep2_current].insn;
4158 attempt = peephole2_insns (PATTERN (head), head, &match_len);
4159 if (attempt != NULLnullptr)
4160 {
4161 rtx_insn *last = peep2_attempt (bb, head, match_len, attempt);
4162 if (last)
4163 {
4164 peep2_update_life (bb, match_len, last, PREV_INSN (attempt));
4165 continue;
4166 }
4167 }
4168
4169 /* No match: advance the buffer by one insn. */
4170 peep2_current = peep2_buf_position (peep2_current + 1);
4171 peep2_current_count--;
4172 }
4173 }
4174
4175 default_rtl_profile ();
4176 for (i = 0; i < MAX_INSNS_PER_PEEP25 + 1; ++i)
4177 BITMAP_FREE (peep2_insn_data[i].live_before)((void) (bitmap_obstack_free ((bitmap) peep2_insn_data[i].live_before
), (peep2_insn_data[i].live_before) = (bitmap) nullptr))
;
4178 BITMAP_FREE (live)((void) (bitmap_obstack_free ((bitmap) live), (live) = (bitmap
) nullptr))
;
4179 if (peep2_do_rebuild_jump_labels)
4180 rebuild_jump_labels (get_insns ());
4181 if (peep2_do_cleanup_cfg)
4182 cleanup_cfg (CLEANUP_CFG_CHANGED64);
4183}
4184
4185/* Common predicates for use with define_bypass. */
4186
4187/* Helper function for store_data_bypass_p, handle just a single SET
4188 IN_SET. */
4189
4190static bool
4191store_data_bypass_p_1 (rtx_insn *out_insn, rtx in_set)
4192{
4193 if (!MEM_P (SET_DEST (in_set))(((enum rtx_code) ((((in_set)->u.fld[0]).rt_rtx))->code
) == MEM)
)
4194 return false;
4195
4196 rtx out_set = single_set (out_insn);
4197 if (out_set)
4198 return !reg_mentioned_p (SET_DEST (out_set)(((out_set)->u.fld[0]).rt_rtx), SET_DEST (in_set)(((in_set)->u.fld[0]).rt_rtx));
4199
4200 rtx out_pat = PATTERN (out_insn);
4201 if (GET_CODE (out_pat)((enum rtx_code) (out_pat)->code) != PARALLEL)
4202 return false;
4203
4204 for (int i = 0; i < XVECLEN (out_pat, 0)(((((out_pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
4205 {
4206 rtx out_exp = XVECEXP (out_pat, 0, i)(((((out_pat)->u.fld[0]).rt_rtvec))->elem[i]);
4207
4208 if (GET_CODE (out_exp)((enum rtx_code) (out_exp)->code) == CLOBBER || GET_CODE (out_exp)((enum rtx_code) (out_exp)->code) == USE)
4209 continue;
4210
4211 gcc_assert (GET_CODE (out_exp) == SET)((void)(!(((enum rtx_code) (out_exp)->code) == SET) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 4211, __FUNCTION__), 0 : 0))
;
4212
4213 if (reg_mentioned_p (SET_DEST (out_exp)(((out_exp)->u.fld[0]).rt_rtx), SET_DEST (in_set)(((in_set)->u.fld[0]).rt_rtx)))
4214 return false;
4215 }
4216
4217 return true;
4218}
4219
4220/* True if the dependency between OUT_INSN and IN_INSN is on the store
4221 data not the address operand(s) of the store. IN_INSN and OUT_INSN
4222 must be either a single_set or a PARALLEL with SETs inside. */
4223
4224int
4225store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
4226{
4227 rtx in_set = single_set (in_insn);
4228 if (in_set)
4229 return store_data_bypass_p_1 (out_insn, in_set);
4230
4231 rtx in_pat = PATTERN (in_insn);
4232 if (GET_CODE (in_pat)((enum rtx_code) (in_pat)->code) != PARALLEL)
4233 return false;
4234
4235 for (int i = 0; i < XVECLEN (in_pat, 0)(((((in_pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
4236 {
4237 rtx in_exp = XVECEXP (in_pat, 0, i)(((((in_pat)->u.fld[0]).rt_rtvec))->elem[i]);
4238
4239 if (GET_CODE (in_exp)((enum rtx_code) (in_exp)->code) == CLOBBER || GET_CODE (in_exp)((enum rtx_code) (in_exp)->code) == USE)
4240 continue;
4241
4242 gcc_assert (GET_CODE (in_exp) == SET)((void)(!(((enum rtx_code) (in_exp)->code) == SET) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 4242, __FUNCTION__), 0 : 0))
;
4243
4244 if (!store_data_bypass_p_1 (out_insn, in_exp))
4245 return false;
4246 }
4247
4248 return true;
4249}
4250
4251/* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
4252 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
4253 or multiple set; IN_INSN should be single_set for truth, but for convenience
4254 of insn categorization may be any JUMP or CALL insn. */
4255
4256int
4257if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
4258{
4259 rtx out_set, in_set;
4260
4261 in_set = single_set (in_insn);
4262 if (! in_set)
4263 {
4264 gcc_assert (JUMP_P (in_insn) || CALL_P (in_insn))((void)(!((((enum rtx_code) (in_insn)->code) == JUMP_INSN)
|| (((enum rtx_code) (in_insn)->code) == CALL_INSN)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 4264, __FUNCTION__), 0 : 0))
;
4265 return false;
4266 }
4267
4268 if (GET_CODE (SET_SRC (in_set))((enum rtx_code) ((((in_set)->u.fld[1]).rt_rtx))->code) != IF_THEN_ELSE)
4269 return false;
4270 in_set = SET_SRC (in_set)(((in_set)->u.fld[1]).rt_rtx);
4271
4272 out_set = single_set (out_insn);
4273 if (out_set)
4274 {
4275 if (reg_mentioned_p (SET_DEST (out_set)(((out_set)->u.fld[0]).rt_rtx), XEXP (in_set, 1)(((in_set)->u.fld[1]).rt_rtx))
4276 || reg_mentioned_p (SET_DEST (out_set)(((out_set)->u.fld[0]).rt_rtx), XEXP (in_set, 2)(((in_set)->u.fld[2]).rt_rtx)))
4277 return false;
4278 }
4279 else
4280 {
4281 rtx out_pat;
4282 int i;
4283
4284 out_pat = PATTERN (out_insn);
4285 gcc_assert (GET_CODE (out_pat) == PARALLEL)((void)(!(((enum rtx_code) (out_pat)->code) == PARALLEL) ?
fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 4285, __FUNCTION__), 0 : 0))
;
4286
4287 for (i = 0; i < XVECLEN (out_pat, 0)(((((out_pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
4288 {
4289 rtx exp = XVECEXP (out_pat, 0, i)(((((out_pat)->u.fld[0]).rt_rtvec))->elem[i]);
4290
4291 if (GET_CODE (exp)((enum rtx_code) (exp)->code) == CLOBBER)
4292 continue;
4293
4294 gcc_assert (GET_CODE (exp) == SET)((void)(!(((enum rtx_code) (exp)->code) == SET) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/recog.c"
, 4294, __FUNCTION__), 0 : 0))
;
4295
4296 if (reg_mentioned_p (SET_DEST (out_set)(((out_set)->u.fld[0]).rt_rtx), XEXP (in_set, 1)(((in_set)->u.fld[1]).rt_rtx))
4297 || reg_mentioned_p (SET_DEST (out_set)(((out_set)->u.fld[0]).rt_rtx), XEXP (in_set, 2)(((in_set)->u.fld[2]).rt_rtx)))
4298 return false;
4299 }
4300 }
4301
4302 return true;
4303}
4304
4305static unsigned int
4306rest_of_handle_peephole2 (void)
4307{
4308 if (HAVE_peephole21)
4309 peephole2_optimize ();
4310
4311 return 0;
4312}
4313
4314namespace {
4315
4316const pass_data pass_data_peephole2 =
4317{
4318 RTL_PASS, /* type */
4319 "peephole2", /* name */
4320 OPTGROUP_NONE, /* optinfo_flags */
4321 TV_PEEPHOLE2, /* tv_id */
4322 0, /* properties_required */
4323 0, /* properties_provided */
4324 0, /* properties_destroyed */
4325 0, /* todo_flags_start */
4326 TODO_df_finish(1 << 17), /* todo_flags_finish */
4327};
4328
4329class pass_peephole2 : public rtl_opt_pass
4330{
4331public:
4332 pass_peephole2 (gcc::context *ctxt)
4333 : rtl_opt_pass (pass_data_peephole2, ctxt)
4334 {}
4335
4336 /* opt_pass methods: */
4337 /* The epiphany backend creates a second instance of this pass, so we need
4338 a clone method. */
4339 opt_pass * clone () { return new pass_peephole2 (m_ctxt); }
4340 virtual bool gate (function *) { return (optimizeglobal_options.x_optimize > 0 && flag_peephole2global_options.x_flag_peephole2); }
4341 virtual unsigned int execute (function *)
4342 {
4343 return rest_of_handle_peephole2 ();
4344 }
4345
4346}; // class pass_peephole2
4347
4348} // anon namespace
4349
4350rtl_opt_pass *
4351make_pass_peephole2 (gcc::context *ctxt)
4352{
4353 return new pass_peephole2 (ctxt);
4354}
4355
4356namespace {
4357
4358const pass_data pass_data_split_all_insns =
4359{
4360 RTL_PASS, /* type */
4361 "split1", /* name */
4362 OPTGROUP_NONE, /* optinfo_flags */
4363 TV_NONE, /* tv_id */
4364 0, /* properties_required */
4365 PROP_rtl_split_insns(1 << 17), /* properties_provided */
4366 0, /* properties_destroyed */
4367 0, /* todo_flags_start */
4368 0, /* todo_flags_finish */
4369};
4370
4371class pass_split_all_insns : public rtl_opt_pass
4372{
4373public:
4374 pass_split_all_insns (gcc::context *ctxt)
4375 : rtl_opt_pass (pass_data_split_all_insns, ctxt)
4376 {}
4377
4378 /* opt_pass methods: */
4379 /* The epiphany backend creates a second instance of this pass, so
4380 we need a clone method. */
4381 opt_pass * clone () { return new pass_split_all_insns (m_ctxt); }
4382 virtual unsigned int execute (function *)
4383 {
4384 split_all_insns ();
4385 return 0;
4386 }
4387
4388}; // class pass_split_all_insns
4389
4390} // anon namespace
4391
4392rtl_opt_pass *
4393make_pass_split_all_insns (gcc::context *ctxt)
4394{
4395 return new pass_split_all_insns (ctxt);
4396}
4397
4398namespace {
4399
4400const pass_data pass_data_split_after_reload =
4401{
4402 RTL_PASS, /* type */
4403 "split2", /* name */
4404 OPTGROUP_NONE, /* optinfo_flags */
4405 TV_NONE, /* tv_id */
4406 0, /* properties_required */
4407 0, /* properties_provided */
4408 0, /* properties_destroyed */
4409 0, /* todo_flags_start */
4410 0, /* todo_flags_finish */
4411};
4412
4413class pass_split_after_reload : public rtl_opt_pass
4414{
4415public:
4416 pass_split_after_reload (gcc::context *ctxt)
4417 : rtl_opt_pass (pass_data_split_after_reload, ctxt)
4418 {}
4419
4420 /* opt_pass methods: */
4421 virtual bool gate (function *)
4422 {
4423 /* If optimizing, then go ahead and split insns now. */
4424 return optimizeglobal_options.x_optimize > 0;
4425 }
4426
4427 virtual unsigned int execute (function *)
4428 {
4429 split_all_insns ();
4430 return 0;
4431 }
4432
4433}; // class pass_split_after_reload
4434
4435} // anon namespace
4436
4437rtl_opt_pass *
4438make_pass_split_after_reload (gcc::context *ctxt)
4439{
4440 return new pass_split_after_reload (ctxt);
4441}
4442
4443static bool
4444enable_split_before_sched2 (void)
4445{
4446#ifdef INSN_SCHEDULING
4447 return optimizeglobal_options.x_optimize > 0 && flag_schedule_insns_after_reloadglobal_options.x_flag_schedule_insns_after_reload;
4448#else
4449 return false;
4450#endif
4451}
4452
4453namespace {
4454
4455const pass_data pass_data_split_before_sched2 =
4456{
4457 RTL_PASS, /* type */
4458 "split3", /* name */
4459 OPTGROUP_NONE, /* optinfo_flags */
4460 TV_NONE, /* tv_id */
4461 0, /* properties_required */
4462 0, /* properties_provided */
4463 0, /* properties_destroyed */
4464 0, /* todo_flags_start */
4465 0, /* todo_flags_finish */
4466};
4467
4468class pass_split_before_sched2 : public rtl_opt_pass
4469{
4470public:
4471 pass_split_before_sched2 (gcc::context *ctxt)
4472 : rtl_opt_pass (pass_data_split_before_sched2, ctxt)
4473 {}
4474
4475 /* opt_pass methods: */
4476 virtual bool gate (function *)
4477 {
4478 return enable_split_before_sched2 ();
4479 }
4480
4481 virtual unsigned int execute (function *)
4482 {
4483 split_all_insns ();
4484 return 0;
4485 }
4486
4487}; // class pass_split_before_sched2
4488
4489} // anon namespace
4490
4491rtl_opt_pass *
4492make_pass_split_before_sched2 (gcc::context *ctxt)
4493{
4494 return new pass_split_before_sched2 (ctxt);
4495}
4496
4497namespace {
4498
4499const pass_data pass_data_split_before_regstack =
4500{
4501 RTL_PASS, /* type */
4502 "split4", /* name */
4503 OPTGROUP_NONE, /* optinfo_flags */
4504 TV_NONE, /* tv_id */
4505 0, /* properties_required */
4506 0, /* properties_provided */
4507 0, /* properties_destroyed */
4508 0, /* todo_flags_start */
4509 0, /* todo_flags_finish */
4510};
4511
4512class pass_split_before_regstack : public rtl_opt_pass
4513{
4514public:
4515 pass_split_before_regstack (gcc::context *ctxt)
4516 : rtl_opt_pass (pass_data_split_before_regstack, ctxt)
4517 {}
4518
4519 /* opt_pass methods: */
4520 virtual bool gate (function *);
4521 virtual unsigned int execute (function *)
4522 {
4523 split_all_insns ();
4524 return 0;
4525 }
4526
4527}; // class pass_split_before_regstack
4528
4529bool
4530pass_split_before_regstack::gate (function *)
4531{
4532#if HAVE_ATTR_length1 && defined (STACK_REGS)
4533 /* If flow2 creates new instructions which need splitting
4534 and scheduling after reload is not done, they might not be
4535 split until final which doesn't allow splitting
4536 if HAVE_ATTR_length. Selective scheduling can result in
4537 further instructions that need splitting. */
4538#ifdef INSN_SCHEDULING
4539 return !enable_split_before_sched2 () || flag_selective_scheduling2global_options.x_flag_selective_scheduling2;
4540#else
4541 return !enable_split_before_sched2 ();
4542#endif
4543#else
4544 return false;
4545#endif
4546}
4547
4548} // anon namespace
4549
4550rtl_opt_pass *
4551make_pass_split_before_regstack (gcc::context *ctxt)
4552{
4553 return new pass_split_before_regstack (ctxt);
4554}
4555
4556namespace {
4557
4558const pass_data pass_data_split_for_shorten_branches =
4559{
4560 RTL_PASS, /* type */
4561 "split5", /* name */
4562 OPTGROUP_NONE, /* optinfo_flags */
4563 TV_NONE, /* tv_id */
4564 0, /* properties_required */
4565 0, /* properties_provided */
4566 0, /* properties_destroyed */
4567 0, /* todo_flags_start */
4568 0, /* todo_flags_finish */
4569};
4570
4571class pass_split_for_shorten_branches : public rtl_opt_pass
4572{
4573public:
4574 pass_split_for_shorten_branches (gcc::context *ctxt)
4575 : rtl_opt_pass (pass_data_split_for_shorten_branches, ctxt)
4576 {}
4577
4578 /* opt_pass methods: */
4579 virtual bool gate (function *)
4580 {
4581 /* The placement of the splitting that we do for shorten_branches
4582 depends on whether regstack is used by the target or not. */
4583#if HAVE_ATTR_length1 && !defined (STACK_REGS)
4584 return true;
4585#else
4586 return false;
4587#endif
4588 }
4589
4590 virtual unsigned int execute (function *)
4591 {
4592 return split_all_insns_noflow ();
4593 }
4594
4595}; // class pass_split_for_shorten_branches
4596
4597} // anon namespace
4598
4599rtl_opt_pass *
4600make_pass_split_for_shorten_branches (gcc::context *ctxt)
4601{
4602 return new pass_split_for_shorten_branches (ctxt);
4603}
4604
4605/* (Re)initialize the target information after a change in target. */
4606
4607void
4608recog_init ()
4609{
4610 /* The information is zero-initialized, so we don't need to do anything
4611 first time round. */
4612 if (!this_target_recog->x_initialized)
4613 {
4614 this_target_recog->x_initialized = true;
4615 return;
4616 }
4617 memset (this_target_recog->x_bool_attr_masks, 0,
4618 sizeof (this_target_recog->x_bool_attr_masks));
4619 for (unsigned int i = 0; i < NUM_INSN_CODES; ++i)
4620 if (this_target_recog->x_op_alt[i])
4621 {
4622 free (this_target_recog->x_op_alt[i]);
4623 this_target_recog->x_op_alt[i] = 0;
4624 }
4625}