/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc

Bug Summary

File:	build/gcc/rtlanal.cc
Warning:	line 5194, column 25 The result of the left shift is undefined because the right operand is negative
Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-suse-linux -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name rtlanal.cc -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -resource-dir /usr/lib64/clang/15.0.7 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/backward -internal-isystem /usr/lib64/clang/15.0.7/include -internal-isystem /usr/local/include -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../x86_64-suse-linux/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2023-03-27-141847-20772-1/report-kjurYM.plist -x c++ /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc
/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc

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1/* Analyze RTL for GNU compiler.
 Copyright (C) 1987-2023 Free Software Foundation, Inc.

4This file is part of GCC.

6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8Software Foundation; either version 3, or (at your option) any later
9version.

11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14for more details.

16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3.  If not see
18<http://www.gnu.org/licenses/>.  */


21#include "config.h"
22#include "system.h"
23#include "coretypes.h"
24#include "backend.h"
25#include "target.h"
26#include "rtl.h"
27#include "rtlanal.h"
28#include "tree.h"
29#include "predict.h"
30#include "df.h"
31#include "memmodel.h"
32#include "tm_p.h"
33#include "insn-config.h"
34#include "regs.h"
35#include "emit-rtl.h"  /* FIXME: Can go away once crtl is moved to rtl.h.  */
36#include "recog.h"
37#include "addresses.h"
38#include "rtl-iter.h"
39#include "hard-reg-set.h"
40#include "function-abi.h"

42/* Forward declarations */
43static void set_of_1 (rtx, const_rtx, void *);
44static bool covers_regno_p (const_rtx, unsigned int);
45static bool covers_regno_no_parallel_p (const_rtx, unsigned int);
46static int computed_jump_p_1 (const_rtx);
47static void parms_set (rtx, const_rtx, void *);

49static unsigned HOST_WIDE_INTlong cached_nonzero_bits (const_rtx, scalar_int_mode,
                                                 const_rtx, machine_mode,
                                                 unsigned HOST_WIDE_INTlong);
52static unsigned HOST_WIDE_INTlong nonzero_bits1 (const_rtx, scalar_int_mode,
			     const_rtx, machine_mode,
                                           unsigned HOST_WIDE_INTlong);
55static unsigned int cached_num_sign_bit_copies (const_rtx, scalar_int_mode,
				const_rtx, machine_mode,
                                              unsigned int);
58static unsigned int num_sign_bit_copies1 (const_rtx, scalar_int_mode,
			  const_rtx, machine_mode,
			  unsigned int);

62rtx_subrtx_bound_info rtx_all_subrtx_bounds[NUM_RTX_CODE((int) LAST_AND_UNUSED_RTX_CODE)];
63rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds[NUM_RTX_CODE((int) LAST_AND_UNUSED_RTX_CODE)];

65/* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
 SIGN_EXTEND then while narrowing we also have to enforce the
 representation and sign-extend the value to mode DESTINATION_REP.

 If the value is already sign-extended to DESTINATION_REP mode we
 can just switch to DESTINATION mode on it.  For each pair of
 integral modes SOURCE and DESTINATION, when truncating from SOURCE
 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
 contains the number of high-order bits in SOURCE that have to be
 copies of the sign-bit so that we can do this mode-switch to
 DESTINATION.  */

78static unsigned int
79num_sign_bit_copies_in_rep[MAX_MODE_INT + 1][MAX_MODE_INT + 1];
80
81/* Store X into index I of ARRAY.  ARRAY is known to have at least I
 elements.  Return the new base of ARRAY.  */

84template <typename T>
85typename T::value_type *
86generic_subrtx_iterator <T>::add_single_to_queue (array_type &array,
				  value_type *base,
				  size_t i, value_type x)
89{
if (base == array.stack)
  {
    if (i < LOCAL_ELEMS)
{
 base[i] = x;
 return base;
}
    gcc_checking_assert (i == LOCAL_ELEMS)((void)(!(i == LOCAL_ELEMS) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 97, __FUNCTION__), 0 : 0));
    /* A previous iteration might also have moved from the stack to the
heap, in which case the heap array will already be big enough.  */
    if (vec_safe_length (array.heap) <= i)
vec_safe_grow (array.heap, i + 1, true);
    base = array.heap->address ();
    memcpy (base, array.stack, sizeof (array.stack));
    base[LOCAL_ELEMS] = x;
    return base;
  }
unsigned int length = array.heap->length ();
if (length > i)
  {
    gcc_checking_assert (base == array.heap->address ())((void)(!(base == array.heap->address ()) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 110, __FUNCTION__), 0 : 0));
    base[i] = x;
    return base;
  }
else
  {
    gcc_checking_assert (i == length)((void)(!(i == length) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 116, __FUNCTION__), 0 : 0));
    vec_safe_push (array.heap, x);
    return array.heap->address ();
  }
120}

122/* Add the subrtxes of X to worklist ARRAY, starting at END.  Return the
 number of elements added to the worklist.  */

125template <typename T>
126size_t
127generic_subrtx_iterator <T>::add_subrtxes_to_queue (array_type &array,
				    value_type *base,
				    size_t end, rtx_type x)
130{
enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
const char *format = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
size_t orig_end = end;
if (UNLIKELY (INSN_P (x))(__builtin_expect (((((((enum rtx_code) (x)->code) == INSN
) || (((enum rtx_code) (x)->code) == JUMP_INSN) || (((enum
 rtx_code) (x)->code) == CALL_INSN)) || (((enum rtx_code) (
x)->code) == DEBUG_INSN))), 0)))
  {
    /* Put the pattern at the top of the queue, since that's what
we're likely to want most.  It also allows for the SEQUENCE
code below.  */
    for (int i = GET_RTX_LENGTH (GET_CODE (x))(rtx_length[(int) (((enum rtx_code) (x)->code))]) - 1; i >= 0; --i)
if (format[i] == 'e')
 {
   value_type subx = T::get_value (x->u.fld[i].rt_rtx);
   if (LIKELY (end < LOCAL_ELEMS)(__builtin_expect ((end < LOCAL_ELEMS), 1)))
     base[end++] = subx;
   else
     base = add_single_to_queue (array, base, end++, subx);
 }
  }
else
  for (int i = 0; format[i]; ++i)
    if (format[i] == 'e')
{
 value_type subx = T::get_value (x->u.fld[i].rt_rtx);
 if (LIKELY (end < LOCAL_ELEMS)(__builtin_expect ((end < LOCAL_ELEMS), 1)))
   base[end++] = subx;
 else
   base = add_single_to_queue (array, base, end++, subx);
}
    else if (format[i] == 'E')
{
 unsigned int length = GET_NUM_ELEM (x->u.fld[i].rt_rtvec)((x->u.fld[i].rt_rtvec)->num_elem);
 rtx *vec = x->u.fld[i].rt_rtvec->elem;
 if (LIKELY (end + length <= LOCAL_ELEMS)(__builtin_expect ((end + length <= LOCAL_ELEMS), 1)))
   for (unsigned int j = 0; j < length; j++)
     base[end++] = T::get_value (vec[j]);
 else
   for (unsigned int j = 0; j < length; j++)
     base = add_single_to_queue (array, base, end++,
			  T::get_value (vec[j]));
 if (code == SEQUENCE && end == length)
   /* If the subrtxes of the sequence fill the entire array then
      we know that no other parts of a containing insn are queued.
      The caller is therefore iterating over the sequence as a
      PATTERN (...), so we also want the patterns of the
      subinstructions.  */
   for (unsigned int j = 0; j < length; j++)
     {
typename T::rtx_type x = T::get_rtx (base[j]);
if (INSN_P (x)(((((enum rtx_code) (x)->code) == INSN) || (((enum rtx_code
) (x)->code) == JUMP_INSN) || (((enum rtx_code) (x)->code
) == CALL_INSN)) || (((enum rtx_code) (x)->code) == DEBUG_INSN
)))
  base[j] = T::get_value (PATTERN (x));
     }
}
return end - orig_end;
184}

186template <typename T>
187void
188generic_subrtx_iterator <T>::free_array (array_type &array)
189{
vec_free (array.heap);
191}

193template <typename T>
194const size_t generic_subrtx_iterator <T>::LOCAL_ELEMS;

196template class generic_subrtx_iterator <const_rtx_accessor>;
197template class generic_subrtx_iterator <rtx_var_accessor>;
198template class generic_subrtx_iterator <rtx_ptr_accessor>;

200/* Return 1 if the value of X is unstable
 (would be different at a different point in the program).
 The frame pointer, arg pointer, etc. are considered stable
 (within one function) and so is anything marked `unchanging'.  */

205int
206rtx_unstable_p (const_rtx x)
207{
const RTX_CODEenum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
int i;
const char *fmt;

switch (code)
  {
  case MEM:
    return !MEM_READONLY_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 215, __FUNCTION__); _rtx; })->unchanging) || rtx_unstable_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));

  case CONST:
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case SYMBOL_REF:
  case LABEL_REF:
    return 0;

  case REG:
    /* As in rtx_varies_p, we have to use the actual rtx, not reg number.  */
    if (x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER]) || x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER])
 /* The arg pointer varies if it is not a fixed register.  */
 || (x == arg_pointer_rtx((this_target_rtl->x_global_rtl)[GR_ARG_POINTER]) && fixed_regs(this_target_hard_regs->x_fixed_regs)[ARG_POINTER_REGNUM16]))
return 0;
    /* ??? When call-clobbered, the value is stable modulo the restore
that must happen after a call.  This currently screws up local-alloc
into believing that the restore is not needed.  */
    if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED0 && x == pic_offset_table_rtx(this_target_rtl->x_pic_offset_table_rtx))
return 0;
    return 1;

  case ASM_OPERANDS:
    if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 237, __FUNCTION__); _rtx; })->volatil))
return 1;

    /* Fall through.  */

  default:
    break;
  }

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  if (fmt[i] == 'e')
    {
if (rtx_unstable_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
 return 1;
    }
  else if (fmt[i] == 'E')
    {
int j;
for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
 if (rtx_unstable_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
   return 1;
    }

return 0;
262}

264/* Return 1 if X has a value that can vary even between two
 executions of the program.  0 means X can be compared reliably
 against certain constants or near-constants.
 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
 zero, we are slightly more conservative.
 The frame pointer and the arg pointer are considered constant.  */

271bool
272rtx_varies_p (const_rtx x, bool for_alias)
273{
RTX_CODEenum rtx_code code;
int i;
const char *fmt;

if (!x)
  return 0;

code = GET_CODE (x)((enum rtx_code) (x)->code);
switch (code)
  {
  case MEM:
    return !MEM_READONLY_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 285, __FUNCTION__); _rtx; })->unchanging) || rtx_varies_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), for_alias);

  case CONST:
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case SYMBOL_REF:
  case LABEL_REF:
    return 0;

  case REG:
    /* Note that we have to test for the actual rtx used for the frame
and arg pointers and not just the register number in case we have
eliminated the frame and/or arg pointer and are using it
for pseudos.  */
    if (x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER]) || x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER])
 /* The arg pointer varies if it is not a fixed register.  */
 || (x == arg_pointer_rtx((this_target_rtl->x_global_rtl)[GR_ARG_POINTER]) && fixed_regs(this_target_hard_regs->x_fixed_regs)[ARG_POINTER_REGNUM16]))
return 0;
    if (x == pic_offset_table_rtx(this_target_rtl->x_pic_offset_table_rtx)
 /* ??? When call-clobbered, the value is stable modulo the restore
    that must happen after a call.  This currently screws up
    local-alloc into believing that the restore is not needed, so we
    must return 0 only if we are called from alias analysis.  */
 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED0 || for_alias))
return 0;
    return 1;

  case LO_SUM:
    /* The operand 0 of a LO_SUM is considered constant
(in fact it is related specifically to operand 1)
during alias analysis.  */
    return (! for_alias && rtx_varies_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), for_alias))
    || rtx_varies_p (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), for_alias);

  case ASM_OPERANDS:
    if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 319, __FUNCTION__); _rtx; })->volatil))
return 1;

    /* Fall through.  */

  default:
    break;
  }

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  if (fmt[i] == 'e')
    {
if (rtx_varies_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), for_alias))
 return 1;
    }
  else if (fmt[i] == 'E')
    {
int j;
for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
 if (rtx_varies_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), for_alias))
   return 1;
    }

return 0;
344}

346/* Compute an approximation for the offset between the register
 FROM and TO for the current function, as it was at the start
 of the routine.  */

350static poly_int64
351get_initial_register_offset (int from, int to)
352{
static const struct elim_table_t
{
  const int from;
  const int to;
} table[] = ELIMINABLE_REGS{{ 16, 7}, { 16, 6}, { 19, 7}, { 19, 6}};
poly_int64 offset1, offset2;
unsigned int i, j;

if (to == from)
  return 0;

/* It is not safe to call INITIAL_ELIMINATION_OFFSET before the epilogue
   is completed, but we need to give at least an estimate for the stack
   pointer based on the frame size.  */
if (!epilogue_completed)
  {
    offset1 = crtl(&x_rtl)->outgoing_args_size + get_frame_size ();
370#if !STACK_GROWS_DOWNWARD1
    offset1 = - offset1;
372#endif
    if (to == STACK_POINTER_REGNUM7)
return offset1;
    else if (from == STACK_POINTER_REGNUM7)
return - offset1;
    else
return 0;
   }

for (i = 0; i < ARRAY_SIZE (table)(sizeof (table) / sizeof ((table)[0])); i++)
    if (table[i].from == from)
{
 if (table[i].to == to)
   {
     INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
			  offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)));
     return offset1;
   }
 for (j = 0; j < ARRAY_SIZE (table)(sizeof (table) / sizeof ((table)[0])); j++)
   {
     if (table[j].to == to
  && table[j].from == table[i].to)
{
  INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
			      offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)));
  INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
			      offset2)((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)));
  return offset1 + offset2;
}
     if (table[j].from == to
  && table[j].to == table[i].to)
{
  INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
			      offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)));
  INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
			      offset2)((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)));
  return offset1 - offset2;
}
   }
}
    else if (table[i].to == from)
{
 if (table[i].from == to)
   {
     INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
			  offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)));
     return - offset1;
   }
 for (j = 0; j < ARRAY_SIZE (table)(sizeof (table) / sizeof ((table)[0])); j++)
   {
     if (table[j].to == to
  && table[j].from == table[i].from)
{
  INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
			      offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)));
  INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
			      offset2)((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)));
  return - offset1 + offset2;
}
     if (table[j].from == to
  && table[j].to == table[i].from)
{
  INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
			      offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)));
  INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
			      offset2)((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)));
  return - offset1 - offset2;
}
   }
}

/* If the requested register combination was not found,
   try a different more simple combination.  */
if (from == ARG_POINTER_REGNUM16)
  return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM6, to);
else if (to == ARG_POINTER_REGNUM16)
  return get_initial_register_offset (from, HARD_FRAME_POINTER_REGNUM6);
else if (from == HARD_FRAME_POINTER_REGNUM6)
  return get_initial_register_offset (FRAME_POINTER_REGNUM19, to);
else if (to == HARD_FRAME_POINTER_REGNUM6)
  return get_initial_register_offset (from, FRAME_POINTER_REGNUM19);
else
  return 0;
455}

457/* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
 bytes can cause a trap.  MODE is the mode of the MEM (not that of X) and
 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
 references on strict alignment machines.  */

462static int
463rtx_addr_can_trap_p_1 (const_rtx x, poly_int64 offset, poly_int64 size,
       machine_mode mode, bool unaligned_mems)
465{
enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
gcc_checking_assert (mode == BLKmode((void)(!(mode == ((void) 0, E_BLKmode) || mode == ((void) 0,
 E_VOIDmode) || known_size_p (size)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 469, __FUNCTION__), 0 : 0))
       || mode == VOIDmode((void)(!(mode == ((void) 0, E_BLKmode) || mode == ((void) 0,
 E_VOIDmode) || known_size_p (size)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 469, __FUNCTION__), 0 : 0))
       || known_size_p (size))((void)(!(mode == ((void) 0, E_BLKmode) || mode == ((void) 0,
 E_VOIDmode) || known_size_p (size)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 469, __FUNCTION__), 0 : 0));
poly_int64 const_x1;

/* The offset must be a multiple of the mode size if we are considering
   unaligned memory references on strict alignment machines.  */
if (STRICT_ALIGNMENT0
    && unaligned_mems
    && mode != BLKmode((void) 0, E_BLKmode)
    && mode != VOIDmode((void) 0, E_VOIDmode))
  {
    poly_int64 actual_offset = offset;

481#ifdef SPARC_STACK_BOUNDARY_HACK
    /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
    the real alignment of %sp.  However, when it does this, the
    alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY.  */
    if (SPARC_STACK_BOUNDARY_HACK
 && (x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]) || x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER])))
actual_offset -= STACK_POINTER_OFFSET0;
488#endif

    if (!multiple_p (actual_offset, GET_MODE_SIZE (mode)))
return 1;
  }

switch (code)
  {
  case SYMBOL_REF:
    if (SYMBOL_REF_WEAK (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("SYMBOL_REF_WEAK", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 497, __FUNCTION__); _rtx; })->return_val))
return 1;
    if (!CONSTANT_POOL_ADDRESS_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("CONSTANT_POOL_ADDRESS_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 499, __FUNCTION__); _rtx; })->unchanging) && !SYMBOL_REF_FUNCTION_P (x)(((__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((
enum rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("SYMBOL_REF_FLAGS", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 499, __FUNCTION__); _rtx; }) ->u2.symbol_ref_flags) &
 (1 << 0)) != 0))
{
 tree decl;
 poly_int64 decl_size;

 if (maybe_lt (offset, 0))
   return 1;
 if (!known_size_p (size))
   return maybe_ne (offset, 0);

 /* If the size of the access or of the symbol is unknown,
    assume the worst.  */
 decl = SYMBOL_REF_DECL (x)((__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("CONSTANT_POOL_ADDRESS_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 511, __FUNCTION__); _rtx; })->unchanging) ? nullptr : ((
((x))->u.fld[1]).rt_tree));

 /* Else check that the access is in bounds.  TODO: restructure
    expr_size/tree_expr_size/int_expr_size and just use the latter.  */
 if (!decl)
   decl_size = -1;
 else if (DECL_P (decl)(tree_code_type_tmpl <0>::tree_code_type[(int) (((enum tree_code
) (decl)->base.code))] == tcc_declaration) && DECL_SIZE_UNIT (decl)((contains_struct_check ((decl), (TS_DECL_COMMON), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 517, __FUNCTION__))->decl_common.size_unit))
   {
     if (!poly_int_tree_p (DECL_SIZE_UNIT (decl)((contains_struct_check ((decl), (TS_DECL_COMMON), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 519, __FUNCTION__))->decl_common.size_unit), &decl_size))
decl_size = -1;
   }
 else if (TREE_CODE (decl)((enum tree_code) (decl)->base.code) == STRING_CST)
   decl_size = TREE_STRING_LENGTH (decl)((tree_check ((decl), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 523, __FUNCTION__, (STRING_CST)))->string.length);
 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl))((tree_class_check ((((contains_struct_check ((decl), (TS_TYPED
), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 524, __FUNCTION__))->typed.type)), (tcc_type), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 524, __FUNCTION__))->type_common.size_unit))
   decl_size = int_size_in_bytes (TREE_TYPE (decl)((contains_struct_check ((decl), (TS_TYPED), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 525, __FUNCTION__))->typed.type));
 else
   decl_size = -1;

 return (!known_size_p (decl_size) || known_eq (decl_size, 0)(!maybe_ne (decl_size, 0))
  ? maybe_ne (offset, 0)
  : !known_subrange_p (offset, size, 0, decl_size));
      }

    return 0;

  case LABEL_REF:
    return 0;

  case REG:
    /* Stack references are assumed not to trap, but we need to deal with
nonsensical offsets.  */
    if (x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER]) || x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER])
|| x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
/* The arg pointer varies if it is not a fixed register.  */
|| (x == arg_pointer_rtx((this_target_rtl->x_global_rtl)[GR_ARG_POINTER]) && fixed_regs(this_target_hard_regs->x_fixed_regs)[ARG_POINTER_REGNUM16]))
{
547#ifdef RED_ZONE_SIZE128
 poly_int64 red_zone_size = RED_ZONE_SIZE128;
549#else
 poly_int64 red_zone_size = 0;
551#endif
 poly_int64 stack_boundary = PREFERRED_STACK_BOUNDARYix86_preferred_stack_boundary / BITS_PER_UNIT(8);
 poly_int64 low_bound, high_bound;

 if (!known_size_p (size))
   return 1;

 if (x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER]))
   {
     if (FRAME_GROWS_DOWNWARD1)
{
  high_bound = targetm.starting_frame_offset ();
  low_bound  = high_bound - get_frame_size ();
}
     else
{
  low_bound  = targetm.starting_frame_offset ();
  high_bound = low_bound + get_frame_size ();
}
   }
 else if (x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER]))
   {
     poly_int64 sp_offset
= get_initial_register_offset (STACK_POINTER_REGNUM7,
			       HARD_FRAME_POINTER_REGNUM6);
     poly_int64 ap_offset
= get_initial_register_offset (ARG_POINTER_REGNUM16,
			       HARD_FRAME_POINTER_REGNUM6);

580#if STACK_GROWS_DOWNWARD1
     low_bound  = sp_offset - red_zone_size - stack_boundary;
     high_bound = ap_offset
	   + FIRST_PARM_OFFSET (current_function_decl)0
584#if !ARGS_GROW_DOWNWARD0
	   + crtl(&x_rtl)->args.size
586#endif
	   + stack_boundary;
588#else
     high_bound = sp_offset + red_zone_size + stack_boundary;
     low_bound  = ap_offset
	   + FIRST_PARM_OFFSET (current_function_decl)0
592#if ARGS_GROW_DOWNWARD0
	   - crtl(&x_rtl)->args.size
594#endif
	   - stack_boundary;
596#endif
   }
 else if (x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
   {
     poly_int64 ap_offset
= get_initial_register_offset (ARG_POINTER_REGNUM16,
			       STACK_POINTER_REGNUM7);

604#if STACK_GROWS_DOWNWARD1
     low_bound  = - red_zone_size - stack_boundary;
     high_bound = ap_offset
	   + FIRST_PARM_OFFSET (current_function_decl)0
608#if !ARGS_GROW_DOWNWARD0
	   + crtl(&x_rtl)->args.size
610#endif
	   + stack_boundary;
612#else
     high_bound = red_zone_size + stack_boundary;
     low_bound  = ap_offset
	   + FIRST_PARM_OFFSET (current_function_decl)0
616#if ARGS_GROW_DOWNWARD0
	   - crtl(&x_rtl)->args.size
618#endif
	   - stack_boundary;
620#endif
   }
 else
   {
     /* We assume that accesses are safe to at least the
 next stack boundary.
 Examples are varargs and __builtin_return_address.  */
627#if ARGS_GROW_DOWNWARD0
     high_bound = FIRST_PARM_OFFSET (current_function_decl)0
	   + stack_boundary;
     low_bound  = FIRST_PARM_OFFSET (current_function_decl)0
	   - crtl(&x_rtl)->args.size - stack_boundary;
632#else
     low_bound  = FIRST_PARM_OFFSET (current_function_decl)0
	   - stack_boundary;
     high_bound = FIRST_PARM_OFFSET (current_function_decl)0
	   + crtl(&x_rtl)->args.size + stack_boundary;
637#endif
   }

 if (known_ge (offset, low_bound)(!maybe_lt (offset, low_bound))
     && known_le (offset, high_bound - size)(!maybe_lt (high_bound - size, offset)))
   return 0;
 return 1;
}
    /* All of the virtual frame registers are stack references.  */
    if (REGNO (x)(rhs_regno(x)) >= FIRST_VIRTUAL_REGISTER(76)
 && REGNO (x)(rhs_regno(x)) <= LAST_VIRTUAL_REGISTER(((76)) + 5))
return 0;
    return 1;

  case CONST:
    return rtx_addr_can_trap_p_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), offset, size,
		    mode, unaligned_mems);

  case PLUS:
    /* An address is assumed not to trap if:
- it is the pic register plus a const unspec without offset.  */
    if (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) == pic_offset_table_rtx(this_target_rtl->x_pic_offset_table_rtx)
 && GET_CODE (XEXP (x, 1))((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST
 && GET_CODE (XEXP (XEXP (x, 1), 0))((enum rtx_code) (((((((x)->u.fld[1]).rt_rtx))->u.fld[0
]).rt_rtx))->code) == UNSPEC
 && known_eq (offset, 0)(!maybe_ne (offset, 0)))
return 0;

    /* - or it is an address that can't trap plus a constant integer.  */
    if (poly_int_rtx_p (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), &const_x1)
 && !rtx_addr_can_trap_p_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), offset + const_x1,
		     size, mode, unaligned_mems))
return 0;

    return 1;

  case LO_SUM:
  case PRE_MODIFY:
    return rtx_addr_can_trap_p_1 (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), offset, size,
		    mode, unaligned_mems);

  case PRE_DEC:
  case PRE_INC:
  case POST_DEC:
  case POST_INC:
  case POST_MODIFY:
    return rtx_addr_can_trap_p_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), offset, size,
		    mode, unaligned_mems);

  default:
    break;
  }

/* If it isn't one of the case above, it can cause a trap.  */
return 1;
691}

693/* Return nonzero if the use of X as an address in a MEM can cause a trap.  */

695int
696rtx_addr_can_trap_p (const_rtx x)
697{
return rtx_addr_can_trap_p_1 (x, 0, -1, BLKmode((void) 0, E_BLKmode), false);
699}

701/* Return true if X contains a MEM subrtx.  */

703bool
704contains_mem_rtx_p (rtx x)
705{
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, ALL)for (subrtx_iterator iter (array, x, rtx_all_subrtx_bounds); !
iter.at_end (); iter.next ())
  if (MEM_P (*iter)(((enum rtx_code) (*iter)->code) == MEM))
    return true;

return false;
712}

714/* Return true if X is an address that is known to not be zero.  */

716bool
717nonzero_address_p (const_rtx x)
718{
const enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);

switch (code)
  {
  case SYMBOL_REF:
    return flag_delete_null_pointer_checksglobal_options.x_flag_delete_null_pointer_checks && !SYMBOL_REF_WEAK (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("SYMBOL_REF_WEAK", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 724, __FUNCTION__); _rtx; })->return_val);

  case LABEL_REF:
    return true;

  case REG:
    /* As in rtx_varies_p, we have to use the actual rtx, not reg number.  */
    if (x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER]) || x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER])
 || x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
 || (x == arg_pointer_rtx((this_target_rtl->x_global_rtl)[GR_ARG_POINTER]) && fixed_regs(this_target_hard_regs->x_fixed_regs)[ARG_POINTER_REGNUM16]))
return true;
    /* All of the virtual frame registers are stack references.  */
    if (REGNO (x)(rhs_regno(x)) >= FIRST_VIRTUAL_REGISTER(76)
 && REGNO (x)(rhs_regno(x)) <= LAST_VIRTUAL_REGISTER(((76)) + 5))
return true;
    return false;

  case CONST:
    return nonzero_address_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));

  case PLUS:
    /* Handle PIC references.  */
    if (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) == pic_offset_table_rtx(this_target_rtl->x_pic_offset_table_rtx)
      && CONSTANT_P (XEXP (x, 1))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
return true;
    return false;

  case PRE_MODIFY:
    /* Similar to the above; allow positive offsets.  Further, since
auto-inc is only allowed in memories, the register must be a
pointer.  */
    if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) > 0)
return true;
    return nonzero_address_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));

  case PRE_INC:
    /* Similarly.  Further, the offset is always positive.  */
    return true;

  case PRE_DEC:
  case POST_DEC:
  case POST_INC:
  case POST_MODIFY:
    return nonzero_address_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));

  case LO_SUM:
    return nonzero_address_p (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));

  default:
    break;
  }

/* If it isn't one of the case above, might be zero.  */
return false;
779}

781/* Return 1 if X refers to a memory location whose address
 cannot be compared reliably with constant addresses,
 or if X refers to a BLKmode memory object.
 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
 zero, we are slightly more conservative.  */

787bool
788rtx_addr_varies_p (const_rtx x, bool for_alias)
789{
enum rtx_code code;
int i;
const char *fmt;

if (x == 0)
  return 0;

code = GET_CODE (x)((enum rtx_code) (x)->code);
if (code == MEM)
  return GET_MODE (x)((machine_mode) (x)->mode) == BLKmode((void) 0, E_BLKmode) || rtx_varies_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), for_alias);

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  if (fmt[i] == 'e')
    {
if (rtx_addr_varies_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), for_alias))
 return 1;
    }
  else if (fmt[i] == 'E')
    {
int j;
for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
 if (rtx_addr_varies_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), for_alias))
   return 1;
    }
return 0;
816}
817
818/* Return the CALL in X if there is one.  */

820rtx
821get_call_rtx_from (const rtx_insn *insn)
822{
rtx x = PATTERN (insn);
if (GET_CODE (x)((enum rtx_code) (x)->code) == PARALLEL)
  x = XVECEXP (x, 0, 0)(((((x)->u.fld[0]).rt_rtvec))->elem[0]);
if (GET_CODE (x)((enum rtx_code) (x)->code) == SET)
  x = SET_SRC (x)(((x)->u.fld[1]).rt_rtx);
if (GET_CODE (x)((enum rtx_code) (x)->code) == CALL && MEM_P (XEXP (x, 0))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == MEM
))
  return x;
return NULL_RTX(rtx) 0;
831}

833/* Get the declaration of the function called by INSN.  */

835tree
836get_call_fndecl (const rtx_insn *insn)
837{
rtx note, datum;

note = find_reg_note (insn, REG_CALL_DECL, NULL_RTX(rtx) 0);
if (note == NULL_RTX(rtx) 0)
  return NULL_TREE(tree) nullptr;

datum = XEXP (note, 0)(((note)->u.fld[0]).rt_rtx);
if (datum != NULL_RTX(rtx) 0)
  return SYMBOL_REF_DECL (datum)((__extension__ ({ __typeof ((datum)) const _rtx = ((datum));
 if (((enum rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("CONSTANT_POOL_ADDRESS_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 846, __FUNCTION__); _rtx; })->unchanging) ? nullptr : ((
((datum))->u.fld[1]).rt_tree));

return NULL_TREE(tree) nullptr;
849}
850
851/* Return the value of the integer term in X, if one is apparent;
 otherwise return 0.
 Only obvious integer terms are detected.
 This is used in cse.cc with the `related_value' field.  */

856HOST_WIDE_INTlong
857get_integer_term (const_rtx x)
858{
if (GET_CODE (x)((enum rtx_code) (x)->code) == CONST)
  x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);

if (GET_CODE (x)((enum rtx_code) (x)->code) == MINUS
    && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
))
  return - INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]);
if (GET_CODE (x)((enum rtx_code) (x)->code) == PLUS
    && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
))
  return INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]);
return 0;
869}

871/* If X is a constant, return the value sans apparent integer term;
 otherwise return 0.
 Only obvious integer terms are detected.  */

875rtx
876get_related_value (const_rtx x)
877{
if (GET_CODE (x)((enum rtx_code) (x)->code) != CONST)
  return 0;
x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
if (GET_CODE (x)((enum rtx_code) (x)->code) == PLUS
    && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
))
  return XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
else if (GET_CODE (x)((enum rtx_code) (x)->code) == MINUS
  && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
))
  return XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
return 0;
888}
889
890/* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
 to somewhere in the same object or object_block as SYMBOL.  */

893bool
894offset_within_block_p (const_rtx symbol, HOST_WIDE_INTlong offset)
895{
tree decl;

if (GET_CODE (symbol)((enum rtx_code) (symbol)->code) != SYMBOL_REF)
  return false;

if (offset == 0)
  return true;

if (offset > 0)
  {
    if (CONSTANT_POOL_ADDRESS_P (symbol)(__extension__ ({ __typeof ((symbol)) const _rtx = ((symbol))
; if (((enum rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("CONSTANT_POOL_ADDRESS_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 906, __FUNCTION__); _rtx; })->unchanging)
 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
return true;

    decl = SYMBOL_REF_DECL (symbol)((__extension__ ({ __typeof ((symbol)) const _rtx = ((symbol)
); if (((enum rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("CONSTANT_POOL_ADDRESS_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 910, __FUNCTION__); _rtx; })->unchanging) ? nullptr : ((
((symbol))->u.fld[1]).rt_tree));
    if (decl && offset < int_size_in_bytes (TREE_TYPE (decl)((contains_struct_check ((decl), (TS_TYPED), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 911, __FUNCTION__))->typed.type)))
return true;
  }

if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol)(((__extension__ ({ __typeof ((symbol)) const _rtx = ((symbol
)); if (((enum rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("SYMBOL_REF_FLAGS", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 915, __FUNCTION__); _rtx; }) ->u2.symbol_ref_flags) &
 (1 << 7)) != 0)
    && SYMBOL_REF_BLOCK (symbol)((&(symbol)->u.block_sym)->block)
    && SYMBOL_REF_BLOCK_OFFSET (symbol)((&(symbol)->u.block_sym)->offset) >= 0
    && ((unsigned HOST_WIDE_INTlong) offset + SYMBOL_REF_BLOCK_OFFSET (symbol)((&(symbol)->u.block_sym)->offset)
 < (unsigned HOST_WIDE_INTlong) SYMBOL_REF_BLOCK (symbol)((&(symbol)->u.block_sym)->block)->size))
  return true;

return false;
923}

925/* Split X into a base and a constant offset, storing them in *BASE_OUT
 and *OFFSET_OUT respectively.  */

928void
929split_const (rtx x, rtx *base_out, rtx *offset_out)
930{
if (GET_CODE (x)((enum rtx_code) (x)->code) == CONST)
  {
    x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
    if (GET_CODE (x)((enum rtx_code) (x)->code) == PLUS && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
))
{
 *base_out = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
 *offset_out = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);
 return;
}
  }
*base_out = x;
*offset_out = const0_rtx(const_int_rtx[64]);
943}

945/* Express integer value X as some value Y plus a polynomial offset,
 where Y is either const0_rtx, X or something within X (as opposed
 to a new rtx).  Return the Y and store the offset in *OFFSET_OUT.  */

949rtx
950strip_offset (rtx x, poly_int64_pod *offset_out)
951{
rtx base = const0_rtx(const_int_rtx[64]);
rtx test = x;
if (GET_CODE (test)((enum rtx_code) (test)->code) == CONST)
  test = XEXP (test, 0)(((test)->u.fld[0]).rt_rtx);
if (GET_CODE (test)((enum rtx_code) (test)->code) == PLUS)
  {
    base = XEXP (test, 0)(((test)->u.fld[0]).rt_rtx);
    test = XEXP (test, 1)(((test)->u.fld[1]).rt_rtx);
  }
if (poly_int_rtx_p (test, offset_out))
  return base;
*offset_out = 0;
return x;
965}

967/* Return the argument size in REG_ARGS_SIZE note X.  */

969poly_int64
970get_args_size (const_rtx x)
971{
gcc_checking_assert (REG_NOTE_KIND (x) == REG_ARGS_SIZE)((void)(!(((enum reg_note) ((machine_mode) (x)->mode)) == REG_ARGS_SIZE
) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 972, __FUNCTION__), 0 : 0));
return rtx_to_poly_int64 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));
974}
975
976/* Return the number of places FIND appears within X.  If COUNT_DEST is
 zero, we do not count occurrences inside the destination of a SET.  */

979int
980count_occurrences (const_rtx x, const_rtx find, int count_dest)
981{
int i, j;
enum rtx_code code;
const char *format_ptr;
int count;

if (x == find)
  return 1;

code = GET_CODE (x)((enum rtx_code) (x)->code);

switch (code)
  {
  case REG:
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case SYMBOL_REF:
  case CODE_LABEL:
  case PC:
    return 0;

  case EXPR_LIST:
    count = count_occurrences (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), find, count_dest);
    if (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
count += count_occurrences (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), find, count_dest);
    return count;

  case MEM:
    if (MEM_P (find)(((enum rtx_code) (find)->code) == MEM) && rtx_equal_p (x, find))
return 1;
    break;

  case SET:
    if (SET_DEST (x)(((x)->u.fld[0]).rt_rtx) == find && ! count_dest)
return count_occurrences (SET_SRC (x)(((x)->u.fld[1]).rt_rtx), find, count_dest);
    break;

  default:
    break;
  }

format_ptr = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
count = 0;

for (i = 0; i < GET_RTX_LENGTH (code)(rtx_length[(int) (code)]); i++)
  {
    switch (*format_ptr++)
{
case 'e':
 count += count_occurrences (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), find, count_dest);
 break;

case 'E':
 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
   count += count_occurrences (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), find, count_dest);
 break;
}
  }
return count;
1039}

1041
1042/* Return TRUE if OP is a register or subreg of a register that
 holds an unsigned quantity.  Otherwise, return FALSE.  */

1045bool
1046unsigned_reg_p (rtx op)
1047{
if (REG_P (op)(((enum rtx_code) (op)->code) == REG)
    && REG_EXPR (op)(((&(op)->u.reg)->attrs) == 0 ? 0 : ((&(op)->
u.reg)->attrs)->decl)
    && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op)))((tree_class_check ((((contains_struct_check (((((&(op)->
u.reg)->attrs) == 0 ? 0 : ((&(op)->u.reg)->attrs
)->decl)), (TS_TYPED), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 1050, __FUNCTION__))->typed.type)), (tcc_type), "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 1050, __FUNCTION__))->base.u.bits.unsigned_flag))
  return true;

if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG
    && SUBREG_PROMOTED_SIGN (op)((__extension__ ({ __typeof ((op)) const _rtx = ((op)); if ((
(enum rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag
 ("SUBREG_PROMOTED_SIGN", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 1054, __FUNCTION__); _rtx; })->volatil) ? 1 : (op)->unchanging
 - 1))
  return true;

return false;
1058}

1060
1061/* Nonzero if register REG appears somewhere within IN.
 Also works if REG is not a register; in this case it checks
 for a subexpression of IN that is Lisp "equal" to REG.  */

1065int
1066reg_mentioned_p (const_rtx reg, const_rtx in)
1067{
const char *fmt;
int i;
enum rtx_code code;

if (in == 0)
  return 0;

if (reg == in)
  return 1;

if (GET_CODE (in)((enum rtx_code) (in)->code) == LABEL_REF)
  return reg == label_ref_label (in);

code = GET_CODE (in)((enum rtx_code) (in)->code);

switch (code)
  {
    /* Compare registers by number.  */
  case REG:
    return REG_P (reg)(((enum rtx_code) (reg)->code) == REG) && REGNO (in)(rhs_regno(in)) == REGNO (reg)(rhs_regno(reg));

    /* These codes have no constituent expressions
and are unique.  */
  case SCRATCH:
  case PC:
    return 0;

  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
    /* These are kept unique for a given value.  */
    return 0;

  default:
    break;
  }

if (GET_CODE (reg)((enum rtx_code) (reg)->code) == code && rtx_equal_p (reg, in))
  return 1;

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);

for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'E')
{
 int j;
 for (j = XVECLEN (in, i)(((((in)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
   if (reg_mentioned_p (reg, XVECEXP (in, i, j)(((((in)->u.fld[i]).rt_rtvec))->elem[j])))
     return 1;
}
    else if (fmt[i] == 'e'
      && reg_mentioned_p (reg, XEXP (in, i)(((in)->u.fld[i]).rt_rtx)))
return 1;
  }
return 0;
1122}
1123
1124/* Return 1 if in between BEG and END, exclusive of BEG and END, there is
 no CODE_LABEL insn.  */

1127int
1128no_labels_between_p (const rtx_insn *beg, const rtx_insn *end)
1129{
rtx_insn *p;
if (beg == end)
  return 0;
for (p = NEXT_INSN (beg); p != end; p = NEXT_INSN (p))
  if (LABEL_P (p)(((enum rtx_code) (p)->code) == CODE_LABEL))
    return 0;
return 1;
1137}

1139/* Nonzero if register REG is used in an insn between
 FROM_INSN and TO_INSN (exclusive of those two).  */

1142int
1143reg_used_between_p (const_rtx reg, const rtx_insn *from_insn,
    const rtx_insn *to_insn)
1145{
rtx_insn *insn;

if (from_insn == to_insn)
  return 0;

for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn))
  if (NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN))
&& (reg_overlap_mentioned_p (reg, PATTERN (insn))
  || (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN) && find_reg_fusage (insn, USE, reg))))
    return 1;
return 0;
1157}
1158
1159/* Nonzero if the old value of X, a register, is referenced in BODY.  If X
 is entirely replaced by a new value and the only use is as a SET_DEST,
 we do not consider it a reference.  */

1163int
1164reg_referenced_p (const_rtx x, const_rtx body)
1165{
int i;

switch (GET_CODE (body)((enum rtx_code) (body)->code))
  {
  case SET:
    if (reg_overlap_mentioned_p (x, SET_SRC (body)(((body)->u.fld[1]).rt_rtx)))
return 1;

    /* If the destination is anything other than PC, a REG or a SUBREG
of a REG that occupies all of the REG, the insn references X if
it is mentioned in the destination.  */
    if (GET_CODE (SET_DEST (body))((enum rtx_code) ((((body)->u.fld[0]).rt_rtx))->code) != PC
 && !REG_P (SET_DEST (body))(((enum rtx_code) ((((body)->u.fld[0]).rt_rtx))->code) ==
 REG)
 && ! (GET_CODE (SET_DEST (body))((enum rtx_code) ((((body)->u.fld[0]).rt_rtx))->code) == SUBREG
&& REG_P (SUBREG_REG (SET_DEST (body)))(((enum rtx_code) (((((((body)->u.fld[0]).rt_rtx))->u.fld
[0]).rt_rtx))->code) == REG)
&& !read_modify_subreg_p (SET_DEST (body)(((body)->u.fld[0]).rt_rtx)))
 && reg_overlap_mentioned_p (x, SET_DEST (body)(((body)->u.fld[0]).rt_rtx)))
return 1;
    return 0;

  case ASM_OPERANDS:
    for (i = ASM_OPERANDS_INPUT_LENGTH (body)(((((body)->u.fld[3]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
if (reg_overlap_mentioned_p (x, ASM_OPERANDS_INPUT (body, i)(((((body)->u.fld[3]).rt_rtvec))->elem[i])))
 return 1;
    return 0;

  case CALL:
  case USE:
  case IF_THEN_ELSE:
    return reg_overlap_mentioned_p (x, body);

  case TRAP_IF:
    return reg_overlap_mentioned_p (x, TRAP_CONDITION (body)(((body)->u.fld[0]).rt_rtx));

  case PREFETCH:
    return reg_overlap_mentioned_p (x, XEXP (body, 0)(((body)->u.fld[0]).rt_rtx));

  case UNSPEC:
  case UNSPEC_VOLATILE:
    for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
if (reg_overlap_mentioned_p (x, XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i])))
 return 1;
    return 0;

  case PARALLEL:
    for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
if (reg_referenced_p (x, XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i])))
 return 1;
    return 0;

  case CLOBBER:
    if (MEM_P (XEXP (body, 0))(((enum rtx_code) ((((body)->u.fld[0]).rt_rtx))->code) ==
 MEM))
if (reg_overlap_mentioned_p (x, XEXP (XEXP (body, 0), 0)((((((body)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx)))
 return 1;
    return 0;

  case COND_EXEC:
    if (reg_overlap_mentioned_p (x, COND_EXEC_TEST (body)(((body)->u.fld[0]).rt_rtx)))
return 1;
    return reg_referenced_p (x, COND_EXEC_CODE (body)(((body)->u.fld[1]).rt_rtx));

  default:
    return 0;
  }
1230}
1231
1232/* Nonzero if register REG is set or clobbered in an insn between
 FROM_INSN and TO_INSN (exclusive of those two).  */

1235int
1236reg_set_between_p (const_rtx reg, const rtx_insn *from_insn,
   const rtx_insn *to_insn)
1238{
const rtx_insn *insn;

if (from_insn == to_insn)
  return 0;

for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn))
  if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)) && reg_set_p (reg, insn))
    return 1;
return 0;
1248}

1250/* Return true if REG is set or clobbered inside INSN.  */

1252int
1253reg_set_p (const_rtx reg, const_rtx insn)
1254{
/* After delay slot handling, call and branch insns might be in a
   sequence.  Check all the elements there.  */
if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)) && GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == SEQUENCE)
  {
    for (int i = 0; i < XVECLEN (PATTERN (insn), 0)(((((PATTERN (insn))->u.fld[0]).rt_rtvec))->num_elem); ++i)
if (reg_set_p (reg, XVECEXP (PATTERN (insn), 0, i)(((((PATTERN (insn))->u.fld[0]).rt_rtvec))->elem[i])))
 return true;

    return false;
  }

/* We can be passed an insn or part of one.  If we are passed an insn,
   check if a side-effect of the insn clobbers REG.  */
if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN))
    && (FIND_REG_INC_NOTE (insn, reg)0
 || (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN)
     && ((REG_P (reg)(((enum rtx_code) (reg)->code) == REG)
   && REGNO (reg)(rhs_regno(reg)) < FIRST_PSEUDO_REGISTER76
   && (insn_callee_abi (as_a<const rtx_insn *> (insn))
       .clobbers_reg_p (GET_MODE (reg)((machine_mode) (reg)->mode), REGNO (reg)(rhs_regno(reg)))))
  || MEM_P (reg)(((enum rtx_code) (reg)->code) == MEM)
  || find_reg_fusage (insn, CLOBBER, reg)))))
  return true;

/* There are no REG_INC notes for SP autoinc.  */
if (reg == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]) && INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
  {
    subrtx_var_iterator::array_type array;
    FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (insn), NONCONST)for (subrtx_var_iterator iter (array, PATTERN (insn), rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
{
 rtx mem = *iter;
 if (mem
     && MEM_P (mem)(((enum rtx_code) (mem)->code) == MEM)
     && GET_RTX_CLASS (GET_CODE (XEXP (mem, 0)))(rtx_class[(int) (((enum rtx_code) ((((mem)->u.fld[0]).rt_rtx
))->code))]) == RTX_AUTOINC)
   {
     if (XEXP (XEXP (mem, 0), 0)((((((mem)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
return true;
     iter.skip_subrtxes ();
   }
}
  }

return set_of (reg, insn) != NULL_RTX(rtx) 0;
1298}

1300/* Similar to reg_set_between_p, but check all registers in X.  Return 0
 only if none of them are modified between START and END.  Return 1 if
 X contains a MEM; this routine does use memory aliasing.  */

1304int
1305modified_between_p (const_rtx x, const rtx_insn *start, const rtx_insn *end)
1306{
const enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
const char *fmt;
int i, j;
rtx_insn *insn;

if (start == end)
  return 0;

switch (code)
  {
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case CONST:
  case SYMBOL_REF:
  case LABEL_REF:
    return 0;

  case PC:
    return 1;

  case MEM:
    if (modified_between_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), start, end))
return 1;
    if (MEM_READONLY_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 1329, __FUNCTION__); _rtx; })->unchanging))
return 0;
    for (insn = NEXT_INSN (start); insn != end; insn = NEXT_INSN (insn))
if (memory_modified_in_insn_p (x, insn))
 return 1;
    return 0;

  case REG:
    return reg_set_between_p (x, start, end);

  default:
    break;
  }

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'e' && modified_between_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), start, end))
return 1;

    else if (fmt[i] == 'E')
for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
 if (modified_between_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), start, end))
   return 1;
  }

return 0;
1356}

1358/* Similar to reg_set_p, but check all registers in X.  Return 0 only if none
 of them are modified in INSN.  Return 1 if X contains a MEM; this routine
 does use memory aliasing.  */

1362int
1363modified_in_p (const_rtx x, const_rtx insn)
1364{
const enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
const char *fmt;
int i, j;

switch (code)
  {
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case CONST:
  case SYMBOL_REF:
  case LABEL_REF:
    return 0;

  case PC:
    return 1;

  case MEM:
    if (modified_in_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), insn))
return 1;
    if (MEM_READONLY_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 1383, __FUNCTION__); _rtx; })->unchanging))
return 0;
    if (memory_modified_in_insn_p (x, insn))
return 1;
    return 0;

  case REG:
    return reg_set_p (x, insn);

  default:
    break;
  }

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'e' && modified_in_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), insn))
return 1;

    else if (fmt[i] == 'E')
for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
 if (modified_in_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), insn))
   return 1;
  }

return 0;
1409}

1411/* Return true if X is a SUBREG and if storing a value to X would
 preserve some of its SUBREG_REG.  For example, on a normal 32-bit
 target, using a SUBREG to store to one half of a DImode REG would
 preserve the other half.  */

1416bool
1417read_modify_subreg_p (const_rtx x)
1418{
if (GET_CODE (x)((enum rtx_code) (x)->code) != SUBREG)
  return false;
poly_uint64 isize = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode));
poly_uint64 osize = GET_MODE_SIZE (GET_MODE (x)((machine_mode) (x)->mode));
poly_uint64 regsize = REGMODE_NATURAL_SIZE (GET_MODE (SUBREG_REG (x)))ix86_regmode_natural_size (((machine_mode) ((((x)->u.fld[0
]).rt_rtx))->mode));
/* The inner and outer modes of a subreg must be ordered, so that we
   can tell whether they're paradoxical or partial.  */
gcc_checking_assert (ordered_p (isize, osize))((void)(!(ordered_p (isize, osize)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 1426, __FUNCTION__), 0 : 0));
return (maybe_gt (isize, osize)maybe_lt (osize, isize) && maybe_gt (isize, regsize)maybe_lt (regsize, isize));
1428}
1429
1430/* Helper function for set_of.  */
1431struct set_of_data
{
  const_rtx found;
  const_rtx pat;
};

1437static void
1438set_of_1 (rtx x, const_rtx pat, void *data1)
1439{
struct set_of_data *const data = (struct set_of_data *) (data1);
if (rtx_equal_p (x, data->pat)
    || (!MEM_P (x)(((enum rtx_code) (x)->code) == MEM) && reg_overlap_mentioned_p (data->pat, x)))
  data->found = pat;
1444}

1446/* Give an INSN, return a SET or CLOBBER expression that does modify PAT
 (either directly or via STRICT_LOW_PART and similar modifiers).  */
1448const_rtx
1449set_of (const_rtx pat, const_rtx insn)
1450{
struct set_of_data data;
data.found = NULL_RTX(rtx) 0;
data.pat = pat;
note_pattern_stores (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)) ? PATTERN (insn) : insn, set_of_1, &data);
return data.found;
1456}

1458/* Check whether instruction pattern PAT contains a SET with the following
 properties:

 - the SET is executed unconditionally; and
 - either:
   - the destination of the SET is a REG that contains REGNO; or
   - both:
     - the destination of the SET is a SUBREG of such a REG; and
     - writing to the subreg clobbers all of the SUBREG_REG
(in other words, read_modify_subreg_p is false).

 If PAT does have a SET like that, return the set, otherwise return null.

 This is intended to be an alternative to single_set for passes that
 can handle patterns with multiple_sets.  */
1473rtx
1474simple_regno_set (rtx pat, unsigned int regno)
1475{
if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
  {
    int last = XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem) - 1;
    for (int i = 0; i < last; ++i)
if (rtx set = simple_regno_set (XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]), regno))
 return set;

    pat = XVECEXP (pat, 0, last)(((((pat)->u.fld[0]).rt_rtvec))->elem[last]);
  }

if (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET
    && covers_regno_no_parallel_p (SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx), regno))
  return pat;

return nullptr;
1491}

1493/* Add all hard register in X to *PSET.  */
1494void
1495find_all_hard_regs (const_rtx x, HARD_REG_SET *pset)
1496{
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, NONCONST)for (subrtx_iterator iter (array, x, rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
  {
    const_rtx x = *iter;
    if (REG_P (x)(((enum rtx_code) (x)->code) == REG) && REGNO (x)(rhs_regno(x)) < FIRST_PSEUDO_REGISTER76)
add_to_hard_reg_set (pset, GET_MODE (x)((machine_mode) (x)->mode), REGNO (x)(rhs_regno(x)));
  }
1504}

1506/* This function, called through note_stores, collects sets and
 clobbers of hard registers in a HARD_REG_SET, which is pointed to
 by DATA.  */
1509void
1510record_hard_reg_sets (rtx x, const_rtx pat ATTRIBUTE_UNUSED__attribute__ ((__unused__)), void *data)
1511{
HARD_REG_SET *pset = (HARD_REG_SET *)data;
if (REG_P (x)(((enum rtx_code) (x)->code) == REG) && HARD_REGISTER_P (x)((((rhs_regno(x))) < 76)))
  add_to_hard_reg_set (pset, GET_MODE (x)((machine_mode) (x)->mode), REGNO (x)(rhs_regno(x)));
1515}

1517/* Examine INSN, and compute the set of hard registers written by it.
 Store it in *PSET.  Should only be called after reload.

 IMPLICIT is true if we should include registers that are fully-clobbered
 by calls.  This should be used with caution, since it doesn't include
 partially-clobbered registers.  */
1523void
1524find_all_hard_reg_sets (const rtx_insn *insn, HARD_REG_SET *pset, bool implicit)
1525{
rtx link;

CLEAR_HARD_REG_SET (*pset);
note_stores (insn, record_hard_reg_sets, pset);
if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN) && implicit)
  *pset |= insn_callee_abi (insn).full_reg_clobbers ();
for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
  if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == REG_INC)
    record_hard_reg_sets (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), NULLnullptr, pset);
1535}

1537/* Like record_hard_reg_sets, but called through note_uses.  */
1538void
1539record_hard_reg_uses (rtx *px, void *data)
1540{
find_all_hard_regs (*px, (HARD_REG_SET *) data);
1542}
1543
1544/* Given an INSN, return a SET expression if this insn has only a single SET.
 It may also have CLOBBERs, USEs, or SET whose output
 will not be used, which we ignore.  */

1548rtx
1549single_set_2 (const rtx_insn *insn, const_rtx pat)
1550{
rtx set = NULLnullptr;
int set_verified = 1;
int i;

if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
  {
    for (i = 0; i < XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
{
 rtx sub = XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]);
 switch (GET_CODE (sub)((enum rtx_code) (sub)->code))
   {
   case USE:
   case CLOBBER:
     break;

   case SET:
     /* We can consider insns having multiple sets, where all
 but one are dead as single set insns.  In common case
 only single set is present in the pattern so we want
 to avoid checking for REG_UNUSED notes unless necessary.

 When we reach set first time, we just expect this is
 the single set we are looking for and only when more
 sets are found in the insn, we check them.  */
     if (!set_verified)
{
  if (find_reg_note (insn, REG_UNUSED, SET_DEST (set)(((set)->u.fld[0]).rt_rtx))
      && !side_effects_p (set))
    set = NULLnullptr;
  else
    set_verified = 1;
}
     if (!set)
set = sub, set_verified = 0;
     else if (!find_reg_note (insn, REG_UNUSED, SET_DEST (sub)(((sub)->u.fld[0]).rt_rtx))
       || side_effects_p (sub))
return NULL_RTX(rtx) 0;
     break;

   default:
     return NULL_RTX(rtx) 0;
   }
}
  }
return set;
1596}

1598/* Given an INSN, return nonzero if it has more than one SET, else return
 zero.  */

1601int
1602multiple_sets (const_rtx insn)
1603{
int found;
int i;

/* INSN must be an insn.  */
if (! INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
  return 0;

/* Only a PARALLEL can have multiple SETs.  */
if (GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == PARALLEL)
  {
    for (i = 0, found = 0; i < XVECLEN (PATTERN (insn), 0)(((((PATTERN (insn))->u.fld[0]).rt_rtvec))->num_elem); i++)
if (GET_CODE (XVECEXP (PATTERN (insn), 0, i))((enum rtx_code) ((((((PATTERN (insn))->u.fld[0]).rt_rtvec
))->elem[i]))->code) == SET)
 {
   /* If we have already found a SET, then return now.  */
   if (found)
     return 1;
   else
     found = 1;
 }
  }

/* Either zero or one SET.  */
return 0;
1627}
1628
1629/* Return nonzero if the destination of SET equals the source
 and there are no side effects.  */

1632int
1633set_noop_p (const_rtx set)
1634{
rtx src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
rtx dst = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);

if (dst == pc_rtx && src == pc_rtx)
  return 1;

if (MEM_P (dst)(((enum rtx_code) (dst)->code) == MEM) && MEM_P (src)(((enum rtx_code) (src)->code) == MEM))
  return rtx_equal_p (dst, src) && !side_effects_p (dst);

if (GET_CODE (dst)((enum rtx_code) (dst)->code) == ZERO_EXTRACT)
  return rtx_equal_p (XEXP (dst, 0)(((dst)->u.fld[0]).rt_rtx), src)
  && !BITS_BIG_ENDIAN0 && XEXP (dst, 2)(((dst)->u.fld[2]).rt_rtx) == const0_rtx(const_int_rtx[64])
  && !side_effects_p (src);

if (GET_CODE (dst)((enum rtx_code) (dst)->code) == STRICT_LOW_PART)
  dst = XEXP (dst, 0)(((dst)->u.fld[0]).rt_rtx);

if (GET_CODE (src)((enum rtx_code) (src)->code) == SUBREG && GET_CODE (dst)((enum rtx_code) (dst)->code) == SUBREG)
  {
    if (maybe_ne (SUBREG_BYTE (src)(((src)->u.fld[1]).rt_subreg), SUBREG_BYTE (dst)(((dst)->u.fld[1]).rt_subreg)))
return 0;
    src = SUBREG_REG (src)(((src)->u.fld[0]).rt_rtx);
    dst = SUBREG_REG (dst)(((dst)->u.fld[0]).rt_rtx);
    if (GET_MODE (src)((machine_mode) (src)->mode) != GET_MODE (dst)((machine_mode) (dst)->mode))
/* It is hard to tell whether subregs refer to the same bits, so act
  conservatively and return 0.  */
return 0;
  }

/* It is a NOOP if destination overlaps with selected src vector
   elements.  */
if (GET_CODE (src)((enum rtx_code) (src)->code) == VEC_SELECT
    && REG_P (XEXP (src, 0))(((enum rtx_code) ((((src)->u.fld[0]).rt_rtx))->code) ==
 REG) && REG_P (dst)(((enum rtx_code) (dst)->code) == REG)
    && HARD_REGISTER_P (XEXP (src, 0))((((rhs_regno((((src)->u.fld[0]).rt_rtx)))) < 76))
    && HARD_REGISTER_P (dst)((((rhs_regno(dst))) < 76)))
  {
    int i;
    rtx par = XEXP (src, 1)(((src)->u.fld[1]).rt_rtx);
    rtx src0 = XEXP (src, 0)(((src)->u.fld[0]).rt_rtx);
    poly_int64 c0;
    if (!poly_int_rtx_p (XVECEXP (par, 0, 0)(((((par)->u.fld[0]).rt_rtvec))->elem[0]), &c0))
return 0;
    poly_int64 offset = GET_MODE_UNIT_SIZE (GET_MODE (src0))mode_to_unit_size (((machine_mode) (src0)->mode)) * c0;

    for (i = 1; i < XVECLEN (par, 0)(((((par)->u.fld[0]).rt_rtvec))->num_elem); i++)
{
 poly_int64 c0i;
 if (!poly_int_rtx_p (XVECEXP (par, 0, i)(((((par)->u.fld[0]).rt_rtvec))->elem[i]), &c0i)
     || maybe_ne (c0i, c0 + i))
   return 0;
}
    return
REG_CAN_CHANGE_MODE_P (REGNO (dst), GET_MODE (src0), GET_MODE (dst))(targetm.can_change_mode_class (((machine_mode) (src0)->mode
), ((machine_mode) (dst)->mode), (regclass_map[((rhs_regno
(dst)))])))
&& simplify_subreg_regno (REGNO (src0)(rhs_regno(src0)), GET_MODE (src0)((machine_mode) (src0)->mode),
		  offset, GET_MODE (dst)((machine_mode) (dst)->mode)) == (int) REGNO (dst)(rhs_regno(dst));
  }

return (REG_P (src)(((enum rtx_code) (src)->code) == REG) && REG_P (dst)(((enum rtx_code) (dst)->code) == REG)
 && REGNO (src)(rhs_regno(src)) == REGNO (dst)(rhs_regno(dst)));
1694}
1695
1696/* Return nonzero if an insn consists only of SETs, each of which only sets a
 value to itself.  */

1699int
1700noop_move_p (const rtx_insn *insn)
1701{
rtx pat = PATTERN (insn);

if (INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) == NOOP_MOVE_INSN_CODE2147483647)
  return 1;

/* Check the code to be executed for COND_EXEC.  */
if (GET_CODE (pat)((enum rtx_code) (pat)->code) == COND_EXEC)
  pat = COND_EXEC_CODE (pat)(((pat)->u.fld[1]).rt_rtx);

if (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET && set_noop_p (pat))
  return 1;

if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
  {
    int i;
    /* If nothing but SETs of registers to themselves,
this insn can also be deleted.  */
    for (i = 0; i < XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
{
 rtx tem = XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]);

 if (GET_CODE (tem)((enum rtx_code) (tem)->code) == USE || GET_CODE (tem)((enum rtx_code) (tem)->code) == CLOBBER)
   continue;

 if (GET_CODE (tem)((enum rtx_code) (tem)->code) != SET || ! set_noop_p (tem))
   return 0;
}

    return 1;
  }
return 0;
1733}
1734

1736/* Return nonzero if register in range [REGNO, ENDREGNO)
 appears either explicitly or implicitly in X
 other than being stored into.

 References contained within the substructure at LOC do not count.
 LOC may be zero, meaning don't ignore anything.  */

1743bool
1744refers_to_regno_p (unsigned int regno, unsigned int endregno, const_rtx x,
   rtx *loc)
1746{
int i;
unsigned int x_regno;
RTX_CODEenum rtx_code code;
const char *fmt;

repeat:
/* The contents of a REG_NONNEG note is always zero, so we must come here
   upon repeat in case the last REG_NOTE is a REG_NONNEG note.  */
if (x == 0)
  return false;

code = GET_CODE (x)((enum rtx_code) (x)->code);

switch (code)
  {
  case REG:
    x_regno = REGNO (x)(rhs_regno(x));

    /* If we modifying the stack, frame, or argument pointer, it will
clobber a virtual register.  In fact, we could be more precise,
but it isn't worth it.  */
    if ((x_regno == STACK_POINTER_REGNUM7
  || (FRAME_POINTER_REGNUM19 != ARG_POINTER_REGNUM16
      && x_regno == ARG_POINTER_REGNUM16)
  || x_regno == FRAME_POINTER_REGNUM19)
 && regno >= FIRST_VIRTUAL_REGISTER(76) && regno <= LAST_VIRTUAL_REGISTER(((76)) + 5))
return true;

    return endregno > x_regno && regno < END_REGNO (x);

  case SUBREG:
    /* If this is a SUBREG of a hard reg, we can see exactly which
registers are being modified.  Otherwise, handle normally.  */
    if (REG_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
 && REGNO (SUBREG_REG (x))(rhs_regno((((x)->u.fld[0]).rt_rtx))) < FIRST_PSEUDO_REGISTER76)
{
 unsigned int inner_regno = subreg_regno (x);
 unsigned int inner_endregno
   = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER76
	     ? subreg_nregs (x) : 1);

 return endregno > inner_regno && regno < inner_endregno;
}
    break;

  case CLOBBER:
  case SET:
    if (&SET_DEST (x)(((x)->u.fld[0]).rt_rtx) != loc
 /* Note setting a SUBREG counts as referring to the REG it is in for
    a pseudo but not for hard registers since we can
    treat each word individually.  */
 && ((GET_CODE (SET_DEST (x))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == SUBREG
      && loc != &SUBREG_REG (SET_DEST (x))((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx)
      && REG_P (SUBREG_REG (SET_DEST (x)))(((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[
0]).rt_rtx))->code) == REG)
      && REGNO (SUBREG_REG (SET_DEST (x)))(rhs_regno(((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx
))) >= FIRST_PSEUDO_REGISTER76
      && refers_to_regno_p (regno, endregno,
		     SUBREG_REG (SET_DEST (x))((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx), loc))
     || (!REG_P (SET_DEST (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
  && refers_to_regno_p (regno, endregno, SET_DEST (x)(((x)->u.fld[0]).rt_rtx), loc))))
return true;

    if (code == CLOBBER || loc == &SET_SRC (x)(((x)->u.fld[1]).rt_rtx))
return false;
    x = SET_SRC (x)(((x)->u.fld[1]).rt_rtx);
    goto repeat;

  default:
    break;
  }

/* X does not match, so try its subexpressions.  */

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'e' && loc != &XEXP (x, i)(((x)->u.fld[i]).rt_rtx))
{
 if (i == 0)
   {
     x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
     goto repeat;
   }
 else
   if (refers_to_regno_p (regno, endregno, XEXP (x, i)(((x)->u.fld[i]).rt_rtx), loc))
     return true;
}
    else if (fmt[i] == 'E')
{
 int j;
 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
   if (loc != &XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])
&& refers_to_regno_p (regno, endregno, XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), loc))
     return true;
}
  }
return false;
1843}

1845/* Nonzero if modifying X will affect IN.  If X is a register or a SUBREG,
 we check if any register number in X conflicts with the relevant register
 numbers.  If X is a constant, return 0.  If X is a MEM, return 1 iff IN
 contains a MEM (we don't bother checking for memory addresses that can't
 conflict because we expect this to be a rare case.  */

1851int
1852reg_overlap_mentioned_p (const_rtx x, const_rtx in)
1853{
unsigned int regno, endregno;

/* If either argument is a constant, then modifying X cannot
   affect IN.  Here we look at IN, we can profitably combine
   CONSTANT_P (x) with the switch statement below.  */
if (CONSTANT_P (in)((rtx_class[(int) (((enum rtx_code) (in)->code))]) == RTX_CONST_OBJ
))
  return 0;

recurse:
switch (GET_CODE (x)((enum rtx_code) (x)->code))
  {
  case CLOBBER:
  case STRICT_LOW_PART:
  case ZERO_EXTRACT:
  case SIGN_EXTRACT:
    /* Overly conservative.  */
    x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
    goto recurse;

  case SUBREG:
    regno = REGNO (SUBREG_REG (x))(rhs_regno((((x)->u.fld[0]).rt_rtx)));
    if (regno < FIRST_PSEUDO_REGISTER76)
regno = subreg_regno (x);
    endregno = regno + (regno < FIRST_PSEUDO_REGISTER76
	  ? subreg_nregs (x) : 1);
    goto do_reg;

  case REG:
    regno = REGNO (x)(rhs_regno(x));
    endregno = END_REGNO (x);
  do_reg:
    return refers_to_regno_p (regno, endregno, in, (rtx*) 0);

  case MEM:
    {
const char *fmt;
int i;

if (MEM_P (in)(((enum rtx_code) (in)->code) == MEM))
 return 1;

fmt = GET_RTX_FORMAT (GET_CODE (in))(rtx_format[(int) (((enum rtx_code) (in)->code))]);
for (i = GET_RTX_LENGTH (GET_CODE (in))(rtx_length[(int) (((enum rtx_code) (in)->code))]) - 1; i >= 0; i--)
 if (fmt[i] == 'e')
   {
     if (reg_overlap_mentioned_p (x, XEXP (in, i)(((in)->u.fld[i]).rt_rtx)))
return 1;
   }
 else if (fmt[i] == 'E')
   {
     int j;
     for (j = XVECLEN (in, i)(((((in)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; --j)
if (reg_overlap_mentioned_p (x, XVECEXP (in, i, j)(((((in)->u.fld[i]).rt_rtvec))->elem[j])))
  return 1;
   }

return 0;
    }

  case SCRATCH:
  case PC:
    return reg_mentioned_p (x, in);

  case PARALLEL:
    {
int i;

/* If any register in here refers to it we return true.  */
for (i = XVECLEN (x, 0)(((((x)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
 if (XEXP (XVECEXP (x, 0, i), 0)((((((((x)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld[0
]).rt_rtx) != 0
     && reg_overlap_mentioned_p (XEXP (XVECEXP (x, 0, i), 0)((((((((x)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld[0
]).rt_rtx), in))
   return 1;
return 0;
    }

  default:
    gcc_assert (CONSTANT_P (x))((void)(!(((rtx_class[(int) (((enum rtx_code) (x)->code))]
) == RTX_CONST_OBJ)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 1930, __FUNCTION__), 0 : 0));
    return 0;
  }
1933}
1934
1935/* Call FUN on each register or MEM that is stored into or clobbered by X.
 (X would be the pattern of an insn).  DATA is an arbitrary pointer,
 ignored by note_stores, but passed to FUN.

 FUN receives three arguments:
 1. the REG, MEM or PC being stored in or clobbered,
 2. the SET or CLOBBER rtx that does the store,
 3. the pointer DATA provided to note_stores.

If the item being stored in or clobbered is a SUBREG of a hard register,
the SUBREG will be passed.  */

1947void
1948note_pattern_stores (const_rtx x,
     void (*fun) (rtx, const_rtx, void *), void *data)
1950{
int i;

if (GET_CODE (x)((enum rtx_code) (x)->code) == COND_EXEC)
  x = COND_EXEC_CODE (x)(((x)->u.fld[1]).rt_rtx);

if (GET_CODE (x)((enum rtx_code) (x)->code) == SET || GET_CODE (x)((enum rtx_code) (x)->code) == CLOBBER)
  {
    rtx dest = SET_DEST (x)(((x)->u.fld[0]).rt_rtx);

    while ((GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG
     && (!REG_P (SUBREG_REG (dest))(((enum rtx_code) ((((dest)->u.fld[0]).rt_rtx))->code) ==
 REG)
  || REGNO (SUBREG_REG (dest))(rhs_regno((((dest)->u.fld[0]).rt_rtx))) >= FIRST_PSEUDO_REGISTER76))
    || GET_CODE (dest)((enum rtx_code) (dest)->code) == ZERO_EXTRACT
    || GET_CODE (dest)((enum rtx_code) (dest)->code) == STRICT_LOW_PART)
dest = XEXP (dest, 0)(((dest)->u.fld[0]).rt_rtx);

    /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
each of whose first operand is a register.  */
    if (GET_CODE (dest)((enum rtx_code) (dest)->code) == PARALLEL)
{
 for (i = XVECLEN (dest, 0)(((((dest)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
   if (XEXP (XVECEXP (dest, 0, i), 0)((((((((dest)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx) != 0)
     (*fun) (XEXP (XVECEXP (dest, 0, i), 0)((((((((dest)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx), x, data);
}
    else
(*fun) (dest, x, data);
  }

else if (GET_CODE (x)((enum rtx_code) (x)->code) == PARALLEL)
  for (i = XVECLEN (x, 0)(((((x)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
    note_pattern_stores (XVECEXP (x, 0, i)(((((x)->u.fld[0]).rt_rtvec))->elem[i]), fun, data);
1982}

1984/* Same, but for an instruction.  If the instruction is a call, include
 any CLOBBERs in its CALL_INSN_FUNCTION_USAGE.  */

1987void
1988note_stores (const rtx_insn *insn,
    void (*fun) (rtx, const_rtx, void *), void *data)
1990{
if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
  for (rtx link = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx);
link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
    if (GET_CODE (XEXP (link, 0))((enum rtx_code) ((((link)->u.fld[0]).rt_rtx))->code) == CLOBBER)
note_pattern_stores (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), fun, data);
note_pattern_stores (PATTERN (insn), fun, data);
1997}
1998
1999/* Like notes_stores, but call FUN for each expression that is being
 referenced in PBODY, a pointer to the PATTERN of an insn.  We only call
 FUN for each expression, not any interior subexpressions.  FUN receives a
 pointer to the expression and the DATA passed to this function.

 Note that this is not quite the same test as that done in reg_referenced_p
 since that considers something as being referenced if it is being
 partially set, while we do not.  */

2008void
2009note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data)
2010{
rtx body = *pbody;
int i;

switch (GET_CODE (body)((enum rtx_code) (body)->code))
  {
  case COND_EXEC:
    (*fun) (&COND_EXEC_TEST (body)(((body)->u.fld[0]).rt_rtx), data);
    note_uses (&COND_EXEC_CODE (body)(((body)->u.fld[1]).rt_rtx), fun, data);
    return;

  case PARALLEL:
    for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
note_uses (&XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i]), fun, data);
    return;

  case SEQUENCE:
    for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
note_uses (&PATTERN (XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i])), fun, data);
    return;

  case USE:
    (*fun) (&XEXP (body, 0)(((body)->u.fld[0]).rt_rtx), data);
    return;

  case ASM_OPERANDS:
    for (i = ASM_OPERANDS_INPUT_LENGTH (body)(((((body)->u.fld[3]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
(*fun) (&ASM_OPERANDS_INPUT (body, i)(((((body)->u.fld[3]).rt_rtvec))->elem[i]), data);
    return;

  case TRAP_IF:
    (*fun) (&TRAP_CONDITION (body)(((body)->u.fld[0]).rt_rtx), data);
    return;

  case PREFETCH:
    (*fun) (&XEXP (body, 0)(((body)->u.fld[0]).rt_rtx), data);
    return;

  case UNSPEC:
  case UNSPEC_VOLATILE:
    for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
(*fun) (&XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i]), data);
    return;

  case CLOBBER:
    if (MEM_P (XEXP (body, 0))(((enum rtx_code) ((((body)->u.fld[0]).rt_rtx))->code) ==
 MEM))
(*fun) (&XEXP (XEXP (body, 0), 0)((((((body)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx), data);
    return;

  case SET:
    {
rtx dest = SET_DEST (body)(((body)->u.fld[0]).rt_rtx);

/* For sets we replace everything in source plus registers in memory
  expression in store and operands of a ZERO_EXTRACT.  */
(*fun) (&SET_SRC (body)(((body)->u.fld[1]).rt_rtx), data);

if (GET_CODE (dest)((enum rtx_code) (dest)->code) == ZERO_EXTRACT)
 {
   (*fun) (&XEXP (dest, 1)(((dest)->u.fld[1]).rt_rtx), data);
   (*fun) (&XEXP (dest, 2)(((dest)->u.fld[2]).rt_rtx), data);
 }

while (GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG || GET_CODE (dest)((enum rtx_code) (dest)->code) == STRICT_LOW_PART)
 dest = XEXP (dest, 0)(((dest)->u.fld[0]).rt_rtx);

if (MEM_P (dest)(((enum rtx_code) (dest)->code) == MEM))
 (*fun) (&XEXP (dest, 0)(((dest)->u.fld[0]).rt_rtx), data);
    }
    return;

  default:
    /* All the other possibilities never store.  */
    (*fun) (pbody, data);
    return;
  }
2086}

2088/* Try to add a description of REG X to this object, stopping once
 the REF_END limit has been reached.  FLAGS is a bitmask of
 rtx_obj_reference flags that describe the context.  */

2092void
2093rtx_properties::try_to_add_reg (const_rtx x, unsigned int flags)
2094{
if (REG_NREGS (x)((&(x)->u.reg)->nregs) != 1)
  flags |= rtx_obj_flags::IS_MULTIREG;
machine_mode mode = GET_MODE (x)((machine_mode) (x)->mode);
unsigned int start_regno = REGNO (x)(rhs_regno(x));
unsigned int end_regno = END_REGNO (x);
for (unsigned int regno = start_regno; regno < end_regno; ++regno)
  if (ref_iter != ref_end)
    *ref_iter++ = rtx_obj_reference (regno, flags, mode,
		       regno - start_regno);
2104}

2106/* Add a description of destination X to this object.  FLAGS is a bitmask
 of rtx_obj_reference flags that describe the context.

 This routine accepts all rtxes that can legitimately appear in a
 SET_DEST.  */

2112void
2113rtx_properties::try_to_add_dest (const_rtx x, unsigned int flags)
2114{
/* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
   each of whose first operand is a register.  */
if (UNLIKELY (GET_CODE (x) == PARALLEL)(__builtin_expect ((((enum rtx_code) (x)->code) == PARALLEL
), 0)))
  {
    for (int i = XVECLEN (x, 0)(((((x)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; --i)
if (rtx dest = XEXP (XVECEXP (x, 0, i), 0)((((((((x)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld[0
]).rt_rtx))
 try_to_add_dest (dest, flags);
    return;
  }

unsigned int base_flags = flags & rtx_obj_flags::STICKY_FLAGS;
flags |= rtx_obj_flags::IS_WRITE;
for (;;)
  if (GET_CODE (x)((enum rtx_code) (x)->code) == ZERO_EXTRACT)
    {
try_to_add_src (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), base_flags);
try_to_add_src (XEXP (x, 2)(((x)->u.fld[2]).rt_rtx), base_flags);
flags |= rtx_obj_flags::IS_READ;
x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
    }
  else if (GET_CODE (x)((enum rtx_code) (x)->code) == STRICT_LOW_PART)
    {
flags |= rtx_obj_flags::IS_READ;
x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
    }
  else if (GET_CODE (x)((enum rtx_code) (x)->code) == SUBREG)
    {
flags |= rtx_obj_flags::IN_SUBREG;
if (read_modify_subreg_p (x))
 flags |= rtx_obj_flags::IS_READ;
x = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
    }
  else
    break;

if (MEM_P (x)(((enum rtx_code) (x)->code) == MEM))
  {
    if (ref_iter != ref_end)
*ref_iter++ = rtx_obj_reference (MEM_REGNO, flags, GET_MODE (x)((machine_mode) (x)->mode));

    unsigned int addr_flags = base_flags | rtx_obj_flags::IN_MEM_STORE;
    if (flags & rtx_obj_flags::IS_READ)
addr_flags |= rtx_obj_flags::IN_MEM_LOAD;
    try_to_add_src (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), addr_flags);
    return;
  }

if (LIKELY (REG_P (x))(__builtin_expect (((((enum rtx_code) (x)->code) == REG)),
 1)))
  {
    /* We want to keep sp alive everywhere -  by making all
writes to sp also use sp. */
    if (REGNO (x)(rhs_regno(x)) == STACK_POINTER_REGNUM7)
flags |= rtx_obj_flags::IS_READ;
    try_to_add_reg (x, flags);
    return;
  }
2171}

2173/* Try to add a description of source X to this object, stopping once
 the REF_END limit has been reached.  FLAGS is a bitmask of
 rtx_obj_reference flags that describe the context.

 This routine accepts all rtxes that can legitimately appear in a SET_SRC.  */

2179void
2180rtx_properties::try_to_add_src (const_rtx x, unsigned int flags)
2181{
unsigned int base_flags = flags & rtx_obj_flags::STICKY_FLAGS;
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, NONCONST)for (subrtx_iterator iter (array, x, rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
  {
    const_rtx x = *iter;
    rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
    if (code == REG)
try_to_add_reg (x, flags | rtx_obj_flags::IS_READ);
    else if (code == MEM)
{
 if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2192, __FUNCTION__); _rtx; })->volatil))
   has_volatile_refs = true;

 if (!MEM_READONLY_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2195, __FUNCTION__); _rtx; })->unchanging) && ref_iter != ref_end)
   {
     auto mem_flags = flags | rtx_obj_flags::IS_READ;
     *ref_iter++ = rtx_obj_reference (MEM_REGNO, mem_flags,
			       GET_MODE (x)((machine_mode) (x)->mode));
   }

 try_to_add_src (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx),
	  base_flags | rtx_obj_flags::IN_MEM_LOAD);
 iter.skip_subrtxes ();
}
    else if (code == SUBREG)
{
 try_to_add_src (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), flags | rtx_obj_flags::IN_SUBREG);
 iter.skip_subrtxes ();
}
    else if (code == UNSPEC_VOLATILE)
has_volatile_refs = true;
    else if (code == ASM_INPUT || code == ASM_OPERANDS)
{
 has_asm = true;
 if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2216, __FUNCTION__); _rtx; })->volatil))
   has_volatile_refs = true;
}
    else if (code == PRE_INC
      || code == PRE_DEC
      || code == POST_INC
      || code == POST_DEC
      || code == PRE_MODIFY
      || code == POST_MODIFY)
{
 has_pre_post_modify = true;

 unsigned int addr_flags = (base_flags
		     | rtx_obj_flags::IS_PRE_POST_MODIFY
		     | rtx_obj_flags::IS_READ);
 try_to_add_dest (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), addr_flags);
 if (code == PRE_MODIFY || code == POST_MODIFY)
   iter.substitute (XEXP (XEXP (x, 1), 1)((((((x)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx));
 else
   iter.skip_subrtxes ();
}
    else if (code == CALL)
has_call = true;
  }
2240}

2242/* Try to add a description of instruction pattern PAT to this object,
 stopping once the REF_END limit has been reached.  */

2245void
2246rtx_properties::try_to_add_pattern (const_rtx pat)
2247{
switch (GET_CODE (pat)((enum rtx_code) (pat)->code))
  {
  case COND_EXEC:
    try_to_add_src (COND_EXEC_TEST (pat)(((pat)->u.fld[0]).rt_rtx));
    try_to_add_pattern (COND_EXEC_CODE (pat)(((pat)->u.fld[1]).rt_rtx));
    break;

  case PARALLEL:
    {
int last = XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem) - 1;
for (int i = 0; i < last; ++i)
 try_to_add_pattern (XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]));
try_to_add_pattern (XVECEXP (pat, 0, last)(((((pat)->u.fld[0]).rt_rtvec))->elem[last]));
break;
    }

  case ASM_OPERANDS:
    for (int i = 0, len = ASM_OPERANDS_INPUT_LENGTH (pat)(((((pat)->u.fld[3]).rt_rtvec))->num_elem); i < len; ++i)
try_to_add_src (ASM_OPERANDS_INPUT (pat, i)(((((pat)->u.fld[3]).rt_rtvec))->elem[i]));
    break;

  case CLOBBER:
    try_to_add_dest (XEXP (pat, 0)(((pat)->u.fld[0]).rt_rtx), rtx_obj_flags::IS_CLOBBER);
    break;

  case SET:
    try_to_add_dest (SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx));
    try_to_add_src (SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx));
    break;

  default:
    /* All the other possibilities never store and can use a normal
rtx walk.  This includes:

- USE
- TRAP_IF
- PREFETCH
- UNSPEC
- UNSPEC_VOLATILE.  */
    try_to_add_src (pat);
    break;
  }
2290}

2292/* Try to add a description of INSN to this object, stopping once
 the REF_END limit has been reached.  INCLUDE_NOTES is true if the
 description should include REG_EQUAL and REG_EQUIV notes; all such
 references will then be marked with rtx_obj_flags::IN_NOTE.

 For calls, this description includes all accesses in
 CALL_INSN_FUNCTION_USAGE.  It also include all implicit accesses
 to global registers by the target function.  However, it does not
 include clobbers performed by the target function; callers that want
 this information should instead use the function_abi interface.  */

2303void
2304rtx_properties::try_to_add_insn (const rtx_insn *insn, bool include_notes)
2305{
if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
  {
    /* Non-const functions can read from global registers.  Impure
functions can also set them.

Adding the global registers first removes a situation in which
a fixed-form clobber of register R could come before a real set
of register R.  */
    if (!hard_reg_set_empty_p (global_reg_set)
 && !RTL_CONST_CALL_P (insn)(__extension__ ({ __typeof ((insn)) const _rtx = ((insn)); if
 (((enum rtx_code) (_rtx)->code) != CALL_INSN) rtl_check_failed_flag
 ("RTL_CONST_CALL_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2315, __FUNCTION__); _rtx; })->unchanging))
{
 unsigned int flags = rtx_obj_flags::IS_READ;
 if (!RTL_PURE_CALL_P (insn)(__extension__ ({ __typeof ((insn)) const _rtx = ((insn)); if
 (((enum rtx_code) (_rtx)->code) != CALL_INSN) rtl_check_failed_flag
 ("RTL_PURE_CALL_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2318, __FUNCTION__); _rtx; })->return_val))
   flags |= rtx_obj_flags::IS_WRITE;
 for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER76; ++regno)
   /* As a special case, the stack pointer is invariant across calls
      even if it has been marked global; see the corresponding
      handling in df_get_call_refs.  */
   if (regno != STACK_POINTER_REGNUM7
&& global_regs[regno]
&& ref_iter != ref_end)
     *ref_iter++ = rtx_obj_reference (regno, flags,
			       reg_raw_mode(this_target_regs->x_reg_raw_mode)[regno], 0);
}
    /* Untyped calls implicitly set all function value registers.
Again, we add them first in case the main pattern contains
a fixed-form clobber.  */
    if (find_reg_note (insn, REG_UNTYPED_CALL, NULL_RTX(rtx) 0))
for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER76; ++regno)
 if (targetm.calls.function_value_regno_p (regno)
     && ref_iter != ref_end)
   *ref_iter++ = rtx_obj_reference (regno, rtx_obj_flags::IS_WRITE,
			     reg_raw_mode(this_target_regs->x_reg_raw_mode)[regno], 0);
    if (ref_iter != ref_end && !RTL_CONST_CALL_P (insn)(__extension__ ({ __typeof ((insn)) const _rtx = ((insn)); if
 (((enum rtx_code) (_rtx)->code) != CALL_INSN) rtl_check_failed_flag
 ("RTL_CONST_CALL_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2339, __FUNCTION__); _rtx; })->unchanging))
{
 auto mem_flags = rtx_obj_flags::IS_READ;
 if (!RTL_PURE_CALL_P (insn)(__extension__ ({ __typeof ((insn)) const _rtx = ((insn)); if
 (((enum rtx_code) (_rtx)->code) != CALL_INSN) rtl_check_failed_flag
 ("RTL_PURE_CALL_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2342, __FUNCTION__); _rtx; })->return_val))
   mem_flags |= rtx_obj_flags::IS_WRITE;
 *ref_iter++ = rtx_obj_reference (MEM_REGNO, mem_flags, BLKmode((void) 0, E_BLKmode));
}
    try_to_add_pattern (PATTERN (insn));
    for (rtx link = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx); link;
  link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
{
 rtx x = XEXP (link, 0)(((link)->u.fld[0]).rt_rtx);
 if (GET_CODE (x)((enum rtx_code) (x)->code) == CLOBBER)
   try_to_add_dest (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), rtx_obj_flags::IS_CLOBBER);
 else if (GET_CODE (x)((enum rtx_code) (x)->code) == USE)
   try_to_add_src (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));
}
  }
else
  try_to_add_pattern (PATTERN (insn));

if (include_notes)
  for (rtx note = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); note; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
    if (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_EQUAL
 || REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_EQUIV)
try_to_add_note (XEXP (note, 0)(((note)->u.fld[0]).rt_rtx));
2365}

2367/* Grow the storage by a bit while keeping the contents of the first
 START elements.  */

2370void
2371vec_rtx_properties_base::grow (ptrdiff_t start)
2372{
/* The same heuristic that vec uses.  */
ptrdiff_t new_elems = (ref_end - ref_begin) * 3 / 2;
if (ref_begin == m_storage)
  {
    ref_begin = XNEWVEC (rtx_obj_reference, new_elems)((rtx_obj_reference *) xmalloc (sizeof (rtx_obj_reference) * (
new_elems)));
    if (start)
memcpy (ref_begin, m_storage, start * sizeof (rtx_obj_reference));
  }
else
  ref_begin = reinterpret_cast<rtx_obj_reference *>
    (xrealloc (ref_begin, new_elems * sizeof (rtx_obj_reference)));
ref_iter = ref_begin + start;
ref_end = ref_begin + new_elems;
2386}
2387
2388/* Return nonzero if X's old contents don't survive after INSN.
 This will be true if X is a register and X dies in INSN or because
 INSN entirely sets X.

 "Entirely set" means set directly and not through a SUBREG, or
 ZERO_EXTRACT, so no trace of the old contents remains.
 Likewise, REG_INC does not count.

 REG may be a hard or pseudo reg.  Renumbering is not taken into account,
 but for this use that makes no difference, since regs don't overlap
 during their lifetimes.  Therefore, this function may be used
 at any time after deaths have been computed.

 If REG is a hard reg that occupies multiple machine registers, this
 function will only return 1 if each of those registers will be replaced
 by INSN.  */

2405int
2406dead_or_set_p (const rtx_insn *insn, const_rtx x)
2407{
unsigned int regno, end_regno;
unsigned int i;

gcc_assert (REG_P (x))((void)(!((((enum rtx_code) (x)->code) == REG)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2411, __FUNCTION__), 0 : 0));

regno = REGNO (x)(rhs_regno(x));
end_regno = END_REGNO (x);
for (i = regno; i < end_regno; i++)
  if (! dead_or_set_regno_p (insn, i))
    return 0;

return 1;
2420}

2422/* Return TRUE iff DEST is a register or subreg of a register, is a
 complete rather than read-modify-write destination, and contains
 register TEST_REGNO.  */

2426static bool
2427covers_regno_no_parallel_p (const_rtx dest, unsigned int test_regno)
2428{
unsigned int regno, endregno;

if (GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG && !read_modify_subreg_p (dest))
  dest = SUBREG_REG (dest)(((dest)->u.fld[0]).rt_rtx);

if (!REG_P (dest)(((enum rtx_code) (dest)->code) == REG))
  return false;

regno = REGNO (dest)(rhs_regno(dest));
endregno = END_REGNO (dest);
return (test_regno >= regno && test_regno < endregno);
2440}

2442/* Like covers_regno_no_parallel_p, but also handles PARALLELs where
 any member matches the covers_regno_no_parallel_p criteria.  */

2445static bool
2446covers_regno_p (const_rtx dest, unsigned int test_regno)
2447{
if (GET_CODE (dest)((enum rtx_code) (dest)->code) == PARALLEL)
  {
    /* Some targets place small structures in registers for return
values of functions, and those registers are wrapped in
PARALLELs that we may see as the destination of a SET.  */
    int i;

    for (i = XVECLEN (dest, 0)(((((dest)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
{
 rtx inner = XEXP (XVECEXP (dest, 0, i), 0)((((((((dest)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx);
 if (inner != NULL_RTX(rtx) 0
     && covers_regno_no_parallel_p (inner, test_regno))
   return true;
}

    return false;
  }
else
  return covers_regno_no_parallel_p (dest, test_regno);
2467}

2469/* Utility function for dead_or_set_p to check an individual register. */

2471int
2472dead_or_set_regno_p (const rtx_insn *insn, unsigned int test_regno)
2473{
const_rtx pattern;

/* See if there is a death note for something that includes TEST_REGNO.  */
if (find_regno_note (insn, REG_DEAD, test_regno))
  return 1;

if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN)
    && find_regno_fusage (insn, CLOBBER, test_regno))
  return 1;

pattern = PATTERN (insn);

/* If a COND_EXEC is not executed, the value survives.  */
if (GET_CODE (pattern)((enum rtx_code) (pattern)->code) == COND_EXEC)
  return 0;

if (GET_CODE (pattern)((enum rtx_code) (pattern)->code) == SET || GET_CODE (pattern)((enum rtx_code) (pattern)->code) == CLOBBER)
  return covers_regno_p (SET_DEST (pattern)(((pattern)->u.fld[0]).rt_rtx), test_regno);
else if (GET_CODE (pattern)((enum rtx_code) (pattern)->code) == PARALLEL)
  {
    int i;

    for (i = XVECLEN (pattern, 0)(((((pattern)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
{
 rtx body = XVECEXP (pattern, 0, i)(((((pattern)->u.fld[0]).rt_rtvec))->elem[i]);

 if (GET_CODE (body)((enum rtx_code) (body)->code) == COND_EXEC)
   body = COND_EXEC_CODE (body)(((body)->u.fld[1]).rt_rtx);

 if ((GET_CODE (body)((enum rtx_code) (body)->code) == SET || GET_CODE (body)((enum rtx_code) (body)->code) == CLOBBER)
     && covers_regno_p (SET_DEST (body)(((body)->u.fld[0]).rt_rtx), test_regno))
   return 1;
}
  }

return 0;
2510}

2512/* Return the reg-note of kind KIND in insn INSN, if there is one.
 If DATUM is nonzero, look for one whose datum is DATUM.  */

2515rtx
2516find_reg_note (const_rtx insn, enum reg_note kind, const_rtx datum)
2517{
rtx link;

gcc_checking_assert (insn)((void)(!(insn) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2520, __FUNCTION__), 0 : 0));

/* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN.  */
if (! INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
  return 0;
if (datum == 0)
  {
    for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == kind)
 return link;
    return 0;
  }

for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
  if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == kind && datum == XEXP (link, 0)(((link)->u.fld[0]).rt_rtx))
    return link;
return 0;
2537}

2539/* Return the reg-note of kind KIND in insn INSN which applies to register
 number REGNO, if any.  Return 0 if there is no such reg-note.  Note that
 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
 it might be the case that the note overlaps REGNO.  */

2544rtx
2545find_regno_note (const_rtx insn, enum reg_note kind, unsigned int regno)
2546{
rtx link;

/* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN.  */
if (! INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
  return 0;

for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
  if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == kind
/* Verify that it is a register, so that scratch and MEM won't cause a
  problem here.  */
&& REG_P (XEXP (link, 0))(((enum rtx_code) ((((link)->u.fld[0]).rt_rtx))->code) ==
 REG)
&& REGNO (XEXP (link, 0))(rhs_regno((((link)->u.fld[0]).rt_rtx))) <= regno
&& END_REGNO (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx)) > regno)
    return link;
return 0;
2562}

2564/* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
 has such a note.  */

2567rtx
2568find_reg_equal_equiv_note (const_rtx insn)
2569{
rtx link;

if (!INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
  return 0;

for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
  if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == REG_EQUAL
|| REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == REG_EQUIV)
    {
/* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
  insns that have multiple sets.  Checking single_set to
  make sure of this is not the proper check, as explained
  in the comment in set_unique_reg_note.

  This should be changed into an assert.  */
if (GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == PARALLEL && multiple_sets (insn))
 return 0;
return link;
    }
return NULLnullptr;
2590}

2592/* Check whether INSN is a single_set whose source is known to be
 equivalent to a constant.  Return that constant if so, otherwise
 return null.  */

2596rtx
2597find_constant_src (const rtx_insn *insn)
2598{
rtx note, set, x;

set = single_set (insn);
if (set)
  {
    x = avoid_constant_pool_reference (SET_SRC (set)(((set)->u.fld[1]).rt_rtx));
    if (CONSTANT_P (x)((rtx_class[(int) (((enum rtx_code) (x)->code))]) == RTX_CONST_OBJ
))
return x;
  }

note = find_reg_equal_equiv_note (insn);
if (note && CONSTANT_P (XEXP (note, 0))((rtx_class[(int) (((enum rtx_code) ((((note)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
  return XEXP (note, 0)(((note)->u.fld[0]).rt_rtx);

return NULL_RTX(rtx) 0;
2614}

2616/* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
 in the CALL_INSN_FUNCTION_USAGE information of INSN.  */

2619int
2620find_reg_fusage (const_rtx insn, enum rtx_code code, const_rtx datum)
2621{
/* If it's not a CALL_INSN, it can't possibly have a
   CALL_INSN_FUNCTION_USAGE field, so don't bother checking.  */
if (!CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
  return 0;

gcc_assert (datum)((void)(!(datum) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2627, __FUNCTION__), 0 : 0));

if (!REG_P (datum)(((enum rtx_code) (datum)->code) == REG))
  {
    rtx link;

    for (link = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx);
  link;
  link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
if (GET_CODE (XEXP (link, 0))((enum rtx_code) ((((link)->u.fld[0]).rt_rtx))->code) == code
   && rtx_equal_p (datum, XEXP (XEXP (link, 0), 0)((((((link)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx)))
 return 1;
  }
else
  {
    unsigned int regno = REGNO (datum)(rhs_regno(datum));

    /* CALL_INSN_FUNCTION_USAGE information cannot contain references
to pseudo registers, so don't bother checking.  */

    if (regno < FIRST_PSEUDO_REGISTER76)
{
 unsigned int end_regno = END_REGNO (datum);
 unsigned int i;

 for (i = regno; i < end_regno; i++)
   if (find_regno_fusage (insn, code, i))
     return 1;
}
  }

return 0;
2659}

2661/* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
 in the CALL_INSN_FUNCTION_USAGE information of INSN.  */

2664int
2665find_regno_fusage (const_rtx insn, enum rtx_code code, unsigned int regno)
2666{
rtx link;

/* CALL_INSN_FUNCTION_USAGE information cannot contain references
   to pseudo registers, so don't bother checking.  */

if (regno >= FIRST_PSEUDO_REGISTER76
    || !CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN) )
  return 0;

for (link = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
  {
    rtx op, reg;

    if (GET_CODE (op = XEXP (link, 0))((enum rtx_code) (op = (((link)->u.fld[0]).rt_rtx))->code
) == code
 && REG_P (reg = XEXP (op, 0))(((enum rtx_code) (reg = (((op)->u.fld[0]).rt_rtx))->code
) == REG)
 && REGNO (reg)(rhs_regno(reg)) <= regno
 && END_REGNO (reg) > regno)
return 1;
  }

return 0;
2688}

2690
2691/* Return true if KIND is an integer REG_NOTE.  */

2693static bool
2694int_reg_note_p (enum reg_note kind)
2695{
return kind == REG_BR_PROB;
2697}

2699/* Allocate a register note with kind KIND and datum DATUM.  LIST is
 stored as the pointer to the next register note.  */

2702rtx
2703alloc_reg_note (enum reg_note kind, rtx datum, rtx list)
2704{
rtx note;

gcc_checking_assert (!int_reg_note_p (kind))((void)(!(!int_reg_note_p (kind)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2707, __FUNCTION__), 0 : 0));
switch (kind)
  {
  case REG_LABEL_TARGET:
  case REG_LABEL_OPERAND:
  case REG_TM:
    /* These types of register notes use an INSN_LIST rather than an
EXPR_LIST, so that copying is done right and dumps look
better.  */
    note = alloc_INSN_LIST (datum, list);
    PUT_REG_NOTE_KIND (note, kind)((note)->mode = ((machine_mode) (kind)));
    break;

  default:
    note = alloc_EXPR_LIST (kind, datum, list);
    break;
  }

return note;
2726}

2728/* Add register note with kind KIND and datum DATUM to INSN.  */

2730void
2731add_reg_note (rtx insn, enum reg_note kind, rtx datum)
2732{
REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) = alloc_reg_note (kind, datum, REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx));
2734}

2736/* Add an integer register note with kind KIND and datum DATUM to INSN.  */

2738void
2739add_int_reg_note (rtx_insn *insn, enum reg_note kind, int datum)
2740{
gcc_checking_assert (int_reg_note_p (kind))((void)(!(int_reg_note_p (kind)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2741, __FUNCTION__), 0 : 0));
REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) = gen_rtx_INT_LIST ((machine_mode) kind,gen_rtx_fmt_ie_stat ((INT_LIST), (((machine_mode) kind)), ((datum
)), (((((insn)->u.fld[6]).rt_rtx))) )
		       datum, REG_NOTES (insn))gen_rtx_fmt_ie_stat ((INT_LIST), (((machine_mode) kind)), ((datum
)), (((((insn)->u.fld[6]).rt_rtx))) );
2744}

2746/* Add a REG_ARGS_SIZE note to INSN with value VALUE.  */

2748void
2749add_args_size_note (rtx_insn *insn, poly_int64 value)
2750{
gcc_checking_assert (!find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX))((void)(!(!find_reg_note (insn, REG_ARGS_SIZE, (rtx) 0)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2751, __FUNCTION__), 0 : 0));
add_reg_note (insn, REG_ARGS_SIZE, gen_int_mode (value, Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))));
2753}

2755/* Add a register note like NOTE to INSN.  */

2757void
2758add_shallow_copy_of_reg_note (rtx_insn *insn, rtx note)
2759{
if (GET_CODE (note)((enum rtx_code) (note)->code) == INT_LIST)
  add_int_reg_note (insn, REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)), XINT (note, 0)(((note)->u.fld[0]).rt_int));
else
  add_reg_note (insn, REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)), XEXP (note, 0)(((note)->u.fld[0]).rt_rtx));
2764}

2766/* Duplicate NOTE and return the copy.  */
2767rtx
2768duplicate_reg_note (rtx note)
2769{
reg_note kind = REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode));

if (GET_CODE (note)((enum rtx_code) (note)->code) == INT_LIST)
  return gen_rtx_INT_LIST ((machine_mode) kind, XINT (note, 0), NULL_RTX)gen_rtx_fmt_ie_stat ((INT_LIST), (((machine_mode) kind)), (((
((note)->u.fld[0]).rt_int))), (((rtx) 0)) );
else if (GET_CODE (note)((enum rtx_code) (note)->code) == EXPR_LIST)
  return alloc_reg_note (kind, copy_insn_1 (XEXP (note, 0)(((note)->u.fld[0]).rt_rtx)), NULL_RTX(rtx) 0);
else
  return alloc_reg_note (kind, XEXP (note, 0)(((note)->u.fld[0]).rt_rtx), NULL_RTX(rtx) 0);
2778}

2780/* Remove register note NOTE from the REG_NOTES of INSN.  */

2782void
2783remove_note (rtx_insn *insn, const_rtx note)
2784{
rtx link;

if (note == NULL_RTX(rtx) 0)
  return;

if (REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) == note)
  REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx);
else
  for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
    if (XEXP (link, 1)(((link)->u.fld[1]).rt_rtx) == note)
{
 XEXP (link, 1)(((link)->u.fld[1]).rt_rtx) = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx);
 break;
}

switch (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)))
  {
  case REG_EQUAL:
  case REG_EQUIV:
    df_notes_rescan (insn);
    break;
  default:
    break;
  }
2809}

2811/* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes.
 If NO_RESCAN is false and any notes were removed, call
 df_notes_rescan.  Return true if any note has been removed.  */

2815bool
2816remove_reg_equal_equiv_notes (rtx_insn *insn, bool no_rescan)
2817{
rtx *loc;
bool ret = false;

loc = &REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx);
while (*loc)
  {
    enum reg_note kind = REG_NOTE_KIND (*loc)((enum reg_note) ((machine_mode) (*loc)->mode));
    if (kind == REG_EQUAL || kind == REG_EQUIV)
{
 *loc = XEXP (*loc, 1)(((*loc)->u.fld[1]).rt_rtx);
 ret = true;
}
    else
loc = &XEXP (*loc, 1)(((*loc)->u.fld[1]).rt_rtx);
  }
if (ret && !no_rescan)
  df_notes_rescan (insn);
return ret;
2836}

2838/* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO.  */

2840void
2841remove_reg_equal_equiv_notes_for_regno (unsigned int regno)
2842{
df_ref eq_use;

if (!df)
  return;

/* This loop is a little tricky.  We cannot just go down the chain because
   it is being modified by some actions in the loop.  So we just iterate
   over the head.  We plan to drain the list anyway.  */
while ((eq_use = DF_REG_EQ_USE_CHAIN (regno)(df->eq_use_regs[(regno)]->reg_chain)) != NULLnullptr)
  {
    rtx_insn *insn = DF_REF_INSN (eq_use)((eq_use)->base.insn_info->insn);
    rtx note = find_reg_equal_equiv_note (insn);

    /* This assert is generally triggered when someone deletes a REG_EQUAL
or REG_EQUIV note by hacking the list manually rather than calling
remove_note.  */
    gcc_assert (note)((void)(!(note) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2859, __FUNCTION__), 0 : 0));

    remove_note (insn, note);
  }
2863}

2865/* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
 return 1 if it is found.  A simple equality test is used to determine if
 NODE matches.  */

2869bool
2870in_insn_list_p (const rtx_insn_list *listp, const rtx_insn *node)
2871{
const_rtx x;

for (x = listp; x; x = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
  if (node == XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
    return true;

return false;
2879}

2881/* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
 remove that entry from the list if it is found.

 A simple equality test is used to determine if NODE matches.  */

2886void
2887remove_node_from_insn_list (const rtx_insn *node, rtx_insn_list **listp)
2888{
rtx_insn_list *temp = *listp;
rtx_insn_list *prev = NULLnullptr;

while (temp)
  {
    if (node == temp->insn ())
{
 /* Splice the node out of the list.  */
 if (prev)
   XEXP (prev, 1)(((prev)->u.fld[1]).rt_rtx) = temp->next ();
 else
   *listp = temp->next ();

 gcc_checking_assert (!in_insn_list_p (temp->next (), node))((void)(!(!in_insn_list_p (temp->next (), node)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2902, __FUNCTION__), 0 : 0));
 return;
}

    prev = temp;
    temp = temp->next ();
  }
2909}
2910
2911/* Nonzero if X contains any volatile instructions.  These are instructions
 which may cause unpredictable machine state instructions, and thus no
 instructions or register uses should be moved or combined across them.
 This includes only volatile asms and UNSPEC_VOLATILE instructions.  */

2916int
2917volatile_insn_p (const_rtx x)
2918{
const RTX_CODEenum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
switch (code)
  {
  case LABEL_REF:
  case SYMBOL_REF:
  case CONST:
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case PC:
  case REG:
  case SCRATCH:
  case CLOBBER:
  case ADDR_VEC:
  case ADDR_DIFF_VEC:
  case CALL:
  case MEM:
    return 0;

  case UNSPEC_VOLATILE:
    return 1;

  case ASM_INPUT:
  case ASM_OPERANDS:
    if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 2941, __FUNCTION__); _rtx; })->volatil))
return 1;

  default:
    break;
  }

/* Recursively scan the operands of this expression.  */

{
  const char *const fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
  int i;

  for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
    {
if (fmt[i] == 'e')
 {
   if (volatile_insn_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
     return 1;
 }
else if (fmt[i] == 'E')
 {
   int j;
   for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
     if (volatile_insn_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
return 1;
 }
    }
}
return 0;
2971}

2973/* Nonzero if X contains any volatile memory references
 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions.  */

2976int
2977volatile_refs_p (const_rtx x)
2978{
const RTX_CODEenum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
switch (code)
  {
  case LABEL_REF:
  case SYMBOL_REF:
  case CONST:
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case PC:
  case REG:
  case SCRATCH:
  case CLOBBER:
  case ADDR_VEC:
  case ADDR_DIFF_VEC:
    return 0;

  case UNSPEC_VOLATILE:
    return 1;

  case MEM:
  case ASM_INPUT:
  case ASM_OPERANDS:
    if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3000, __FUNCTION__); _rtx; })->volatil))
return 1;

  default:
    break;
  }

/* Recursively scan the operands of this expression.  */

{
  const char *const fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
  int i;

  for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
    {
if (fmt[i] == 'e')
 {
   if (volatile_refs_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
     return 1;
 }
else if (fmt[i] == 'E')
 {
   int j;
   for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
     if (volatile_refs_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
return 1;
 }
    }
}
return 0;
3030}

3032/* Similar to above, except that it also rejects register pre- and post-
 incrementing.  */

3035int
3036side_effects_p (const_rtx x)
3037{
const RTX_CODEenum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
switch (code)
  {
  case LABEL_REF:
  case SYMBOL_REF:
  case CONST:
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case PC:
  case REG:
  case SCRATCH:
  case ADDR_VEC:
  case ADDR_DIFF_VEC:
  case VAR_LOCATION:
    return 0;

  case CLOBBER:
    /* Reject CLOBBER with a non-VOID mode.  These are made by combine.cc
when some combination can't be done.  If we see one, don't think
that we can simplify the expression.  */
    return (GET_MODE (x)((machine_mode) (x)->mode) != VOIDmode((void) 0, E_VOIDmode));

  case PRE_INC:
  case PRE_DEC:
  case POST_INC:
  case POST_DEC:
  case PRE_MODIFY:
  case POST_MODIFY:
  case CALL:
  case UNSPEC_VOLATILE:
    return 1;

  case MEM:
  case ASM_INPUT:
  case ASM_OPERANDS:
    if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3072, __FUNCTION__); _rtx; })->volatil))
return 1;

  default:
    break;
  }

/* Recursively scan the operands of this expression.  */

{
  const char *fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
  int i;

  for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
    {
if (fmt[i] == 'e')
 {
   if (side_effects_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
     return 1;
 }
else if (fmt[i] == 'E')
 {
   int j;
   for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
     if (side_effects_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
return 1;
 }
    }
}
return 0;
3102}
3103
3104/* Return nonzero if evaluating rtx X might cause a trap.
 FLAGS controls how to consider MEMs.  A nonzero means the context
 of the access may have changed from the original, such that the
 address may have become invalid.  */

3109int
3110may_trap_p_1 (const_rtx x, unsigned flags)
3111{
int i;
enum rtx_code code;
const char *fmt;

/* We make no distinction currently, but this function is part of
   the internal target-hooks ABI so we keep the parameter as
   "unsigned flags".  */
bool code_changed = flags != 0;

if (x == 0)
  return 0;
code = GET_CODE (x)((enum rtx_code) (x)->code);
switch (code)
  {
    /* Handle these cases quickly.  */
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case SYMBOL_REF:
  case LABEL_REF:
  case CONST:
  case PC:
  case REG:
  case SCRATCH:
    return 0;

  case UNSPEC:
    return targetm.unspec_may_trap_p (x, flags);

  case UNSPEC_VOLATILE:
  case ASM_INPUT:
  case TRAP_IF:
    return 1;

  case ASM_OPERANDS:
    return MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3145, __FUNCTION__); _rtx; })->volatil);

    /* Memory ref can trap unless it's a static var or a stack slot.  */
  case MEM:
    /* Recognize specific pattern of stack checking probes.  */
    if (flag_stack_checkglobal_options.x_flag_stack_check
 && MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3151, __FUNCTION__); _rtx; })->volatil)
 && XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
return 1;
    if (/* MEM_NOTRAP_P only relates to the actual position of the memory
    reference; moving it out of context such as when moving code
    when optimizing, might cause its address to become invalid.  */
 code_changed
 || !MEM_NOTRAP_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_NOTRAP_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3158, __FUNCTION__); _rtx; })->call))
{
 poly_int64 size = MEM_SIZE_KNOWN_P (x)(get_mem_attrs (x)->size_known_p) ? MEM_SIZE (x)(get_mem_attrs (x)->size) : -1;
 return rtx_addr_can_trap_p_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), 0, size,
			GET_MODE (x)((machine_mode) (x)->mode), code_changed);
}

    return 0;

    /* Division by a non-constant might trap.  */
  case DIV:
  case MOD:
  case UDIV:
  case UMOD:
    if (HONOR_SNANS (x))
return 1;
    if (FLOAT_MODE_P (GET_MODE (x))(((enum mode_class) mode_class[((machine_mode) (x)->mode)]
) == MODE_FLOAT || ((enum mode_class) mode_class[((machine_mode
) (x)->mode)]) == MODE_DECIMAL_FLOAT || ((enum mode_class)
 mode_class[((machine_mode) (x)->mode)]) == MODE_COMPLEX_FLOAT
 || ((enum mode_class) mode_class[((machine_mode) (x)->mode
)]) == MODE_VECTOR_FLOAT))
return flag_trapping_mathglobal_options.x_flag_trapping_math;
    if (!CONSTANT_P (XEXP (x, 1))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ) || (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx) == const0_rtx(const_int_rtx[64])))
return 1;
    if (GET_CODE (XEXP (x, 1))((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_VECTOR)
{
 /* For CONST_VECTOR, return 1 if any element is or might be zero.  */
 unsigned int n_elts;
 rtx op = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);
 if (!GET_MODE_NUNITS (GET_MODE (op)((machine_mode) (op)->mode)).is_constant (&n_elts))
   {
     if (!CONST_VECTOR_DUPLICATE_P (op)((__extension__ ({ __typeof ((op)) const _rtx = ((op)); if ((
(enum rtx_code) (_rtx)->code) != CONST_VECTOR) rtl_check_failed_flag
 ("CONST_VECTOR_NELTS_PER_PATTERN", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3185, __FUNCTION__); _rtx; }) ->u2.const_vector.nelts_per_pattern
) == 1))
return 1;
     for (unsigned i = 0; i < (unsigned int) XVECLEN (op, 0)(((((op)->u.fld[0]).rt_rtvec))->num_elem); i++)
if (CONST_VECTOR_ENCODED_ELT (op, i)(((((op)->u.fld[0]).rt_rtvec))->elem[i]) == const0_rtx(const_int_rtx[64]))
  return 1;
   }
 else
   for (unsigned i = 0; i < n_elts; i++)
     if (CONST_VECTOR_ELT (op, i)const_vector_elt (op, i) == const0_rtx(const_int_rtx[64]))
return 1;
}
    break;

  case EXPR_LIST:
    /* An EXPR_LIST is used to represent a function call.  This
certainly may trap.  */
    return 1;

  case GE:
  case GT:
  case LE:
  case LT:
  case LTGT:
  case COMPARE:
    /* Some floating point comparisons may trap.  */
    if (!flag_trapping_mathglobal_options.x_flag_trapping_math)
break;
    /* ??? There is no machine independent way to check for tests that trap
when COMPARE is used, though many targets do make this distinction.
For instance, sparc uses CCFPE for compares which generate exceptions
and CCFP for compares which do not generate exceptions.  */
    if (HONOR_NANS (x))
return 1;
    /* But often the compare has some CC mode, so check operand
modes as well.  */
    if (HONOR_NANS (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
 || HONOR_NANS (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
return 1;
    break;

  case EQ:
  case NE:
    if (HONOR_SNANS (x))
return 1;
    /* Often comparison is CC mode, so check operand modes.  */
    if (HONOR_SNANS (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
 || HONOR_SNANS (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
return 1;
    break;

  case FIX:
  case UNSIGNED_FIX:
    /* Conversion of floating point might trap.  */
    if (flag_trapping_mathglobal_options.x_flag_trapping_math && HONOR_NANS (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx)))
return 1;
    break;

  case NEG:
  case ABS:
  case SUBREG:
  case VEC_MERGE:
  case VEC_SELECT:
  case VEC_CONCAT:
  case VEC_DUPLICATE:
    /* These operations don't trap even with floating point.  */
    break;

  default:
    /* Any floating arithmetic may trap.  */
    if (FLOAT_MODE_P (GET_MODE (x))(((enum mode_class) mode_class[((machine_mode) (x)->mode)]
) == MODE_FLOAT || ((enum mode_class) mode_class[((machine_mode
) (x)->mode)]) == MODE_DECIMAL_FLOAT || ((enum mode_class)
 mode_class[((machine_mode) (x)->mode)]) == MODE_COMPLEX_FLOAT
 || ((enum mode_class) mode_class[((machine_mode) (x)->mode
)]) == MODE_VECTOR_FLOAT) && flag_trapping_mathglobal_options.x_flag_trapping_math)
return 1;
  }

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'e')
{
 if (may_trap_p_1 (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), flags))
   return 1;
}
    else if (fmt[i] == 'E')
{
 int j;
 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
   if (may_trap_p_1 (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), flags))
     return 1;
}
  }
return 0;
3275}

3277/* Return nonzero if evaluating rtx X might cause a trap.  */

3279int
3280may_trap_p (const_rtx x)
3281{
return may_trap_p_1 (x, 0);
3283}

3285/* Same as above, but additionally return nonzero if evaluating rtx X might
 cause a fault.  We define a fault for the purpose of this function as a
 erroneous execution condition that cannot be encountered during the normal
 execution of a valid program; the typical example is an unaligned memory
 access on a strict alignment machine.  The compiler guarantees that it
 doesn't generate code that will fault from a valid program, but this
 guarantee doesn't mean anything for individual instructions.  Consider
 the following example:

    struct S { int d; union { char *cp; int *ip; }; };

    int foo(struct S *s)
    {
if (s->d == 1)
 return *s->ip;
else
 return *s->cp;
    }

 on a strict alignment machine.  In a valid program, foo will never be
 invoked on a structure for which d is equal to 1 and the underlying
 unique field of the union not aligned on a 4-byte boundary, but the
 expression *s->ip might cause a fault if considered individually.

 At the RTL level, potentially problematic expressions will almost always
 verify may_trap_p; for example, the above dereference can be emitted as
 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
 However, suppose that foo is inlined in a caller that causes s->cp to
 point to a local character variable and guarantees that s->d is not set
 to 1; foo may have been effectively translated into pseudo-RTL as:

    if ((reg:SI) == 1)
(set (reg:SI) (mem:SI (%fp - 7)))
    else
(set (reg:QI) (mem:QI (%fp - 7)))

 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
 memory reference to a stack slot, but it will certainly cause a fault
 on a strict alignment machine.  */

3325int
3326may_trap_or_fault_p (const_rtx x)
3327{
return may_trap_p_1 (x, 1);
3329}
3330
3331/* Replace any occurrence of FROM in X with TO.  The function does
 not enter into CONST_DOUBLE for the replace.

 Note that copying is not done so X must not be shared unless all copies
 are to be modified.

 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
 those pointer-equal ones.  */

3340rtx
3341replace_rtx (rtx x, rtx from, rtx to, bool all_regs)
3342{
int i, j;
const char *fmt;

if (x == from)
  return to;

/* Allow this function to make replacements in EXPR_LISTs.  */
if (x == 0)
  return 0;

if (all_regs
    && REG_P (x)(((enum rtx_code) (x)->code) == REG)
    && REG_P (from)(((enum rtx_code) (from)->code) == REG)
    && REGNO (x)(rhs_regno(x)) == REGNO (from)(rhs_regno(from)))
  {
    gcc_assert (GET_MODE (x) == GET_MODE (from))((void)(!(((machine_mode) (x)->mode) == ((machine_mode) (from
)->mode)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3358, __FUNCTION__), 0 : 0));
    return to;
  }
else if (GET_CODE (x)((enum rtx_code) (x)->code) == SUBREG)
  {
    rtx new_rtx = replace_rtx (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), from, to, all_regs);

    if (CONST_SCALAR_INT_P (new_rtx)((((enum rtx_code) (new_rtx)->code) == CONST_INT) || (((enum
 rtx_code) (new_rtx)->code) == CONST_WIDE_INT)))
{
 x = simplify_subreg (GET_MODE (x)((machine_mode) (x)->mode), new_rtx,
	       GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode),
	       SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg));
 gcc_assert (x)((void)(!(x) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3370, __FUNCTION__), 0 : 0));
}
    else
SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx) = new_rtx;

    return x;
  }
else if (GET_CODE (x)((enum rtx_code) (x)->code) == ZERO_EXTEND)
  {
    rtx new_rtx = replace_rtx (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), from, to, all_regs);

    if (CONST_SCALAR_INT_P (new_rtx)((((enum rtx_code) (new_rtx)->code) == CONST_INT) || (((enum
 rtx_code) (new_rtx)->code) == CONST_WIDE_INT)))
{
 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x)((machine_mode) (x)->mode),
			new_rtx, GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode));
 gcc_assert (x)((void)(!(x) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3385, __FUNCTION__), 0 : 0));
}
    else
XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) = new_rtx;

    return x;
  }

fmt = GET_RTX_FORMAT (GET_CODE (x))(rtx_format[(int) (((enum rtx_code) (x)->code))]);
for (i = GET_RTX_LENGTH (GET_CODE (x))(rtx_length[(int) (((enum rtx_code) (x)->code))]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'e')
XEXP (x, i)(((x)->u.fld[i]).rt_rtx) = replace_rtx (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), from, to, all_regs);
    else if (fmt[i] == 'E')
for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
 XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]) = replace_rtx (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]),
			   from, to, all_regs);
  }

return x;
3405}
3406
3407/* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL.  Also track
 the change in LABEL_NUSES if UPDATE_LABEL_NUSES.  */

3410void
3411replace_label (rtx *loc, rtx old_label, rtx new_label, bool update_label_nuses)
3412{
/* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long.  */
rtx x = *loc;
if (JUMP_TABLE_DATA_P (x)(((enum rtx_code) (x)->code) == JUMP_TABLE_DATA))
  {
    x = PATTERN (x);
    rtvec vec = XVEC (x, GET_CODE (x) == ADDR_DIFF_VEC)(((x)->u.fld[((enum rtx_code) (x)->code) == ADDR_DIFF_VEC
]).rt_rtvec);
    int len = GET_NUM_ELEM (vec)((vec)->num_elem);
    for (int i = 0; i < len; ++i)
{
 rtx ref = RTVEC_ELT (vec, i)((vec)->elem[i]);
 if (XEXP (ref, 0)(((ref)->u.fld[0]).rt_rtx) == old_label)
   {
     XEXP (ref, 0)(((ref)->u.fld[0]).rt_rtx) = new_label;
     if (update_label_nuses)
{
  ++LABEL_NUSES (new_label)(((new_label)->u.fld[4]).rt_int);
  --LABEL_NUSES (old_label)(((old_label)->u.fld[4]).rt_int);
}
   }
}
    return;
  }

/* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
   field.  This is not handled by the iterator because it doesn't
   handle unprinted ('0') fields.  */
if (JUMP_P (x)(((enum rtx_code) (x)->code) == JUMP_INSN) && JUMP_LABEL (x)(((x)->u.fld[7]).rt_rtx) == old_label)
  JUMP_LABEL (x)(((x)->u.fld[7]).rt_rtx) = new_label;

subrtx_ptr_iterator::array_type array;
FOR_EACH_SUBRTX_PTR (iter, array, loc, ALL)for (subrtx_ptr_iterator iter (array, loc, rtx_all_subrtx_bounds
); !iter.at_end (); iter.next ())
  {
    rtx *loc = *iter;
    if (rtx x = *loc)
{
 if (GET_CODE (x)((enum rtx_code) (x)->code) == SYMBOL_REF
     && CONSTANT_POOL_ADDRESS_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("CONSTANT_POOL_ADDRESS_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3449, __FUNCTION__); _rtx; })->unchanging))
   {
     rtx c = get_pool_constant (x);
     if (rtx_referenced_p (old_label, c))
{
  /* Create a copy of constant C; replace the label inside
     but do not update LABEL_NUSES because uses in constant pool
     are not counted.  */
  rtx new_c = copy_rtx (c);
  replace_label (&new_c, old_label, new_label, false);

  /* Add the new constant NEW_C to constant pool and replace
     the old reference to constant by new reference.  */
  rtx new_mem = force_const_mem (get_pool_mode (x), new_c);
  *loc = replace_rtx (x, x, XEXP (new_mem, 0)(((new_mem)->u.fld[0]).rt_rtx));
}
   }

 if ((GET_CODE (x)((enum rtx_code) (x)->code) == LABEL_REF
      || GET_CODE (x)((enum rtx_code) (x)->code) == INSN_LIST)
     && XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) == old_label)
   {
     XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) = new_label;
     if (update_label_nuses)
{
  ++LABEL_NUSES (new_label)(((new_label)->u.fld[4]).rt_int);
  --LABEL_NUSES (old_label)(((old_label)->u.fld[4]).rt_int);
}
   }
}
  }
3480}

3482void
3483replace_label_in_insn (rtx_insn *insn, rtx_insn *old_label,
       rtx_insn *new_label, bool update_label_nuses)
3485{
rtx insn_as_rtx = insn;
replace_label (&insn_as_rtx, old_label, new_label, update_label_nuses);
gcc_checking_assert (insn_as_rtx == insn)((void)(!(insn_as_rtx == insn) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3488, __FUNCTION__), 0 : 0));
3489}

3491/* Return true if X is referenced in BODY.  */

3493bool
3494rtx_referenced_p (const_rtx x, const_rtx body)
3495{
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, body, ALL)for (subrtx_iterator iter (array, body, rtx_all_subrtx_bounds
); !iter.at_end (); iter.next ())
  if (const_rtx y = *iter)
    {
/* Check if a label_ref Y refers to label X.  */
if (GET_CODE (y)((enum rtx_code) (y)->code) == LABEL_REF
   && LABEL_P (x)(((enum rtx_code) (x)->code) == CODE_LABEL)
   && label_ref_label (y) == x)
 return true;

if (rtx_equal_p (x, y))
 return true;

/* If Y is a reference to pool constant traverse the constant.  */
if (GET_CODE (y)((enum rtx_code) (y)->code) == SYMBOL_REF
   && CONSTANT_POOL_ADDRESS_P (y)(__extension__ ({ __typeof ((y)) const _rtx = ((y)); if (((enum
 rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("CONSTANT_POOL_ADDRESS_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3511, __FUNCTION__); _rtx; })->unchanging))
 iter.substitute (get_pool_constant (y));
    }
return false;
3515}

3517/* If INSN is a tablejump return true and store the label (before jump table) to
 *LABELP and the jump table to *TABLEP.  LABELP and TABLEP may be NULL.  */

3520bool
3521tablejump_p (const rtx_insn *insn, rtx_insn **labelp,
    rtx_jump_table_data **tablep)
3523{
if (!JUMP_P (insn)(((enum rtx_code) (insn)->code) == JUMP_INSN))
  return false;

rtx target = JUMP_LABEL (insn)(((insn)->u.fld[7]).rt_rtx);
if (target == NULL_RTX(rtx) 0 || ANY_RETURN_P (target)(((enum rtx_code) (target)->code) == RETURN || ((enum rtx_code
) (target)->code) == SIMPLE_RETURN))
  return false;

rtx_insn *label = as_a<rtx_insn *> (target);
rtx_insn *table = next_insn (label);
if (table == NULL_RTX(rtx) 0 || !JUMP_TABLE_DATA_P (table)(((enum rtx_code) (table)->code) == JUMP_TABLE_DATA))
  return false;

if (labelp)
  *labelp = label;
if (tablep)
  *tablep = as_a <rtx_jump_table_data *> (table);
return true;
3541}

3543/* For INSN known to satisfy tablejump_p, determine if it actually is a
 CASESI.  Return the insn pattern if so, NULL_RTX otherwise.  */

3546rtx
3547tablejump_casesi_pattern (const rtx_insn *insn)
3548{
rtx tmp;

if ((tmp = single_set (insn)) != NULLnullptr
    && SET_DEST (tmp)(((tmp)->u.fld[0]).rt_rtx) == pc_rtx
    && GET_CODE (SET_SRC (tmp))((enum rtx_code) ((((tmp)->u.fld[1]).rt_rtx))->code) == IF_THEN_ELSE
    && GET_CODE (XEXP (SET_SRC (tmp), 2))((enum rtx_code) (((((((tmp)->u.fld[1]).rt_rtx))->u.fld
[2]).rt_rtx))->code) == LABEL_REF)
  return tmp;

return NULL_RTX(rtx) 0;
3558}

3560/* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
 constant that is not in the constant pool and not in the condition
 of an IF_THEN_ELSE.  */

3564static int
3565computed_jump_p_1 (const_rtx x)
3566{
const enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
int i, j;
const char *fmt;

switch (code)
  {
  case LABEL_REF:
  case PC:
    return 0;

  case CONST:
  CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
 CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR:
  case SYMBOL_REF:
  case REG:
    return 1;

  case MEM:
    return ! (GET_CODE (XEXP (x, 0))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))(__extension__ ({ __typeof (((((x)->u.fld[0]).rt_rtx))) const
 _rtx = (((((x)->u.fld[0]).rt_rtx))); if (((enum rtx_code)
 (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag ("CONSTANT_POOL_ADDRESS_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3585, __FUNCTION__); _rtx; })->unchanging));

  case IF_THEN_ELSE:
    return (computed_jump_p_1 (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
     || computed_jump_p_1 (XEXP (x, 2)(((x)->u.fld[2]).rt_rtx)));

  default:
    break;
  }

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'e'
 && computed_jump_p_1 (XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
return 1;

    else if (fmt[i] == 'E')
for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
 if (computed_jump_p_1 (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
   return 1;
  }

return 0;
3609}

3611/* Return nonzero if INSN is an indirect jump (aka computed jump).

 Tablejumps and casesi insns are not considered indirect jumps;
 we can recognize them by a (use (label_ref)).  */

3616int
3617computed_jump_p (const rtx_insn *insn)
3618{
int i;
if (JUMP_P (insn)(((enum rtx_code) (insn)->code) == JUMP_INSN))
  {
    rtx pat = PATTERN (insn);

    /* If we have a JUMP_LABEL set, we're not a computed jump.  */
    if (JUMP_LABEL (insn)(((insn)->u.fld[7]).rt_rtx) != NULLnullptr)
return 0;

    if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
{
 int len = XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem);
 int has_use_labelref = 0;

 for (i = len - 1; i >= 0; i--)
   if (GET_CODE (XVECEXP (pat, 0, i))((enum rtx_code) ((((((pat)->u.fld[0]).rt_rtvec))->elem
[i]))->code) == USE
&& (GET_CODE (XEXP (XVECEXP (pat, 0, i), 0))((enum rtx_code) (((((((((pat)->u.fld[0]).rt_rtvec))->elem
[i]))->u.fld[0]).rt_rtx))->code)
    == LABEL_REF))
     {
       has_use_labelref = 1;
       break;
     }

 if (! has_use_labelref)
   for (i = len - 1; i >= 0; i--)
     if (GET_CODE (XVECEXP (pat, 0, i))((enum rtx_code) ((((((pat)->u.fld[0]).rt_rtvec))->elem
[i]))->code) == SET
  && SET_DEST (XVECEXP (pat, 0, i))((((((((pat)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx) == pc_rtx
  && computed_jump_p_1 (SET_SRC (XVECEXP (pat, 0, i))((((((((pat)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[1]).rt_rtx)))
return 1;
}
    else if (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET
      && SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx) == pc_rtx
      && computed_jump_p_1 (SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx)))
return 1;
  }
return 0;
3655}

3657

3659/* MEM has a PRE/POST-INC/DEC/MODIFY address X.  Extract the operands of
 the equivalent add insn and pass the result to FN, using DATA as the
 final argument.  */

3663static int
3664for_each_inc_dec_find_inc_dec (rtx mem, for_each_inc_dec_fn fn, void *data)
3665{
rtx x = XEXP (mem, 0)(((mem)->u.fld[0]).rt_rtx);
switch (GET_CODE (x)((enum rtx_code) (x)->code))
  {
  case PRE_INC:
  case POST_INC:
    {
poly_int64 size = GET_MODE_SIZE (GET_MODE (mem)((machine_mode) (mem)->mode));
rtx r1 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
rtx c = gen_int_mode (size, GET_MODE (r1)((machine_mode) (r1)->mode));
return fn (mem, x, r1, r1, c, data);
    }

  case PRE_DEC:
  case POST_DEC:
    {
poly_int64 size = GET_MODE_SIZE (GET_MODE (mem)((machine_mode) (mem)->mode));
rtx r1 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
rtx c = gen_int_mode (-size, GET_MODE (r1)((machine_mode) (r1)->mode));
return fn (mem, x, r1, r1, c, data);
    }

  case PRE_MODIFY:
  case POST_MODIFY:
    {
rtx r1 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
rtx add = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);
return fn (mem, x, r1, add, NULLnullptr, data);
    }

  default:
    gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3696, __FUNCTION__));
  }
3698}

3700/* Traverse *LOC looking for MEMs that have autoinc addresses.
 For each such autoinc operation found, call FN, passing it
 the innermost enclosing MEM, the operation itself, the RTX modified
 by the operation, two RTXs (the second may be NULL) that, once
 added, represent the value to be held by the modified RTX
 afterwards, and DATA.  FN is to return 0 to continue the
 traversal or any other value to have it returned to the caller of
 for_each_inc_dec.  */

3709int
3710for_each_inc_dec (rtx x,
  for_each_inc_dec_fn fn,
  void *data)
3713{
subrtx_var_iterator::array_type array;
FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST)for (subrtx_var_iterator iter (array, x, rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
  {
    rtx mem = *iter;
    if (mem
 && MEM_P (mem)(((enum rtx_code) (mem)->code) == MEM)
 && GET_RTX_CLASS (GET_CODE (XEXP (mem, 0)))(rtx_class[(int) (((enum rtx_code) ((((mem)->u.fld[0]).rt_rtx
))->code))]) == RTX_AUTOINC)
{
 int res = for_each_inc_dec_find_inc_dec (mem, fn, data);
 if (res != 0)
   return res;
 iter.skip_subrtxes ();
}
  }
return 0;
3729}

3731
3732/* Searches X for any reference to REGNO, returning the rtx of the
 reference found if any.  Otherwise, returns NULL_RTX.  */

3735rtx
3736regno_use_in (unsigned int regno, rtx x)
3737{
const char *fmt;
int i, j;
rtx tem;

if (REG_P (x)(((enum rtx_code) (x)->code) == REG) && REGNO (x)(rhs_regno(x)) == regno)
  return x;

fmt = GET_RTX_FORMAT (GET_CODE (x))(rtx_format[(int) (((enum rtx_code) (x)->code))]);
for (i = GET_RTX_LENGTH (GET_CODE (x))(rtx_length[(int) (((enum rtx_code) (x)->code))]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'e')
{
 if ((tem = regno_use_in (regno, XEXP (x, i)(((x)->u.fld[i]).rt_rtx))))
   return tem;
}
    else if (fmt[i] == 'E')
for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
 if ((tem = regno_use_in (regno , XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]))))
   return tem;
  }

return NULL_RTX(rtx) 0;
3760}

3762/* Return a value indicating whether OP, an operand of a commutative
 operation, is preferred as the first or second operand.  The more
 positive the value, the stronger the preference for being the first
 operand.  */

3767int
3768commutative_operand_precedence (rtx op)
3769{
enum rtx_code code = GET_CODE (op)((enum rtx_code) (op)->code);

/* Constants always become the second operand.  Prefer "nice" constants.  */
if (code == CONST_INT)
  return -10;
if (code == CONST_WIDE_INT)
  return -9;
if (code == CONST_POLY_INT)
  return -8;
if (code == CONST_DOUBLE)
  return -8;
if (code == CONST_FIXED)
  return -8;
op = avoid_constant_pool_reference (op);
code = GET_CODE (op)((enum rtx_code) (op)->code);

switch (GET_RTX_CLASS (code)(rtx_class[(int) (code)]))
  {
  case RTX_CONST_OBJ:
    if (code == CONST_INT)
return -7;
    if (code == CONST_WIDE_INT)
return -6;
    if (code == CONST_POLY_INT)
return -5;
    if (code == CONST_DOUBLE)
return -5;
    if (code == CONST_FIXED)
return -5;
    return -4;

  case RTX_EXTRA:
    /* SUBREGs of objects should come second.  */
    if (code == SUBREG && OBJECT_P (SUBREG_REG (op))(((rtx_class[(int) (((enum rtx_code) ((((op)->u.fld[0]).rt_rtx
))->code))]) & (~1)) == (RTX_OBJ & (~1))))
      return -3;
    return 0;

  case RTX_OBJ:
    /* Complex expressions should be the first, so decrease priority
       of objects.  Prefer pointer objects over non pointer objects.  */
    if ((REG_P (op)(((enum rtx_code) (op)->code) == REG) && REG_POINTER (op)(__extension__ ({ __typeof ((op)) const _rtx = ((op)); if (((
enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
 ("REG_POINTER", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3810, __FUNCTION__); _rtx; })->frame_related))
 || (MEM_P (op)(((enum rtx_code) (op)->code) == MEM) && MEM_POINTER (op)(__extension__ ({ __typeof ((op)) const _rtx = ((op)); if (((
enum rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag
 ("MEM_POINTER", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3811, __FUNCTION__); _rtx; })->frame_related)))
return -1;
    return -2;

  case RTX_COMM_ARITH:
    /* Prefer operands that are themselves commutative to be first.
       This helps to make things linear.  In particular,
       (and (and (reg) (reg)) (not (reg))) is canonical.  */
    return 4;

  case RTX_BIN_ARITH:
    /* If only one operand is a binary expression, it will be the first
       operand.  In particular,  (plus (minus (reg) (reg)) (neg (reg)))
       is canonical, although it will usually be further simplified.  */
    return 2;

  case RTX_UNARY:
    /* Then prefer NEG and NOT.  */
    if (code == NEG || code == NOT)
      return 1;
    /* FALLTHRU */

  default:
    return 0;
  }
3836}

3838/* Return 1 iff it is necessary to swap operands of commutative operation
 in order to canonicalize expression.  */

3841bool
3842swap_commutative_operands_p (rtx x, rtx y)
3843{
return (commutative_operand_precedence (x)
 < commutative_operand_precedence (y));
3846}

3848/* Return 1 if X is an autoincrement side effect and the register is
 not the stack pointer.  */
3850int
3851auto_inc_p (const_rtx x)
3852{
switch (GET_CODE (x)((enum rtx_code) (x)->code))
  {
  case PRE_INC:
  case POST_INC:
  case PRE_DEC:
  case POST_DEC:
  case PRE_MODIFY:
  case POST_MODIFY:
    /* There are no REG_INC notes for SP.  */
    if (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) != stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
return 1;
  default:
    break;
  }
return 0;
3868}

3870/* Return nonzero if IN contains a piece of rtl that has the address LOC.  */
3871int
3872loc_mentioned_in_p (rtx *loc, const_rtx in)
3873{
enum rtx_code code;
const char *fmt;
int i, j;

if (!in)
  return 0;

code = GET_CODE (in)((enum rtx_code) (in)->code);
fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  {
    if (fmt[i] == 'e')
{
 if (loc == &XEXP (in, i)(((in)->u.fld[i]).rt_rtx) || loc_mentioned_in_p (loc, XEXP (in, i)(((in)->u.fld[i]).rt_rtx)))
   return 1;
}
    else if (fmt[i] == 'E')
for (j = XVECLEN (in, i)(((((in)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
 if (loc == &XVECEXP (in, i, j)(((((in)->u.fld[i]).rt_rtvec))->elem[j])
     || loc_mentioned_in_p (loc, XVECEXP (in, i, j)(((((in)->u.fld[i]).rt_rtvec))->elem[j])))
   return 1;
  }
return 0;
3897}

3899/* Reinterpret a subreg as a bit extraction from an integer and return
 the position of the least significant bit of the extracted value.
 In other words, if the extraction were performed as a shift right
 and mask, return the number of bits to shift right.

 The outer value of the subreg has OUTER_BYTES bytes and starts at
 byte offset SUBREG_BYTE within an inner value of INNER_BYTES bytes.  */

3907poly_uint64
3908subreg_size_lsb (poly_uint64 outer_bytes,
 poly_uint64 inner_bytes,
 poly_uint64 subreg_byte)
3911{
poly_uint64 subreg_end, trailing_bytes, byte_pos;

/* A paradoxical subreg begins at bit position 0.  */
gcc_checking_assert (ordered_p (outer_bytes, inner_bytes))((void)(!(ordered_p (outer_bytes, inner_bytes)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3915, __FUNCTION__), 0 : 0));
if (maybe_gt (outer_bytes, inner_bytes)maybe_lt (inner_bytes, outer_bytes))
  {
    gcc_checking_assert (known_eq (subreg_byte, 0U))((void)(!((!maybe_ne (subreg_byte, 0U))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3918, __FUNCTION__), 0 : 0));
    return 0;
  }

subreg_end = subreg_byte + outer_bytes;
trailing_bytes = inner_bytes - subreg_end;
if (WORDS_BIG_ENDIAN0 && BYTES_BIG_ENDIAN0)
  byte_pos = trailing_bytes;
else if (!WORDS_BIG_ENDIAN0 && !BYTES_BIG_ENDIAN0)
  byte_pos = subreg_byte;
else
  {
    /* When bytes and words have opposite endianness, we must be able
to split offsets into words and bytes at compile time.  */
    poly_uint64 leading_word_part
= force_align_down (subreg_byte, UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
 0) ? 8 : 4));
    poly_uint64 trailing_word_part
= force_align_down (trailing_bytes, UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
 0) ? 8 : 4));
    /* If the subreg crosses a word boundary ensure that
it also begins and ends on a word boundary.  */
    gcc_assert (known_le (subreg_end - leading_word_part,((void)(!((!maybe_lt ((unsigned int) (((global_options.x_ix86_isa_flags
 & (1UL << 1)) != 0) ? 8 : 4), subreg_end - leading_word_part
)) || ((!maybe_ne (leading_word_part, subreg_byte)) &&
 (!maybe_ne (trailing_word_part, trailing_bytes)))) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3941, __FUNCTION__), 0 : 0))
	    (unsigned int) UNITS_PER_WORD)((void)(!((!maybe_lt ((unsigned int) (((global_options.x_ix86_isa_flags
 & (1UL << 1)) != 0) ? 8 : 4), subreg_end - leading_word_part
)) || ((!maybe_ne (leading_word_part, subreg_byte)) &&
 (!maybe_ne (trailing_word_part, trailing_bytes)))) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3941, __FUNCTION__), 0 : 0))
  || (known_eq (leading_word_part, subreg_byte)((void)(!((!maybe_lt ((unsigned int) (((global_options.x_ix86_isa_flags
 & (1UL << 1)) != 0) ? 8 : 4), subreg_end - leading_word_part
)) || ((!maybe_ne (leading_word_part, subreg_byte)) &&
 (!maybe_ne (trailing_word_part, trailing_bytes)))) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3941, __FUNCTION__), 0 : 0))
      && known_eq (trailing_word_part, trailing_bytes)))((void)(!((!maybe_lt ((unsigned int) (((global_options.x_ix86_isa_flags
 & (1UL << 1)) != 0) ? 8 : 4), subreg_end - leading_word_part
)) || ((!maybe_ne (leading_word_part, subreg_byte)) &&
 (!maybe_ne (trailing_word_part, trailing_bytes)))) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3941, __FUNCTION__), 0 : 0));
    if (WORDS_BIG_ENDIAN0)
byte_pos = trailing_word_part + (subreg_byte - leading_word_part);
    else
byte_pos = leading_word_part + (trailing_bytes - trailing_word_part);
  }

return byte_pos * BITS_PER_UNIT(8);
3949}

3951/* Given a subreg X, return the bit offset where the subreg begins
 (counting from the least significant bit of the reg).  */

3954poly_uint64
3955subreg_lsb (const_rtx x)
3956{
return subreg_lsb_1 (GET_MODE (x)((machine_mode) (x)->mode), GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode),
       SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg));
3959}

3961/* Return the subreg byte offset for a subreg whose outer value has
 OUTER_BYTES bytes, whose inner value has INNER_BYTES bytes, and where
 there are LSB_SHIFT *bits* between the lsb of the outer value and the
 lsb of the inner value.  This is the inverse of the calculation
 performed by subreg_lsb_1 (which converts byte offsets to bit shifts).  */

3967poly_uint64
3968subreg_size_offset_from_lsb (poly_uint64 outer_bytes, poly_uint64 inner_bytes,
	     poly_uint64 lsb_shift)
3970{
/* A paradoxical subreg begins at bit position 0.  */
gcc_checking_assert (ordered_p (outer_bytes, inner_bytes))((void)(!(ordered_p (outer_bytes, inner_bytes)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3972, __FUNCTION__), 0 : 0));
if (maybe_gt (outer_bytes, inner_bytes)maybe_lt (inner_bytes, outer_bytes))
  {
    gcc_checking_assert (known_eq (lsb_shift, 0U))((void)(!((!maybe_ne (lsb_shift, 0U))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 3975, __FUNCTION__), 0 : 0));
    return 0;
  }

poly_uint64 lower_bytes = exact_div (lsb_shift, BITS_PER_UNIT(8));
poly_uint64 upper_bytes = inner_bytes - (lower_bytes + outer_bytes);
if (WORDS_BIG_ENDIAN0 && BYTES_BIG_ENDIAN0)
  return upper_bytes;
else if (!WORDS_BIG_ENDIAN0 && !BYTES_BIG_ENDIAN0)
  return lower_bytes;
else
  {
    /* When bytes and words have opposite endianness, we must be able
to split offsets into words and bytes at compile time.  */
    poly_uint64 lower_word_part = force_align_down (lower_bytes,
				      UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
 0) ? 8 : 4));
    poly_uint64 upper_word_part = force_align_down (upper_bytes,
				      UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
 0) ? 8 : 4));
    if (WORDS_BIG_ENDIAN0)
return upper_word_part + (lower_bytes - lower_word_part);
    else
return lower_word_part + (upper_bytes - upper_word_part);
  }
3998}

4000/* Fill in information about a subreg of a hard register.
 xregno - A regno of an inner hard subreg_reg (or what will become one).
 xmode  - The mode of xregno.
 offset - The byte offset.
 ymode  - The mode of a top level SUBREG (or what may become one).
 info   - Pointer to structure to fill in.

 Rather than considering one particular inner register (and thus one
 particular "outer" register) in isolation, this function really uses
 XREGNO as a model for a sequence of isomorphic hard registers.  Thus the
 function does not check whether adding INFO->offset to XREGNO gives
 a valid hard register; even if INFO->offset + XREGNO is out of range,
 there might be another register of the same type that is in range.
 Likewise it doesn't check whether targetm.hard_regno_mode_ok accepts
 the new register, since that can depend on things like whether the final
 register number is even or odd.  Callers that want to check whether
 this particular subreg can be replaced by a simple (reg ...) should
 use simplify_subreg_regno.  */

4019void
4020subreg_get_info (unsigned int xregno, machine_mode xmode,
 poly_uint64 offset, machine_mode ymode,
 struct subreg_info *info)
4023{
unsigned int nregs_xmode, nregs_ymode;

gcc_assert (xregno < FIRST_PSEUDO_REGISTER)((void)(!(xregno < 76) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4026, __FUNCTION__), 0 : 0));

poly_uint64 xsize = GET_MODE_SIZE (xmode);
poly_uint64 ysize = GET_MODE_SIZE (ymode);

bool rknown = false;

/* If the register representation of a non-scalar mode has holes in it,
   we expect the scalar units to be concatenated together, with the holes
   distributed evenly among the scalar units.  Each scalar unit must occupy
   at least one register.  */
if (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode)(((global_options.x_target_flags & (1U << 0)) != 0)
 && !((global_options.x_ix86_isa_flags & (1UL <<
 1)) != 0) && ((((unsigned long) ((xregno)) - (unsigned
 long) (0) <= (unsigned long) (7) - (unsigned long) (0))) ||
 ((unsigned long) ((xregno)) - (unsigned long) (36) <= (unsigned
 long) (43) - (unsigned long) (36))) && ((xmode) == (
scalar_float_mode ((scalar_float_mode::from_int) E_XFmode)) ||
 (xmode) == (complex_mode ((complex_mode::from_int) E_XCmode)
))))
  {
    /* As a consequence, we must be dealing with a constant number of
scalars, and thus a constant offset and number of units.  */
    HOST_WIDE_INTlong coffset = offset.to_constant ();
    HOST_WIDE_INTlong cysize = ysize.to_constant ();
    nregs_xmode = HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode)((xmode) == (scalar_float_mode ((scalar_float_mode::from_int)
 E_XFmode)) ? 4 : 8);
    unsigned int nunits = GET_MODE_NUNITS (xmode).to_constant ();
    scalar_mode xmode_unit = GET_MODE_INNER (xmode)(mode_to_inner (xmode));
    gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode_unit))((void)(!((((global_options.x_target_flags & (1U <<
 0)) != 0) && !((global_options.x_ix86_isa_flags &
 (1UL << 1)) != 0) && ((((unsigned long) ((xregno
)) - (unsigned long) (0) <= (unsigned long) (7) - (unsigned
 long) (0))) || ((unsigned long) ((xregno)) - (unsigned long)
 (36) <= (unsigned long) (43) - (unsigned long) (36))) &&
 ((xmode_unit) == (scalar_float_mode ((scalar_float_mode::from_int
) E_XFmode)) || (xmode_unit) == (complex_mode ((complex_mode::
from_int) E_XCmode))))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4046, __FUNCTION__), 0 : 0));
    gcc_assert (nregs_xmode((void)(!(nregs_xmode == (nunits * ((xmode_unit) == (scalar_float_mode
 ((scalar_float_mode::from_int) E_XFmode)) ? 4 : 8))) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4049, __FUNCTION__), 0 : 0))
  == (nunits((void)(!(nregs_xmode == (nunits * ((xmode_unit) == (scalar_float_mode
 ((scalar_float_mode::from_int) E_XFmode)) ? 4 : 8))) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4049, __FUNCTION__), 0 : 0))
      * HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode_unit)))((void)(!(nregs_xmode == (nunits * ((xmode_unit) == (scalar_float_mode
 ((scalar_float_mode::from_int) E_XFmode)) ? 4 : 8))) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4049, __FUNCTION__), 0 : 0));
    gcc_assert (hard_regno_nregs (xregno, xmode)((void)(!(hard_regno_nregs (xregno, xmode) == hard_regno_nregs
 (xregno, xmode_unit) * nunits) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4051, __FUNCTION__), 0 : 0))
  == hard_regno_nregs (xregno, xmode_unit) * nunits)((void)(!(hard_regno_nregs (xregno, xmode) == hard_regno_nregs
 (xregno, xmode_unit) * nunits) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4051, __FUNCTION__), 0 : 0));

    /* You can only ask for a SUBREG of a value with holes in the middle
if you don't cross the holes.  (Such a SUBREG should be done by
picking a different register class, or doing it in memory if
necessary.)  An example of a value with holes is XCmode on 32-bit
x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
3 for each part, but in memory it's two 128-bit parts.
Padding is assumed to be at the end (not necessarily the 'high part')
of each unit.  */
    if ((coffset / GET_MODE_SIZE (xmode_unit) + 1 < nunits)
 && (coffset / GET_MODE_SIZE (xmode_unit)
     != ((coffset + cysize - 1) / GET_MODE_SIZE (xmode_unit))))
{
 info->representable_p = false;
 rknown = true;
}
  }
else
  nregs_xmode = hard_regno_nregs (xregno, xmode);

nregs_ymode = hard_regno_nregs (xregno, ymode);

/* Subreg sizes must be ordered, so that we can tell whether they are
   partial, paradoxical or complete.  */
gcc_checking_assert (ordered_p (xsize, ysize))((void)(!(ordered_p (xsize, ysize)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4076, __FUNCTION__), 0 : 0));

/* Paradoxical subregs are otherwise valid.  */
if (!rknown && known_eq (offset, 0U)(!maybe_ne (offset, 0U)) && maybe_gt (ysize, xsize)maybe_lt (xsize, ysize))
  {
    info->representable_p = true;
    /* If this is a big endian paradoxical subreg, which uses more
actual hard registers than the original register, we must
return a negative offset so that we find the proper highpart
of the register.

We assume that the ordering of registers within a multi-register
value has a consistent endianness: if bytes and register words
have different endianness, the hard registers that make up a
multi-register value must be at least word-sized.  */
    if (REG_WORDS_BIG_ENDIAN0)
info->offset = (int) nregs_xmode - (int) nregs_ymode;
    else
info->offset = 0;
    info->nregs = nregs_ymode;
    return;
  }

/* If registers store different numbers of bits in the different
   modes, we cannot generally form this subreg.  */
poly_uint64 regsize_xmode, regsize_ymode;
if (!HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode)(((global_options.x_target_flags & (1U << 0)) != 0)
 && !((global_options.x_ix86_isa_flags & (1UL <<
 1)) != 0) && ((((unsigned long) ((xregno)) - (unsigned
 long) (0) <= (unsigned long) (7) - (unsigned long) (0))) ||
 ((unsigned long) ((xregno)) - (unsigned long) (36) <= (unsigned
 long) (43) - (unsigned long) (36))) && ((xmode) == (
scalar_float_mode ((scalar_float_mode::from_int) E_XFmode)) ||
 (xmode) == (complex_mode ((complex_mode::from_int) E_XCmode)
)))
    && !HARD_REGNO_NREGS_HAS_PADDING (xregno, ymode)(((global_options.x_target_flags & (1U << 0)) != 0)
 && !((global_options.x_ix86_isa_flags & (1UL <<
 1)) != 0) && ((((unsigned long) ((xregno)) - (unsigned
 long) (0) <= (unsigned long) (7) - (unsigned long) (0))) ||
 ((unsigned long) ((xregno)) - (unsigned long) (36) <= (unsigned
 long) (43) - (unsigned long) (36))) && ((ymode) == (
scalar_float_mode ((scalar_float_mode::from_int) E_XFmode)) ||
 (ymode) == (complex_mode ((complex_mode::from_int) E_XCmode)
)))
    && multiple_p (xsize, nregs_xmode, &regsize_xmode)
    && multiple_p (ysize, nregs_ymode, &regsize_ymode))
  {
    if (!rknown
 && ((nregs_ymode > 1 && maybe_gt (regsize_xmode, regsize_ymode)maybe_lt (regsize_ymode, regsize_xmode))
     || (nregs_xmode > 1 && maybe_gt (regsize_ymode, regsize_xmode)maybe_lt (regsize_xmode, regsize_ymode))))
{
 info->representable_p = false;
 if (!can_div_away_from_zero_p (ysize, regsize_xmode, &info->nregs)
     || !can_div_trunc_p (offset, regsize_xmode, &info->offset))
   /* Checked by validate_subreg.  We must know at compile time
      which inner registers are being accessed.  */
   gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4116, __FUNCTION__));
 return;
}
    /* It's not valid to extract a subreg of mode YMODE at OFFSET that
would go outside of XMODE.  */
    if (!rknown && maybe_gt (ysize + offset, xsize)maybe_lt (xsize, ysize + offset))
{
 info->representable_p = false;
 info->nregs = nregs_ymode;
 if (!can_div_trunc_p (offset, regsize_xmode, &info->offset))
   /* Checked by validate_subreg.  We must know at compile time
      which inner registers are being accessed.  */
   gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4128, __FUNCTION__));
 return;
}
    /* Quick exit for the simple and common case of extracting whole
subregisters from a multiregister value.  */
    /* ??? It would be better to integrate this into the code below,
if we can generalize the concept enough and figure out how
odd-sized modes can coexist with the other weird cases we support.  */
    HOST_WIDE_INTlong count;
    if (!rknown
 && WORDS_BIG_ENDIAN0 == REG_WORDS_BIG_ENDIAN0
 && known_eq (regsize_xmode, regsize_ymode)(!maybe_ne (regsize_xmode, regsize_ymode))
 && constant_multiple_p (offset, regsize_ymode, &count))
{
 info->representable_p = true;
 info->nregs = nregs_ymode;
 info->offset = count;
 gcc_assert (info->offset + info->nregs <= (int) nregs_xmode)((void)(!(info->offset + info->nregs <= (int) nregs_xmode
) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4145, __FUNCTION__), 0 : 0));
 return;
}
  }

/* Lowpart subregs are otherwise valid.  */
if (!rknown && known_eq (offset, subreg_lowpart_offset (ymode, xmode))(!maybe_ne (offset, subreg_lowpart_offset (ymode, xmode))))
  {
    info->representable_p = true;
    rknown = true;

    if (known_eq (offset, 0U)(!maybe_ne (offset, 0U)) || nregs_xmode == nregs_ymode)
{
 info->offset = 0;
 info->nregs = nregs_ymode;
 return;
}
  }

/* Set NUM_BLOCKS to the number of independently-representable YMODE
   values there are in (reg:XMODE XREGNO).  We can view the register
   as consisting of this number of independent "blocks", where each
   block occupies NREGS_YMODE registers and contains exactly one
   representable YMODE value.  */
gcc_assert ((nregs_xmode % nregs_ymode) == 0)((void)(!((nregs_xmode % nregs_ymode) == 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4169, __FUNCTION__), 0 : 0));
unsigned int num_blocks = nregs_xmode / nregs_ymode;

/* Calculate the number of bytes in each block.  This must always
   be exact, otherwise we don't know how to verify the constraint.
   These conditions may be relaxed but subreg_regno_offset would
   need to be redesigned.  */
poly_uint64 bytes_per_block = exact_div (xsize, num_blocks);

/* Get the number of the first block that contains the subreg and the byte
   offset of the subreg from the start of that block.  */
unsigned int block_number;
poly_uint64 subblock_offset;
if (!can_div_trunc_p (offset, bytes_per_block, &block_number,
	&subblock_offset))
  /* Checked by validate_subreg.  We must know at compile time which
     inner registers are being accessed.  */
  gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4186, __FUNCTION__));

if (!rknown)
  {
    /* Only the lowpart of each block is representable.  */
    info->representable_p
= known_eq (subblock_offset,(!maybe_ne (subblock_offset, subreg_size_lowpart_offset (ysize
, bytes_per_block)))
    subreg_size_lowpart_offset (ysize, bytes_per_block))(!maybe_ne (subblock_offset, subreg_size_lowpart_offset (ysize
, bytes_per_block)));
    rknown = true;
  }

/* We assume that the ordering of registers within a multi-register
   value has a consistent endianness: if bytes and register words
   have different endianness, the hard registers that make up a
   multi-register value must be at least word-sized.  */
if (WORDS_BIG_ENDIAN0 != REG_WORDS_BIG_ENDIAN0)
  /* The block number we calculated above followed memory endianness.
     Convert it to register endianness by counting back from the end.
     (Note that, because of the assumption above, each block must be
     at least word-sized.)  */
  info->offset = (num_blocks - block_number - 1) * nregs_ymode;
else
  info->offset = block_number * nregs_ymode;
info->nregs = nregs_ymode;
4210}

4212/* This function returns the regno offset of a subreg expression.
 xregno - A regno of an inner hard subreg_reg (or what will become one).
 xmode  - The mode of xregno.
 offset - The byte offset.
 ymode  - The mode of a top level SUBREG (or what may become one).
 RETURN - The regno offset which would be used.  */
4218unsigned int
4219subreg_regno_offset (unsigned int xregno, machine_mode xmode,
     poly_uint64 offset, machine_mode ymode)
4221{
struct subreg_info info;
subreg_get_info (xregno, xmode, offset, ymode, &info);
return info.offset;
4225}

4227/* This function returns true when the offset is representable via
 subreg_offset in the given regno.
 xregno - A regno of an inner hard subreg_reg (or what will become one).
 xmode  - The mode of xregno.
 offset - The byte offset.
 ymode  - The mode of a top level SUBREG (or what may become one).
 RETURN - Whether the offset is representable.  */
4234bool
4235subreg_offset_representable_p (unsigned int xregno, machine_mode xmode,
	       poly_uint64 offset, machine_mode ymode)
4237{
struct subreg_info info;
subreg_get_info (xregno, xmode, offset, ymode, &info);
return info.representable_p;
4241}

4243/* Return the number of a YMODE register to which

     (subreg:YMODE (reg:XMODE XREGNO) OFFSET)

 can be simplified.  Return -1 if the subreg can't be simplified.

 XREGNO is a hard register number.  */

4251int
4252simplify_subreg_regno (unsigned int xregno, machine_mode xmode,
       poly_uint64 offset, machine_mode ymode)
4254{
struct subreg_info info;
unsigned int yregno;

/* Give the backend a chance to disallow the mode change.  */
if (GET_MODE_CLASS (xmode)((enum mode_class) mode_class[xmode]) != MODE_COMPLEX_INT
    && GET_MODE_CLASS (xmode)((enum mode_class) mode_class[xmode]) != MODE_COMPLEX_FLOAT
    && !REG_CAN_CHANGE_MODE_P (xregno, xmode, ymode)(targetm.can_change_mode_class (xmode, ymode, (regclass_map[(
xregno)]))))
  return -1;

/* We shouldn't simplify stack-related registers.  */
if ((!reload_completed || frame_pointer_needed((&x_rtl)->frame_pointer_needed))
    && xregno == FRAME_POINTER_REGNUM19)
  return -1;

if (FRAME_POINTER_REGNUM19 != ARG_POINTER_REGNUM16
    && xregno == ARG_POINTER_REGNUM16)
  return -1;

if (xregno == STACK_POINTER_REGNUM7
    /* We should convert hard stack register in LRA if it is
possible.  */
    && ! lra_in_progress)
  return -1;

/* Try to get the register offset.  */
subreg_get_info (xregno, xmode, offset, ymode, &info);
if (!info.representable_p)
  return -1;

/* Make sure that the offsetted register value is in range.  */
yregno = xregno + info.offset;
if (!HARD_REGISTER_NUM_P (yregno)((yregno) < 76))
  return -1;

/* See whether (reg:YMODE YREGNO) is valid.

   ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
   This is a kludge to work around how complex FP arguments are passed
   on IA-64 and should be fixed.  See PR target/49226.  */
if (!targetm.hard_regno_mode_ok (yregno, ymode)
    && targetm.hard_regno_mode_ok (xregno, xmode))
  return -1;

return (int) yregno;
4299}

4301/* A wrapper around simplify_subreg_regno that uses subreg_lowpart_offset
 (xmode, ymode) as the offset.  */

4304int
4305lowpart_subreg_regno (unsigned int regno, machine_mode xmode,
      machine_mode ymode)
4307{
poly_uint64 offset = subreg_lowpart_offset (xmode, ymode);
return simplify_subreg_regno (regno, xmode, offset, ymode);
4310}

4312/* Return the final regno that a subreg expression refers to.  */
4313unsigned int
4314subreg_regno (const_rtx x)
4315{
unsigned int ret;
rtx subreg = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
int regno = REGNO (subreg)(rhs_regno(subreg));

ret = regno + subreg_regno_offset (regno,
		     GET_MODE (subreg)((machine_mode) (subreg)->mode),
		     SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg),
		     GET_MODE (x)((machine_mode) (x)->mode));
return ret;

4326}

4328/* Return the number of registers that a subreg expression refers
 to.  */
4330unsigned int
4331subreg_nregs (const_rtx x)
4332{
return subreg_nregs_with_regno (REGNO (SUBREG_REG (x))(rhs_regno((((x)->u.fld[0]).rt_rtx))), x);
4334}

4336/* Return the number of registers that a subreg REG with REGNO
 expression refers to.  This is a copy of the rtlanal.cc:subreg_nregs
 changed so that the regno can be passed in. */

4340unsigned int
4341subreg_nregs_with_regno (unsigned int regno, const_rtx x)
4342{
struct subreg_info info;
rtx subreg = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);

subreg_get_info (regno, GET_MODE (subreg)((machine_mode) (subreg)->mode), SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg), GET_MODE (x)((machine_mode) (x)->mode),
   &info);
return info.nregs;
4349}

4351struct parms_set_data
4352{
int nregs;
HARD_REG_SET regs;
4355};

4357/* Helper function for noticing stores to parameter registers.  */
4358static void
4359parms_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED__attribute__ ((__unused__)), void *data)
4360{
struct parms_set_data *const d = (struct parms_set_data *) data;
if (REG_P (x)(((enum rtx_code) (x)->code) == REG) && REGNO (x)(rhs_regno(x)) < FIRST_PSEUDO_REGISTER76
    && TEST_HARD_REG_BIT (d->regs, REGNO (x)(rhs_regno(x))))
  {
    CLEAR_HARD_REG_BIT (d->regs, REGNO (x)(rhs_regno(x)));
    d->nregs--;
  }
4368}

4370/* Look backward for first parameter to be loaded.
 Note that loads of all parameters will not necessarily be
 found if CSE has eliminated some of them (e.g., an argument
 to the outer function is passed down as a parameter).
 Do not skip BOUNDARY.  */
4375rtx_insn *
4376find_first_parameter_load (rtx_insn *call_insn, rtx_insn *boundary)
4377{
struct parms_set_data parm;
rtx p;
rtx_insn *before, *first_set;

/* Since different machines initialize their parameter registers
   in different orders, assume nothing.  Collect the set of all
   parameter registers.  */
CLEAR_HARD_REG_SET (parm.regs);
parm.nregs = 0;
for (p = CALL_INSN_FUNCTION_USAGE (call_insn)(((call_insn)->u.fld[7]).rt_rtx); p; p = XEXP (p, 1)(((p)->u.fld[1]).rt_rtx))
  if (GET_CODE (XEXP (p, 0))((enum rtx_code) ((((p)->u.fld[0]).rt_rtx))->code) == USE
&& REG_P (XEXP (XEXP (p, 0), 0))(((enum rtx_code) (((((((p)->u.fld[0]).rt_rtx))->u.fld[
0]).rt_rtx))->code) == REG)
&& !STATIC_CHAIN_REG_P (XEXP (XEXP (p, 0), 0))(__extension__ ({ __typeof ((((((((p)->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx))) const _rtx = ((((((((p)->u.fld[0]).rt_rtx
))->u.fld[0]).rt_rtx))); if (((enum rtx_code) (_rtx)->code
) != REG) rtl_check_failed_flag ("STATIC_CHAIN_REG_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4390, __FUNCTION__); _rtx; })->jump))
    {
gcc_assert (REGNO (XEXP (XEXP (p, 0), 0)) < FIRST_PSEUDO_REGISTER)((void)(!((rhs_regno(((((((p)->u.fld[0]).rt_rtx))->u.fld
[0]).rt_rtx))) < 76) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4392, __FUNCTION__), 0 : 0));

/* We only care about registers which can hold function
  arguments.  */
if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p, 0), 0)))ix86_function_arg_regno_p ((rhs_regno(((((((p)->u.fld[0]).
rt_rtx))->u.fld[0]).rt_rtx)))))
 continue;

SET_HARD_REG_BIT (parm.regs, REGNO (XEXP (XEXP (p, 0), 0))(rhs_regno(((((((p)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx
))));
parm.nregs++;
    }
before = call_insn;
first_set = call_insn;

/* Search backward for the first set of a register in this set.  */
while (parm.nregs && before != boundary)
  {
    before = PREV_INSN (before);

    /* It is possible that some loads got CSEed from one call to
       another.  Stop in that case.  */
    if (CALL_P (before)(((enum rtx_code) (before)->code) == CALL_INSN))
break;

    /* Our caller needs either ensure that we will find all sets
       (in case code has not been optimized yet), or take care
       for possible labels in a way by setting boundary to preceding
       CODE_LABEL.  */
    if (LABEL_P (before)(((enum rtx_code) (before)->code) == CODE_LABEL))
{
 gcc_assert (before == boundary)((void)(!(before == boundary) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4421, __FUNCTION__), 0 : 0));
 break;
}

    if (INSN_P (before)(((((enum rtx_code) (before)->code) == INSN) || (((enum rtx_code
) (before)->code) == JUMP_INSN) || (((enum rtx_code) (before
)->code) == CALL_INSN)) || (((enum rtx_code) (before)->
code) == DEBUG_INSN)))
{
 int nregs_old = parm.nregs;
 note_stores (before, parms_set, &parm);
 /* If we found something that did not set a parameter reg,
    we're done.  Do not keep going, as that might result
    in hoisting an insn before the setting of a pseudo
    that is used by the hoisted insn. */
 if (nregs_old != parm.nregs)
   first_set = before;
 else
   break;
}
  }
return first_set;
4440}

4442/* Return true if we should avoid inserting code between INSN and preceding
 call instruction.  */

4445bool
4446keep_with_call_p (const rtx_insn *insn)
4447{
rtx set;

if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)) && (set = single_set (insn)) != NULLnullptr)
  {
    if (REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 REG)
 && REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx))) < FIRST_PSEUDO_REGISTER76
 && fixed_regs(this_target_hard_regs->x_fixed_regs)[REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx)))]
 && general_operand (SET_SRC (set)(((set)->u.fld[1]).rt_rtx), VOIDmode((void) 0, E_VOIDmode)))
return true;
    if (REG_P (SET_SRC (set))(((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) ==
 REG)
 && targetm.calls.function_value_regno_p (REGNO (SET_SRC (set))(rhs_regno((((set)->u.fld[1]).rt_rtx))))
 && REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 REG)
 && REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx))) >= FIRST_PSEUDO_REGISTER76)
return true;
    /* There may be a stack pop just after the call and before the store
of the return register.  Search for the actual store when deciding
if we can break or not.  */
    if (SET_DEST (set)(((set)->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
{
 /* This CONST_CAST is okay because next_nonnote_insn just
    returns its argument and we assign it to a const_rtx
    variable.  */
 const rtx_insn *i2
   = next_nonnote_insn (const_cast<rtx_insn *> (insn));
 if (i2 && keep_with_call_p (i2))
   return true;
}
  }
return false;
4477}

4479/* Return true if LABEL is a target of JUMP_INSN.  This applies only
 to non-complex jumps.  That is, direct unconditional, conditional,
 and tablejumps, but not computed jumps or returns.  It also does
 not apply to the fallthru case of a conditional jump.  */

4484bool
4485label_is_jump_target_p (const_rtx label, const rtx_insn *jump_insn)
4486{
rtx tmp = JUMP_LABEL (jump_insn)(((jump_insn)->u.fld[7]).rt_rtx);
rtx_jump_table_data *table;

if (label == tmp)
  return true;

if (tablejump_p (jump_insn, NULLnullptr, &table))
  {
    rtvec vec = table->get_labels ();
    int i, veclen = GET_NUM_ELEM (vec)((vec)->num_elem);

    for (i = 0; i < veclen; ++i)
if (XEXP (RTVEC_ELT (vec, i), 0)(((((vec)->elem[i]))->u.fld[0]).rt_rtx) == label)
 return true;
  }

if (find_reg_note (jump_insn, REG_LABEL_TARGET, label))
  return true;

return false;
4507}

4509
4510/* Return an estimate of the cost of computing rtx X.
 One use is in cse, to decide which expression to keep in the hash table.
 Another is in rtl generation, to pick the cheapest way to multiply.
 Other uses like the latter are expected in the future.

 X appears as operand OPNO in an expression with code OUTER_CODE.
 SPEED specifies whether costs optimized for speed or size should
 be returned.  */

4519int
4520rtx_cost (rtx x, machine_mode mode, enum rtx_code outer_code,
 int opno, bool speed)
4522{
int i, j;
enum rtx_code code;
const char *fmt;
int total;
int factor;
unsigned mode_size;

if (x == 0)
  return 0;

if (GET_CODE (x)((enum rtx_code) (x)->code) == SET)
  /* A SET doesn't have a mode, so let's look at the SET_DEST to get
     the mode for the factor.  */
  mode = GET_MODE (SET_DEST (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
else if (GET_MODE (x)((machine_mode) (x)->mode) != VOIDmode((void) 0, E_VOIDmode))
  mode = GET_MODE (x)((machine_mode) (x)->mode);

mode_size = estimated_poly_value (GET_MODE_SIZE (mode));

/* A size N times larger than UNITS_PER_WORD likely needs N times as
   many insns, taking N times as long.  */
factor = mode_size > UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
 0) ? 8 : 4) ? mode_size / UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
 0) ? 8 : 4) : 1;

/* Compute the default costs of certain things.
   Note that targetm.rtx_costs can override the defaults.  */

code = GET_CODE (x)((enum rtx_code) (x)->code);
switch (code)
  {
  case MULT:
  case FMA:
  case SS_MULT:
  case US_MULT:
  case SMUL_HIGHPART:
  case UMUL_HIGHPART:
    /* Multiplication has time-complexity O(N*N), where N is the
number of units (translated from digits) when using
schoolbook long multiplication.  */
    total = factor * factor * COSTS_N_INSNS (5)((5) * 4);
    break;
  case DIV:
  case UDIV:
  case MOD:
  case UMOD:
  case SS_DIV:
  case US_DIV:
    /* Similarly, complexity for schoolbook long division.  */
    total = factor * factor * COSTS_N_INSNS (7)((7) * 4);
    break;
  case USE:
    /* Used in combine.cc as a marker.  */
    total = 0;
    break;
  default:
    total = factor * COSTS_N_INSNS (1)((1) * 4);
  }

switch (code)
  {
  case REG:
    return 0;

  case SUBREG:
    total = 0;
    /* If we can't tie these modes, make this expensive.  The larger
the mode, the more expensive it is.  */
    if (!targetm.modes_tieable_p (mode, GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode)))
return COSTS_N_INSNS (2 + factor)((2 + factor) * 4);
    break;

  case TRUNCATE:
    if (targetm.modes_tieable_p (mode, GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode)))
{
 total = 0;
 break;
}
    /* FALLTHRU */
  default:
    if (targetm.rtx_costs (x, mode, outer_code, opno, &total, speed))
return total;
    break;
  }

/* Sum the costs of the sub-rtx's, plus cost of this operation,
   which is already in total.  */

fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  if (fmt[i] == 'e')
    total += rtx_cost (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), mode, code, i, speed);
  else if (fmt[i] == 'E')
    for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
total += rtx_cost (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), mode, code, i, speed);

return total;
4618}

4620/* Fill in the structure C with information about both speed and size rtx
 costs for X, which is operand OPNO in an expression with code OUTER.  */

4623void
4624get_full_rtx_cost (rtx x, machine_mode mode, enum rtx_code outer, int opno,
   struct full_rtx_costs *c)
4626{
c->speed = rtx_cost (x, mode, outer, opno, true);
c->size = rtx_cost (x, mode, outer, opno, false);
4629}

4631
4632/* Return cost of address expression X.
 Expect that X is properly formed address reference.

 SPEED parameter specify whether costs optimized for speed or size should
 be returned.  */

4638int
4639address_cost (rtx x, machine_mode mode, addr_space_t as, bool speed)
4640{
/* We may be asked for cost of various unusual addresses, such as operands
   of push instruction.  It is not worthwhile to complicate writing
   of the target hook by such cases.  */

if (!memory_address_addr_space_p (mode, x, as))
  return 1000;

return targetm.address_cost (x, mode, as, speed);
4649}

4651/* If the target doesn't override, compute the cost as with arithmetic.  */

4653int
4654default_address_cost (rtx x, machine_mode, addr_space_t, bool speed)
4655{
return rtx_cost (x, Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), MEM, 0, speed);
4657}
4658

4660unsigned HOST_WIDE_INTlong
4661nonzero_bits (const_rtx x, machine_mode mode)
4662{
if (mode == VOIDmode((void) 0, E_VOIDmode))
  mode = GET_MODE (x)((machine_mode) (x)->mode);
scalar_int_mode int_mode;
if (!is_a <scalar_int_mode> (mode, &int_mode))
  return GET_MODE_MASK (mode)mode_mask_array[mode];
return cached_nonzero_bits (x, int_mode, NULL_RTX(rtx) 0, VOIDmode((void) 0, E_VOIDmode), 0);
4669}

4671unsigned int
4672num_sign_bit_copies (const_rtx x, machine_mode mode)
4673{
if (mode == VOIDmode((void) 0, E_VOIDmode))
  mode = GET_MODE (x)((machine_mode) (x)->mode);
scalar_int_mode int_mode;
if (!is_a <scalar_int_mode> (mode, &int_mode))
  return 1;
return cached_num_sign_bit_copies (x, int_mode, NULL_RTX(rtx) 0, VOIDmode((void) 0, E_VOIDmode), 0);
4680}

4682/* Return true if nonzero_bits1 might recurse into both operands
 of X.  */

4685static inline bool
4686nonzero_bits_binary_arith_p (const_rtx x)
4687{
if (!ARITHMETIC_P (x)(((rtx_class[(int) (((enum rtx_code) (x)->code))]) & (
~1)) == (RTX_COMM_ARITH & (~1))))
  return false;
switch (GET_CODE (x)((enum rtx_code) (x)->code))
  {
  case AND:
  case XOR:
  case IOR:
  case UMIN:
  case UMAX:
  case SMIN:
  case SMAX:
  case PLUS:
  case MINUS:
  case MULT:
  case DIV:
  case UDIV:
  case MOD:
  case UMOD:
    return true;
  default:
    return false;
  }
4710}

4712/* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
 It avoids exponential behavior in nonzero_bits1 when X has
 identical subexpressions on the first or the second level.  */

4716static unsigned HOST_WIDE_INTlong
4717cached_nonzero_bits (const_rtx x, scalar_int_mode mode, const_rtx known_x,
     machine_mode known_mode,
     unsigned HOST_WIDE_INTlong known_ret)
4720{
if (x == known_x && mode == known_mode)
  return known_ret;

/* Try to find identical subexpressions.  If found call
   nonzero_bits1 on X with the subexpressions as KNOWN_X and the
   precomputed value for the subexpression as KNOWN_RET.  */

if (nonzero_bits_binary_arith_p (x))
  {
    rtx x0 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
    rtx x1 = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);

    /* Check the first level.  */
    if (x0 == x1)
return nonzero_bits1 (x, mode, x0, mode,
	      cached_nonzero_bits (x0, mode, known_x,
				   known_mode, known_ret));

    /* Check the second level.  */
    if (nonzero_bits_binary_arith_p (x0)
 && (x1 == XEXP (x0, 0)(((x0)->u.fld[0]).rt_rtx) || x1 == XEXP (x0, 1)(((x0)->u.fld[1]).rt_rtx)))
return nonzero_bits1 (x, mode, x1, mode,
	      cached_nonzero_bits (x1, mode, known_x,
				   known_mode, known_ret));

    if (nonzero_bits_binary_arith_p (x1)
 && (x0 == XEXP (x1, 0)(((x1)->u.fld[0]).rt_rtx) || x0 == XEXP (x1, 1)(((x1)->u.fld[1]).rt_rtx)))
return nonzero_bits1 (x, mode, x0, mode,
	      cached_nonzero_bits (x0, mode, known_x,
				   known_mode, known_ret));
  }

return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
4754}

4756/* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
 We don't let nonzero_bits recur into num_sign_bit_copies, because that
 is less useful.  We can't allow both, because that results in exponential
 run time recursion.  There is a nullstone testcase that triggered
 this.  This macro avoids accidental uses of num_sign_bit_copies.  */
4761#define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior

4763/* Given an expression, X, compute which bits in X can be nonzero.
 We don't care about bits outside of those defined in MODE.

 For most X this is simply GET_MODE_MASK (GET_MODE (X)), but if X is
 an arithmetic operation, we can do better.  */

4769static unsigned HOST_WIDE_INTlong
4770nonzero_bits1 (const_rtx x, scalar_int_mode mode, const_rtx known_x,
      machine_mode known_mode,
      unsigned HOST_WIDE_INTlong known_ret)
4773{
unsigned HOST_WIDE_INTlong nonzero = GET_MODE_MASK (mode)mode_mask_array[mode];
unsigned HOST_WIDE_INTlong inner_nz;
enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
machine_mode inner_mode;
unsigned int inner_width;
scalar_int_mode xmode;

unsigned int mode_width = GET_MODE_PRECISION (mode);

if (CONST_INT_P (x)(((enum rtx_code) (x)->code) == CONST_INT))
1
Assuming field 'code' is not equal to CONST_INT→
2
←
Taking false branch→
  {
    if (SHORT_IMMEDIATES_SIGN_EXTEND0
 && INTVAL (x)((x)->u.hwint[0]) > 0
 && mode_width < BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
 1)) != 0) ? 8 : 4))
 && (UINTVAL (x)((unsigned long) ((x)->u.hwint[0])) & (HOST_WIDE_INT_1U1UL << (mode_width - 1))) != 0)
return UINTVAL (x)((unsigned long) ((x)->u.hwint[0])) | (HOST_WIDE_INT_M1U-1UL << mode_width);

    return UINTVAL (x)((unsigned long) ((x)->u.hwint[0]));
  }

if (!is_a <scalar_int_mode> (GET_MODE (x)((machine_mode) (x)->mode), &xmode))
3
←
Taking false branch→
  return nonzero;
unsigned int xmode_width = GET_MODE_PRECISION (xmode);

/* If X is wider than MODE, use its mode instead.  */
if (xmode_width > mode_width)
4
←
Assuming 'xmode_width' is <= 'mode_width'→
5
←
Taking false branch→
  {
    mode = xmode;
    nonzero = GET_MODE_MASK (mode)mode_mask_array[mode];
    mode_width = xmode_width;
  }

if (mode_width > HOST_BITS_PER_WIDE_INT64)
6
←
Assuming 'mode_width' is <= HOST_BITS_PER_WIDE_INT→
  /* Our only callers in this case look for single bit values.  So
     just return the mode mask.  Those tests will then be false.  */
  return nonzero;

/* If MODE is wider than X, but both are a single word for both the host
   and target machines, we can compute this from which bits of the object
   might be nonzero in its own mode, taking into account the fact that, on
   CISC machines, accessing an object in a wider mode generally causes the
   high-order bits to become undefined, so they are not known to be zero.
   We extend this reasoning to RISC machines for operations that might not
   operate on the full registers.  */
if (mode_width > xmode_width
7
←
Assuming 'mode_width' is <= 'xmode_width'→
    && xmode_width <= BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
 1)) != 0) ? 8 : 4))
    && xmode_width <= HOST_BITS_PER_WIDE_INT64
    && !(WORD_REGISTER_OPERATIONS0 && word_register_operation_p (x)))
  {
    nonzero &= cached_nonzero_bits (x, xmode,
		      known_x, known_mode, known_ret);
    nonzero |= GET_MODE_MASK (mode)mode_mask_array[mode] & ~GET_MODE_MASK (xmode)mode_mask_array[xmode];
    return nonzero;
  }

/* Please keep nonzero_bits_binary_arith_p above in sync with
   the code in the switch below.  */
switch (code)
8
←
Control jumps to 'case CLZ:'  at line 5189→
  {
  case REG:
4834#if defined(POINTERS_EXTEND_UNSIGNED1)
    /* If pointers extend unsigned and this is a pointer in Pmode, say that
all the bits above ptr_mode are known to be zero.  */
    /* As we do not know which address space the pointer is referring to,
we can do this only if the target does not support different pointer
or address modes depending on the address space.  */
    if (target_default_pointer_address_modes_p ()
 && POINTERS_EXTEND_UNSIGNED1
 && xmode == Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
 && REG_POINTER (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag ("REG_POINTER"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 4843, __FUNCTION__); _rtx; })->frame_related)
 && !targetm.have_ptr_extend ())
nonzero &= GET_MODE_MASK (ptr_mode)mode_mask_array[ptr_mode];
4846#endif

    /* Include declared information about alignment of pointers.  */
    /* ??? We don't properly preserve REG_POINTER changes across
pointer-to-integer casts, so we can't trust it except for
things that we know must be pointers.  See execute/960116-1.c.  */
    if ((x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
  || x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER])
  || x == arg_pointer_rtx((this_target_rtl->x_global_rtl)[GR_ARG_POINTER]))
 && REGNO_POINTER_ALIGN (REGNO (x))((&x_rtl)->emit.regno_pointer_align[(rhs_regno(x))]))
{
 unsigned HOST_WIDE_INTlong alignment
   = REGNO_POINTER_ALIGN (REGNO (x))((&x_rtl)->emit.regno_pointer_align[(rhs_regno(x))]) / BITS_PER_UNIT(8);

4860#ifdef PUSH_ROUNDING
 /* If PUSH_ROUNDING is defined, it is possible for the
    stack to be momentarily aligned only to that amount,
    so we pick the least alignment.  */
 if (x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]) && targetm.calls.push_argument (0))
   {
     poly_uint64 rounded_1 = PUSH_ROUNDING (poly_int64 (1))ix86_push_rounding (poly_int64 (1));
     alignment = MIN (known_alignment (rounded_1), alignment)((known_alignment (rounded_1)) < (alignment) ? (known_alignment
 (rounded_1)) : (alignment));
   }
4869#endif

 nonzero &= ~(alignment - 1);
}

    {
unsigned HOST_WIDE_INTlong nonzero_for_hook = nonzero;
rtx new_rtx = rtl_hooks.reg_nonzero_bits (x, xmode, mode,
				  &nonzero_for_hook);

if (new_rtx)
 nonzero_for_hook &= cached_nonzero_bits (new_rtx, mode, known_x,
				   known_mode, known_ret);

return nonzero_for_hook;
    }

  case MEM:
    /* In many, if not most, RISC machines, reading a byte from memory
zeros the rest of the register.  Noticing that fact saves a lot
of extra zero-extends.  */
    if (load_extend_op (xmode) == ZERO_EXTEND)
nonzero &= GET_MODE_MASK (xmode)mode_mask_array[xmode];
    break;

  case EQ:  case NE:
  case UNEQ:  case LTGT:
  case GT:  case GTU:  case UNGT:
  case LT:  case LTU:  case UNLT:
  case GE:  case GEU:  case UNGE:
  case LE:  case LEU:  case UNLE:
  case UNORDERED: case ORDERED:
    /* If this produces an integer result, we know which bits are set.
Code here used to clear bits outside the mode of X, but that is
now done above.  */
    /* Mind that MODE is the mode the caller wants to look at this
operation in, and not the actual operation mode.  We can wind
up with (subreg:DI (gt:V4HI x y)), and we don't have anything
that describes the results of a vector compare.  */
    if (GET_MODE_CLASS (xmode)((enum mode_class) mode_class[xmode]) == MODE_INT
 && mode_width <= HOST_BITS_PER_WIDE_INT64)
nonzero = STORE_FLAG_VALUE1;
    break;

  case NEG:
4914#if 0
    /* Disabled to avoid exponential mutual recursion between nonzero_bits
and num_sign_bit_copies.  */
    if (num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), xmode) == xmode_width)
nonzero = 1;
4919#endif

    if (xmode_width < mode_width)
nonzero |= (GET_MODE_MASK (mode)mode_mask_array[mode] & ~GET_MODE_MASK (xmode)mode_mask_array[xmode]);
    break;

  case ABS:
4926#if 0
    /* Disabled to avoid exponential mutual recursion between nonzero_bits
and num_sign_bit_copies.  */
    if (num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), xmode) == xmode_width)
nonzero = 1;
4931#endif
    break;

  case TRUNCATE:
    nonzero &= (cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
		       known_x, known_mode, known_ret)
  & GET_MODE_MASK (mode)mode_mask_array[mode]);
    break;

  case ZERO_EXTEND:
    nonzero &= cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
		      known_x, known_mode, known_ret);
    if (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) != VOIDmode((void) 0, E_VOIDmode))
nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)))mode_mask_array[((machine_mode) ((((x)->u.fld[0]).rt_rtx))
->mode)];
    break;

  case SIGN_EXTEND:
    /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
Otherwise, show all the bits in the outer mode but not the inner
may be nonzero.  */
    inner_nz = cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
		      known_x, known_mode, known_ret);
    if (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) != VOIDmode((void) 0, E_VOIDmode))
{
 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)))mode_mask_array[((machine_mode) ((((x)->u.fld[0]).rt_rtx))
->mode)];
 if (val_signbit_known_set_p (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode), inner_nz))
   inner_nz |= (GET_MODE_MASK (mode)mode_mask_array[mode]
	 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))mode_mask_array[((machine_mode) ((((x)->u.fld[0]).rt_rtx))
->mode)]);
}

    nonzero &= inner_nz;
    break;

  case AND:
    nonzero &= cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
		       known_x, known_mode, known_ret)
    		 & cached_nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
			known_x, known_mode, known_ret);
    break;

  case XOR:   case IOR:
  case UMIN:  case UMAX:  case SMIN:  case SMAX:
    {
unsigned HOST_WIDE_INTlong nonzero0
  = cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
		  known_x, known_mode, known_ret);

/* Don't call nonzero_bits for the second time if it cannot change
  anything.  */
if ((nonzero & nonzero0) != nonzero)
 nonzero &= nonzero0
    		     | cached_nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
			    known_x, known_mode, known_ret);
    }
    break;

  case PLUS:  case MINUS:
  case MULT:
  case DIV:   case UDIV:
  case MOD:   case UMOD:
    /* We can apply the rules of arithmetic to compute the number of
high- and low-order zero bits of these operations.  We start by
computing the width (position of the highest-order nonzero bit)
and the number of low-order zero bits for each value.  */
    {
unsigned HOST_WIDE_INTlong nz0
 = cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
		 known_x, known_mode, known_ret);
unsigned HOST_WIDE_INTlong nz1
 = cached_nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
		 known_x, known_mode, known_ret);
int sign_index = xmode_width - 1;
int width0 = floor_log2 (nz0) + 1;
int width1 = floor_log2 (nz1) + 1;
int low0 = ctz_or_zero (nz0);
int low1 = ctz_or_zero (nz1);
unsigned HOST_WIDE_INTlong op0_maybe_minusp
 = nz0 & (HOST_WIDE_INT_1U1UL << sign_index);
unsigned HOST_WIDE_INTlong op1_maybe_minusp
 = nz1 & (HOST_WIDE_INT_1U1UL << sign_index);
unsigned int result_width = mode_width;
int result_low = 0;

switch (code)
 {
 case PLUS:
   result_width = MAX (width0, width1)((width0) > (width1) ? (width0) : (width1)) + 1;
   result_low = MIN (low0, low1)((low0) < (low1) ? (low0) : (low1));
   break;
 case MINUS:
   result_low = MIN (low0, low1)((low0) < (low1) ? (low0) : (low1));
   break;
 case MULT:
   result_width = width0 + width1;
   result_low = low0 + low1;
   break;
 case DIV:
   if (width1 == 0)
     break;
   if (!op0_maybe_minusp && !op1_maybe_minusp)
     result_width = width0;
   break;
 case UDIV:
   if (width1 == 0)
     break;
   result_width = width0;
   break;
 case MOD:
   if (width1 == 0)
     break;
   if (!op0_maybe_minusp && !op1_maybe_minusp)
     result_width = MIN (width0, width1)((width0) < (width1) ? (width0) : (width1));
   result_low = MIN (low0, low1)((low0) < (low1) ? (low0) : (low1));
   break;
 case UMOD:
   if (width1 == 0)
     break;
   result_width = MIN (width0, width1)((width0) < (width1) ? (width0) : (width1));
   result_low = MIN (low0, low1)((low0) < (low1) ? (low0) : (low1));
   break;
 default:
   gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 5052, __FUNCTION__));
 }

/* Note that mode_width <= HOST_BITS_PER_WIDE_INT, see above.  */
if (result_width < mode_width)
 nonzero &= (HOST_WIDE_INT_1U1UL << result_width) - 1;

if (result_low > 0)
 {
   if (result_low < HOST_BITS_PER_WIDE_INT64)
     nonzero &= ~((HOST_WIDE_INT_1U1UL << result_low) - 1);
   else
     nonzero = 0;
 }
    }
    break;

  case ZERO_EXTRACT:
    if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) < HOST_BITS_PER_WIDE_INT64)
nonzero &= (HOST_WIDE_INT_1U1UL << INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0])) - 1;
    break;

  case SUBREG:
    /* If this is a SUBREG formed for a promoted variable that has
been zero-extended, we know that at least the high-order bits
are zero, though others might be too.  */
    if (SUBREG_PROMOTED_VAR_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag (
"SUBREG_PROMOTED", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 5079, __FUNCTION__); _rtx; })->in_struct) && SUBREG_PROMOTED_UNSIGNED_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag (
"SUBREG_PROMOTED_UNSIGNED_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 5079, __FUNCTION__); _rtx; })->volatil))
nonzero = GET_MODE_MASK (xmode)mode_mask_array[xmode]
  & cached_nonzero_bits (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), xmode,
			 known_x, known_mode, known_ret);

    /* If the inner mode is a single word for both the host and target
machines, we can compute this from which bits of the inner
object might be nonzero.  */
    inner_mode = GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
    if (GET_MODE_PRECISION (inner_mode).is_constant (&inner_width)
 && inner_width <= BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
 1)) != 0) ? 8 : 4))
 && inner_width <= HOST_BITS_PER_WIDE_INT64)
{
 nonzero &= cached_nonzero_bits (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), mode,
			  known_x, known_mode, known_ret);

        /* On a typical CISC machine, accessing an object in a wider mode
    causes the high-order bits to become undefined.  So they are
    not known to be zero.

    On a typical RISC machine, we only have to worry about the way
    loads are extended.  Otherwise, if we get a reload for the inner
    part, it may be loaded from the stack, and then we may lose all
    the zero bits that existed before the store to the stack.  */
 rtx_code extend_op;
 if ((!WORD_REGISTER_OPERATIONS0
      || ((extend_op = load_extend_op (inner_mode)) == SIGN_EXTEND
   ? val_signbit_known_set_p (inner_mode, nonzero)
   : extend_op != ZERO_EXTEND)
      || !MEM_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == MEM
))
     && xmode_width > inner_width)
   nonzero
     |= (GET_MODE_MASK (GET_MODE (x))mode_mask_array[((machine_mode) (x)->mode)] & ~GET_MODE_MASK (inner_mode)mode_mask_array[inner_mode]);
}
    break;

  case ASHIFT:
  case ASHIFTRT:
  case LSHIFTRT:
  case ROTATE:
  case ROTATERT:
    /* The nonzero bits are in two classes: any bits within MODE
that aren't in xmode are always significant.  The rest of the
nonzero bits are those that are significant in the operand of
the shift when shifted the appropriate number of bits.  This
shows that high-order bits are cleared by the right shift and
low-order bits by left shifts.  */
    if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) >= 0
 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) < HOST_BITS_PER_WIDE_INT64
 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) < xmode_width)
{
 int count = INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]);
 unsigned HOST_WIDE_INTlong mode_mask = GET_MODE_MASK (xmode)mode_mask_array[xmode];
 unsigned HOST_WIDE_INTlong op_nonzero
   = cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
		   known_x, known_mode, known_ret);
 unsigned HOST_WIDE_INTlong inner = op_nonzero & mode_mask;
 unsigned HOST_WIDE_INTlong outer = 0;

 if (mode_width > xmode_width)
   outer = (op_nonzero & nonzero & ~mode_mask);

 switch (code)
   {
   case ASHIFT:
     inner <<= count;
     break;

   case LSHIFTRT:
     inner >>= count;
     break;

   case ASHIFTRT:
     inner >>= count;

     /* If the sign bit may have been nonzero before the shift, we
 need to mark all the places it could have been copied to
 by the shift as possibly nonzero.  */
     if (inner & (HOST_WIDE_INT_1U1UL << (xmode_width - 1 - count)))
inner |= (((HOST_WIDE_INT_1U1UL << count) - 1)
	  << (xmode_width - count));
     break;

   case ROTATE:
     inner = (inner << (count % xmode_width)
       | (inner >> (xmode_width - (count % xmode_width))))
      & mode_mask;
     break;

   case ROTATERT:
     inner = (inner >> (count % xmode_width)
       | (inner << (xmode_width - (count % xmode_width))))
      & mode_mask;
     break;

   default:
     gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 5176, __FUNCTION__));
   }

 nonzero &= (outer | inner);
}
    break;

  case FFS:
  case POPCOUNT:
    /* This is at most the number of bits in the mode.  */
    nonzero = ((unsigned HOST_WIDE_INTlong) 2 << (floor_log2 (mode_width))) - 1;
    break;

  case CLZ:
    /* If CLZ has a known value at zero, then the nonzero bits are
that value, plus the number of bits in the mode minus one.  */
    if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero)((nonzero) = GET_MODE_BITSIZE (mode), ((global_options.x_ix86_isa_flags
 & (1UL << 35)) != 0) ? 2 : 0))
9
←
Assuming the condition is true→
10
←
'?' condition is true→
11
←
Taking true branch→
nonzero
 |= (HOST_WIDE_INT_1U1UL << (floor_log2 (mode_width))) - 1;
12
←
Calling 'floor_log2'→
14
←
Returning from 'floor_log2'→
15
←
The result of the left shift is undefined because the right operand is negative
    else
nonzero = -1;
    break;

  case CTZ:
    /* If CTZ has a known value at zero, then the nonzero bits are
that value, plus the number of bits in the mode minus one.  */
    if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero)((nonzero) = GET_MODE_BITSIZE (mode), ((global_options.x_ix86_isa_flags
 & (1UL << 23)) != 0) ? 2 : 0))
nonzero
 |= (HOST_WIDE_INT_1U1UL << (floor_log2 (mode_width))) - 1;
    else
nonzero = -1;
    break;

  case CLRSB:
    /* This is at most the number of bits in the mode minus 1.  */
    nonzero = (HOST_WIDE_INT_1U1UL << (floor_log2 (mode_width))) - 1;
    break;

  case PARITY:
    nonzero = 1;
    break;

  case IF_THEN_ELSE:
    {
unsigned HOST_WIDE_INTlong nonzero_true
 = cached_nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
		 known_x, known_mode, known_ret);

/* Don't call nonzero_bits for the second time if it cannot change
  anything.  */
if ((nonzero & nonzero_true) != nonzero)
 nonzero &= nonzero_true
    		     | cached_nonzero_bits (XEXP (x, 2)(((x)->u.fld[2]).rt_rtx), mode,
			    known_x, known_mode, known_ret);
    }
    break;

  default:
    break;
  }

return nonzero;
5238}

5240/* See the macro definition above.  */
5241#undef cached_num_sign_bit_copies

5243
5244/* Return true if num_sign_bit_copies1 might recurse into both operands
 of X.  */

5247static inline bool
5248num_sign_bit_copies_binary_arith_p (const_rtx x)
5249{
if (!ARITHMETIC_P (x)(((rtx_class[(int) (((enum rtx_code) (x)->code))]) & (
~1)) == (RTX_COMM_ARITH & (~1))))
  return false;
switch (GET_CODE (x)((enum rtx_code) (x)->code))
  {
  case IOR:
  case AND:
  case XOR:
  case SMIN:
  case SMAX:
  case UMIN:
  case UMAX:
  case PLUS:
  case MINUS:
  case MULT:
    return true;
  default:
    return false;
  }
5268}

5270/* The function cached_num_sign_bit_copies is a wrapper around
 num_sign_bit_copies1.  It avoids exponential behavior in
 num_sign_bit_copies1 when X has identical subexpressions on the
 first or the second level.  */

5275static unsigned int
5276cached_num_sign_bit_copies (const_rtx x, scalar_int_mode mode,
	    const_rtx known_x, machine_mode known_mode,
	    unsigned int known_ret)
5279{
if (x == known_x && mode == known_mode)
  return known_ret;

/* Try to find identical subexpressions.  If found call
   num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
   the precomputed value for the subexpression as KNOWN_RET.  */

if (num_sign_bit_copies_binary_arith_p (x))
  {
    rtx x0 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
    rtx x1 = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);

    /* Check the first level.  */
    if (x0 == x1)
return
 num_sign_bit_copies1 (x, mode, x0, mode,
		cached_num_sign_bit_copies (x0, mode, known_x,
					    known_mode,
					    known_ret));

    /* Check the second level.  */
    if (num_sign_bit_copies_binary_arith_p (x0)
 && (x1 == XEXP (x0, 0)(((x0)->u.fld[0]).rt_rtx) || x1 == XEXP (x0, 1)(((x0)->u.fld[1]).rt_rtx)))
return
 num_sign_bit_copies1 (x, mode, x1, mode,
		cached_num_sign_bit_copies (x1, mode, known_x,
					    known_mode,
					    known_ret));

    if (num_sign_bit_copies_binary_arith_p (x1)
 && (x0 == XEXP (x1, 0)(((x1)->u.fld[0]).rt_rtx) || x0 == XEXP (x1, 1)(((x1)->u.fld[1]).rt_rtx)))
return
 num_sign_bit_copies1 (x, mode, x0, mode,
		cached_num_sign_bit_copies (x0, mode, known_x,
					    known_mode,
					    known_ret));
  }

return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
5319}

5321/* Return the number of bits at the high-order end of X that are known to
 be equal to the sign bit.  X will be used in mode MODE.  The returned
 value will always be between 1 and the number of bits in MODE.  */

5325static unsigned int
5326num_sign_bit_copies1 (const_rtx x, scalar_int_mode mode, const_rtx known_x,
      machine_mode known_mode,
      unsigned int known_ret)
5329{
enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
unsigned int bitwidth = GET_MODE_PRECISION (mode);
int num0, num1, result;
unsigned HOST_WIDE_INTlong nonzero;

if (CONST_INT_P (x)(((enum rtx_code) (x)->code) == CONST_INT))
  {
    /* If the constant is negative, take its 1's complement and remask.
Then see how many zero bits we have.  */
    nonzero = UINTVAL (x)((unsigned long) ((x)->u.hwint[0])) & GET_MODE_MASK (mode)mode_mask_array[mode];
    if (bitwidth <= HOST_BITS_PER_WIDE_INT64
 && (nonzero & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0)
nonzero = (~nonzero) & GET_MODE_MASK (mode)mode_mask_array[mode];

    return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
  }

scalar_int_mode xmode, inner_mode;
if (!is_a <scalar_int_mode> (GET_MODE (x)((machine_mode) (x)->mode), &xmode))
  return 1;

unsigned int xmode_width = GET_MODE_PRECISION (xmode);

/* For a smaller mode, just ignore the high bits.  */
if (bitwidth < xmode_width)
  {
    num0 = cached_num_sign_bit_copies (x, xmode,
			 known_x, known_mode, known_ret);
    return MAX (1, num0 - (int) (xmode_width - bitwidth))((1) > (num0 - (int) (xmode_width - bitwidth)) ? (1) : (num0
 - (int) (xmode_width - bitwidth)));
  }

if (bitwidth > xmode_width)
  {
    /* If this machine does not do all register operations on the entire
register and MODE is wider than the mode of X, we can say nothing
at all about the high-order bits.  We extend this reasoning to RISC
machines for operations that might not operate on full registers.  */
    if (!(WORD_REGISTER_OPERATIONS0 && word_register_operation_p (x)))
return 1;

    /* Likewise on machines that do, if the mode of the object is smaller
than a word and loads of that size don't sign extend, we can say
nothing about the high order bits.  */
    if (xmode_width < BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
 1)) != 0) ? 8 : 4))
 && load_extend_op (xmode) != SIGN_EXTEND)
return 1;
  }

/* Please keep num_sign_bit_copies_binary_arith_p above in sync with
   the code in the switch below.  */
switch (code)
  {
  case REG:

5384#if defined(POINTERS_EXTEND_UNSIGNED1)
    /* If pointers extend signed and this is a pointer in Pmode, say that
all the bits above ptr_mode are known to be sign bit copies.  */
    /* As we do not know which address space the pointer is referring to,
we can do this only if the target does not support different pointer
or address modes depending on the address space.  */
    if (target_default_pointer_address_modes_p ()
 && ! POINTERS_EXTEND_UNSIGNED1 && xmode == Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
 && mode == Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))) && REG_POINTER (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag ("REG_POINTER"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 5392, __FUNCTION__); _rtx; })->frame_related)
 && !targetm.have_ptr_extend ())
return GET_MODE_PRECISION (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))) - GET_MODE_PRECISION (ptr_mode) + 1;
5395#endif

    {
unsigned int copies_for_hook = 1, copies = 1;
rtx new_rtx = rtl_hooks.reg_num_sign_bit_copies (x, xmode, mode,
					 &copies_for_hook);

if (new_rtx)
 copies = cached_num_sign_bit_copies (new_rtx, mode, known_x,
			       known_mode, known_ret);

if (copies > 1 || copies_for_hook > 1)
 return MAX (copies, copies_for_hook)((copies) > (copies_for_hook) ? (copies) : (copies_for_hook
));

/* Else, use nonzero_bits to guess num_sign_bit_copies (see below).  */
    }
    break;

  case MEM:
    /* Some RISC machines sign-extend all loads of smaller than a word.  */
    if (load_extend_op (xmode) == SIGN_EXTEND)
return MAX (1, ((int) bitwidth - (int) xmode_width + 1))((1) > (((int) bitwidth - (int) xmode_width + 1)) ? (1) : (
((int) bitwidth - (int) xmode_width + 1)));
    break;

  case SUBREG:
    /* If this is a SUBREG for a promoted object that is sign-extended
and we are looking at it in a wider mode, we know that at least the
high-order bits are known to be sign bit copies.  */

    if (SUBREG_PROMOTED_VAR_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag (
"SUBREG_PROMOTED", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 5424, __FUNCTION__); _rtx; })->in_struct) && SUBREG_PROMOTED_SIGNED_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag (
"SUBREG_PROMOTED_SIGNED_P", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.cc"
, 5424, __FUNCTION__); _rtx; })->unchanging))
{
 num0 = cached_num_sign_bit_copies (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), mode,
			     known_x, known_mode, known_ret);
 return MAX ((int) bitwidth - (int) xmode_width + 1, num0)(((int) bitwidth - (int) xmode_width + 1) > (num0) ? ((int
) bitwidth - (int) xmode_width + 1) : (num0));
}

    if (is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode), &inner_mode))
{
 /* For a smaller object, just ignore the high bits.  */
 if (bitwidth <= GET_MODE_PRECISION (inner_mode))
   {
     num0 = cached_num_sign_bit_copies (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), inner_mode,
				 known_x, known_mode,
				 known_ret);
     return MAX (1, num0 - (int) (GET_MODE_PRECISION (inner_mode)((1) > (num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
)) ? (1) : (num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
)))
			   - bitwidth))((1) > (num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
)) ? (1) : (num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
)));
   }

 /* For paradoxical SUBREGs on machines where all register operations
    affect the entire register, just look inside.  Note that we are
    passing MODE to the recursive call, so the number of sign bit
    copies will remain relative to that mode, not the inner mode.

    This works only if loads sign extend.  Otherwise, if we get a
    reload for the inner part, it may be loaded from the stack, and
    then we lose all sign bit copies that existed before the store
    to the stack.  */
 if (WORD_REGISTER_OPERATIONS0
     && load_extend_op (inner_mode) == SIGN_EXTEND
     && paradoxical_subreg_p (x)
     && MEM_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == MEM
))
   return cached_num_sign_bit_copies (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), mode,
			       known_x, known_mode, known_ret);
}
    break;

  case SIGN_EXTRACT:
    if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
))
return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)))((1) > ((int) bitwidth - (((((x)->u.fld[1]).rt_rtx))->
u.hwint[0])) ? (1) : ((int) bitwidth - (((((x)->u.fld[1]).
rt_rtx))->u.hwint[0])));
    break;

  case SIGN_EXTEND:
    if (is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode), &inner_mode))
return (bitwidth - GET_MODE_PRECISION (inner_mode)
+ cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), inner_mode,
			      known_x, known_mode, known_ret));
    break;

  case TRUNCATE:
    /* For a smaller object, just ignore the high bits.  */
    inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode));
    num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), inner_mode,
			 known_x, known_mode, known_ret);
    return MAX (1, (num0 - (int) (GET_MODE_PRECISION (inner_mode)((1) > ((num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
))) ? (1) : ((num0 - (int) (GET_MODE_PRECISION (inner_mode) -
 bitwidth))))
		    - bitwidth)))((1) > ((num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
))) ? (1) : ((num0 - (int) (GET_MODE_PRECISION (inner_mode) -
 bitwidth))));

  case NOT:
    return cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
			 known_x, known_mode, known_ret);

  case ROTATE:       case ROTATERT:
    /* If we are rotating left by a number of bits less than the number
of sign bit copies, we can just subtract that amount from the
number.  */
    if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) >= 0
 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) < (int) bitwidth)
{
 num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
			     known_x, known_mode, known_ret);
 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))((1) > (num0 - (code == ROTATE ? (((((x)->u.fld[1]).rt_rtx
))->u.hwint[0]) : (int) bitwidth - (((((x)->u.fld[1]).rt_rtx
))->u.hwint[0]))) ? (1) : (num0 - (code == ROTATE ? (((((x
)->u.fld[1]).rt_rtx))->u.hwint[0]) : (int) bitwidth - (
((((x)->u.fld[1]).rt_rtx))->u.hwint[0]))))
		 : (int) bitwidth - INTVAL (XEXP (x, 1))))((1) > (num0 - (code == ROTATE ? (((((x)->u.fld[1]).rt_rtx
))->u.hwint[0]) : (int) bitwidth - (((((x)->u.fld[1]).rt_rtx
))->u.hwint[0]))) ? (1) : (num0 - (code == ROTATE ? (((((x
)->u.fld[1]).rt_rtx))->u.hwint[0]) : (int) bitwidth - (
((((x)->u.fld[1]).rt_rtx))->u.hwint[0]))));
}
    break;

  case NEG:
    /* In general, this subtracts one sign bit copy.  But if the value
is known to be positive, the number of sign bit copies is the
same as that of the input.  Finally, if the input has just one bit
that might be nonzero, all the bits are copies of the sign bit.  */
    num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
			 known_x, known_mode, known_ret);
    if (bitwidth > HOST_BITS_PER_WIDE_INT64)
return num0 > 1 ? num0 - 1 : 1;

    nonzero = nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode);
    if (nonzero == 1)
return bitwidth;

    if (num0 > 1
 && ((HOST_WIDE_INT_1U1UL << (bitwidth - 1)) & nonzero))
num0--;

    return num0;

  case IOR:   case AND:   case XOR:
  case SMIN:  case SMAX:  case UMIN:  case UMAX:
    /* Logical operations will preserve the number of sign-bit copies.
MIN and MAX operations always return one of the operands.  */
    num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
			 known_x, known_mode, known_ret);
    num1 = cached_num_sign_bit_copies (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
			 known_x, known_mode, known_ret);

    /* If num1 is clearing some of the top bits then regardless of
the other term, we are guaranteed to have at least that many
high-order zero bits.  */
    if (code == AND
 && num1 > 1
 && bitwidth <= HOST_BITS_PER_WIDE_INT64
 && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
 && (UINTVAL (XEXP (x, 1))((unsigned long) (((((x)->u.fld[1]).rt_rtx))->u.hwint[0
]))
     & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) == 0)
return num1;

    /* Similarly for IOR when setting high-order bits.  */
    if (code == IOR
 && num1 > 1
 && bitwidth <= HOST_BITS_PER_WIDE_INT64
 && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
 && (UINTVAL (XEXP (x, 1))((unsigned long) (((((x)->u.fld[1]).rt_rtx))->u.hwint[0
]))
     & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0)
return num1;

    return MIN (num0, num1)((num0) < (num1) ? (num0) : (num1));

  case PLUS:  case MINUS:
    /* For addition and subtraction, we can have a 1-bit carry.  However,
if we are subtracting 1 from a positive number, there will not
be such a carry.  Furthermore, if the positive number is known to
be 0 or 1, we know the result is either -1 or 0.  */

    if (code == PLUS && XEXP (x, 1)(((x)->u.fld[1]).rt_rtx) == constm1_rtx(const_int_rtx[64 -1])
 && bitwidth <= HOST_BITS_PER_WIDE_INT64)
{
 nonzero = nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode);
 if (((HOST_WIDE_INT_1U1UL << (bitwidth - 1)) & nonzero) == 0)
   return (nonzero == 1 || nonzero == 0 ? bitwidth
    : bitwidth - floor_log2 (nonzero) - 1);
}

    num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
			 known_x, known_mode, known_ret);
    num1 = cached_num_sign_bit_copies (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
			 known_x, known_mode, known_ret);
    result = MAX (1, MIN (num0, num1) - 1)((1) > (((num0) < (num1) ? (num0) : (num1)) - 1) ? (1) :
 (((num0) < (num1) ? (num0) : (num1)) - 1));

    return result;

  case MULT:
    /* The number of bits of the product is the sum of the number of
bits of both terms.  However, unless one of the terms if known
to be positive, we must allow for an additional bit since negating
a negative number can remove one sign bit copy.  */

    num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
			 known_x, known_mode, known_ret);
    num1 = cached_num_sign_bit_copies (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
			 known_x, known_mode, known_ret);

    result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
    if (result > 0
 && (bitwidth > HOST_BITS_PER_WIDE_INT64
     || (((nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode)
    & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0)
  && ((nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode)
       & (HOST_WIDE_INT_1U1UL << (bitwidth - 1)))
      != 0))))
result--;

    return MAX (1, result)((1) > (result) ? (1) : (result));

  case UDIV:
    /* The result must be <= the first operand.  If the first operand
has the high bit set, we know nothing about the number of sign
bit copies.  */
    if (bitwidth > HOST_BITS_PER_WIDE_INT64)
return 1;
    else if ((nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode)
& (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0)
return 1;
    else
return cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
			   known_x, known_mode, known_ret);

  case UMOD:
    /* The result must be <= the second operand.  If the second operand
has (or just might have) the high bit set, we know nothing about
the number of sign bit copies.  */
    if (bitwidth > HOST_BITS_PER_WIDE_INT64)
return 1;
    else if ((nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode)
& (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0)
return 1;
    else
return cached_num_sign_bit_copies (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
			   known_x, known_mode, known_ret);

  case DIV:
    /* Similar to unsigned division, except that we have to worry about
the case w