/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc

Bug Summary

File:	build/gcc/haifa-sched.cc
Warning:	line 3240, column 52 The right operand of '!=' is a garbage value
Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-suse-linux -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name haifa-sched.cc -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -resource-dir /usr/lib64/clang/15.0.7 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/backward -internal-isystem /usr/lib64/clang/15.0.7/include -internal-isystem /usr/local/include -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../x86_64-suse-linux/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2023-03-27-141847-20772-1/report-9gqhk4.plist -x c++ /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc
1/* Instruction scheduling pass.
 Copyright (C) 1992-2023 Free Software Foundation, Inc.
 Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by,
 and currently maintained by, Jim Wilson (wilson@cygnus.com)

6This file is part of GCC.

8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 3, or (at your option) any later
11version.

13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16for more details.

18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING3.  If not see
20<http://www.gnu.org/licenses/>.  */

22/* Instruction scheduling pass.  This file, along with sched-deps.cc,
 contains the generic parts.  The actual entry point for
 the normal instruction scheduling pass is found in sched-rgn.cc.

 We compute insn priorities based on data dependencies.  Flow
 analysis only creates a fraction of the data-dependencies we must
 observe: namely, only those dependencies which the combiner can be
 expected to use.  For this pass, we must therefore create the
 remaining dependencies we need to observe: register dependencies,
 memory dependencies, dependencies to keep function calls in order,
 and the dependence between a conditional branch and the setting of
 condition codes are all dealt with here.

 The scheduler first traverses the data flow graph, starting with
 the last instruction, and proceeding to the first, assigning values
 to insn_priority as it goes.  This sorts the instructions
 topologically by data dependence.

 Once priorities have been established, we order the insns using
 list scheduling.  This works as follows: starting with a list of
 all the ready insns, and sorted according to priority number, we
 schedule the insn from the end of the list by placing its
 predecessors in the list according to their priority order.  We
 consider this insn scheduled by setting the pointer to the "end" of
 the list to point to the previous insn.  When an insn has no
 predecessors, we either queue it until sufficient time has elapsed
 or add it to the ready list.  As the instructions are scheduled or
 when stalls are introduced, the queue advances and dumps insns into
 the ready list.  When all insns down to the lowest priority have
 been scheduled, the critical path of the basic block has been made
 as short as possible.  The remaining insns are then scheduled in
 remaining slots.

 The following list shows the order in which we want to break ties
 among insns in the ready list:

 1.  choose insn with the longest path to end of bb, ties
 broken by
 2.  choose insn with least contribution to register pressure,
 ties broken by
 3.  prefer in-block upon interblock motion, ties broken by
 4.  prefer useful upon speculative motion, ties broken by
 5.  choose insn with largest control flow probability, ties
 broken by
 6.  choose insn with the least dependences upon the previously
 scheduled insn, or finally
 7   choose the insn which has the most insns dependent on it.
 8.  choose insn with lowest UID.

 Memory references complicate matters.  Only if we can be certain
 that memory references are not part of the data dependency graph
 (via true, anti, or output dependence), can we move operations past
 memory references.  To first approximation, reads can be done
 independently, while writes introduce dependencies.  Better
 approximations will yield fewer dependencies.

 Before reload, an extended analysis of interblock data dependences
 is required for interblock scheduling.  This is performed in
 compute_block_dependences ().

 Dependencies set up by memory references are treated in exactly the
 same way as other dependencies, by using insn backward dependences
 INSN_BACK_DEPS.  INSN_BACK_DEPS are translated into forward dependences
 INSN_FORW_DEPS for the purpose of forward list scheduling.

 Having optimized the critical path, we may have also unduly
 extended the lifetimes of some registers.  If an operation requires
 that constants be loaded into registers, it is certainly desirable
 to load those constants as early as necessary, but no earlier.
 I.e., it will not do to load up a bunch of registers at the
 beginning of a basic block only to use them at the end, if they
 could be loaded later, since this may result in excessive register
 utilization.

 Note that since branches are never in basic blocks, but only end
 basic blocks, this pass will not move branches.  But that is ok,
 since we can use GNU's delayed branch scheduling pass to take care
 of this case.

 Also note that no further optimizations based on algebraic
 identities are performed, so this pass would be a good one to
 perform instruction splitting, such as breaking up a multiply
 instruction into shifts and adds where that is profitable.

 Given the memory aliasing analysis that this pass should perform,
 it should be possible to remove redundant stores to memory, and to
 load values from registers instead of hitting memory.

 Before reload, speculative insns are moved only if a 'proof' exists
 that no exception will be caused by this, and if no live registers
 exist that inhibit the motion (live registers constraints are not
 represented by data dependence edges).

 This pass must update information that subsequent passes expect to
 be correct.  Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
 reg_n_calls_crossed, and reg_live_length.  Also, BB_HEAD, BB_END.

 The information in the line number notes is carefully retained by
 this pass.  Notes that refer to the starting and ending of
 exception regions are also carefully retained by this pass.  All
 other NOTE insns are grouped in their same relative order at the
 beginning of basic blocks and regions that have been scheduled.  */
124
125#include "config.h"
126#include "system.h"
127#include "coretypes.h"
128#include "backend.h"
129#include "target.h"
130#include "rtl.h"
131#include "cfghooks.h"
132#include "df.h"
133#include "memmodel.h"
134#include "tm_p.h"
135#include "insn-config.h"
136#include "regs.h"
137#include "ira.h"
138#include "recog.h"
139#include "insn-attr.h"
140#include "cfgrtl.h"
141#include "cfgbuild.h"
142#include "sched-int.h"
143#include "common/common-target.h"
144#include "dbgcnt.h"
145#include "cfgloop.h"
146#include "dumpfile.h"
147#include "print-rtl.h"
148#include "function-abi.h"

150#ifdef INSN_SCHEDULING

152/* True if we do register pressure relief through live-range
 shrinkage.  */
154static bool live_range_shrinkage_p;

156/* Switch on live range shrinkage.  */
157void
158initialize_live_range_shrinkage (void)
159{
live_range_shrinkage_p = true;
161}

163/* Switch off live range shrinkage.  */
164void
165finish_live_range_shrinkage (void)
166{
live_range_shrinkage_p = false;
168}

170/* issue_rate is the number of insns that can be scheduled in the same
 machine cycle.  It can be defined in the config/mach/mach.h file,
 otherwise we set it to 1.  */

174int issue_rate;

176/* This can be set to true by a backend if the scheduler should not
 enable a DCE pass.  */
178bool sched_no_dce;

180/* The current initiation interval used when modulo scheduling.  */
181static int modulo_ii;

183/* The maximum number of stages we are prepared to handle.  */
184static int modulo_max_stages;

186/* The number of insns that exist in each iteration of the loop.  We use this
 to detect when we've scheduled all insns from the first iteration.  */
188static int modulo_n_insns;

190/* The current count of insns in the first iteration of the loop that have
 already been scheduled.  */
192static int modulo_insns_scheduled;

194/* The maximum uid of insns from the first iteration of the loop.  */
195static int modulo_iter0_max_uid;

197/* The number of times we should attempt to backtrack when modulo scheduling.
 Decreased each time we have to backtrack.  */
199static int modulo_backtracks_left;

201/* The stage in which the last insn from the original loop was
 scheduled.  */
203static int modulo_last_stage;

205/* sched-verbose controls the amount of debugging output the
 scheduler prints.  It is controlled by -fsched-verbose=N:
 N=0: no debugging output.
 N=1: default value.
 N=2: bb's probabilities, detailed ready list info, unit/insn info.
 N=3: rtl at abort point, control-flow, regions info.
 N=5: dependences info.  */
212int sched_verbose = 0;

214/* Debugging file.  All printouts are sent to dump. */
215FILE *sched_dump = 0;

217/* This is a placeholder for the scheduler parameters common
 to all schedulers.  */
219struct common_sched_info_def *common_sched_info;

221#define INSN_TICK(INSN)((&h_i_d[INSN_UID (INSN)])->tick)	(HID (INSN)(&h_i_d[INSN_UID (INSN)])->tick)
222#define INSN_EXACT_TICK(INSN)((&h_i_d[INSN_UID (INSN)])->exact_tick) (HID (INSN)(&h_i_d[INSN_UID (INSN)])->exact_tick)
223#define INSN_TICK_ESTIMATE(INSN)((&h_i_d[INSN_UID (INSN)])->tick_estimate) (HID (INSN)(&h_i_d[INSN_UID (INSN)])->tick_estimate)
224#define INTER_TICK(INSN)((&h_i_d[INSN_UID (INSN)])->inter_tick) (HID (INSN)(&h_i_d[INSN_UID (INSN)])->inter_tick)
225#define FEEDS_BACKTRACK_INSN(INSN)((&h_i_d[INSN_UID (INSN)])->feeds_backtrack_insn) (HID (INSN)(&h_i_d[INSN_UID (INSN)])->feeds_backtrack_insn)
226#define SHADOW_P(INSN)((&h_i_d[INSN_UID (INSN)])->shadow_p) (HID (INSN)(&h_i_d[INSN_UID (INSN)])->shadow_p)
227#define MUST_RECOMPUTE_SPEC_P(INSN)((&h_i_d[INSN_UID (INSN)])->must_recompute_spec) (HID (INSN)(&h_i_d[INSN_UID (INSN)])->must_recompute_spec)
228/* Cached cost of the instruction.  Use insn_sched_cost to get cost of the
 insn.  -1 here means that the field is not initialized.  */
230#define INSN_COST(INSN)((&h_i_d[INSN_UID (INSN)])->cost)	(HID (INSN)(&h_i_d[INSN_UID (INSN)])->cost)

232/* If INSN_TICK of an instruction is equal to INVALID_TICK,
 then it should be recalculated from scratch.  */
234#define INVALID_TICK(-(max_insn_queue_index + 1)) (-(max_insn_queue_index + 1))
235/* The minimal value of the INSN_TICK of an instruction.  */
236#define MIN_TICK(-max_insn_queue_index) (-max_insn_queue_index)

238/* Original order of insns in the ready list.
 Used to keep order of normal insns while separating DEBUG_INSNs.  */
240#define INSN_RFS_DEBUG_ORIG_ORDER(INSN)((&h_i_d[INSN_UID (INSN)])->rfs_debug_orig_order) (HID (INSN)(&h_i_d[INSN_UID (INSN)])->rfs_debug_orig_order)

242/* The deciding reason for INSN's place in the ready list.  */
243#define INSN_LAST_RFS_WIN(INSN)((&h_i_d[INSN_UID (INSN)])->last_rfs_win) (HID (INSN)(&h_i_d[INSN_UID (INSN)])->last_rfs_win)

245/* List of important notes we must keep around.  This is a pointer to the
 last element in the list.  */
247rtx_insn *note_list;

249static struct spec_info_def spec_info_var;
250/* Description of the speculative part of the scheduling.
 If NULL - no speculation.  */
252spec_info_t spec_info = NULLnullptr;

254/* True, if recovery block was added during scheduling of current block.
 Used to determine, if we need to fix INSN_TICKs.  */
256static bool haifa_recovery_bb_recently_added_p;

258/* True, if recovery block was added during this scheduling pass.
 Used to determine if we should have empty memory pools of dependencies
 after finishing current region.  */
261bool haifa_recovery_bb_ever_added_p;

263/* Counters of different types of speculative instructions.  */
264static int nr_begin_data, nr_be_in_data, nr_begin_control, nr_be_in_control;

266/* Array used in {unlink, restore}_bb_notes.  */
267static rtx_insn **bb_header = 0;

269/* Basic block after which recovery blocks will be created.  */
270static basic_block before_recovery;

272/* Basic block just before the EXIT_BLOCK and after recovery, if we have
 created it.  */
274basic_block after_recovery;

276/* FALSE if we add bb to another region, so we don't need to initialize it.  */
277bool adding_bb_to_current_region_p = true;

279/* Queues, etc.  */

281/* An instruction is ready to be scheduled when all insns preceding it
 have already been scheduled.  It is important to ensure that all
 insns which use its result will not be executed until its result
 has been computed.  An insn is maintained in one of four structures:

 (P) the "Pending" set of insns which cannot be scheduled until
 their dependencies have been satisfied.
 (Q) the "Queued" set of insns that can be scheduled when sufficient
 time has passed.
 (R) the "Ready" list of unscheduled, uncommitted insns.
 (S) the "Scheduled" list of insns.

 Initially, all insns are either "Pending" or "Ready" depending on
 whether their dependencies are satisfied.

 Insns move from the "Ready" list to the "Scheduled" list as they
 are committed to the schedule.  As this occurs, the insns in the
 "Pending" list have their dependencies satisfied and move to either
 the "Ready" list or the "Queued" set depending on whether
 sufficient time has passed to make them ready.  As time passes,
 insns move from the "Queued" set to the "Ready" list.

 The "Pending" list (P) are the insns in the INSN_FORW_DEPS of the
 unscheduled insns, i.e., those that are ready, queued, and pending.
 The "Queued" set (Q) is implemented by the variable `insn_queue'.
 The "Ready" list (R) is implemented by the variables `ready' and
 `n_ready'.
 The "Scheduled" list (S) is the new insn chain built by this pass.

 The transition (R->S) is implemented in the scheduling loop in
 `schedule_block' when the best insn to schedule is chosen.
 The transitions (P->R and P->Q) are implemented in `schedule_insn' as
 insns move from the ready list to the scheduled list.
 The transition (Q->R) is implemented in 'queue_to_insn' as time
 passes or stalls are introduced.  */

317/* Implement a circular buffer to delay instructions until sufficient
 time has passed.  For the new pipeline description interface,
 MAX_INSN_QUEUE_INDEX is a power of two minus one which is not less
 than maximal time of instruction execution computed by genattr.cc on
 the base maximal time of functional unit reservations and getting a
 result.  This is the longest time an insn may be queued.  */

324static rtx_insn_list **insn_queue;
325static int q_ptr = 0;
326static int q_size = 0;
327#define NEXT_Q(X)(((X)+1) & max_insn_queue_index) (((X)+1) & max_insn_queue_index)
328#define NEXT_Q_AFTER(X, C)(((X)+C) & max_insn_queue_index) (((X)+C) & max_insn_queue_index)

330#define QUEUE_SCHEDULED(-3) (-3)
331#define QUEUE_NOWHERE(-2)   (-2)
332#define QUEUE_READY(-1)     (-1)
333/* QUEUE_SCHEDULED - INSN is scheduled.
 QUEUE_NOWHERE   - INSN isn't scheduled yet and is neither in
 queue or ready list.
 QUEUE_READY     - INSN is in ready list.
 N >= 0 - INSN queued for X [where NEXT_Q_AFTER (q_ptr, X) == N] cycles.  */

339#define QUEUE_INDEX(INSN)((&h_i_d[INSN_UID (INSN)])->queue_index) (HID (INSN)(&h_i_d[INSN_UID (INSN)])->queue_index)

341/* The following variable value refers for all current and future
 reservations of the processor units.  */
343state_t curr_state;

345/* The following variable value is size of memory representing all
 current and future reservations of the processor units.  */
347size_t dfa_state_size;

349/* The following array is used to find the best insn from ready when
 the automaton pipeline interface is used.  */
351signed char *ready_try = NULLnullptr;

353/* The ready list.  */
354struct ready_list ready = {NULLnullptr, 0, 0, 0, 0};

356/* The pointer to the ready list (to be removed).  */
357static struct ready_list *readyp = &ready;

359/* Scheduling clock.  */
360static int clock_var;

362/* Clock at which the previous instruction was issued.  */
363static int last_clock_var;

365/* Set to true if, when queuing a shadow insn, we discover that it would be
 scheduled too late.  */
367static bool must_backtrack;

369/* The following variable value is number of essential insns issued on
 the current cycle.  An insn is essential one if it changes the
 processors state.  */
372int cycle_issued_insns;

374/* This records the actual schedule.  It is built up during the main phase
 of schedule_block, and afterwards used to reorder the insns in the RTL.  */
376static vec<rtx_insn *> scheduled_insns;

378static int may_trap_exp (const_rtx, int);

380/* Nonzero iff the address is comprised from at most 1 register.  */
381#define CONST_BASED_ADDRESS_P(x)((((enum rtx_code) (x)->code) == REG) || ((((enum rtx_code
) (x)->code) == PLUS || ((enum rtx_code) (x)->code) == MINUS
 || (((enum rtx_code) (x)->code) == LO_SUM)) && ((
(rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ) || ((rtx_class[(int) (((enum
 rtx_code) ((((x)->u.fld[1]).rt_rtx))->code))]) == RTX_CONST_OBJ
))))			\
(REG_P (x)(((enum rtx_code) (x)->code) == REG)					\
 || ((GET_CODE (x)((enum rtx_code) (x)->code) == PLUS || GET_CODE (x)((enum rtx_code) (x)->code) == MINUS	\
|| (GET_CODE (x)((enum rtx_code) (x)->code) == LO_SUM))			\
     && (CONSTANT_P (XEXP (x, 0))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ)			\
  || CONSTANT_P (XEXP (x, 1))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ))))

388/* Returns a class that insn with GET_DEST(insn)=x may belong to,
 as found by analyzing insn's expression.  */

391
392static int haifa_luid_for_non_insn (rtx x);

394/* Haifa version of sched_info hooks common to all headers.  */
395const struct common_sched_info_def haifa_common_sched_info =
{
  NULLnullptr, /* fix_recovery_cfg */
  NULLnullptr, /* add_block */
  NULLnullptr, /* estimate_number_of_insns */
  haifa_luid_for_non_insn, /* luid_for_non_insn */
  SCHED_PASS_UNKNOWN /* sched_pass_id */
};

404/* Mapping from instruction UID to its Logical UID.  */
405vec<int> sched_luids;

407/* Next LUID to assign to an instruction.  */
408int sched_max_luid = 1;

410/* Haifa Instruction Data.  */
411vec<haifa_insn_data_def> h_i_d;

413void (* sched_init_only_bb) (basic_block, basic_block);

415/* Split block function.  Different schedulers might use different functions
 to handle their internal data consistent.  */
417basic_block (* sched_split_block) (basic_block, rtx);

419/* Create empty basic block after the specified block.  */
420basic_block (* sched_create_empty_bb) (basic_block);

422/* Return the number of cycles until INSN is expected to be ready.
 Return zero if it already is.  */
424static int
425insn_delay (rtx_insn *insn)
426{
return MAX (INSN_TICK (insn) - clock_var, 0)((((&h_i_d[INSN_UID (insn)])->tick) - clock_var) > (
0) ? (((&h_i_d[INSN_UID (insn)])->tick) - clock_var) :
 (0));
428}

430static int
431may_trap_exp (const_rtx x, int is_store)
432{
enum rtx_code code;

if (x == 0)
  return TRAP_FREE;
code = GET_CODE (x)((enum rtx_code) (x)->code);
if (is_store)
  {
    if (code == MEM && may_trap_p (x))
return TRAP_RISKY;
    else
return TRAP_FREE;
  }
if (code == MEM)
  {
    /* The insn uses memory:  a volatile load.  */
    if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
 rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 448, __FUNCTION__); _rtx; })->volatil))
return IRISKY;
    /* An exception-free load.  */
    if (!may_trap_p (x))
return IFREE;
    /* A load with 1 base register, to be further checked.  */
    if (CONST_BASED_ADDRESS_P (XEXP (x, 0))((((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) ==
 REG) || ((((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->
code) == PLUS || ((enum rtx_code) ((((x)->u.fld[0]).rt_rtx
))->code) == MINUS || (((enum rtx_code) ((((x)->u.fld[0
]).rt_rtx))->code) == LO_SUM)) && (((rtx_class[(int
) (((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld
[0]).rt_rtx))->code))]) == RTX_CONST_OBJ) || ((rtx_class[(
int) (((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u
.fld[1]).rt_rtx))->code))]) == RTX_CONST_OBJ)))))
return PFREE_CANDIDATE;
    /* No info on the load, to be further checked.  */
    return PRISKY_CANDIDATE;
  }
else
  {
    const char *fmt;
    int i, insn_class = TRAP_FREE;

    /* Neither store nor load, check if it may cause a trap.  */
    if (may_trap_p (x))
return TRAP_RISKY;
    /* Recursive step: walk the insn...  */
    fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
    for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
{
 if (fmt[i] == 'e')
   {
     int tmp_class = may_trap_exp (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), is_store);
     insn_class = WORST_CLASS (insn_class, tmp_class)((insn_class > tmp_class) ? insn_class : tmp_class);
   }
 else if (fmt[i] == 'E')
   {
     int j;
     for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
{
  int tmp_class = may_trap_exp (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), is_store);
  insn_class = WORST_CLASS (insn_class, tmp_class)((insn_class > tmp_class) ? insn_class : tmp_class);
  if (insn_class == TRAP_RISKY || insn_class == IRISKY)
    break;
}
   }
 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
   break;
}
    return insn_class;
  }
492}

494/* Classifies rtx X of an insn for the purpose of verifying that X can be
 executed speculatively (and consequently the insn can be moved
 speculatively), by examining X, returning:
 TRAP_RISKY: store, or risky non-load insn (e.g. division by variable).
 TRAP_FREE: non-load insn.
 IFREE: load from a globally safe location.
 IRISKY: volatile load.
 PFREE_CANDIDATE, PRISKY_CANDIDATE: load that need to be checked for
 being either PFREE or PRISKY.  */

504static int
505haifa_classify_rtx (const_rtx x)
506{
int tmp_class = TRAP_FREE;
int insn_class = TRAP_FREE;
enum rtx_code code;

if (GET_CODE (x)((enum rtx_code) (x)->code) == PARALLEL)
  {
    int i, len = XVECLEN (x, 0)(((((x)->u.fld[0]).rt_rtvec))->num_elem);

    for (i = len - 1; i >= 0; i--)
{
 tmp_class = haifa_classify_rtx (XVECEXP (x, 0, i)(((((x)->u.fld[0]).rt_rtvec))->elem[i]));
 insn_class = WORST_CLASS (insn_class, tmp_class)((insn_class > tmp_class) ? insn_class : tmp_class);
 if (insn_class == TRAP_RISKY || insn_class == IRISKY)
   break;
}
  }
else
  {
    code = GET_CODE (x)((enum rtx_code) (x)->code);
    switch (code)
{
case CLOBBER:
 /* Test if it is a 'store'.  */
 tmp_class = may_trap_exp (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), 1);
 break;
case SET:
 /* Test if it is a store.  */
 tmp_class = may_trap_exp (SET_DEST (x)(((x)->u.fld[0]).rt_rtx), 1);
 if (tmp_class == TRAP_RISKY)
   break;
 /* Test if it is a load.  */
 tmp_class =
   WORST_CLASS (tmp_class,((tmp_class > may_trap_exp ((((x)->u.fld[1]).rt_rtx), 0
)) ? tmp_class : may_trap_exp ((((x)->u.fld[1]).rt_rtx), 0
))
	 may_trap_exp (SET_SRC (x), 0))((tmp_class > may_trap_exp ((((x)->u.fld[1]).rt_rtx), 0
)) ? tmp_class : may_trap_exp ((((x)->u.fld[1]).rt_rtx), 0
));
 break;
case COND_EXEC:
 tmp_class = haifa_classify_rtx (COND_EXEC_CODE (x)(((x)->u.fld[1]).rt_rtx));
 if (tmp_class == TRAP_RISKY)
   break;
 tmp_class = WORST_CLASS (tmp_class,((tmp_class > may_trap_exp ((((x)->u.fld[0]).rt_rtx), 0
)) ? tmp_class : may_trap_exp ((((x)->u.fld[0]).rt_rtx), 0
))
		   may_trap_exp (COND_EXEC_TEST (x), 0))((tmp_class > may_trap_exp ((((x)->u.fld[0]).rt_rtx), 0
)) ? tmp_class : may_trap_exp ((((x)->u.fld[0]).rt_rtx), 0
));
 break;
case TRAP_IF:
 tmp_class = TRAP_RISKY;
 break;
default:;
}
    insn_class = tmp_class;
  }

return insn_class;
558}

560int
561haifa_classify_insn (const_rtx insn)
562{
return haifa_classify_rtx (PATTERN (insn));
564}
565
566/* After the scheduler initialization function has been called, this function
 can be called to enable modulo scheduling.  II is the initiation interval
 we should use, it affects the delays for delay_pairs that were recorded as
 separated by a given number of stages.

 MAX_STAGES provides us with a limit
 after which we give up scheduling; the caller must have unrolled at least
 as many copies of the loop body and recorded delay_pairs for them.
 
 INSNS is the number of real (non-debug) insns in one iteration of
 the loop.  MAX_UID can be used to test whether an insn belongs to
 the first iteration of the loop; all of them have a uid lower than
 MAX_UID.  */
579void
580set_modulo_params (int ii, int max_stages, int insns, int max_uid)
581{
modulo_ii = ii;
modulo_max_stages = max_stages;
modulo_n_insns = insns;
modulo_iter0_max_uid = max_uid;
modulo_backtracks_left = param_max_modulo_backtrack_attemptsglobal_options.x_param_max_modulo_backtrack_attempts;
587}

589/* A structure to record a pair of insns where the first one is a real
 insn that has delay slots, and the second is its delayed shadow.
 I1 is scheduled normally and will emit an assembly instruction,
 while I2 describes the side effect that takes place at the
 transition between cycles CYCLES and (CYCLES + 1) after I1.  */
594struct delay_pair
595{
struct delay_pair *next_same_i1;
rtx_insn *i1, *i2;
int cycles;
/* When doing modulo scheduling, we a delay_pair can also be used to
   show that I1 and I2 are the same insn in a different stage.  If that
   is the case, STAGES will be nonzero.  */
int stages;
603};

605/* Helpers for delay hashing.  */

607struct delay_i1_hasher : nofree_ptr_hash <delay_pair>
608{
typedef void *compare_type;
static inline hashval_t hash (const delay_pair *);
static inline bool equal (const delay_pair *, const void *);
612};

614/* Returns a hash value for X, based on hashing just I1.  */

616inline hashval_t
617delay_i1_hasher::hash (const delay_pair *x)
618{
return htab_hash_pointer (x->i1);
620}

622/* Return true if I1 of pair X is the same as that of pair Y.  */

624inline bool
625delay_i1_hasher::equal (const delay_pair *x, const void *y)
626{
return x->i1 == y;
628}

630struct delay_i2_hasher : free_ptr_hash <delay_pair>
631{
typedef void *compare_type;
static inline hashval_t hash (const delay_pair *);
static inline bool equal (const delay_pair *, const void *);
635};

637/* Returns a hash value for X, based on hashing just I2.  */

639inline hashval_t
640delay_i2_hasher::hash (const delay_pair *x)
641{
return htab_hash_pointer (x->i2);
643}

645/* Return true if I2 of pair X is the same as that of pair Y.  */

647inline bool
648delay_i2_hasher::equal (const delay_pair *x, const void *y)
649{
return x->i2 == y;
651}

653/* Two hash tables to record delay_pairs, one indexed by I1 and the other
 indexed by I2.  */
655static hash_table<delay_i1_hasher> *delay_htab;
656static hash_table<delay_i2_hasher> *delay_htab_i2;

658/* Called through htab_traverse.  Walk the hashtable using I2 as
 index, and delete all elements involving an UID higher than
 that pointed to by *DATA.  */
661int
662haifa_htab_i2_traverse (delay_pair **slot, int *data)
663{
int maxuid = *data;
struct delay_pair *p = *slot;
if (INSN_UID (p->i2) >= maxuid || INSN_UID (p->i1) >= maxuid)
  {
    delay_htab_i2->clear_slot (slot);
  }
return 1;
671}

673/* Called through htab_traverse.  Walk the hashtable using I2 as
 index, and delete all elements involving an UID higher than
 that pointed to by *DATA.  */
676int
677haifa_htab_i1_traverse (delay_pair **pslot, int *data)
678{
int maxuid = *data;
struct delay_pair *p, *first, **pprev;

if (INSN_UID ((*pslot)->i1) >= maxuid)
  {
    delay_htab->clear_slot (pslot);
    return 1;
  }
pprev = &first;
for (p = *pslot; p; p = p->next_same_i1)
  {
    if (INSN_UID (p->i2) < maxuid)
{
 *pprev = p;
 pprev = &p->next_same_i1;
}
  }
*pprev = NULLnullptr;
if (first == NULLnullptr)
  delay_htab->clear_slot (pslot);
else
  *pslot = first;
return 1;
702}

704/* Discard all delay pairs which involve an insn with an UID higher
 than MAX_UID.  */
706void
707discard_delay_pairs_above (int max_uid)
708{
delay_htab->traverse <int *, haifa_htab_i1_traverse> (&max_uid);
delay_htab_i2->traverse <int *, haifa_htab_i2_traverse> (&max_uid);
711}

713/* This function can be called by a port just before it starts the final
 scheduling pass.  It records the fact that an instruction with delay
 slots has been split into two insns, I1 and I2.  The first one will be
 scheduled normally and initiates the operation.  The second one is a
 shadow which must follow a specific number of cycles after I1; its only
 purpose is to show the side effect that occurs at that cycle in the RTL.
 If a JUMP_INSN or a CALL_INSN has been split, I1 should be a normal INSN,
 while I2 retains the original insn type.

 There are two ways in which the number of cycles can be specified,
 involving the CYCLES and STAGES arguments to this function.  If STAGES
 is zero, we just use the value of CYCLES.  Otherwise, STAGES is a factor
 which is multiplied by MODULO_II to give the number of cycles.  This is
 only useful if the caller also calls set_modulo_params to enable modulo
 scheduling.  */

729void
730record_delay_slot_pair (rtx_insn *i1, rtx_insn *i2, int cycles, int stages)
731{
struct delay_pair *p = XNEW (struct delay_pair)((struct delay_pair *) xmalloc (sizeof (struct delay_pair)));
struct delay_pair **slot;

p->i1 = i1;
p->i2 = i2;
p->cycles = cycles;
p->stages = stages;

if (!delay_htab)
  {
    delay_htab = new hash_table<delay_i1_hasher> (10);
    delay_htab_i2 = new hash_table<delay_i2_hasher> (10);
  }
slot = delay_htab->find_slot_with_hash (i1, htab_hash_pointer (i1), INSERT);
p->next_same_i1 = *slot;
*slot = p;
slot = delay_htab_i2->find_slot (p, INSERT);
*slot = p;
750}

752/* Examine the delay pair hashtable to see if INSN is a shadow for another,
 and return the other insn if so.  Return NULL otherwise.  */
754rtx_insn *
755real_insn_for_shadow (rtx_insn *insn)
756{
struct delay_pair *pair;

if (!delay_htab)
  return NULLnullptr;

pair = delay_htab_i2->find_with_hash (insn, htab_hash_pointer (insn));
if (!pair || pair->stages > 0)
  return NULLnullptr;
return pair->i1;
766}

768/* For a pair P of insns, return the fixed distance in cycles from the first
 insn after which the second must be scheduled.  */
770static int
771pair_delay (struct delay_pair *p)
772{
if (p->stages == 0)
  return p->cycles;
else
  return p->stages * modulo_ii;
777}

779/* Given an insn INSN, add a dependence on its delayed shadow if it
 has one.  Also try to find situations where shadows depend on each other
 and add dependencies to the real insns to limit the amount of backtracking
 needed.  */
783void
784add_delay_dependencies (rtx_insn *insn)
785{
struct delay_pair *pair;
sd_iterator_def sd_it;
dep_t dep;

if (!delay_htab)
  return;

pair = delay_htab_i2->find_with_hash (insn, htab_hash_pointer (insn));
if (!pair)
  return;
add_dependence (insn, pair->i1, REG_DEP_ANTI);
if (pair->stages)
  return;

FOR_EACH_DEP (pair->i2, SD_LIST_BACK, sd_it, dep)for ((sd_it) = sd_iterator_start ((pair->i2), (((1) | (2))
)); sd_iterator_cond (&(sd_it), &(dep)); sd_iterator_next
 (&(sd_it)))
  {
    rtx_insn *pro = DEP_PRO (dep)((dep)->pro);
    struct delay_pair *other_pair
= delay_htab_i2->find_with_hash (pro, htab_hash_pointer (pro));
    if (!other_pair || other_pair->stages)
continue;
    if (pair_delay (other_pair) >= pair_delay (pair))
{
 if (sched_verbose >= 4)
   {
     fprintf (sched_dump, ";;\tadding dependence %d <- %d\n",
       INSN_UID (other_pair->i1),
       INSN_UID (pair->i1));
     fprintf (sched_dump, ";;\tpair1 %d <- %d, cost %d\n",
       INSN_UID (pair->i1),
       INSN_UID (pair->i2),
       pair_delay (pair));
     fprintf (sched_dump, ";;\tpair2 %d <- %d, cost %d\n",
       INSN_UID (other_pair->i1),
       INSN_UID (other_pair->i2),
       pair_delay (other_pair));
   }
 add_dependence (pair->i1, other_pair->i1, REG_DEP_ANTI);
}
  }
826}
827
828/* Forward declarations.  */

830static int priority (rtx_insn *, bool force_recompute = false);
831static int autopref_rank_for_schedule (const rtx_insn *, const rtx_insn *);
832static int rank_for_schedule (const void *, const void *);
833static void swap_sort (rtx_insn **, int);
834static void queue_insn (rtx_insn *, int, const char *);
835static int schedule_insn (rtx_insn *);
836static void adjust_priority (rtx_insn *);
837static void advance_one_cycle (void);
838static void extend_h_i_d (void);


841/* Notes handling mechanism:
 =========================
 Generally, NOTES are saved before scheduling and restored after scheduling.
 The scheduler distinguishes between two types of notes:

 (1) LOOP_BEGIN, LOOP_END, SETJMP, EHREGION_BEG, EHREGION_END notes:
 Before scheduling a region, a pointer to the note is added to the insn
 that follows or precedes it.  (This happens as part of the data dependence
 computation).  After scheduling an insn, the pointer contained in it is
 used for regenerating the corresponding note (in reemit_notes).

 (2) All other notes (e.g. INSN_DELETED):  Before scheduling a block,
 these notes are put in a list (in rm_other_notes() and
 unlink_other_notes ()).  After scheduling the block, these notes are
 inserted at the beginning of the block (in schedule_block()).  */

857static void ready_add (struct ready_list *, rtx_insn *, bool);
858static rtx_insn *ready_remove_first (struct ready_list *);
859static rtx_insn *ready_remove_first_dispatch (struct ready_list *ready);

861static void queue_to_ready (struct ready_list *);
862static int early_queue_to_ready (state_t, struct ready_list *);

864/* The following functions are used to implement multi-pass scheduling
 on the first cycle.  */
866static rtx_insn *ready_remove (struct ready_list *, int);
867static void ready_remove_insn (rtx_insn *);

869static void fix_inter_tick (rtx_insn *, rtx_insn *);
870static int fix_tick_ready (rtx_insn *);
871static void change_queue_index (rtx_insn *, int);

873/* The following functions are used to implement scheduling of data/control
 speculative instructions.  */

876static void extend_h_i_d (void);
877static void init_h_i_d (rtx_insn *);
878static int haifa_speculate_insn (rtx_insn *, ds_t, rtx *);
879static void generate_recovery_code (rtx_insn *);
880static void process_insn_forw_deps_be_in_spec (rtx_insn *, rtx_insn *, ds_t);
881static void begin_speculative_block (rtx_insn *);
882static void add_to_speculative_block (rtx_insn *);
883static void init_before_recovery (basic_block *);
884static void create_check_block_twin (rtx_insn *, bool);
885static void fix_recovery_deps (basic_block);
886static bool haifa_change_pattern (rtx_insn *, rtx);
887static void dump_new_block_header (int, basic_block, rtx_insn *, rtx_insn *);
888static void restore_bb_notes (basic_block);
889static void fix_jump_move (rtx_insn *);
890static void move_block_after_check (rtx_insn *);
891static void move_succs (vec<edge, va_gc> **, basic_block);
892static void sched_remove_insn (rtx_insn *);
893static void clear_priorities (rtx_insn *, rtx_vec_t *);
894static void calc_priorities (const rtx_vec_t &);
895static void add_jump_dependencies (rtx_insn *, rtx_insn *);

897#endif /* INSN_SCHEDULING */
898
899/* Point to state used for the current scheduling pass.  */
900struct haifa_sched_info *current_sched_info;
901
902#ifndef INSN_SCHEDULING
903void
904schedule_insns (void)
905{
906}
907#else

909/* Do register pressure sensitive insn scheduling if the flag is set
 up.  */
911enum sched_pressure_algorithm sched_pressure;

913/* Map regno -> its pressure class.  The map defined only when
 SCHED_PRESSURE != SCHED_PRESSURE_NONE.  */
915enum reg_class *sched_regno_pressure_class;

917/* The current register pressure.  Only elements corresponding pressure
 classes are defined.  */
919static int curr_reg_pressure[N_REG_CLASSES((int) LIM_REG_CLASSES)];

921/* Saved value of the previous array.  */
922static int saved_reg_pressure[N_REG_CLASSES((int) LIM_REG_CLASSES)];

924/* Register living at given scheduling point.  */
925static bitmap curr_reg_live;

927/* Saved value of the previous array.  */
928static bitmap saved_reg_live;

930/* Registers mentioned in the current region.  */
931static bitmap region_ref_regs;

933/* Temporary bitmap used for SCHED_PRESSURE_MODEL.  */
934static bitmap tmp_bitmap;

936/* Effective number of available registers of a given class (see comment
 in sched_pressure_start_bb).  */
938static int sched_class_regs_num[N_REG_CLASSES((int) LIM_REG_CLASSES)];
939/* The number of registers that the function would need to save before it
 uses them, and the number of fixed_regs.  Helpers for calculating of
 sched_class_regs_num.  */
942static int call_saved_regs_num[N_REG_CLASSES((int) LIM_REG_CLASSES)];
943static int fixed_regs_num[N_REG_CLASSES((int) LIM_REG_CLASSES)];

945/* Initiate register pressure relative info for scheduling the current
 region.  Currently it is only clearing register mentioned in the
 current region.  */
948void
949sched_init_region_reg_pressure_info (void)
950{
bitmap_clear (region_ref_regs);
952}

954/* PRESSURE[CL] describes the pressure on register class CL.  Update it
 for the birth (if BIRTH_P) or death (if !BIRTH_P) of register REGNO.
 LIVE tracks the set of live registers; if it is null, assume that
 every birth or death is genuine.  */
958static inline void
959mark_regno_birth_or_death (bitmap live, int *pressure, int regno, bool birth_p)
960{
enum reg_class pressure_class;

pressure_class = sched_regno_pressure_class[regno];
if (regno >= FIRST_PSEUDO_REGISTER76)
  {
    if (pressure_class != NO_REGS)
{
 if (birth_p)
   {
     if (!live || bitmap_set_bit (live, regno))
pressure[pressure_class]
  += (ira_reg_class_max_nregs(this_target_ira->x_ira_reg_class_max_nregs)
      [pressure_class][PSEUDO_REGNO_MODE (regno)((machine_mode) (regno_reg_rtx[regno])->mode)]);
   }
 else
   {
     if (!live || bitmap_clear_bit (live, regno))
pressure[pressure_class]
  -= (ira_reg_class_max_nregs(this_target_ira->x_ira_reg_class_max_nregs)
      [pressure_class][PSEUDO_REGNO_MODE (regno)((machine_mode) (regno_reg_rtx[regno])->mode)]);
   }
}
  }
else if (pressure_class != NO_REGS
  && ! TEST_HARD_REG_BIT (ira_no_alloc_regs(this_target_ira->x_ira_no_alloc_regs), regno))
  {
    if (birth_p)
{
 if (!live || bitmap_set_bit (live, regno))
   pressure[pressure_class]++;
}
    else
{
 if (!live || bitmap_clear_bit (live, regno))
   pressure[pressure_class]--;
}
  }
998}

1000/* Initiate current register pressure related info from living
 registers given by LIVE.  */
1002static void
1003initiate_reg_pressure_info (bitmap live)
1004{
int i;
unsigned int j;
bitmap_iterator bi;

for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
  curr_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]] = 0;
bitmap_clear (curr_reg_live);
EXECUTE_IF_SET_IN_BITMAP (live, 0, j, bi)for (bmp_iter_set_init (&(bi), (live), (0), &(j)); bmp_iter_set
 (&(bi), &(j)); bmp_iter_next (&(bi), &(j)))
  if (sched_pressure == SCHED_PRESSURE_MODEL
|| current_nr_blocks == 1
|| bitmap_bit_p (region_ref_regs, j))
    mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure, j, true);
1017}

1019/* Mark registers in X as mentioned in the current region.  */
1020static void
1021setup_ref_regs (rtx x)
1022{
int i, j;
const RTX_CODEenum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
const char *fmt;

if (REG_P (x)(((enum rtx_code) (x)->code) == REG))
  {
    bitmap_set_range (region_ref_regs, REGNO (x)(rhs_regno(x)), REG_NREGS (x)((&(x)->u.reg)->nregs));
    return;
  }
fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
  if (fmt[i] == 'e')
    setup_ref_regs (XEXP (x, i)(((x)->u.fld[i]).rt_rtx));
  else if (fmt[i] == 'E')
    {
for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
 setup_ref_regs (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]));
    }
1041}

1043/* Initiate current register pressure related info at the start of
 basic block BB.  */
1045static void
1046initiate_bb_reg_pressure_info (basic_block bb)
1047{
unsigned int i ATTRIBUTE_UNUSED__attribute__ ((__unused__));
rtx_insn *insn;

if (current_nr_blocks > 1)
  FOR_BB_INSNS (bb, insn)for ((insn) = (bb)->il.x.head_; (insn) && (insn) !=
 NEXT_INSN ((bb)->il.x.rtl->end_); (insn) = NEXT_INSN (
insn))
    if (NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)))
setup_ref_regs (PATTERN (insn));
initiate_reg_pressure_info (df_get_live_in (bb));
if (bb_has_eh_pred (bb))
  for (i = 0; ; ++i)
    {
unsigned int regno = EH_RETURN_DATA_REGNO (i)((i) <= 1 ? (i) : (~(unsigned int) 0));

if (regno == INVALID_REGNUM(~(unsigned int) 0))
 break;
if (! bitmap_bit_p (df_get_live_in (bb), regno))
 mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure,
		     regno, true);
    }
1067}

1069/* Save current register pressure related info.  */
1070static void
1071save_reg_pressure (void)
1072{
int i;

for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
  saved_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]]
    = curr_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]];
bitmap_copy (saved_reg_live, curr_reg_live);
1079}

1081/* Restore saved register pressure related info.  */
1082static void
1083restore_reg_pressure (void)
1084{
int i;

for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
  curr_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]]
    = saved_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]];
bitmap_copy (curr_reg_live, saved_reg_live);
1091}

1093/* Return TRUE if the register is dying after its USE.  */
1094static bool
1095dying_use_p (struct reg_use_data *use)
1096{
struct reg_use_data *next;

for (next = use->next_regno_use; next != use; next = next->next_regno_use)
  if (NONDEBUG_INSN_P (next->insn)((((enum rtx_code) (next->insn)->code) == INSN) || (((enum
 rtx_code) (next->insn)->code) == JUMP_INSN) || (((enum
 rtx_code) (next->insn)->code) == CALL_INSN))
&& QUEUE_INDEX (next->insn)((&h_i_d[INSN_UID (next->insn)])->queue_index) != QUEUE_SCHEDULED(-3))
    return false;
return true;
1104}

1106/* Print info about the current register pressure and its excess for
 each pressure class.  */
1108static void
1109print_curr_reg_pressure (void)
1110{
int i;
enum reg_class cl;

fprintf (sched_dump, ";;\t");
for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
  {
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i];
    gcc_assert (curr_reg_pressure[cl] >= 0)((void)(!(curr_reg_pressure[cl] >= 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1118, __FUNCTION__), 0 : 0));
    fprintf (sched_dump, "  %s:%d(%d)", reg_class_names[cl],
      curr_reg_pressure[cl],
      curr_reg_pressure[cl] - sched_class_regs_num[cl]);
  }
fprintf (sched_dump, "\n");
1124}
1125
1126/* Determine if INSN has a condition that is clobbered if a register
 in SET_REGS is modified.  */
1128static bool
1129cond_clobbered_p (rtx_insn *insn, HARD_REG_SET set_regs)
1130{
rtx pat = PATTERN (insn);
gcc_assert (GET_CODE (pat) == COND_EXEC)((void)(!(((enum rtx_code) (pat)->code) == COND_EXEC) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1132, __FUNCTION__), 0 : 0));
if (TEST_HARD_REG_BIT (set_regs, REGNO (XEXP (COND_EXEC_TEST (pat), 0))(rhs_regno(((((((pat)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx
)))))
  {
    sd_iterator_def sd_it;
    dep_t dep;
    haifa_change_pattern (insn, ORIG_PAT (insn)((&h_i_d[INSN_UID (insn)])->orig_pat));
    FOR_EACH_DEP (insn, SD_LIST_BACK, sd_it, dep)for ((sd_it) = sd_iterator_start ((insn), (((1) | (2)))); sd_iterator_cond
 (&(sd_it), &(dep)); sd_iterator_next (&(sd_it)))
DEP_STATUS (dep)((dep)->status) &= ~DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1);
    TODO_SPEC (insn)((&h_i_d[INSN_UID (insn)])->todo_spec) = HARD_DEP(((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) << 1);
    if (sched_verbose >= 2)
fprintf (sched_dump,
 ";;\t\tdequeue insn %s because of clobbered condition\n",
 (*current_sched_info->print_insn) (insn, 0));
    return true;
  }

return false;
1149}

1151/* This function should be called after modifying the pattern of INSN,
 to update scheduler data structures as needed.  */
1153static void
1154update_insn_after_change (rtx_insn *insn)
1155{
sd_iterator_def sd_it;
dep_t dep;

dfa_clear_single_insn_cache (insn);

sd_it = sd_iterator_start (insn,
	     SD_LIST_FORW(4) | SD_LIST_BACK((1) | (2)) | SD_LIST_RES_BACK(8));
while (sd_iterator_cond (&sd_it, &dep))
  {
    DEP_COST (dep)((dep)->cost) = UNKNOWN_DEP_COST((int) ((unsigned int) -1 << 19));
    sd_iterator_next (&sd_it);
  }

/* Invalidate INSN_COST, so it'll be recalculated.  */
INSN_COST (insn)((&h_i_d[INSN_UID (insn)])->cost) = -1;
/* Invalidate INSN_TICK, so it'll be recalculated.  */
INSN_TICK (insn)((&h_i_d[INSN_UID (insn)])->tick) = INVALID_TICK(-(max_insn_queue_index + 1));

/* Invalidate autoprefetch data entry.  */
INSN_AUTOPREF_MULTIPASS_DATA (insn)((&h_i_d[INSN_UID (insn)])->autopref_multipass_data)[0].status
  = AUTOPREF_MULTIPASS_DATA_UNINITIALIZED;
INSN_AUTOPREF_MULTIPASS_DATA (insn)((&h_i_d[INSN_UID (insn)])->autopref_multipass_data)[1].status
  = AUTOPREF_MULTIPASS_DATA_UNINITIALIZED;
1179}


1182/* Two VECs, one to hold dependencies for which pattern replacements
 need to be applied or restored at the start of the next cycle, and
 another to hold an integer that is either one, to apply the
 corresponding replacement, or zero to restore it.  */
1186static vec<dep_t> next_cycle_replace_deps;
1187static vec<int> next_cycle_apply;

1189static void apply_replacement (dep_t, bool);
1190static void restore_pattern (dep_t, bool);

1192/* Look at the remaining dependencies for insn NEXT, and compute and return
 the TODO_SPEC value we should use for it.  This is called after one of
 NEXT's dependencies has been resolved.
 We also perform pattern replacements for predication, and for broken
 replacement dependencies.  The latter is only done if FOR_BACKTRACK is
 false.  */

1199static ds_t
1200recompute_todo_spec (rtx_insn *next, bool for_backtrack)
1201{
ds_t new_ds;
sd_iterator_def sd_it;
dep_t dep, modify_dep = NULLnullptr;
int n_spec = 0;
int n_control = 0;
int n_replace = 0;
bool first_p = true;

if (sd_lists_empty_p (next, SD_LIST_BACK((1) | (2))))
  /* NEXT has all its dependencies resolved.  */
  return 0;

if (!sd_lists_empty_p (next, SD_LIST_HARD_BACK(1)))
  return HARD_DEP(((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) << 1);

/* If NEXT is intended to sit adjacent to this instruction, we don't
   want to try to break any dependencies.  Treat it as a HARD_DEP.  */
if (SCHED_GROUP_P (next)(__extension__ ({ __typeof ((next)) const _rtx = ((next)); if
 (((enum rtx_code) (_rtx)->code) != DEBUG_INSN && (
(enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != JUMP_INSN && ((enum rtx_code) (
_rtx)->code) != CALL_INSN) rtl_check_failed_flag ("SCHED_GROUP_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1219, __FUNCTION__); _rtx; })->in_struct))
  return HARD_DEP(((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) << 1);

/* Now we've got NEXT with speculative deps only.
   1. Look at the deps to see what we have to do.
   2. Check if we can do 'todo'.  */
new_ds = 0;

FOR_EACH_DEP (next, SD_LIST_BACK, sd_it, dep)for ((sd_it) = sd_iterator_start ((next), (((1) | (2)))); sd_iterator_cond
 (&(sd_it), &(dep)); sd_iterator_next (&(sd_it)))
  {
    rtx_insn *pro = DEP_PRO (dep)((dep)->pro);
    ds_t ds = DEP_STATUS (dep)((dep)->status) & SPECULATIVE(((((ds_t) ((1 << (((8 * 4) - 8) / 4)) - 1)) << BEGIN_DATA_BITS_OFFSET
) | (((ds_t) ((1 << (((8 * 4) - 8) / 4)) - 1)) <<
 BE_IN_DATA_BITS_OFFSET)) | ((((ds_t) ((1 << (((8 * 4) -
 8) / 4)) - 1)) << BEGIN_CONTROL_BITS_OFFSET) | (((ds_t
) ((1 << (((8 * 4) - 8) / 4)) - 1)) << BE_IN_CONTROL_BITS_OFFSET
)));

    if (DEBUG_INSN_P (pro)(((enum rtx_code) (pro)->code) == DEBUG_INSN) && !DEBUG_INSN_P (next)(((enum rtx_code) (next)->code) == DEBUG_INSN))
continue;

    if (ds)
{
 n_spec++;
 if (first_p)
   {
     first_p = false;

     new_ds = ds;
   }
 else
   new_ds = ds_merge (new_ds, ds);
}
    else if (DEP_TYPE (dep)((dep)->type) == REG_DEP_CONTROL)
{
 if (QUEUE_INDEX (pro)((&h_i_d[INSN_UID (pro)])->queue_index) != QUEUE_SCHEDULED(-3))
   {
     n_control++;
     modify_dep = dep;
   }
 DEP_STATUS (dep)((dep)->status) &= ~DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1);
}
    else if (DEP_REPLACE (dep)((dep)->replace) != NULLnullptr)
{
 if (QUEUE_INDEX (pro)((&h_i_d[INSN_UID (pro)])->queue_index) != QUEUE_SCHEDULED(-3))
   {
     n_replace++;
     modify_dep = dep;
   }
 DEP_STATUS (dep)((dep)->status) &= ~DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1);
}
  }

if (n_replace > 0 && n_control == 0 && n_spec == 0)
  {
    if (!dbg_cnt (sched_breakdep))
return HARD_DEP(((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) << 1);
    FOR_EACH_DEP (next, SD_LIST_BACK, sd_it, dep)for ((sd_it) = sd_iterator_start ((next), (((1) | (2)))); sd_iterator_cond
 (&(sd_it), &(dep)); sd_iterator_next (&(sd_it)))
{
 struct dep_replacement *desc = DEP_REPLACE (dep)((dep)->replace);
 if (desc != NULLnullptr)
   {
     if (desc->insn == next && !for_backtrack)
{
  gcc_assert (n_replace == 1)((void)(!(n_replace == 1) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1278, __FUNCTION__), 0 : 0));
  apply_replacement (dep, true);
}
     DEP_STATUS (dep)((dep)->status) |= DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1);
   }
}
    return 0;
  }

else if (n_control == 1 && n_replace == 0 && n_spec == 0)
  {
    rtx_insn *pro, *other;
    rtx new_pat;
    rtx cond = NULL_RTX(rtx) 0;
    bool success;
    rtx_insn *prev = NULLnullptr;
    int i;
    unsigned regno;

    if ((current_sched_info->flags & DO_PREDICATION) == 0
 || (ORIG_PAT (next)((&h_i_d[INSN_UID (next)])->orig_pat) != NULL_RTX(rtx) 0
     && PREDICATED_PAT (next)((&h_i_d[INSN_UID (next)])->predicated_pat) == NULL_RTX(rtx) 0))
return HARD_DEP(((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) << 1);

    pro = DEP_PRO (modify_dep)((modify_dep)->pro);
    other = real_insn_for_shadow (pro);
    if (other != NULL_RTX(rtx) 0)
pro = other;

    cond = sched_get_reverse_condition_uncached (pro);
    regno = REGNO (XEXP (cond, 0))(rhs_regno((((cond)->u.fld[0]).rt_rtx)));

    /* Find the last scheduled insn that modifies the condition register.
We can stop looking once we find the insn we depend on through the
REG_DEP_CONTROL; if the condition register isn't modified after it,
we know that it still has the right value.  */
    if (QUEUE_INDEX (pro)((&h_i_d[INSN_UID (pro)])->queue_index) == QUEUE_SCHEDULED(-3))
FOR_EACH_VEC_ELT_REVERSE (scheduled_insns, i, prev)for (i = (scheduled_insns).length () - 1; (scheduled_insns).iterate
 ((i), &(prev)); (i)--)
 {
   HARD_REG_SET t;

   find_all_hard_reg_sets (prev, &t, true);
   if (TEST_HARD_REG_BIT (t, regno))
     return HARD_DEP(((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) << 1);
   if (prev == pro)
     break;
 }
    if (ORIG_PAT (next)((&h_i_d[INSN_UID (next)])->orig_pat) == NULL_RTX(rtx) 0)
{
 ORIG_PAT (next)((&h_i_d[INSN_UID (next)])->orig_pat) = PATTERN (next);

 new_pat = gen_rtx_COND_EXEC (VOIDmode, cond, PATTERN (next))gen_rtx_fmt_ee_stat ((COND_EXEC), ((((void) 0, E_VOIDmode))),
 ((cond)), ((PATTERN (next))) );
 success = haifa_change_pattern (next, new_pat);
 if (!success)
   return HARD_DEP(((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) << 1);
 PREDICATED_PAT (next)((&h_i_d[INSN_UID (next)])->predicated_pat) = new_pat;
}
    else if (PATTERN (next) != PREDICATED_PAT (next)((&h_i_d[INSN_UID (next)])->predicated_pat))
{
 bool success = haifa_change_pattern (next,
			       PREDICATED_PAT (next)((&h_i_d[INSN_UID (next)])->predicated_pat));
 gcc_assert (success)((void)(!(success) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1339, __FUNCTION__), 0 : 0));
}
    DEP_STATUS (modify_dep)((modify_dep)->status) |= DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1);
    return DEP_CONTROL((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1);
  }

if (PREDICATED_PAT (next)((&h_i_d[INSN_UID (next)])->predicated_pat) != NULL_RTX(rtx) 0)
  {
    int tick = INSN_TICK (next)((&h_i_d[INSN_UID (next)])->tick);
    bool success = haifa_change_pattern (next,
			   ORIG_PAT (next)((&h_i_d[INSN_UID (next)])->orig_pat));
    INSN_TICK (next)((&h_i_d[INSN_UID (next)])->tick) = tick;
    gcc_assert (success)((void)(!(success) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1351, __FUNCTION__), 0 : 0));
  }

/* We can't handle the case where there are both speculative and control
   dependencies, so we return HARD_DEP in such a case.  Also fail if
   we have speculative dependencies with not enough points, or more than
   one control dependency.  */
if ((n_spec > 0 && (n_control > 0 || n_replace > 0))
    || (n_spec > 0
 /* Too few points?  */
 && ds_weak (new_ds) < spec_info->data_weakness_cutoff)
    || n_control > 0
    || n_replace > 0)
  return HARD_DEP(((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) << 1);

return new_ds;
1367}
1368
1369/* Pointer to the last instruction scheduled.  */
1370static rtx_insn *last_scheduled_insn;

1372/* Pointer to the last nondebug instruction scheduled within the
 block, or the prev_head of the scheduling block.  Used by
 rank_for_schedule, so that insns independent of the last scheduled
 insn will be preferred over dependent instructions.  */
1376static rtx_insn *last_nondebug_scheduled_insn;

1378/* Pointer that iterates through the list of unscheduled insns if we
 have a dbg_cnt enabled.  It always points at an insn prior to the
 first unscheduled one.  */
1381static rtx_insn *nonscheduled_insns_begin;

1383/* Compute cost of executing INSN.
 This is the number of cycles between instruction issue and
 instruction results.  */
1386int
1387insn_sched_cost (rtx_insn *insn)
1388{
int cost;

if (sched_fusion)
  return 0;

if (sel_sched_p ())
  {
    if (recog_memoized (insn) < 0)
return 0;

    cost = insn_default_latency (insn);
    if (cost < 0)
cost = 0;

    return cost;
  }

cost = INSN_COST (insn)((&h_i_d[INSN_UID (insn)])->cost);

if (cost < 0)
  {
    /* A USE insn, or something else we don't need to
understand.  We can't pass these directly to
result_ready_cost or insn_default_latency because it will
trigger a fatal error for unrecognizable insns.  */
    if (recog_memoized (insn) < 0)
{
 INSN_COST (insn)((&h_i_d[INSN_UID (insn)])->cost) = 0;
 return 0;
}
    else
{
 cost = insn_default_latency (insn);
 if (cost < 0)
   cost = 0;

 INSN_COST (insn)((&h_i_d[INSN_UID (insn)])->cost) = cost;
}
  }

return cost;
1430}

1432/* Compute cost of dependence LINK.
 This is the number of cycles between instruction issue and
 instruction results.
 ??? We also use this function to call recog_memoized on all insns.  */
1436int
1437dep_cost_1 (dep_t link, dw_t dw)
1438{
rtx_insn *insn = DEP_PRO (link)((link)->pro);
rtx_insn *used = DEP_CON (link)((link)->con);
int cost;

if (DEP_COST (link)((link)->cost) != UNKNOWN_DEP_COST((int) ((unsigned int) -1 << 19)))
  return DEP_COST (link)((link)->cost);

if (delay_htab)
  {
    struct delay_pair *delay_entry;
    delay_entry
= delay_htab_i2->find_with_hash (used, htab_hash_pointer (used));
    if (delay_entry)
{
 if (delay_entry->i1 == insn)
   {
     DEP_COST (link)((link)->cost) = pair_delay (delay_entry);
     return DEP_COST (link)((link)->cost);
   }
}
  }

/* A USE insn should never require the value used to be computed.
   This allows the computation of a function's result and parameter
   values to overlap the return and call.  We don't care about the
   dependence cost when only decreasing register pressure.  */
if (recog_memoized (used) < 0)
  {
    cost = 0;
    recog_memoized (insn);
  }
else
  {
    enum reg_note dep_type = DEP_TYPE (link)((link)->type);

    cost = insn_sched_cost (insn);

    if (INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) >= 0)
{
 if (dep_type == REG_DEP_ANTI)
   cost = 0;
 else if (dep_type == REG_DEP_OUTPUT)
   {
     cost = (insn_default_latency (insn)
      - insn_default_latency (used));
     if (cost <= 0)
cost = 1;
   }
 else if (bypass_p (insn))
   cost = insn_latency (insn, used);
}


    if (targetm.sched.adjust_cost)
cost = targetm.sched.adjust_cost (used, (int) dep_type, insn, cost,
			  dw);

    if (cost < 0)
cost = 0;
  }

DEP_COST (link)((link)->cost) = cost;
return cost;
1502}

1504/* Compute cost of dependence LINK.
 This is the number of cycles between instruction issue and
 instruction results.  */
1507int
1508dep_cost (dep_t link)
1509{
return dep_cost_1 (link, 0);
1511}

1513/* Use this sel-sched.cc friendly function in reorder2 instead of increasing
 INSN_PRIORITY explicitly.  */
1515void
1516increase_insn_priority (rtx_insn *insn, int amount)
1517{
if (!sel_sched_p ())
  {
    /* We're dealing with haifa-sched.cc INSN_PRIORITY.  */
    if (INSN_PRIORITY_KNOWN (insn)(((&h_i_d[INSN_UID (insn)])->priority_status) > 0))
 INSN_PRIORITY (insn)((&h_i_d[INSN_UID (insn)])->priority) += amount;
  }
else
  {
    /* In sel-sched.cc INSN_PRIORITY is not kept up to date.
Use EXPR_PRIORITY instead. */
    sel_add_to_insn_priority (insn, amount);
  }
1530}

1532/* Return 'true' if DEP should be included in priority calculations.  */
1533static bool
1534contributes_to_priority_p (dep_t dep)
1535{
if (DEBUG_INSN_P (DEP_CON (dep))(((enum rtx_code) (((dep)->con))->code) == DEBUG_INSN)
    || DEBUG_INSN_P (DEP_PRO (dep))(((enum rtx_code) (((dep)->pro))->code) == DEBUG_INSN))
  return false;

/* Critical path is meaningful in block boundaries only.  */
if (!current_sched_info->contributes_to_priority (DEP_CON (dep)((dep)->con),
				    DEP_PRO (dep)((dep)->pro)))
  return false;

if (DEP_REPLACE (dep)((dep)->replace) != NULLnullptr)
  return false;

/* If flag COUNT_SPEC_IN_CRITICAL_PATH is set,
   then speculative instructions will less likely be
   scheduled.  That is because the priority of
   their producers will increase, and, thus, the
   producers will more likely be scheduled, thus,
   resolving the dependence.  */
if (sched_deps_info->generate_spec_deps
    && !(spec_info->flags & COUNT_SPEC_IN_CRITICAL_PATH)
    && (DEP_STATUS (dep)((dep)->status) & SPECULATIVE(((((ds_t) ((1 << (((8 * 4) - 8) / 4)) - 1)) << BEGIN_DATA_BITS_OFFSET
) | (((ds_t) ((1 << (((8 * 4) - 8) / 4)) - 1)) <<
 BE_IN_DATA_BITS_OFFSET)) | ((((ds_t) ((1 << (((8 * 4) -
 8) / 4)) - 1)) << BEGIN_CONTROL_BITS_OFFSET) | (((ds_t
) ((1 << (((8 * 4) - 8) / 4)) - 1)) << BE_IN_CONTROL_BITS_OFFSET
)))))
  return false;

return true;
1560}

1562/* Compute the number of nondebug deps in list LIST for INSN.  */

1564static int
1565dep_list_size (rtx_insn *insn, sd_list_types_def list)
1566{
sd_iterator_def sd_it;
dep_t dep;
int dbgcount = 0, nodbgcount = 0;

if (!MAY_HAVE_DEBUG_INSNS(global_options.x_debug_nonbind_markers_p || global_options.x_flag_var_tracking_assignments
))
  return sd_lists_size (insn, list);

FOR_EACH_DEP (insn, list, sd_it, dep)for ((sd_it) = sd_iterator_start ((insn), (list)); sd_iterator_cond
 (&(sd_it), &(dep)); sd_iterator_next (&(sd_it)))
  {
    if (DEBUG_INSN_P (DEP_CON (dep))(((enum rtx_code) (((dep)->con))->code) == DEBUG_INSN))
dbgcount++;
    else if (!DEBUG_INSN_P (DEP_PRO (dep))(((enum rtx_code) (((dep)->pro))->code) == DEBUG_INSN))
nodbgcount++;
  }

gcc_assert (dbgcount + nodbgcount == sd_lists_size (insn, list))((void)(!(dbgcount + nodbgcount == sd_lists_size (insn, list)
) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1582, __FUNCTION__), 0 : 0));

return nodbgcount;
1585}

1587bool sched_fusion;

1589/* Compute the priority number for INSN.  */
1590static int
1591priority (rtx_insn *insn, bool force_recompute)
1592{
if (! INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
  return 0;

/* We should not be interested in priority of an already scheduled insn.  */
gcc_assert (QUEUE_INDEX (insn) != QUEUE_SCHEDULED)((void)(!(((&h_i_d[INSN_UID (insn)])->queue_index) != (
-3)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1597, __FUNCTION__), 0 : 0));

if (force_recompute || !INSN_PRIORITY_KNOWN (insn)(((&h_i_d[INSN_UID (insn)])->priority_status) > 0))
  {
    int this_priority = -1;

    if (sched_fusion)
{
 int this_fusion_priority;

 targetm.sched.fusion_priority (insn, FUSION_MAX_PRIORITY(2147483647),
			 &this_fusion_priority, &this_priority);
 INSN_FUSION_PRIORITY (insn)((&h_i_d[INSN_UID (insn)])->fusion_priority) = this_fusion_priority;
}
    else if (dep_list_size (insn, SD_LIST_FORW(4)) == 0)
/* ??? We should set INSN_PRIORITY to insn_sched_cost when and insn
  has some forward deps but all of them are ignored by
  contributes_to_priority hook.  At the moment we set priority of
  such insn to 0.  */
this_priority = insn_sched_cost (insn);
    else
{
 rtx_insn *prev_first, *twin;
 basic_block rec;

 /* For recovery check instructions we calculate priority slightly
    different than that of normal instructions.  Instead of walking
    through INSN_FORW_DEPS (check) list, we walk through
    INSN_FORW_DEPS list of each instruction in the corresponding
    recovery block.  */

        /* Selective scheduling does not define RECOVERY_BLOCK macro.  */
 rec = sel_sched_p () ? NULLnullptr : RECOVERY_BLOCK (insn)((&h_i_d[INSN_UID (insn)])->recovery_block);
 if (!rec || rec == EXIT_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_exit_block_ptr))
   {
     prev_first = PREV_INSN (insn);
     twin = insn;
   }
 else
   {
     prev_first = NEXT_INSN (BB_HEAD (rec)(rec)->il.x.head_);
     twin = PREV_INSN (BB_END (rec)(rec)->il.x.rtl->end_);
   }

 do
   {
     sd_iterator_def sd_it;
     dep_t dep;

     FOR_EACH_DEP (twin, SD_LIST_FORW, sd_it, dep)for ((sd_it) = sd_iterator_start ((twin), ((4))); sd_iterator_cond
 (&(sd_it), &(dep)); sd_iterator_next (&(sd_it)))
{
  rtx_insn *next;
  int next_priority;

  next = DEP_CON (dep)((dep)->con);

  if (BLOCK_FOR_INSN (next) != rec)
    {
      int cost;

      if (!contributes_to_priority_p (dep))
	continue;

      if (twin == insn)
	cost = dep_cost (dep);
      else
	{
	  struct _dep _dep1, *dep1 = &_dep1;

	  init_dep (dep1, insn, next, REG_DEP_ANTI);

	  cost = dep_cost (dep1);
	}

      next_priority = cost + priority (next);

      if (next_priority > this_priority)
	this_priority = next_priority;
    }
}

     twin = PREV_INSN (twin);
   }
 while (twin != prev_first);
}

    if (this_priority < 0)
{
 gcc_assert (this_priority == -1)((void)(!(this_priority == -1) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1685, __FUNCTION__), 0 : 0));

 this_priority = insn_sched_cost (insn);
}

    INSN_PRIORITY (insn)((&h_i_d[INSN_UID (insn)])->priority) = this_priority;
    INSN_PRIORITY_STATUS (insn)((&h_i_d[INSN_UID (insn)])->priority_status) = 1;
  }

return INSN_PRIORITY (insn)((&h_i_d[INSN_UID (insn)])->priority);
1695}
1696
1697/* Macros and functions for keeping the priority queue sorted, and
 dealing with queuing and dequeuing of instructions.  */

1700/* For each pressure class CL, set DEATH[CL] to the number of registers
 in that class that die in INSN.  */

1703static void
1704calculate_reg_deaths (rtx_insn *insn, int *death)
1705{
int i;
struct reg_use_data *use;

for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
  death[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]] = 0;
for (use = INSN_REG_USE_LIST (insn)((&h_i_d[INSN_UID (insn)])->reg_use_list); use != NULLnullptr; use = use->next_insn_use)
  if (dying_use_p (use))
    mark_regno_birth_or_death (0, death, use->regno, true);
1714}

1716/* Setup info about the current register pressure impact of scheduling
 INSN at the current scheduling point.  */
1718static void
1719setup_insn_reg_pressure_info (rtx_insn *insn)
1720{
int i, change, before, after, hard_regno;
int excess_cost_change;
machine_mode mode;
enum reg_class cl;
struct reg_pressure_data *pressure_info;
int *max_reg_pressure;
static int death[N_REG_CLASSES((int) LIM_REG_CLASSES)];

gcc_checking_assert (!DEBUG_INSN_P (insn))((void)(!(!(((enum rtx_code) (insn)->code) == DEBUG_INSN))
 ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1729, __FUNCTION__), 0 : 0));

excess_cost_change = 0;
calculate_reg_deaths (insn, death);
pressure_info = INSN_REG_PRESSURE (insn)((&h_i_d[INSN_UID (insn)])->reg_pressure);
max_reg_pressure = INSN_MAX_REG_PRESSURE (insn)((&h_i_d[INSN_UID (insn)])->max_reg_pressure);
gcc_assert (pressure_info != NULL && max_reg_pressure != NULL)((void)(!(pressure_info != nullptr && max_reg_pressure
 != nullptr) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1735, __FUNCTION__), 0 : 0));
for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
  {
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i];
    gcc_assert (curr_reg_pressure[cl] >= 0)((void)(!(curr_reg_pressure[cl] >= 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1739, __FUNCTION__), 0 : 0));
    change = (int) pressure_info[i].set_increase - death[cl];
    before = MAX (0, max_reg_pressure[i] - sched_class_regs_num[cl])((0) > (max_reg_pressure[i] - sched_class_regs_num[cl]) ? (
0) : (max_reg_pressure[i] - sched_class_regs_num[cl]));
    after = MAX (0, max_reg_pressure[i] + change((0) > (max_reg_pressure[i] + change - sched_class_regs_num
[cl]) ? (0) : (max_reg_pressure[i] + change - sched_class_regs_num
[cl]))
   - sched_class_regs_num[cl])((0) > (max_reg_pressure[i] + change - sched_class_regs_num
[cl]) ? (0) : (max_reg_pressure[i] + change - sched_class_regs_num
[cl]));
    hard_regno = ira_class_hard_regs(this_target_ira->x_ira_class_hard_regs)[cl][0];
    gcc_assert (hard_regno >= 0)((void)(!(hard_regno >= 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1745, __FUNCTION__), 0 : 0));
    mode = reg_raw_mode(this_target_regs->x_reg_raw_mode)[hard_regno];
    excess_cost_change += ((after - before)
	     * (ira_memory_move_cost(this_target_ira->x_ira_memory_move_cost)[mode][cl][0]
		+ ira_memory_move_cost(this_target_ira->x_ira_memory_move_cost)[mode][cl][1]));
  }
INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insn)((&h_i_d[INSN_UID (insn)])->reg_pressure_excess_cost_change
) = excess_cost_change;
1752}
1753
1754/* This is the first page of code related to SCHED_PRESSURE_MODEL.
 It tries to make the scheduler take register pressure into account
 without introducing too many unnecessary stalls.  It hooks into the
 main scheduling algorithm at several points:

  - Before scheduling starts, model_start_schedule constructs a
    "model schedule" for the current block.  This model schedule is
    chosen solely to keep register pressure down.  It does not take the
    target's pipeline or the original instruction order into account,
    except as a tie-breaker.  It also doesn't work to a particular
    pressure limit.

    This model schedule gives us an idea of what pressure can be
    achieved for the block and gives us an example of a schedule that
    keeps to that pressure.  It also makes the final schedule less
    dependent on the original instruction order.  This is important
    because the original order can either be "wide" (many values live
    at once, such as in user-scheduled code) or "narrow" (few values
    live at once, such as after loop unrolling, where several
    iterations are executed sequentially).

    We do not apply this model schedule to the rtx stream.  We simply
    record it in model_schedule.  We also compute the maximum pressure,
    MP, that was seen during this schedule.

  - Instructions are added to the ready queue even if they require
    a stall.  The length of the stall is instead computed as:

MAX (INSN_TICK (INSN) - clock_var, 0)

    (= insn_delay).  This allows rank_for_schedule to choose between
    introducing a deliberate stall or increasing pressure.

  - Before sorting the ready queue, model_set_excess_costs assigns
    a pressure-based cost to each ready instruction in the queue.
    This is the instruction's INSN_REG_PRESSURE_EXCESS_COST_CHANGE
    (ECC for short) and is effectively measured in cycles.

  - rank_for_schedule ranks instructions based on:

ECC (insn) + insn_delay (insn)

    then as:

insn_delay (insn)

    So, for example, an instruction X1 with an ECC of 1 that can issue
    now will win over an instruction X0 with an ECC of zero that would
    introduce a stall of one cycle.  However, an instruction X2 with an
    ECC of 2 that can issue now will lose to both X0 and X1.

  - When an instruction is scheduled, model_recompute updates the model
    schedule with the new pressures (some of which might now exceed the
    original maximum pressure MP).  model_update_limit_points then searches
    for the new point of maximum pressure, if not already known.  */

1810/* Used to separate high-verbosity debug information for SCHED_PRESSURE_MODEL
 from surrounding debug information.  */
1812#define MODEL_BAR";;\t\t+------------------------------------------------------\n" \
";;\t\t+------------------------------------------------------\n"

1815/* Information about the pressure on a particular register class at a
 particular point of the model schedule.  */
1817struct model_pressure_data {
/* The pressure at this point of the model schedule, or -1 if the
   point is associated with an instruction that has already been
   scheduled.  */
int ref_pressure;

/* The maximum pressure during or after this point of the model schedule.  */
int max_pressure;
1825};

1827/* Per-instruction information that is used while building the model
 schedule.  Here, "schedule" refers to the model schedule rather
 than the main schedule.  */
1830struct model_insn_info {
/* The instruction itself.  */
rtx_insn *insn;

/* If this instruction is in model_worklist, these fields link to the
   previous (higher-priority) and next (lower-priority) instructions
   in the list.  */
struct model_insn_info *prev;
struct model_insn_info *next;

/* While constructing the schedule, QUEUE_INDEX describes whether an
   instruction has already been added to the schedule (QUEUE_SCHEDULED),
   is in model_worklist (QUEUE_READY), or neither (QUEUE_NOWHERE).
   old_queue records the value that QUEUE_INDEX had before scheduling
   started, so that we can restore it once the schedule is complete.  */
int old_queue;

/* The relative importance of an unscheduled instruction.  Higher
   values indicate greater importance.  */
unsigned int model_priority;

/* The length of the longest path of satisfied true dependencies
   that leads to this instruction.  */
unsigned int depth;

/* The length of the longest path of dependencies of any kind
   that leads from this instruction.  */
unsigned int alap;

/* The number of predecessor nodes that must still be scheduled.  */
int unscheduled_preds;
1861};

1863/* Information about the pressure limit for a particular register class.
 This structure is used when applying a model schedule to the main
 schedule.  */
1866struct model_pressure_limit {
/* The maximum register pressure seen in the original model schedule.  */
int orig_pressure;

/* The maximum register pressure seen in the current model schedule
   (which excludes instructions that have already been scheduled).  */
int pressure;

/* The point of the current model schedule at which PRESSURE is first
   reached.  It is set to -1 if the value needs to be recomputed.  */
int point;
1877};

1879/* Describes a particular way of measuring register pressure.  */
1880struct model_pressure_group {
/* Index PCI describes the maximum pressure on ira_pressure_classes[PCI].  */
struct model_pressure_limit limits[N_REG_CLASSES((int) LIM_REG_CLASSES)];

/* Index (POINT * ira_num_pressure_classes + PCI) describes the pressure
   on register class ira_pressure_classes[PCI] at point POINT of the
   current model schedule.  A POINT of model_num_insns describes the
   pressure at the end of the schedule.  */
struct model_pressure_data *model;
1889};

1891/* Index POINT gives the instruction at point POINT of the model schedule.
 This array doesn't change during main scheduling.  */
1893static vec<rtx_insn *> model_schedule;

1895/* The list of instructions in the model worklist, sorted in order of
 decreasing priority.  */
1897static struct model_insn_info *model_worklist;

1899/* Index I describes the instruction with INSN_LUID I.  */
1900static struct model_insn_info *model_insns;

1902/* The number of instructions in the model schedule.  */
1903static int model_num_insns;

1905/* The index of the first instruction in model_schedule that hasn't yet been
 added to the main schedule, or model_num_insns if all of them have.  */
1907static int model_curr_point;

1909/* Describes the pressure before each instruction in the model schedule.  */
1910static struct model_pressure_group model_before_pressure;

1912/* The first unused model_priority value (as used in model_insn_info).  */
1913static unsigned int model_next_priority;


1916/* The model_pressure_data for ira_pressure_classes[PCI] in GROUP
 at point POINT of the model schedule.  */
1918#define MODEL_PRESSURE_DATA(GROUP, POINT, PCI)(&(GROUP)->model[(POINT) * (this_target_ira->x_ira_pressure_classes_num
) + (PCI)]) \
(&(GROUP)->model[(POINT) * ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num) + (PCI)])

1921/* The maximum pressure on ira_pressure_classes[PCI] in GROUP at or
 after point POINT of the model schedule.  */
1923#define MODEL_MAX_PRESSURE(GROUP, POINT, PCI)((&(GROUP)->model[(POINT) * (this_target_ira->x_ira_pressure_classes_num
) + (PCI)])->max_pressure) \
(MODEL_PRESSURE_DATA (GROUP, POINT, PCI)(&(GROUP)->model[(POINT) * (this_target_ira->x_ira_pressure_classes_num
) + (PCI)])->max_pressure)

1926/* The pressure on ira_pressure_classes[PCI] in GROUP at point POINT
 of the model schedule.  */
1928#define MODEL_REF_PRESSURE(GROUP, POINT, PCI)((&(GROUP)->model[(POINT) * (this_target_ira->x_ira_pressure_classes_num
) + (PCI)])->ref_pressure) \
(MODEL_PRESSURE_DATA (GROUP, POINT, PCI)(&(GROUP)->model[(POINT) * (this_target_ira->x_ira_pressure_classes_num
) + (PCI)])->ref_pressure)

1931/* Information about INSN that is used when creating the model schedule.  */
1932#define MODEL_INSN_INFO(INSN)(&model_insns[(sched_luids[INSN_UID (INSN)])]) \
(&model_insns[INSN_LUID (INSN)(sched_luids[INSN_UID (INSN)])])

1935/* The instruction at point POINT of the model schedule.  */
1936#define MODEL_INSN(POINT)(model_schedule[POINT]) \
(model_schedule[POINT])


1940/* Return INSN's index in the model schedule, or model_num_insns if it
 doesn't belong to that schedule.  */

1943static int
1944model_index (rtx_insn *insn)
1945{
if (INSN_MODEL_INDEX (insn)((&h_i_d[INSN_UID (insn)])->model_index) == 0)
  return model_num_insns;
return INSN_MODEL_INDEX (insn)((&h_i_d[INSN_UID (insn)])->model_index) - 1;
1949}

1951/* Make sure that GROUP->limits is up-to-date for the current point
 of the model schedule.  */

1954static void
1955model_update_limit_points_in_group (struct model_pressure_group *group)
1956{
int pci, max_pressure, point;

for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
  {
    /* We may have passed the final point at which the pressure in
group->limits[pci].pressure was reached.  Update the limit if so.  */
    max_pressure = MODEL_MAX_PRESSURE (group, model_curr_point, pci)((&(group)->model[(model_curr_point) * (this_target_ira
->x_ira_pressure_classes_num) + (pci)])->max_pressure);
    group->limits[pci].pressure = max_pressure;

    /* Find the point at which MAX_PRESSURE is first reached.  We need
to search in three cases:

- We've already moved past the previous pressure point.
  In this case we search forward from model_curr_point.

- We scheduled the previous point of maximum pressure ahead of
  its position in the model schedule, but doing so didn't bring
  the pressure point earlier.  In this case we search forward
  from that previous pressure point.

- Scheduling an instruction early caused the maximum pressure
  to decrease.  In this case we will have set the pressure
  point to -1, and we search forward from model_curr_point.  */
    point = MAX (group->limits[pci].point, model_curr_point)((group->limits[pci].point) > (model_curr_point) ? (group
->limits[pci].point) : (model_curr_point));
    while (point < model_num_insns
    && MODEL_REF_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->ref_pressure) < max_pressure)
point++;
    group->limits[pci].point = point;

    gcc_assert (MODEL_REF_PRESSURE (group, point, pci) == max_pressure)((void)(!(((&(group)->model[(point) * (this_target_ira
->x_ira_pressure_classes_num) + (pci)])->ref_pressure) ==
 max_pressure) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1986, __FUNCTION__), 0 : 0));
    gcc_assert (MODEL_MAX_PRESSURE (group, point, pci) == max_pressure)((void)(!(((&(group)->model[(point) * (this_target_ira
->x_ira_pressure_classes_num) + (pci)])->max_pressure) ==
 max_pressure) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 1987, __FUNCTION__), 0 : 0));
  }
1989}

1991/* Make sure that all register-pressure limits are up-to-date for the
 current position in the model schedule.  */

1994static void
1995model_update_limit_points (void)
1996{
model_update_limit_points_in_group (&model_before_pressure);
1998}

2000/* Return the model_index of the last unscheduled use in chain USE
 outside of USE's instruction.  Return -1 if there are no other uses,
 or model_num_insns if the register is live at the end of the block.  */

2004static int
2005model_last_use_except (struct reg_use_data *use)
2006{
struct reg_use_data *next;
int last, index;

last = -1;
for (next = use->next_regno_use; next != use; next = next->next_regno_use)
  if (NONDEBUG_INSN_P (next->insn)((((enum rtx_code) (next->insn)->code) == INSN) || (((enum
 rtx_code) (next->insn)->code) == JUMP_INSN) || (((enum
 rtx_code) (next->insn)->code) == CALL_INSN))
&& QUEUE_INDEX (next->insn)((&h_i_d[INSN_UID (next->insn)])->queue_index) != QUEUE_SCHEDULED(-3))
    {
index = model_index (next->insn);
if (index == model_num_insns)
 return model_num_insns;
if (last < index)
 last = index;
    }
return last;
2022}

2024/* An instruction with model_index POINT has just been scheduled, and it
 adds DELTA to the pressure on ira_pressure_classes[PCI] after POINT - 1.
 Update MODEL_REF_PRESSURE (GROUP, POINT, PCI) and
 MODEL_MAX_PRESSURE (GROUP, POINT, PCI) accordingly.  */

2029static void
2030model_start_update_pressure (struct model_pressure_group *group,
	     int point, int pci, int delta)
2032{
int next_max_pressure;

if (point == model_num_insns)
  {
    /* The instruction wasn't part of the model schedule; it was moved
from a different block.  Update the pressure for the end of
the model schedule.  */
    MODEL_REF_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->ref_pressure) += delta;
    MODEL_MAX_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->max_pressure) += delta;
  }
else
  {
    /* Record that this instruction has been scheduled.  Nothing now
changes between POINT and POINT + 1, so get the maximum pressure
from the latter.  If the maximum pressure decreases, the new
pressure point may be before POINT.  */
    MODEL_REF_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->ref_pressure) = -1;
    next_max_pressure = MODEL_MAX_PRESSURE (group, point + 1, pci)((&(group)->model[(point + 1) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->max_pressure);
    if (MODEL_MAX_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->max_pressure) > next_max_pressure)
{
 MODEL_MAX_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->max_pressure) = next_max_pressure;
 if (group->limits[pci].point == point)
   group->limits[pci].point = -1;
}
  }
2058}

2060/* Record that scheduling a later instruction has changed the pressure
 at point POINT of the model schedule by DELTA (which might be 0).
 Update GROUP accordingly.  Return nonzero if these changes might
 trigger changes to previous points as well.  */

2065static int
2066model_update_pressure (struct model_pressure_group *group,
       int point, int pci, int delta)
2068{
int ref_pressure, max_pressure, next_max_pressure;

/* If POINT hasn't yet been scheduled, update its pressure.  */
ref_pressure = MODEL_REF_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->ref_pressure);
if (ref_pressure >= 0 && delta != 0)
  {
    ref_pressure += delta;
    MODEL_REF_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->ref_pressure) = ref_pressure;

    /* Check whether the maximum pressure in the overall schedule
has increased.  (This means that the MODEL_MAX_PRESSURE of
every point <= POINT will need to increase too; see below.)  */
    if (group->limits[pci].pressure < ref_pressure)
group->limits[pci].pressure = ref_pressure;

    /* If we are at maximum pressure, and the maximum pressure
point was previously unknown or later than POINT,
bring it forward.  */
    if (group->limits[pci].pressure == ref_pressure
 && !IN_RANGE (group->limits[pci].point, 0, point)((unsigned long) (group->limits[pci].point) - (unsigned long
) (0) <= (unsigned long) (point) - (unsigned long) (0)))
group->limits[pci].point = point;

    /* If POINT used to be the point of maximum pressure, but isn't
any longer, we need to recalculate it using a forward walk.  */
    if (group->limits[pci].pressure > ref_pressure
 && group->limits[pci].point == point)
group->limits[pci].point = -1;
  }

/* Update the maximum pressure at POINT.  Changes here might also
   affect the maximum pressure at POINT - 1.  */
next_max_pressure = MODEL_MAX_PRESSURE (group, point + 1, pci)((&(group)->model[(point + 1) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->max_pressure);
max_pressure = MAX (ref_pressure, next_max_pressure)((ref_pressure) > (next_max_pressure) ? (ref_pressure) : (
next_max_pressure));
if (MODEL_MAX_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->max_pressure) != max_pressure)
  {
    MODEL_MAX_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->max_pressure) = max_pressure;
    return 1;
  }
return 0;
2108}

2110/* INSN has just been scheduled.  Update the model schedule accordingly.  */

2112static void
2113model_recompute (rtx_insn *insn)
2114{
struct {
  int last_use;
  int regno;
} uses[FIRST_PSEUDO_REGISTER76 + MAX_RECOG_OPERANDS30];
struct reg_use_data *use;
struct reg_pressure_data *reg_pressure;
int delta[N_REG_CLASSES((int) LIM_REG_CLASSES)];
int pci, point, mix, new_last, cl, ref_pressure, queue;
unsigned int i, num_uses, num_pending_births;
bool print_p;

/* The destinations of INSN were previously live from POINT onwards, but are
   now live from model_curr_point onwards.  Set up DELTA accordingly.  */
point = model_index (insn);
reg_pressure = INSN_REG_PRESSURE (insn)((&h_i_d[INSN_UID (insn)])->reg_pressure);
for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
  {
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
    delta[cl] = reg_pressure[pci].set_increase;
  }

/* Record which registers previously died at POINT, but which now die
   before POINT.  Adjust DELTA so that it represents the effect of
   this change after POINT - 1.  Set NUM_PENDING_BIRTHS to the number of
   registers that will be born in the range [model_curr_point, POINT).  */
num_uses = 0;
num_pending_births = 0;
bitmap_clear (tmp_bitmap);
for (use = INSN_REG_USE_LIST (insn)((&h_i_d[INSN_UID (insn)])->reg_use_list); use != NULLnullptr; use = use->next_insn_use)
  {
    new_last = model_last_use_except (use);
    if (new_last < point && bitmap_set_bit (tmp_bitmap, use->regno))
{
 gcc_assert (num_uses < ARRAY_SIZE (uses))((void)(!(num_uses < (sizeof (uses) / sizeof ((uses)[0])))
 ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2148, __FUNCTION__), 0 : 0));
 uses[num_uses].last_use = new_last;
 uses[num_uses].regno = use->regno;
 /* This register is no longer live after POINT - 1.  */
 mark_regno_birth_or_death (NULLnullptr, delta, use->regno, false);
 num_uses++;
 if (new_last >= 0)
   num_pending_births++;
}
  }

/* Update the MODEL_REF_PRESSURE and MODEL_MAX_PRESSURE for POINT.
   Also set each group pressure limit for POINT.  */
for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
  {
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
    model_start_update_pressure (&model_before_pressure,
		   point, pci, delta[cl]);
  }

/* Walk the model schedule backwards, starting immediately before POINT.  */
print_p = false;
if (point != model_curr_point)
  do
    {
point--;
insn = MODEL_INSN (point)(model_schedule[point]);
queue = QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index);

if (queue != QUEUE_SCHEDULED(-3))
 {
   /* DELTA describes the effect of the move on the register pressure
      after POINT.  Make it describe the effect on the pressure
      before POINT.  */
   i = 0;
   while (i < num_uses)
     {
if (uses[i].last_use == point)
  {
    /* This register is now live again.  */
    mark_regno_birth_or_death (NULLnullptr, delta,
			       uses[i].regno, true);

    /* Remove this use from the array.  */
    uses[i] = uses[num_uses - 1];
    num_uses--;
    num_pending_births--;
  }
else
  i++;
     }

   if (sched_verbose >= 5)
     {
if (!print_p)
  {
    fprintf (sched_dump, MODEL_BAR";;\t\t+------------------------------------------------------\n");
    fprintf (sched_dump, ";;\t\t| New pressure for model"
	     " schedule\n");
    fprintf (sched_dump, MODEL_BAR";;\t\t+------------------------------------------------------\n");
    print_p = true;
  }

fprintf (sched_dump, ";;\t\t| %3d %4d %-30s ",
	 point, INSN_UID (insn),
	 str_pattern_slim (PATTERN (insn)));
for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
  {
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
    ref_pressure = MODEL_REF_PRESSURE (&model_before_pressure,((&(&model_before_pressure)->model[(point) * (this_target_ira
->x_ira_pressure_classes_num) + (pci)])->ref_pressure)
				       point, pci)((&(&model_before_pressure)->model[(point) * (this_target_ira
->x_ira_pressure_classes_num) + (pci)])->ref_pressure);
    fprintf (sched_dump, " %s:[%d->%d]",
	     reg_class_names[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci]],
	     ref_pressure, ref_pressure + delta[cl]);
  }
fprintf (sched_dump, "\n");
     }
 }

/* Adjust the pressure at POINT.  Set MIX to nonzero if POINT - 1
  might have changed as well.  */
mix = num_pending_births;
for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
 {
   cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
   mix |= delta[cl];
   mix |= model_update_pressure (&model_before_pressure,
			  point, pci, delta[cl]);
 }
    }
  while (mix && point > model_curr_point);

if (print_p)
  fprintf (sched_dump, MODEL_BAR";;\t\t+------------------------------------------------------\n");
2242}

2244/* After DEP, which was cancelled, has been resolved for insn NEXT,
 check whether the insn's pattern needs restoring.  */
2246static bool
2247must_restore_pattern_p (rtx_insn *next, dep_t dep)
2248{
if (QUEUE_INDEX (next)((&h_i_d[INSN_UID (next)])->queue_index) == QUEUE_SCHEDULED(-3))
  return false;

if (DEP_TYPE (dep)((dep)->type) == REG_DEP_CONTROL)
  {
    gcc_assert (ORIG_PAT (next) != NULL_RTX)((void)(!(((&h_i_d[INSN_UID (next)])->orig_pat) != (rtx
) 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2254, __FUNCTION__), 0 : 0));
    gcc_assert (next == DEP_CON (dep))((void)(!(next == ((dep)->con)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2255, __FUNCTION__), 0 : 0));
  }
else
  {
    struct dep_replacement *desc = DEP_REPLACE (dep)((dep)->replace);
    if (desc->insn != next)
{
 gcc_assert (*desc->loc == desc->orig)((void)(!(*desc->loc == desc->orig) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2262, __FUNCTION__), 0 : 0));
 return false;
}
  }
return true;
2267}
2268
2269/* model_spill_cost (CL, P, P') returns the cost of increasing the
 pressure on CL from P to P'.  We use this to calculate a "base ECC",
 baseECC (CL, X), for each pressure class CL and each instruction X.
 Supposing X changes the pressure on CL from P to P', and that the
 maximum pressure on CL in the current model schedule is MP', then:

 * if X occurs before or at the next point of maximum pressure in
   the model schedule and P' > MP', then:

     baseECC (CL, X) = model_spill_cost (CL, MP, P')

   The idea is that the pressure after scheduling a fixed set of
   instructions -- in this case, the set up to and including the
   next maximum pressure point -- is going to be the same regardless
   of the order; we simply want to keep the intermediate pressure
   under control.  Thus X has a cost of zero unless scheduling it
   now would exceed MP'.

   If all increases in the set are by the same amount, no zero-cost
   instruction will ever cause the pressure to exceed MP'.  However,
   if X is instead moved past an instruction X' with pressure in the
   range (MP' - (P' - P), MP'), the pressure at X' will increase
   beyond MP'.  Since baseECC is very much a heuristic anyway,
   it doesn't seem worth the overhead of tracking cases like these.

   The cost of exceeding MP' is always based on the original maximum
   pressure MP.  This is so that going 2 registers over the original
   limit has the same cost regardless of whether it comes from two
   separate +1 deltas or from a single +2 delta.

 * if X occurs after the next point of maximum pressure in the model
   schedule and P' > P, then:

     baseECC (CL, X) = model_spill_cost (CL, MP, MP' + (P' - P))

   That is, if we move X forward across a point of maximum pressure,
   and if X increases the pressure by P' - P, then we conservatively
   assume that scheduling X next would increase the maximum pressure
   by P' - P.  Again, the cost of doing this is based on the original
   maximum pressure MP, for the same reason as above.

 * if P' < P, P > MP, and X occurs at or after the next point of
   maximum pressure, then:

     baseECC (CL, X) = -model_spill_cost (CL, MAX (MP, P'), P)

   That is, if we have already exceeded the original maximum pressure MP,
   and if X might reduce the maximum pressure again -- or at least push
   it further back, and thus allow more scheduling freedom -- it is given
   a negative cost to reflect the improvement.

 * otherwise,

     baseECC (CL, X) = 0

   In this case, X is not expected to affect the maximum pressure MP',
   so it has zero cost.

 We then create a combined value baseECC (X) that is the sum of
 baseECC (CL, X) for each pressure class CL.

 baseECC (X) could itself be used as the ECC value described above.
 However, this is often too conservative, in the sense that it
 tends to make high-priority instructions that increase pressure
 wait too long in cases where introducing a spill would be better.
 For this reason the final ECC is a priority-adjusted form of
 baseECC (X).  Specifically, we calculate:

   P (X) = INSN_PRIORITY (X) - insn_delay (X) - baseECC (X)
   baseP = MAX { P (X) | baseECC (X) <= 0 }

 Then:

   ECC (X) = MAX (MIN (baseP - P (X), baseECC (X)), 0)

 Thus an instruction's effect on pressure is ignored if it has a high
 enough priority relative to the ones that don't increase pressure.
 Negative values of baseECC (X) do not increase the priority of X
 itself, but they do make it harder for other instructions to
 increase the pressure further.

 This pressure cost is deliberately timid.  The intention has been
 to choose a heuristic that rarely interferes with the normal list
 scheduler in cases where that scheduler would produce good code.
 We simply want to curb some of its worst excesses.  */

2355/* Return the cost of increasing the pressure in class CL from FROM to TO.

 Here we use the very simplistic cost model that every register above
 sched_class_regs_num[CL] has a spill cost of 1.  We could use other
 measures instead, such as one based on MEMORY_MOVE_COST.  However:

    (1) In order for an instruction to be scheduled, the higher cost
 would need to be justified in a single saving of that many stalls.
 This is overly pessimistic, because the benefit of spilling is
 often to avoid a sequence of several short stalls rather than
 a single long one.

    (2) The cost is still arbitrary.  Because we are not allocating
 registers during scheduling, we have no way of knowing for
 sure how many memory accesses will be required by each spill,
 where the spills will be placed within the block, or even
 which block(s) will contain the spills.

 So a higher cost than 1 is often too conservative in practice,
 forcing blocks to contain unnecessary stalls instead of spill code.
 The simple cost below seems to be the best compromise.  It reduces
 the interference with the normal list scheduler, which helps make
 it more suitable for a default-on option.  */

2379static int
2380model_spill_cost (int cl, int from, int to)
2381{
from = MAX (from, sched_class_regs_num[cl])((from) > (sched_class_regs_num[cl]) ? (from) : (sched_class_regs_num
[cl]));
return MAX (to, from)((to) > (from) ? (to) : (from)) - from;
2384}

2386/* Return baseECC (ira_pressure_classes[PCI], POINT), given that
 P = curr_reg_pressure[ira_pressure_classes[PCI]] and that
 P' = P + DELTA.  */

2390static int
2391model_excess_group_cost (struct model_pressure_group *group,
	 int point, int pci, int delta)
2393{
int pressure, cl;

cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
if (delta < 0 && point >= group->limits[pci].point)
  {
    pressure = MAX (group->limits[pci].orig_pressure,((group->limits[pci].orig_pressure) > (curr_reg_pressure
[cl] + delta) ? (group->limits[pci].orig_pressure) : (curr_reg_pressure
[cl] + delta))
      curr_reg_pressure[cl] + delta)((group->limits[pci].orig_pressure) > (curr_reg_pressure
[cl] + delta) ? (group->limits[pci].orig_pressure) : (curr_reg_pressure
[cl] + delta));
    return -model_spill_cost (cl, pressure, curr_reg_pressure[cl]);
  }

if (delta > 0)
  {
    if (point > group->limits[pci].point)
pressure = group->limits[pci].pressure + delta;
    else
pressure = curr_reg_pressure[cl] + delta;

    if (pressure > group->limits[pci].pressure)
return model_spill_cost (cl, group->limits[pci].orig_pressure,
		 pressure);
  }

return 0;
2417}

2419/* Return baseECC (MODEL_INSN (INSN)).  Dump the costs to sched_dump
 if PRINT_P.  */

2422static int
2423model_excess_cost (rtx_insn *insn, bool print_p)
2424{
int point, pci, cl, cost, this_cost, delta;
struct reg_pressure_data *insn_reg_pressure;
int insn_death[N_REG_CLASSES((int) LIM_REG_CLASSES)];

calculate_reg_deaths (insn, insn_death);
point = model_index (insn);
insn_reg_pressure = INSN_REG_PRESSURE (insn)((&h_i_d[INSN_UID (insn)])->reg_pressure);
cost = 0;

if (print_p)
  fprintf (sched_dump, ";;\t\t| %3d %4d | %4d %+3d |", point,
    INSN_UID (insn), INSN_PRIORITY (insn)((&h_i_d[INSN_UID (insn)])->priority), insn_delay (insn));

/* Sum up the individual costs for each register class.  */
for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
  {
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
    delta = insn_reg_pressure[pci].set_increase - insn_death[cl];
    this_cost = model_excess_group_cost (&model_before_pressure,
			   point, pci, delta);
    cost += this_cost;
    if (print_p)
fprintf (sched_dump, " %s:[%d base cost %d]",
 reg_class_names[cl], delta, this_cost);
  }

if (print_p)
  fprintf (sched_dump, "\n");

return cost;
2455}

2457/* Dump the next points of maximum pressure for GROUP.  */

2459static void
2460model_dump_pressure_points (struct model_pressure_group *group)
2461{
int pci, cl;

fprintf (sched_dump, ";;\t\t|  pressure points");
for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
  {
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
    fprintf (sched_dump, " %s:[%d->%d at ", reg_class_names[cl],
      curr_reg_pressure[cl], group->limits[pci].pressure);
    if (group->limits[pci].point < model_num_insns)
fprintf (sched_dump, "%d:%d]", group->limits[pci].point,
 INSN_UID (MODEL_INSN (group->limits[pci].point)(model_schedule[group->limits[pci].point])));
    else
fprintf (sched_dump, "end]");
  }
fprintf (sched_dump, "\n");
2477}

2479/* Set INSN_REG_PRESSURE_EXCESS_COST_CHANGE for INSNS[0...COUNT-1].  */

2481static void
2482model_set_excess_costs (rtx_insn **insns, int count)
2483{
int i, cost, priority_base, priority;
bool print_p;

/* Record the baseECC value for each instruction in the model schedule,
   except that negative costs are converted to zero ones now rather than
   later.  Do not assign a cost to debug instructions, since they must
   not change code-generation decisions.  Experiments suggest we also
   get better results by not assigning a cost to instructions from
   a different block.

   Set PRIORITY_BASE to baseP in the block comment above.  This is the
   maximum priority of the "cheap" instructions, which should always
   include the next model instruction.  */
priority_base = 0;
print_p = false;
for (i = 0; i < count; i++)
  if (INSN_MODEL_INDEX (insns[i])((&h_i_d[INSN_UID (insns[i])])->model_index))
    {
if (sched_verbose >= 6 && !print_p)
 {
   fprintf (sched_dump, MODEL_BAR";;\t\t+------------------------------------------------------\n");
   fprintf (sched_dump, ";;\t\t| Pressure costs for ready queue\n");
   model_dump_pressure_points (&model_before_pressure);
   fprintf (sched_dump, MODEL_BAR";;\t\t+------------------------------------------------------\n");
   print_p = true;
 }
cost = model_excess_cost (insns[i], print_p);
if (cost <= 0)
 {
   priority = INSN_PRIORITY (insns[i])((&h_i_d[INSN_UID (insns[i])])->priority) - insn_delay (insns[i]) - cost;
   priority_base = MAX (priority_base, priority)((priority_base) > (priority) ? (priority_base) : (priority
));
   cost = 0;
 }
INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insns[i])((&h_i_d[INSN_UID (insns[i])])->reg_pressure_excess_cost_change
) = cost;
    }
if (print_p)
  fprintf (sched_dump, MODEL_BAR";;\t\t+------------------------------------------------------\n");

/* Use MAX (baseECC, 0) and baseP to calculcate ECC for each
   instruction.  */
for (i = 0; i < count; i++)
  {
    cost = INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insns[i])((&h_i_d[INSN_UID (insns[i])])->reg_pressure_excess_cost_change
);
    priority = INSN_PRIORITY (insns[i])((&h_i_d[INSN_UID (insns[i])])->priority) - insn_delay (insns[i]);
    if (cost > 0 && priority > priority_base)
{
 cost += priority_base - priority;
 INSN_REG_PRESSURE_EXCESS_COST_CHANGE (insns[i])((&h_i_d[INSN_UID (insns[i])])->reg_pressure_excess_cost_change
) = MAX (cost, 0)((cost) > (0) ? (cost) : (0));
}
  }
2534}
2535

2537/* Enum of rank_for_schedule heuristic decisions.  */
2538enum rfs_decision {
RFS_LIVE_RANGE_SHRINK1, RFS_LIVE_RANGE_SHRINK2,
RFS_SCHED_GROUP, RFS_PRESSURE_DELAY, RFS_PRESSURE_TICK,
RFS_FEEDS_BACKTRACK_INSN, RFS_PRIORITY, RFS_AUTOPREF, RFS_SPECULATION,
RFS_SCHED_RANK, RFS_LAST_INSN, RFS_PRESSURE_INDEX,
RFS_DEP_COUNT, RFS_TIE, RFS_FUSION, RFS_COST, RFS_N };

2545/* Corresponding strings for print outs.  */
2546static const char *rfs_str[RFS_N] = {
"RFS_LIVE_RANGE_SHRINK1", "RFS_LIVE_RANGE_SHRINK2",
"RFS_SCHED_GROUP", "RFS_PRESSURE_DELAY", "RFS_PRESSURE_TICK",
"RFS_FEEDS_BACKTRACK_INSN", "RFS_PRIORITY", "RFS_AUTOPREF", "RFS_SPECULATION",
"RFS_SCHED_RANK", "RFS_LAST_INSN", "RFS_PRESSURE_INDEX",
"RFS_DEP_COUNT", "RFS_TIE", "RFS_FUSION", "RFS_COST" };

2553/* Statistical breakdown of rank_for_schedule decisions.  */
2554struct rank_for_schedule_stats_t { unsigned stats[RFS_N]; };
2555static rank_for_schedule_stats_t rank_for_schedule_stats;

2557/* Return the result of comparing insns TMP and TMP2 and update
 Rank_For_Schedule statistics.  */
2559static int
2560rfs_result (enum rfs_decision decision, int result, rtx tmp, rtx tmp2)
2561{
++rank_for_schedule_stats.stats[decision];
if (result < 0)
  INSN_LAST_RFS_WIN (tmp)((&h_i_d[INSN_UID (tmp)])->last_rfs_win) = decision;
else if (result > 0)
  INSN_LAST_RFS_WIN (tmp2)((&h_i_d[INSN_UID (tmp2)])->last_rfs_win) = decision;
else
  gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2568, __FUNCTION__));
return result;
2570}

2572/* Sorting predicate to move DEBUG_INSNs to the top of ready list, while
 keeping normal insns in original order.  */

2575static int
2576rank_for_schedule_debug (const void *x, const void *y)
2577{
rtx_insn *tmp = *(rtx_insn * const *) y;
rtx_insn *tmp2 = *(rtx_insn * const *) x;

/* Schedule debug insns as early as possible.  */
if (DEBUG_INSN_P (tmp)(((enum rtx_code) (tmp)->code) == DEBUG_INSN) && !DEBUG_INSN_P (tmp2)(((enum rtx_code) (tmp2)->code) == DEBUG_INSN))
  return -1;
else if (!DEBUG_INSN_P (tmp)(((enum rtx_code) (tmp)->code) == DEBUG_INSN) && DEBUG_INSN_P (tmp2)(((enum rtx_code) (tmp2)->code) == DEBUG_INSN))
  return 1;
else if (DEBUG_INSN_P (tmp)(((enum rtx_code) (tmp)->code) == DEBUG_INSN) && DEBUG_INSN_P (tmp2)(((enum rtx_code) (tmp2)->code) == DEBUG_INSN))
  return INSN_LUID (tmp)(sched_luids[INSN_UID (tmp)]) - INSN_LUID (tmp2)(sched_luids[INSN_UID (tmp2)]);
else
  return INSN_RFS_DEBUG_ORIG_ORDER (tmp2)((&h_i_d[INSN_UID (tmp2)])->rfs_debug_orig_order) - INSN_RFS_DEBUG_ORIG_ORDER (tmp)((&h_i_d[INSN_UID (tmp)])->rfs_debug_orig_order);
2590}

2592/* Returns a positive value if x is preferred; returns a negative value if
 y is preferred.  Should never return 0, since that will make the sort
 unstable.  */

2596static int
2597rank_for_schedule (const void *x, const void *y)
2598{
rtx_insn *tmp = *(rtx_insn * const *) y;
rtx_insn *tmp2 = *(rtx_insn * const *) x;
int tmp_class, tmp2_class;
int val, priority_val, info_val, diff;

if (live_range_shrinkage_p)
  {
    /* Don't use SCHED_PRESSURE_MODEL -- it results in much worse
code.  */
    gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED)((void)(!(sched_pressure == SCHED_PRESSURE_WEIGHTED) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2608, __FUNCTION__), 0 : 0));
    if ((INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp)((&h_i_d[INSN_UID (tmp)])->reg_pressure_excess_cost_change
) < 0
  || INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp2)((&h_i_d[INSN_UID (tmp2)])->reg_pressure_excess_cost_change
) < 0)
 && (diff = (INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp)((&h_i_d[INSN_UID (tmp)])->reg_pressure_excess_cost_change
)
      - INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp2)((&h_i_d[INSN_UID (tmp2)])->reg_pressure_excess_cost_change
))) != 0)
return rfs_result (RFS_LIVE_RANGE_SHRINK1, diff, tmp, tmp2);
    /* Sort by INSN_LUID (original insn order), so that we make the
sort stable.  This minimizes instruction movement, thus
minimizing sched's effect on debugging and cross-jumping.  */
    return rfs_result (RFS_LIVE_RANGE_SHRINK2,
	 INSN_LUID (tmp)(sched_luids[INSN_UID (tmp)]) - INSN_LUID (tmp2)(sched_luids[INSN_UID (tmp2)]), tmp, tmp2);
  }

/* The insn in a schedule group should be issued the first.  */
if (flag_sched_group_heuristicglobal_options.x_flag_sched_group_heuristic &&
    SCHED_GROUP_P (tmp)(__extension__ ({ __typeof ((tmp)) const _rtx = ((tmp)); if (
((enum rtx_code) (_rtx)->code) != DEBUG_INSN && ((
enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != JUMP_INSN && ((enum rtx_code) (
_rtx)->code) != CALL_INSN) rtl_check_failed_flag ("SCHED_GROUP_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2623, __FUNCTION__); _rtx; })->in_struct) != SCHED_GROUP_P (tmp2)(__extension__ ({ __typeof ((tmp2)) const _rtx = ((tmp2)); if
 (((enum rtx_code) (_rtx)->code) != DEBUG_INSN && (
(enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != JUMP_INSN && ((enum rtx_code) (
_rtx)->code) != CALL_INSN) rtl_check_failed_flag ("SCHED_GROUP_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2623, __FUNCTION__); _rtx; })->in_struct))
  return rfs_result (RFS_SCHED_GROUP, SCHED_GROUP_P (tmp2)(__extension__ ({ __typeof ((tmp2)) const _rtx = ((tmp2)); if
 (((enum rtx_code) (_rtx)->code) != DEBUG_INSN && (
(enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != JUMP_INSN && ((enum rtx_code) (
_rtx)->code) != CALL_INSN) rtl_check_failed_flag ("SCHED_GROUP_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2624, __FUNCTION__); _rtx; })->in_struct) ? 1 : -1,
       tmp, tmp2);

/* Make sure that priority of TMP and TMP2 are initialized.  */
gcc_assert (INSN_PRIORITY_KNOWN (tmp) && INSN_PRIORITY_KNOWN (tmp2))((void)(!((((&h_i_d[INSN_UID (tmp)])->priority_status)
 > 0) && (((&h_i_d[INSN_UID (tmp2)])->priority_status
) > 0)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2628, __FUNCTION__), 0 : 0));

if (sched_fusion)
  {
    /* The instruction that has the same fusion priority as the last
instruction is the instruction we picked next.  If that is not
the case, we sort ready list firstly by fusion priority, then
by priority, and at last by INSN_LUID.  */
    int a = INSN_FUSION_PRIORITY (tmp)((&h_i_d[INSN_UID (tmp)])->fusion_priority);
    int b = INSN_FUSION_PRIORITY (tmp2)((&h_i_d[INSN_UID (tmp2)])->fusion_priority);
    int last = -1;

    if (last_nondebug_scheduled_insn
 && !NOTE_P (last_nondebug_scheduled_insn)(((enum rtx_code) (last_nondebug_scheduled_insn)->code) ==
 NOTE)
 && BLOCK_FOR_INSN (tmp)
      == BLOCK_FOR_INSN (last_nondebug_scheduled_insn))
last = INSN_FUSION_PRIORITY (last_nondebug_scheduled_insn)((&h_i_d[INSN_UID (last_nondebug_scheduled_insn)])->fusion_priority
);

    if (a != last && b != last)
{
 if (a == b)
   {
     a = INSN_PRIORITY (tmp)((&h_i_d[INSN_UID (tmp)])->priority);
     b = INSN_PRIORITY (tmp2)((&h_i_d[INSN_UID (tmp2)])->priority);
   }
 if (a != b)
   return rfs_result (RFS_FUSION, b - a, tmp, tmp2);
 else
   return rfs_result (RFS_FUSION,
	       INSN_LUID (tmp)(sched_luids[INSN_UID (tmp)]) - INSN_LUID (tmp2)(sched_luids[INSN_UID (tmp2)]), tmp, tmp2);
}
    else if (a == b)
{
 gcc_assert (last_nondebug_scheduled_insn((void)(!(last_nondebug_scheduled_insn && !(((enum rtx_code
) (last_nondebug_scheduled_insn)->code) == NOTE)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2662, __FUNCTION__), 0 : 0))
      && !NOTE_P (last_nondebug_scheduled_insn))((void)(!(last_nondebug_scheduled_insn && !(((enum rtx_code
) (last_nondebug_scheduled_insn)->code) == NOTE)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2662, __FUNCTION__), 0 : 0));
 last = INSN_PRIORITY (last_nondebug_scheduled_insn)((&h_i_d[INSN_UID (last_nondebug_scheduled_insn)])->priority
);

 a = abs (INSN_PRIORITY (tmp)((&h_i_d[INSN_UID (tmp)])->priority) - last);
 b = abs (INSN_PRIORITY (tmp2)((&h_i_d[INSN_UID (tmp2)])->priority) - last);
 if (a != b)
   return rfs_result (RFS_FUSION, a - b, tmp, tmp2);
 else
   return rfs_result (RFS_FUSION,
	       INSN_LUID (tmp)(sched_luids[INSN_UID (tmp)]) - INSN_LUID (tmp2)(sched_luids[INSN_UID (tmp2)]), tmp, tmp2);
}
    else if (a == last)
return rfs_result (RFS_FUSION, -1, tmp, tmp2);
    else
return rfs_result (RFS_FUSION, 1, tmp, tmp2);
  }

if (sched_pressure != SCHED_PRESSURE_NONE)
  {
    /* Prefer insn whose scheduling results in the smallest register
pressure excess.  */
    if ((diff = (INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp)((&h_i_d[INSN_UID (tmp)])->reg_pressure_excess_cost_change
)
   + insn_delay (tmp)
   - INSN_REG_PRESSURE_EXCESS_COST_CHANGE (tmp2)((&h_i_d[INSN_UID (tmp2)])->reg_pressure_excess_cost_change
)
   - insn_delay (tmp2))))
return rfs_result (RFS_PRESSURE_DELAY, diff, tmp, tmp2);
  }

if (sched_pressure != SCHED_PRESSURE_NONE
    && (INSN_TICK (tmp2)((&h_i_d[INSN_UID (tmp2)])->tick) > clock_var || INSN_TICK (tmp)((&h_i_d[INSN_UID (tmp)])->tick) > clock_var)
    && INSN_TICK (tmp2)((&h_i_d[INSN_UID (tmp2)])->tick) != INSN_TICK (tmp)((&h_i_d[INSN_UID (tmp)])->tick))
  {
    diff = INSN_TICK (tmp)((&h_i_d[INSN_UID (tmp)])->tick) - INSN_TICK (tmp2)((&h_i_d[INSN_UID (tmp2)])->tick);
    return rfs_result (RFS_PRESSURE_TICK, diff, tmp, tmp2);
  }

/* If we are doing backtracking in this schedule, prefer insns that
   have forward dependencies with negative cost against an insn that
   was already scheduled.  */
if (current_sched_info->flags & DO_BACKTRACKING)
  {
    priority_val = FEEDS_BACKTRACK_INSN (tmp2)((&h_i_d[INSN_UID (tmp2)])->feeds_backtrack_insn) - FEEDS_BACKTRACK_INSN (tmp)((&h_i_d[INSN_UID (tmp)])->feeds_backtrack_insn);
    if (priority_val)
return rfs_result (RFS_FEEDS_BACKTRACK_INSN, priority_val, tmp, tmp2);
  }

/* Prefer insn with higher priority.  */
priority_val = INSN_PRIORITY (tmp2)((&h_i_d[INSN_UID (tmp2)])->priority) - INSN_PRIORITY (tmp)((&h_i_d[INSN_UID (tmp)])->priority);

if (flag_sched_critical_path_heuristicglobal_options.x_flag_sched_critical_path_heuristic && priority_val)
  return rfs_result (RFS_PRIORITY, priority_val, tmp, tmp2);

if (param_sched_autopref_queue_depthglobal_options.x_param_sched_autopref_queue_depth >= 0)
  {
    int autopref = autopref_rank_for_schedule (tmp, tmp2);
    if (autopref != 0)
return rfs_result (RFS_AUTOPREF, autopref, tmp, tmp2);
  }

/* Prefer speculative insn with greater dependencies weakness.  */
if (flag_sched_spec_insn_heuristicglobal_options.x_flag_sched_spec_insn_heuristic && spec_info)
  {
    ds_t ds1, ds2;
    dw_t dw1, dw2;
    int dw;

    ds1 = TODO_SPEC (tmp)((&h_i_d[INSN_UID (tmp)])->todo_spec) & SPECULATIVE(((((ds_t) ((1 << (((8 * 4) - 8) / 4)) - 1)) << BEGIN_DATA_BITS_OFFSET
) | (((ds_t) ((1 << (((8 * 4) - 8) / 4)) - 1)) <<
 BE_IN_DATA_BITS_OFFSET)) | ((((ds_t) ((1 << (((8 * 4) -
 8) / 4)) - 1)) << BEGIN_CONTROL_BITS_OFFSET) | (((ds_t
) ((1 << (((8 * 4) - 8) / 4)) - 1)) << BE_IN_CONTROL_BITS_OFFSET
)));
    if (ds1)
dw1 = ds_weak (ds1);
    else
dw1 = NO_DEP_WEAK((((1 << (((8 * 4) - 8) / 4)) - 1) - 1) + 1);

    ds2 = TODO_SPEC (tmp2)((&h_i_d[INSN_UID (tmp2)])->todo_spec) & SPECULATIVE(((((ds_t) ((1 << (((8 * 4) - 8) / 4)) - 1)) << BEGIN_DATA_BITS_OFFSET
) | (((ds_t) ((1 << (((8 * 4) - 8) / 4)) - 1)) <<
 BE_IN_DATA_BITS_OFFSET)) | ((((ds_t) ((1 << (((8 * 4) -
 8) / 4)) - 1)) << BEGIN_CONTROL_BITS_OFFSET) | (((ds_t
) ((1 << (((8 * 4) - 8) / 4)) - 1)) << BE_IN_CONTROL_BITS_OFFSET
)));
    if (ds2)
dw2 = ds_weak (ds2);
    else
dw2 = NO_DEP_WEAK((((1 << (((8 * 4) - 8) / 4)) - 1) - 1) + 1);

    dw = dw2 - dw1;
    if (dw > (NO_DEP_WEAK((((1 << (((8 * 4) - 8) / 4)) - 1) - 1) + 1) / 8) || dw < -(NO_DEP_WEAK((((1 << (((8 * 4) - 8) / 4)) - 1) - 1) + 1) / 8))
return rfs_result (RFS_SPECULATION, dw, tmp, tmp2);
  }

info_val = (*current_sched_info->rank) (tmp, tmp2);
if (flag_sched_rank_heuristicglobal_options.x_flag_sched_rank_heuristic && info_val)
  return rfs_result (RFS_SCHED_RANK, info_val, tmp, tmp2);

/* Compare insns based on their relation to the last scheduled
   non-debug insn.  */
if (flag_sched_last_insn_heuristicglobal_options.x_flag_sched_last_insn_heuristic && last_nondebug_scheduled_insn)
  {
    dep_t dep1;
    dep_t dep2;
    rtx_insn *last = last_nondebug_scheduled_insn;

    /* Classify the instructions into three classes:
       1) Data dependent on last schedule insn.
       2) Anti/Output dependent on last scheduled insn.
       3) Independent of last scheduled insn, or has latency of one.
       Choose the insn from the highest numbered class if different.  */
    dep1 = sd_find_dep_between (last, tmp, true);

    if (dep1 == NULLnullptr || dep_cost (dep1) == 1)
tmp_class = 3;
    else if (/* Data dependence.  */
      DEP_TYPE (dep1)((dep1)->type) == REG_DEP_TRUE)
tmp_class = 1;
    else
tmp_class = 2;

    dep2 = sd_find_dep_between (last, tmp2, true);

    if (dep2 == NULLnullptr || dep_cost (dep2)  == 1)
tmp2_class = 3;
    else if (/* Data dependence.  */
      DEP_TYPE (dep2)((dep2)->type) == REG_DEP_TRUE)
tmp2_class = 1;
    else
tmp2_class = 2;

    if ((val = tmp2_class - tmp_class))
return rfs_result (RFS_LAST_INSN, val, tmp, tmp2);
  }

/* Prefer instructions that occur earlier in the model schedule.  */
if (sched_pressure == SCHED_PRESSURE_MODEL)
  {
    diff = model_index (tmp) - model_index (tmp2);
    if (diff != 0)
return rfs_result (RFS_PRESSURE_INDEX, diff, tmp, tmp2);
  }

/* Prefer the insn which has more later insns that depend on it.
   This gives the scheduler more freedom when scheduling later
   instructions at the expense of added register pressure.  */

val = (dep_list_size (tmp2, SD_LIST_FORW(4))
- dep_list_size (tmp, SD_LIST_FORW(4)));

if (flag_sched_dep_count_heuristicglobal_options.x_flag_sched_dep_count_heuristic && val != 0)
  return rfs_result (RFS_DEP_COUNT, val, tmp, tmp2);

/* Sort by INSN_COST rather than INSN_LUID.  This means that instructions
   which take longer to execute are prioritised and it leads to more
   dual-issue opportunities on in-order cores which have this feature.  */

if (INSN_COST (tmp)((&h_i_d[INSN_UID (tmp)])->cost) != INSN_COST (tmp2)((&h_i_d[INSN_UID (tmp2)])->cost))
  return rfs_result (RFS_COST, INSN_COST (tmp2)((&h_i_d[INSN_UID (tmp2)])->cost) - INSN_COST (tmp)((&h_i_d[INSN_UID (tmp)])->cost),
       tmp, tmp2);

/* If insns are equally good, sort by INSN_LUID (original insn order),
   so that we make the sort stable.  This minimizes instruction movement,
   thus minimizing sched's effect on debugging and cross-jumping.  */
return rfs_result (RFS_TIE, INSN_LUID (tmp)(sched_luids[INSN_UID (tmp)]) - INSN_LUID (tmp2)(sched_luids[INSN_UID (tmp2)]), tmp, tmp2);
2816}

2818/* Resort the array A in which only element at index N may be out of order.  */

2820HAIFA_INLINE__inline static void
2821swap_sort (rtx_insn **a, int n)
2822{
rtx_insn *insn = a[n - 1];
int i = n - 2;

while (i >= 0 && rank_for_schedule (a + i, &insn) >= 0)
  {
    a[i + 1] = a[i];
    i -= 1;
  }
a[i + 1] = insn;
2832}

2834/* Add INSN to the insn queue so that it can be executed at least
 N_CYCLES after the currently executing insn.  Preserve insns
 chain for debugging purposes.  REASON will be printed in debugging
 output.  */

2839HAIFA_INLINE__inline static void
2840queue_insn (rtx_insn *insn, int n_cycles, const char *reason)
2841{
int next_q = NEXT_Q_AFTER (q_ptr, n_cycles)(((q_ptr)+n_cycles) & max_insn_queue_index);
rtx_insn_list *link = alloc_INSN_LIST (insn, insn_queue[next_q]);
int new_tick;

gcc_assert (n_cycles <= max_insn_queue_index)((void)(!(n_cycles <= max_insn_queue_index) ? fancy_abort (
"/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2846, __FUNCTION__), 0 : 0));
gcc_assert (!DEBUG_INSN_P (insn))((void)(!(!(((enum rtx_code) (insn)->code) == DEBUG_INSN))
 ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2847, __FUNCTION__), 0 : 0));

insn_queue[next_q] = link;
q_size += 1;

if (sched_verbose >= 2)
  {
    fprintf (sched_dump, ";;\t\tReady-->Q: insn %s: ",
      (*current_sched_info->print_insn) (insn, 0));

    fprintf (sched_dump, "queued for %d cycles (%s).\n", n_cycles, reason);
  }

QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index) = next_q;

if (current_sched_info->flags & DO_BACKTRACKING)
  {
    new_tick = clock_var + n_cycles;
    if (INSN_TICK (insn)((&h_i_d[INSN_UID (insn)])->tick) == INVALID_TICK(-(max_insn_queue_index + 1)) || INSN_TICK (insn)((&h_i_d[INSN_UID (insn)])->tick) < new_tick)
INSN_TICK (insn)((&h_i_d[INSN_UID (insn)])->tick) = new_tick;

    if (INSN_EXACT_TICK (insn)((&h_i_d[INSN_UID (insn)])->exact_tick) != INVALID_TICK(-(max_insn_queue_index + 1))
 && INSN_EXACT_TICK (insn)((&h_i_d[INSN_UID (insn)])->exact_tick) < clock_var + n_cycles)
{
 must_backtrack = true;
 if (sched_verbose >= 2)
   fprintf (sched_dump, ";;\t\tcausing a backtrack.\n");
}
  }
2876}

2878/* Remove INSN from queue.  */
2879static void
2880queue_remove (rtx_insn *insn)
2881{
gcc_assert (QUEUE_INDEX (insn) >= 0)((void)(!(((&h_i_d[INSN_UID (insn)])->queue_index) >=
 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2882, __FUNCTION__), 0 : 0));
remove_free_INSN_LIST_elem (insn, &insn_queue[QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index)]);
q_size--;
QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index) = QUEUE_NOWHERE(-2);
2886}

2888/* Return a pointer to the bottom of the ready list, i.e. the insn
 with the lowest priority.  */

2891rtx_insn **
2892ready_lastpos (struct ready_list *ready)
2893{
gcc_assert (ready->n_ready >= 1)((void)(!(ready->n_ready >= 1) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2894, __FUNCTION__), 0 : 0));
return ready->vec + ready->first - ready->n_ready + 1;
2896}

2898/* Add an element INSN to the ready list so that it ends up with the
 lowest/highest priority depending on FIRST_P.  */

2901HAIFA_INLINE__inline static void
2902ready_add (struct ready_list *ready, rtx_insn *insn, bool first_p)
2903{
if (!first_p)
  {
    if (ready->first == ready->n_ready)
{
 memmove (ready->vec + ready->veclen - ready->n_ready,
   ready_lastpos (ready),
   ready->n_ready * sizeof (rtx));
 ready->first = ready->veclen - 1;
}
    ready->vec[ready->first - ready->n_ready] = insn;
  }
else
  {
    if (ready->first == ready->veclen - 1)
{
 if (ready->n_ready)
   /* ready_lastpos() fails when called with (ready->n_ready == 0).  */
   memmove (ready->vec + ready->veclen - ready->n_ready - 1,
     ready_lastpos (ready),
     ready->n_ready * sizeof (rtx));
 ready->first = ready->veclen - 2;
}
    ready->vec[++(ready->first)] = insn;
  }

ready->n_ready++;
if (DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN))
  ready->n_debug++;

gcc_assert (QUEUE_INDEX (insn) != QUEUE_READY)((void)(!(((&h_i_d[INSN_UID (insn)])->queue_index) != (
-1)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2933, __FUNCTION__), 0 : 0));
QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index) = QUEUE_READY(-1);

if (INSN_EXACT_TICK (insn)((&h_i_d[INSN_UID (insn)])->exact_tick) != INVALID_TICK(-(max_insn_queue_index + 1))
    && INSN_EXACT_TICK (insn)((&h_i_d[INSN_UID (insn)])->exact_tick) < clock_var)
  {
    must_backtrack = true;
  }
2941}

2943/* Remove the element with the highest priority from the ready list and
 return it.  */

2946HAIFA_INLINE__inline static rtx_insn *
2947ready_remove_first (struct ready_list *ready)
2948{
rtx_insn *t;

gcc_assert (ready->n_ready)((void)(!(ready->n_ready) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2951, __FUNCTION__), 0 : 0));
t = ready->vec[ready->first--];
ready->n_ready--;
if (DEBUG_INSN_P (t)(((enum rtx_code) (t)->code) == DEBUG_INSN))
  ready->n_debug--;
/* If the queue becomes empty, reset it.  */
if (ready->n_ready == 0)
  ready->first = ready->veclen - 1;

gcc_assert (QUEUE_INDEX (t) == QUEUE_READY)((void)(!(((&h_i_d[INSN_UID (t)])->queue_index) == (-1
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2960, __FUNCTION__), 0 : 0));
QUEUE_INDEX (t)((&h_i_d[INSN_UID (t)])->queue_index) = QUEUE_NOWHERE(-2);

return t;
2964}

2966/* The following code implements multi-pass scheduling for the first
 cycle.  In other words, we will try to choose ready insn which
 permits to start maximum number of insns on the same cycle.  */

2970/* Return a pointer to the element INDEX from the ready.  INDEX for
 insn with the highest priority is 0, and the lowest priority has
 N_READY - 1.  */

2974rtx_insn *
2975ready_element (struct ready_list *ready, int index)
2976{
gcc_assert (ready->n_ready && index < ready->n_ready)((void)(!(ready->n_ready && index < ready->n_ready
) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2977, __FUNCTION__), 0 : 0));

return ready->vec[ready->first - index];
2980}

2982/* Remove the element INDEX from the ready list and return it.  INDEX
 for insn with the highest priority is 0, and the lowest priority
 has N_READY - 1.  */

2986HAIFA_INLINE__inline static rtx_insn *
2987ready_remove (struct ready_list *ready, int index)
2988{
rtx_insn *t;
int i;

if (index == 0)
  return ready_remove_first (ready);
gcc_assert (ready->n_ready && index < ready->n_ready)((void)(!(ready->n_ready && index < ready->n_ready
) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 2994, __FUNCTION__), 0 : 0));
t = ready->vec[ready->first - index];
ready->n_ready--;
if (DEBUG_INSN_P (t)(((enum rtx_code) (t)->code) == DEBUG_INSN))
  ready->n_debug--;
for (i = index; i < ready->n_ready; i++)
  ready->vec[ready->first - i] = ready->vec[ready->first - i - 1];
QUEUE_INDEX (t)((&h_i_d[INSN_UID (t)])->queue_index) = QUEUE_NOWHERE(-2);
return t;
3003}

3005/* Remove INSN from the ready list.  */
3006static void
3007ready_remove_insn (rtx_insn *insn)
3008{
int i;

for (i = 0; i < readyp->n_ready; i++)
  if (ready_element (readyp, i) == insn)
    {
      ready_remove (readyp, i);
      return;
    }
gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 3017, __FUNCTION__));
3018}

3020/* Calculate difference of two statistics set WAS and NOW.
 Result returned in WAS.  */
3022static void
3023rank_for_schedule_stats_diff (rank_for_schedule_stats_t *was,
	      const rank_for_schedule_stats_t *now)
3025{
for (int i = 0; i < RFS_N; ++i)
  was->stats[i] = now->stats[i] - was->stats[i];
3028}

3030/* Print rank_for_schedule statistics.  */
3031static void
3032print_rank_for_schedule_stats (const char *prefix,
	       const rank_for_schedule_stats_t *stats,
	       struct ready_list *ready)
3035{
for (int i = 0; i < RFS_N; ++i)
  if (stats->stats[i])
    {
fprintf (sched_dump, "%s%20s: %u", prefix, rfs_str[i], stats->stats[i]);

if (ready != NULLnullptr)
 /* Print out insns that won due to RFS_<I>.  */
 {
   rtx_insn **p = ready_lastpos (ready);

   fprintf (sched_dump, ":");
   /* Start with 1 since least-priority insn didn't have any wins.  */
   for (int j = 1; j < ready->n_ready; ++j)
     if (INSN_LAST_RFS_WIN (p[j])((&h_i_d[INSN_UID (p[j])])->last_rfs_win) == i)
fprintf (sched_dump, " %s",
	 (*current_sched_info->print_insn) (p[j], 0));
 }
fprintf (sched_dump, "\n");
    }
3055}

3057/* Separate DEBUG_INSNS from normal insns.  DEBUG_INSNs go to the end
 of array.  */
3059static void
3060ready_sort_debug (struct ready_list *ready)
3061{
int i;
rtx_insn **first = ready_lastpos (ready);

for (i = 0; i < ready->n_ready; ++i)
  if (!DEBUG_INSN_P (first[i])(((enum rtx_code) (first[i])->code) == DEBUG_INSN))
    INSN_RFS_DEBUG_ORIG_ORDER (first[i])((&h_i_d[INSN_UID (first[i])])->rfs_debug_orig_order) = i;

qsort (first, ready->n_ready, sizeof (rtx), rank_for_schedule_debug)gcc_qsort (first, ready->n_ready, sizeof (rtx), rank_for_schedule_debug
);
3070}

3072/* Sort non-debug insns in the ready list READY by ascending priority.
 Assumes that all debug insns are separated from the real insns.  */
3074static void
3075ready_sort_real (struct ready_list *ready)
3076{
int i;
rtx_insn **first = ready_lastpos (ready);
int n_ready_real = ready->n_ready - ready->n_debug;

if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
  for (i = 0; i < n_ready_real; ++i)
    setup_insn_reg_pressure_info (first[i]);
else if (sched_pressure == SCHED_PRESSURE_MODEL
  && model_curr_point < model_num_insns)
  model_set_excess_costs (first, n_ready_real);

rank_for_schedule_stats_t stats1;
if (sched_verbose >= 4)
  stats1 = rank_for_schedule_stats;

if (n_ready_real == 2)
  swap_sort (first, n_ready_real);
else if (n_ready_real > 2)
  qsort (first, n_ready_real, sizeof (rtx), rank_for_schedule)gcc_qsort (first, n_ready_real, sizeof (rtx), rank_for_schedule
);

if (sched_verbose >= 4)
  {
    rank_for_schedule_stats_diff (&stats1, &rank_for_schedule_stats);
    print_rank_for_schedule_stats (";;\t\t", &stats1, ready);
  }
3102}

3104/* Sort the ready list READY by ascending priority.  */
3105static void
3106ready_sort (struct ready_list *ready)
3107{
if (ready->n_debug > 0)
  ready_sort_debug (ready);
else
  ready_sort_real (ready);
3112}

3114/* PREV is an insn that is ready to execute.  Adjust its priority if that
 will help shorten or lengthen register lifetimes as appropriate.  Also
 provide a hook for the target to tweak itself.  */

3118HAIFA_INLINE__inline static void
3119adjust_priority (rtx_insn *prev)
3120{
/* ??? There used to be code here to try and estimate how an insn
   affected register lifetimes, but it did it by looking at REG_DEAD
   notes, which we removed in schedule_region.  Nor did it try to
   take into account register pressure or anything useful like that.

   Revisit when we have a machine model to work with and not before.  */

if (targetm.sched.adjust_priority)
  INSN_PRIORITY (prev)((&h_i_d[INSN_UID (prev)])->priority) =
    targetm.sched.adjust_priority (prev, INSN_PRIORITY (prev)((&h_i_d[INSN_UID (prev)])->priority));
3131}

3133/* Advance DFA state STATE on one cycle.  */
3134void
3135advance_state (state_t state)
3136{
if (targetm.sched.dfa_pre_advance_cycle)
  targetm.sched.dfa_pre_advance_cycle ();

if (targetm.sched.dfa_pre_cycle_insn)
  state_transition (state,
      targetm.sched.dfa_pre_cycle_insn ());

state_transition (state, NULLnullptr);

if (targetm.sched.dfa_post_cycle_insn)
  state_transition (state,
      targetm.sched.dfa_post_cycle_insn ());

if (targetm.sched.dfa_post_advance_cycle)
  targetm.sched.dfa_post_advance_cycle ();
3152}

3154/* Advance time on one cycle.  */
3155HAIFA_INLINE__inline static void
3156advance_one_cycle (void)
3157{
int i;

advance_state (curr_state);
for (i = 4; i <= sched_verbose; ++i)
  fprintf (sched_dump, ";;\tAdvance the current state: %d.\n", clock_var);
3163}

3165/* Update register pressure after scheduling INSN.  */
3166static void
3167update_register_pressure (rtx_insn *insn)
3168{
struct reg_use_data *use;
struct reg_set_data *set;

gcc_checking_assert (!DEBUG_INSN_P (insn))((void)(!(!(((enum rtx_code) (insn)->code) == DEBUG_INSN))
 ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 3172, __FUNCTION__), 0 : 0));

for (use = INSN_REG_USE_LIST (insn)((&h_i_d[INSN_UID (insn)])->reg_use_list); use != NULLnullptr; use = use->next_insn_use)
  if (dying_use_p (use))
    mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure,
		 use->regno, false);
for (set = INSN_REG_SET_LIST (insn)((&h_i_d[INSN_UID (insn)])->reg_set_list); set != NULLnullptr; set = set->next_insn_set)
  mark_regno_birth_or_death (curr_reg_live, curr_reg_pressure,
	       set->regno, true);
3181}

3183/* Set up or update (if UPDATE_P) max register pressure (see its
 meaning in sched-int.h::_haifa_insn_data) for all current BB insns
 after insn AFTER.  */
3186static void
3187setup_insn_max_reg_pressure (rtx_insn *after, bool update_p)
3188{
int i, p;
bool eq_p;
rtx_insn *insn;
static int max_reg_pressure[N_REG_CLASSES((int) LIM_REG_CLASSES)];

save_reg_pressure ();
for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
  max_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]]
    = curr_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]];
for (insn = NEXT_INSN (after);
     insn != NULL_RTX(rtx) 0 && ! BARRIER_P (insn)(((enum rtx_code) (insn)->code) == BARRIER)
&& BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (after);
     insn = NEXT_INSN (insn))
  if (NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)))
    {
eq_p = true;
for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
 {
   p = max_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]];
   if (INSN_MAX_REG_PRESSURE (insn)((&h_i_d[INSN_UID (insn)])->max_reg_pressure)[i] != p)
     {
eq_p = false;
INSN_MAX_REG_PRESSURE (insn)((&h_i_d[INSN_UID (insn)])->max_reg_pressure)[i]
  = max_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]];
     }
 }
if (update_p && eq_p)
 break;
update_register_pressure (insn);
for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
 if (max_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]]
     < curr_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]])
   max_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]]
     = curr_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]];
    }
restore_reg_pressure ();
3225}

3227/* Update the current register pressure after scheduling INSN.  Update
 also max register pressure for unscheduled insns of the current
 BB.  */
3230static void
3231update_reg_and_insn_max_reg_pressure (rtx_insn *insn)
3232{
int i;
int before[N_REG_CLASSES((int) LIM_REG_CLASSES)];

for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
6
←
Assuming 'i' is >= field 'x_ira_pressure_classes_num'→
7
←
Loop condition is false. Execution continues on line 3238→
  before[i] = curr_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]];
update_register_pressure (insn);
for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
8
←
The value 0 is assigned to 'i'→
9
←
Assuming 'i' is < field 'x_ira_pressure_classes_num'→
10
←
Loop condition is true.  Entering loop body→
  if (curr_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]] != before[i])
11
←
The right operand of '!=' is a garbage value
    break;
if (i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num))
  setup_insn_max_reg_pressure (insn, true);
3244}

3246/* Set up register pressure at the beginning of basic block BB whose
 insns starting after insn AFTER.  Set up also max register pressure
 for all insns of the basic block.  */
3249void
3250sched_setup_bb_reg_pressure_info (basic_block bb, rtx_insn *after)
3251{
gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED)((void)(!(sched_pressure == SCHED_PRESSURE_WEIGHTED) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 3252, __FUNCTION__), 0 : 0));
initiate_bb_reg_pressure_info (bb);
setup_insn_max_reg_pressure (after, false);
3255}
3256
3257/* If doing predication while scheduling, verify whether INSN, which
 has just been scheduled, clobbers the conditions of any
 instructions that must be predicated in order to break their
 dependencies.  If so, remove them from the queues so that they will
 only be scheduled once their control dependency is resolved.  */

3263static void
3264check_clobbered_conditions (rtx_insn *insn)
3265{
HARD_REG_SET t;
int i;

if ((current_sched_info->flags & DO_PREDICATION) == 0)
  return;

find_all_hard_reg_sets (insn, &t, true);

restart:
for (i = 0; i < ready.n_ready; i++)
  {
    rtx_insn *x = ready_element (&ready, i);
    if (TODO_SPEC (x)((&h_i_d[INSN_UID (x)])->todo_spec) == DEP_CONTROL((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) && cond_clobbered_p (x, t))
{
 ready_remove_insn (x);
 goto restart;
}
  }
for (i = 0; i <= max_insn_queue_index; i++)
  {
    rtx_insn_list *link;
    int q = NEXT_Q_AFTER (q_ptr, i)(((q_ptr)+i) & max_insn_queue_index);

  restart_queue:
    for (link = insn_queue[q]; link; link = link->next ())
{
 rtx_insn *x = link->insn ();
 if (TODO_SPEC (x)((&h_i_d[INSN_UID (x)])->todo_spec) == DEP_CONTROL((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) && cond_clobbered_p (x, t))
   {
     queue_remove (x);
     goto restart_queue;
   }
}
  }
3300}
3301
3302/* Return (in order):

 - positive if INSN adversely affects the pressure on one
   register class

 - negative if INSN reduces the pressure on one register class

 - 0 if INSN doesn't affect the pressure on any register class.  */

3311static int
3312model_classify_pressure (struct model_insn_info *insn)
3313{
struct reg_pressure_data *reg_pressure;
int death[N_REG_CLASSES((int) LIM_REG_CLASSES)];
int pci, cl, sum;

calculate_reg_deaths (insn->insn, death);
reg_pressure = INSN_REG_PRESSURE (insn->insn)((&h_i_d[INSN_UID (insn->insn)])->reg_pressure);
sum = 0;
for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
  {
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
    if (death[cl] < reg_pressure[pci].set_increase)
return 1;
    sum += reg_pressure[pci].set_increase - death[cl];
  }
return sum;
3329}

3331/* Return true if INSN1 should come before INSN2 in the model schedule.  */

3333static int
3334model_order_p (struct model_insn_info *insn1, struct model_insn_info *insn2)
3335{
unsigned int height1, height2;
unsigned int priority1, priority2;

/* Prefer instructions with a higher model priority.  */
if (insn1->model_priority != insn2->model_priority)
  return insn1->model_priority > insn2->model_priority;

/* Combine the length of the longest path of satisfied true dependencies
   that leads to each instruction (depth) with the length of the longest
   path of any dependencies that leads from the instruction (alap).
   Prefer instructions with the greatest combined length.  If the combined
   lengths are equal, prefer instructions with the greatest depth.

   The idea is that, if we have a set S of "equal" instructions that each
   have ALAP value X, and we pick one such instruction I, any true-dependent
   successors of I that have ALAP value X - 1 should be preferred over S.
   This encourages the schedule to be "narrow" rather than "wide".
   However, if I is a low-priority instruction that we decided to
   schedule because of its model_classify_pressure, and if there
   is a set of higher-priority instructions T, the aforementioned
   successors of I should not have the edge over T.  */
height1 = insn1->depth + insn1->alap;
height2 = insn2->depth + insn2->alap;
if (height1 != height2)
  return height1 > height2;
if (insn1->depth != insn2->depth)
  return insn1->depth > insn2->depth;

/* We have no real preference between INSN1 an INSN2 as far as attempts
   to reduce pressure go.  Prefer instructions with higher priorities.  */
priority1 = INSN_PRIORITY (insn1->insn)((&h_i_d[INSN_UID (insn1->insn)])->priority);
priority2 = INSN_PRIORITY (insn2->insn)((&h_i_d[INSN_UID (insn2->insn)])->priority);
if (priority1 != priority2)
  return priority1 > priority2;

/* Use the original rtl sequence as a tie-breaker.  */
return insn1 < insn2;
3373}

3375/* Add INSN to the model worklist immediately after PREV.  Add it to the
 beginning of the list if PREV is null.  */

3378static void
3379model_add_to_worklist_at (struct model_insn_info *insn,
	  struct model_insn_info *prev)
3381{
gcc_assert (QUEUE_INDEX (insn->insn) == QUEUE_NOWHERE)((void)(!(((&h_i_d[INSN_UID (insn->insn)])->queue_index
) == (-2)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 3382, __FUNCTION__), 0 : 0));
QUEUE_INDEX (insn->insn)((&h_i_d[INSN_UID (insn->insn)])->queue_index) = QUEUE_READY(-1);

insn->prev = prev;
if (prev)
  {
    insn->next = prev->next;
    prev->next = insn;
  }
else
  {
    insn->next = model_worklist;
    model_worklist = insn;
  }
if (insn->next)
  insn->next->prev = insn;
3398}

3400/* Remove INSN from the model worklist.  */

3402static void
3403model_remove_from_worklist (struct model_insn_info *insn)
3404{
gcc_assert (QUEUE_INDEX (insn->insn) == QUEUE_READY)((void)(!(((&h_i_d[INSN_UID (insn->insn)])->queue_index
) == (-1)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 3405, __FUNCTION__), 0 : 0));
QUEUE_INDEX (insn->insn)((&h_i_d[INSN_UID (insn->insn)])->queue_index) = QUEUE_NOWHERE(-2);

if (insn->prev)
  insn->prev->next = insn->next;
else
  model_worklist = insn->next;
if (insn->next)
  insn->next->prev = insn->prev;
3414}

3416/* Add INSN to the model worklist.  Start looking for a suitable position
 between neighbors PREV and NEXT, testing at most param_max_sched_ready_insns
 insns either side.  A null PREV indicates the beginning of the list and
 a null NEXT indicates the end.  */

3421static void
3422model_add_to_worklist (struct model_insn_info *insn,
       struct model_insn_info *prev,
       struct model_insn_info *next)
3425{
int count;

count = param_max_sched_ready_insnsglobal_options.x_param_max_sched_ready_insns;
if (count > 0 && prev && model_order_p (insn, prev))
  do
    {
count--;
prev = prev->prev;
    }
  while (count > 0 && prev && model_order_p (insn, prev));
else
  while (count > 0 && next && model_order_p (next, insn))
    {
count--;
prev = next;
next = next->next;
    }
model_add_to_worklist_at (insn, prev);
3444}

3446/* INSN may now have a higher priority (in the model_order_p sense)
 than before.  Move it up the worklist if necessary.  */

3449static void
3450model_promote_insn (struct model_insn_info *insn)
3451{
struct model_insn_info *prev;
int count;

prev = insn->prev;
count = param_max_sched_ready_insnsglobal_options.x_param_max_sched_ready_insns;
while (count > 0 && prev && model_order_p (insn, prev))
  {
    count--;
    prev = prev->prev;
  }
if (prev != insn->prev)
  {
    model_remove_from_worklist (insn);
    model_add_to_worklist_at (insn, prev);
  }
3467}

3469/* Add INSN to the end of the model schedule.  */

3471static void
3472model_add_to_schedule (rtx_insn *insn)
3473{
unsigned int point;

gcc_assert (QUEUE_INDEX (insn) == QUEUE_NOWHERE)((void)(!(((&h_i_d[INSN_UID (insn)])->queue_index) == (
-2)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 3476, __FUNCTION__), 0 : 0));
QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index) = QUEUE_SCHEDULED(-3);

point = model_schedule.length ();
model_schedule.quick_push (insn);
INSN_MODEL_INDEX (insn)((&h_i_d[INSN_UID (insn)])->model_index) = point + 1;
3482}

3484/* Analyze the instructions that are to be scheduled, setting up
 MODEL_INSN_INFO (...) and model_num_insns accordingly.  Add ready
 instructions to model_worklist.  */

3488static void
3489model_analyze_insns (void)
3490{
rtx_insn *start, *end, *iter;
sd_iterator_def sd_it;
dep_t dep;
struct model_insn_info *insn, *con;

model_num_insns = 0;
start = PREV_INSN (current_sched_info->next_tail);
end = current_sched_info->prev_head;
for (iter = start; iter != end; iter = PREV_INSN (iter))
  if (NONDEBUG_INSN_P (iter)((((enum rtx_code) (iter)->code) == INSN) || (((enum rtx_code
) (iter)->code) == JUMP_INSN) || (((enum rtx_code) (iter)->
code) == CALL_INSN)))
    {
insn = MODEL_INSN_INFO (iter)(&model_insns[(sched_luids[INSN_UID (iter)])]);
insn->insn = iter;
FOR_EACH_DEP (iter, SD_LIST_FORW, sd_it, dep)for ((sd_it) = sd_iterator_start ((iter), ((4))); sd_iterator_cond
 (&(sd_it), &(dep)); sd_iterator_next (&(sd_it)))
 {
   con = MODEL_INSN_INFO (DEP_CON (dep))(&model_insns[(sched_luids[INSN_UID (((dep)->con))])]);
   if (con->insn && insn->alap < con->alap + 1)
     insn->alap = con->alap + 1;
 }

insn->old_queue = QUEUE_INDEX (iter)((&h_i_d[INSN_UID (iter)])->queue_index);
QUEUE_INDEX (iter)((&h_i_d[INSN_UID (iter)])->queue_index) = QUEUE_NOWHERE(-2);

insn->unscheduled_preds = dep_list_size (iter, SD_LIST_HARD_BACK(1));
if (insn->unscheduled_preds == 0)
 model_add_to_worklist (insn, NULLnullptr, model_worklist);

model_num_insns++;
    }
3520}

3522/* The global state describes the register pressure at the start of the
 model schedule.  Initialize GROUP accordingly.  */

3525static void
3526model_init_pressure_group (struct model_pressure_group *group)
3527{
int pci, cl;

for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
  {
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
    group->limits[pci].pressure = curr_reg_pressure[cl];
    group->limits[pci].point = 0;
  }
/* Use index model_num_insns to record the state after the last
   instruction in the model schedule.  */
group->model = XNEWVEC (struct model_pressure_data,((struct model_pressure_data *) xmalloc (sizeof (struct model_pressure_data
) * ((model_num_insns + 1) * (this_target_ira->x_ira_pressure_classes_num
))))
	  (model_num_insns + 1) * ira_pressure_classes_num)((struct model_pressure_data *) xmalloc (sizeof (struct model_pressure_data
) * ((model_num_insns + 1) * (this_target_ira->x_ira_pressure_classes_num
))));
3540}

3542/* Record that MODEL_REF_PRESSURE (GROUP, POINT, PCI) is PRESSURE.
 Update the maximum pressure for the whole schedule.  */

3545static void
3546model_record_pressure (struct model_pressure_group *group,
       int point, int pci, int pressure)
3548{
MODEL_REF_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->ref_pressure) = pressure;
if (group->limits[pci].pressure < pressure)
  {
    group->limits[pci].pressure = pressure;
    group->limits[pci].point = point;
  }
3555}

3557/* INSN has just been added to the end of the model schedule.  Record its
 register-pressure information.  */

3560static void
3561model_record_pressures (struct model_insn_info *insn)
3562{
struct reg_pressure_data *reg_pressure;
int point, pci, cl, delta;
int death[N_REG_CLASSES((int) LIM_REG_CLASSES)];

point = model_index (insn->insn);
if (sched_verbose >= 2)
  {
    if (point == 0)
{
 fprintf (sched_dump, "\n;;\tModel schedule:\n;;\n");
 fprintf (sched_dump, ";;\t| idx insn | mpri hght dpth prio |\n");
}
    fprintf (sched_dump, ";;\t| %3d %4d | %4d %4d %4d %4d | %-30s ",
      point, INSN_UID (insn->insn), insn->model_priority,
      insn->depth + insn->alap, insn->depth,
      INSN_PRIORITY (insn->insn)((&h_i_d[INSN_UID (insn->insn)])->priority),
      str_pattern_slim (PATTERN (insn->insn)));
  }
calculate_reg_deaths (insn->insn, death);
reg_pressure = INSN_REG_PRESSURE (insn->insn)((&h_i_d[INSN_UID (insn->insn)])->reg_pressure);
for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
  {
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
    delta = reg_pressure[pci].set_increase - death[cl];
    if (sched_verbose >= 2)
fprintf (sched_dump, " %s:[%d,%+d]", reg_class_names[cl],
 curr_reg_pressure[cl], delta);
    model_record_pressure (&model_before_pressure, point, pci,
	     curr_reg_pressure[cl]);
  }
if (sched_verbose >= 2)
  fprintf (sched_dump, "\n");
3595}

3597/* All instructions have been added to the model schedule.  Record the
 final register pressure in GROUP and set up all MODEL_MAX_PRESSUREs.  */

3600static void
3601model_record_final_pressures (struct model_pressure_group *group)
3602{
int point, pci, max_pressure, ref_pressure, cl;

for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
  {
    /* Record the final pressure for this class.  */
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
    point = model_num_insns;
    ref_pressure = curr_reg_pressure[cl];
    model_record_pressure (group, point, pci, ref_pressure);

    /* Record the original maximum pressure.  */
    group->limits[pci].orig_pressure = group->limits[pci].pressure;

    /* Update the MODEL_MAX_PRESSURE for every point of the schedule.  */
    max_pressure = ref_pressure;
    MODEL_MAX_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->max_pressure) = max_pressure;
    while (point > 0)
{
 point--;
 ref_pressure = MODEL_REF_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->ref_pressure);
 max_pressure = MAX (max_pressure, ref_pressure)((max_pressure) > (ref_pressure) ? (max_pressure) : (ref_pressure
));
 MODEL_MAX_PRESSURE (group, point, pci)((&(group)->model[(point) * (this_target_ira->x_ira_pressure_classes_num
) + (pci)])->max_pressure) = max_pressure;
}
  }
3627}

3629/* Update all successors of INSN, given that INSN has just been scheduled.  */

3631static void
3632model_add_successors_to_worklist (struct model_insn_info *insn)
3633{
sd_iterator_def sd_it;
struct model_insn_info *con;
dep_t dep;

FOR_EACH_DEP (insn->insn, SD_LIST_FORW, sd_it, dep)for ((sd_it) = sd_iterator_start ((insn->insn), ((4))); sd_iterator_cond
 (&(sd_it), &(dep)); sd_iterator_next (&(sd_it)))
  {
    con = MODEL_INSN_INFO (DEP_CON (dep))(&model_insns[(sched_luids[INSN_UID (((dep)->con))])]);
    /* Ignore debug instructions, and instructions from other blocks.  */
    if (con->insn)
{
 con->unscheduled_preds--;

 /* Update the depth field of each true-dependent successor.
    Increasing the depth gives them a higher priority than
    before.  */
 if (DEP_TYPE (dep)((dep)->type) == REG_DEP_TRUE && con->depth < insn->depth + 1)
   {
     con->depth = insn->depth + 1;
     if (QUEUE_INDEX (con->insn)((&h_i_d[INSN_UID (con->insn)])->queue_index) == QUEUE_READY(-1))
model_promote_insn (con);
   }

 /* If this is a true dependency, or if there are no remaining
    dependencies for CON (meaning that CON only had non-true
    dependencies), make sure that CON is on the worklist.
    We don't bother otherwise because it would tend to fill the
    worklist with a lot of low-priority instructions that are not
    yet ready to issue.  */
 if ((con->depth > 0 || con->unscheduled_preds == 0)
     && QUEUE_INDEX (con->insn)((&h_i_d[INSN_UID (con->insn)])->queue_index) == QUEUE_NOWHERE(-2))
   model_add_to_worklist (con, insn, insn->next);
}
  }
3667}

3669/* Give INSN a higher priority than any current instruction, then give
 unscheduled predecessors of INSN a higher priority still.  If any of
 those predecessors are not on the model worklist, do the same for its
 predecessors, and so on.  */

3674static void
3675model_promote_predecessors (struct model_insn_info *insn)
3676{
struct model_insn_info *pro, *first;
sd_iterator_def sd_it;
dep_t dep;

if (sched_verbose >= 7)
  fprintf (sched_dump, ";;\t+--- priority of %d = %d, priority of",
    INSN_UID (insn->insn), model_next_priority);
insn->model_priority = model_next_priority++;
model_remove_from_worklist (insn);
model_add_to_worklist_at (insn, NULLnullptr);

first = NULLnullptr;
for (;;)
  {
    FOR_EACH_DEP (insn->insn, SD_LIST_HARD_BACK, sd_it, dep)for ((sd_it) = sd_iterator_start ((insn->insn), ((1))); sd_iterator_cond
 (&(sd_it), &(dep)); sd_iterator_next (&(sd_it)))
{
 pro = MODEL_INSN_INFO (DEP_PRO (dep))(&model_insns[(sched_luids[INSN_UID (((dep)->pro))])]);
 /* The first test is to ignore debug instructions, and instructions
    from other blocks.  */
 if (pro->insn
     && pro->model_priority != model_next_priority
     && QUEUE_INDEX (pro->insn)((&h_i_d[INSN_UID (pro->insn)])->queue_index) != QUEUE_SCHEDULED(-3))
   {
     pro->model_priority = model_next_priority;
     if (sched_verbose >= 7)
fprintf (sched_dump, " %d", INSN_UID (pro->insn));
     if (QUEUE_INDEX (pro->insn)((&h_i_d[INSN_UID (pro->insn)])->queue_index) == QUEUE_READY(-1))
{
  /* PRO is already in the worklist, but it now has
     a higher priority than before.  Move it at the
     appropriate place.  */
  model_remove_from_worklist (pro);
  model_add_to_worklist (pro, NULLnullptr, model_worklist);
}
     else
{
  /* PRO isn't in the worklist.  Recursively process
     its predecessors until we find one that is.  */
  pro->next = first;
  first = pro;
}
   }
}
    if (!first)
break;
    insn = first;
    first = insn->next;
  }
if (sched_verbose >= 7)
  fprintf (sched_dump, " = %d\n", model_next_priority);
model_next_priority++;
3728}

3730/* Pick one instruction from model_worklist and process it.  */

3732static void
3733model_choose_insn (void)
3734{
struct model_insn_info *insn, *fallback;
int count;

if (sched_verbose >= 7)
  {
    fprintf (sched_dump, ";;\t+--- worklist:\n");
    insn = model_worklist;
    count = param_max_sched_ready_insnsglobal_options.x_param_max_sched_ready_insns;
    while (count > 0 && insn)
{
 fprintf (sched_dump, ";;\t+---   %d [%d, %d, %d, %d]\n",
   INSN_UID (insn->insn), insn->model_priority,
   insn->depth + insn->alap, insn->depth,
   INSN_PRIORITY (insn->insn)((&h_i_d[INSN_UID (insn->insn)])->priority));
 count--;
 insn = insn->next;
}
  }

/* Look for a ready instruction whose model_classify_priority is zero
   or negative, picking the highest-priority one.  Adding such an
   instruction to the schedule now should do no harm, and may actually
   do some good.

   Failing that, see whether there is an instruction with the highest
   extant model_priority that is not yet ready, but which would reduce
   pressure if it became ready.  This is designed to catch cases like:

     (set (mem (reg R1)) (reg R2))

   where the instruction is the last remaining use of R1 and where the
   value of R2 is not yet available (or vice versa).  The death of R1
   means that this instruction already reduces pressure.  It is of
   course possible that the computation of R2 involves other registers
   that are hard to kill, but such cases are rare enough for this
   heuristic to be a win in general.

   Failing that, just pick the highest-priority instruction in the
   worklist.  */
count = param_max_sched_ready_insnsglobal_options.x_param_max_sched_ready_insns;
insn = model_worklist;
fallback = 0;
for (;;)
  {
    if (count == 0 || !insn)
{
 insn = fallback ? fallback : model_worklist;
 break;
}
    if (insn->unscheduled_preds)
{
 if (model_worklist->model_priority == insn->model_priority
     && !fallback
     && model_classify_pressure (insn) < 0)
   fallback = insn;
}
    else
{
 if (model_classify_pressure (insn) <= 0)
   break;
}
    count--;
    insn = insn->next;
  }

if (sched_verbose >= 7 && insn != model_worklist)
  {
    if (insn->unscheduled_preds)
fprintf (sched_dump, ";;\t+--- promoting insn %d, with dependencies\n",
 INSN_UID (insn->insn));
    else
fprintf (sched_dump, ";;\t+--- promoting insn %d, which is ready\n",
 INSN_UID (insn->insn));
  }
if (insn->unscheduled_preds)
  /* INSN isn't yet ready to issue.  Give all its predecessors the
     highest priority.  */
  model_promote_predecessors (insn);
else
  {
    /* INSN is ready.  Add it to the end of model_schedule and
process its successors.  */
    model_add_successors_to_worklist (insn);
    model_remove_from_worklist (insn);
    model_add_to_schedule (insn->insn);
    model_record_pressures (insn);
    update_register_pressure (insn->insn);
  }
3823}

3825/* Restore all QUEUE_INDEXs to the values that they had before
 model_start_schedule was called.  */

3828static void
3829model_reset_queue_indices (void)
3830{
unsigned int i;
rtx_insn *insn;

FOR_EACH_VEC_ELT (model_schedule, i, insn)for (i = 0; (model_schedule).iterate ((i), &(insn)); ++(i
))
  QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index) = MODEL_INSN_INFO (insn)(&model_insns[(sched_luids[INSN_UID (insn)])])->old_queue;
3836}

3838/* We have calculated the model schedule and spill costs.  Print a summary
 to sched_dump.  */

3841static void
3842model_dump_pressure_summary (void)
3843{
int pci, cl;

fprintf (sched_dump, ";; Pressure summary:");
for (pci = 0; pci < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); pci++)
  {
    cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[pci];
    fprintf (sched_dump, " %s:%d", reg_class_names[cl],
      model_before_pressure.limits[pci].pressure);
  }
fprintf (sched_dump, "\n\n");
3854}

3856/* Initialize the SCHED_PRESSURE_MODEL information for the current
 scheduling region.  */

3859static void
3860model_start_schedule (basic_block bb)
3861{
model_next_priority = 1;
model_schedule.create (sched_max_luid);
model_insns = XCNEWVEC (struct model_insn_info, sched_max_luid)((struct model_insn_info *) xcalloc ((sched_max_luid), sizeof
 (struct model_insn_info)));

gcc_assert (bb == BLOCK_FOR_INSN (NEXT_INSN (current_sched_info->prev_head)))((void)(!(bb == BLOCK_FOR_INSN (NEXT_INSN (current_sched_info
->prev_head))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 3866, __FUNCTION__), 0 : 0));
initiate_reg_pressure_info (df_get_live_in (bb));

model_analyze_insns ();
model_init_pressure_group (&model_before_pressure);
while (model_worklist)
  model_choose_insn ();
gcc_assert (model_num_insns == (int) model_schedule.length ())((void)(!(model_num_insns == (int) model_schedule.length ()) ?
 fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 3873, __FUNCTION__), 0 : 0));
if (sched_verbose >= 2)
  fprintf (sched_dump, "\n");

model_record_final_pressures (&model_before_pressure);
model_reset_queue_indices ();

XDELETEVEC (model_insns)free ((void*) (model_insns));

model_curr_point = 0;
initiate_reg_pressure_info (df_get_live_in (bb));
if (sched_verbose >= 1)
  model_dump_pressure_summary ();
3886}

3888/* Free the information associated with GROUP.  */

3890static void
3891model_finalize_pressure_group (struct model_pressure_group *group)
3892{
XDELETEVEC (group->model)free ((void*) (group->model));
3894}

3896/* Free the information created by model_start_schedule.  */

3898static void
3899model_end_schedule (void)
3900{
model_finalize_pressure_group (&model_before_pressure);
model_schedule.release ();
3903}

3905/* Prepare reg pressure scheduling for basic block BB.  */
3906static void
3907sched_pressure_start_bb (basic_block bb)
3908{
/* Set the number of available registers for each class taking into account
   relative probability of current basic block versus function prologue and
   epilogue.
   * If the basic block executes much more often than the prologue/epilogue
   (e.g., inside a hot loop), then cost of spill in the prologue is close to
   nil, so the effective number of available registers is
   (ira_class_hard_regs_num[cl] - fixed_regs_num[cl] - 0).
   * If the basic block executes as often as the prologue/epilogue,
   then spill in the block is as costly as in the prologue, so the effective
   number of available registers is
   (ira_class_hard_regs_num[cl] - fixed_regs_num[cl]
    - call_saved_regs_num[cl]).
   Note that all-else-equal, we prefer to spill in the prologue, since that
   allows "extra" registers for other basic blocks of the function.
   * If the basic block is on the cold path of the function and executes
   rarely, then we should always prefer to spill in the block, rather than
   in the prologue/epilogue.  The effective number of available register is
   (ira_class_hard_regs_num[cl] - fixed_regs_num[cl]
    - call_saved_regs_num[cl]).  */
{
  int i;
  int entry_freq = ENTRY_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_entry_block_ptr)->count.to_frequency (cfun(cfun + 0));
  int bb_freq = bb->count.to_frequency (cfun(cfun + 0));

  if (bb_freq == 0)
    {
if (entry_freq == 0)
 entry_freq = bb_freq = 1;
    }
  if (bb_freq < entry_freq)
    bb_freq = entry_freq;

  for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); ++i)
    {
enum reg_class cl = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i];
sched_class_regs_num[cl] = ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[cl]
		   - fixed_regs_num[cl];
sched_class_regs_num[cl]
 -= (call_saved_regs_num[cl] * entry_freq) / bb_freq;
    }
}

if (sched_pressure == SCHED_PRESSURE_MODEL)
  model_start_schedule (bb);
3953}
3954
3955/* A structure that holds local state for the loop in schedule_block.  */
3956struct sched_block_state
3957{
/* True if no real insns have been scheduled in the current cycle.  */
bool first_cycle_insn_p;
/* True if a shadow insn has been scheduled in the current cycle, which
   means that no more normal insns can be issued.  */
bool shadows_only_p;
/* True if we're winding down a modulo schedule, which means that we only
   issue insns with INSN_EXACT_TICK set.  */
bool modulo_epilogue;
/* Initialized with the machine's issue rate every cycle, and updated
   by calls to the variable_issue hook.  */
int can_issue_more;
3969};

3971/* INSN is the "currently executing insn".  Launch each insn which was
 waiting on INSN.  READY is the ready list which contains the insns
 that are ready to fire.  CLOCK is the current cycle.  The function
 returns necessary cycle advance after issuing the insn (it is not
 zero for insns in a schedule group).  */

3977static int
3978schedule_insn (rtx_insn *insn)
3979{
sd_iterator_def sd_it;
dep_t dep;
int i;
int advance = 0;

if (sched_verbose >= 1)
1
Assuming 'sched_verbose' is < 1→
  {
    struct reg_pressure_data *pressure_info;
    fprintf (sched_dump, ";;\t%3i--> %s %-40s:",
      clock_var, (*current_sched_info->print_insn) (insn, 1),
      str_pattern_slim (PATTERN (insn)));

    if (recog_memoized (insn) < 0)
fprintf (sched_dump, "nothing");
    else
print_reservation (sched_dump, insn);
    pressure_info = INSN_REG_PRESSURE (insn)((&h_i_d[INSN_UID (insn)])->reg_pressure);
    if (pressure_info != NULLnullptr)
{
 fputc (':', sched_dump);
 for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
   fprintf (sched_dump, "%s%s%+d(%d)",
     scheduled_insns.length () > 1
     && INSN_LUID (insn)(sched_luids[INSN_UID (insn)])
     < INSN_LUID (scheduled_insns[scheduled_insns.length () - 2])(sched_luids[INSN_UID (scheduled_insns[scheduled_insns.length
 () - 2])]) ? "@" : "",
     reg_class_names[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]],
     pressure_info[i].set_increase, pressure_info[i].change);
}
    if (sched_pressure == SCHED_PRESSURE_MODEL
 && model_curr_point < model_num_insns
 && model_index (insn) == model_curr_point)
fprintf (sched_dump, ":model %d", model_curr_point);
    fputc ('\n', sched_dump);
  }

if (sched_pressure == SCHED_PRESSURE_WEIGHTED && !DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN))
2
←
Assuming 'sched_pressure' is equal to SCHED_PRESSURE_WEIGHTED→
3
←
Assuming field 'code' is not equal to DEBUG_INSN→
4
←
Taking true branch→
  update_reg_and_insn_max_reg_pressure (insn);
5
←
Calling 'update_reg_and_insn_max_reg_pressure'→

/* Scheduling instruction should have all its dependencies resolved and
   should have been removed from the ready list.  */
gcc_assert (sd_lists_empty_p (insn, SD_LIST_HARD_BACK))((void)(!(sd_lists_empty_p (insn, (1))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4020, __FUNCTION__), 0 : 0));

/* Reset debug insns invalidated by moving this insn.  */
if (MAY_HAVE_DEBUG_BIND_INSNSglobal_options.x_flag_var_tracking_assignments && !DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN))
  for (sd_it = sd_iterator_start (insn, SD_LIST_BACK((1) | (2)));
sd_iterator_cond (&sd_it, &dep);)
    {
rtx_insn *dbg = DEP_PRO (dep)((dep)->pro);
struct reg_use_data *use, *next;

if (DEP_STATUS (dep)((dep)->status) & DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1))
 {
   sd_iterator_next (&sd_it);
   continue;
 }

gcc_assert (DEBUG_BIND_INSN_P (dbg))((void)(!(((((enum rtx_code) (dbg)->code) == DEBUG_INSN) &&
 (((enum rtx_code) (PATTERN (dbg))->code) == VAR_LOCATION)
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4036, __FUNCTION__), 0 : 0));

if (sched_verbose >= 6)
 fprintf (sched_dump, ";;\t\tresetting: debug insn %d\n",
   INSN_UID (dbg));

/* ??? Rather than resetting the debug insn, we might be able
  to emit a debug temp before the just-scheduled insn, but
  this would involve checking that the expression at the
  point of the debug insn is equivalent to the expression
  before the just-scheduled insn.  They might not be: the
  expression in the debug insn may depend on other insns not
  yet scheduled that set MEMs, REGs or even other debug
  insns.  It's not clear that attempting to preserve debug
  information in these cases is worth the effort, given how
  uncommon these resets are and the likelihood that the debug
  temps introduced won't survive the schedule change.  */
INSN_VAR_LOCATION_LOC (dbg)((((((__extension__ ({ __typeof (PATTERN (dbg)) const _rtx = (
PATTERN (dbg)); if (((enum rtx_code) (_rtx)->code) != VAR_LOCATION
) rtl_check_failed_flag ("INSN_VAR_LOCATION", _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4053, __FUNCTION__); _rtx; }))))->u.fld[1]).rt_rtx)) = gen_rtx_UNKNOWN_VAR_LOC ()(gen_rtx_fmt_e_stat ((CLOBBER), ((((void) 0, E_VOIDmode))), (
((const_int_rtx[64]))) ));
df_insn_rescan (dbg);

/* Unknown location doesn't use any registers.  */
for (use = INSN_REG_USE_LIST (dbg)((&h_i_d[INSN_UID (dbg)])->reg_use_list); use != NULLnullptr; use = next)
 {
   struct reg_use_data *prev = use;

   /* Remove use from the cyclic next_regno_use chain first.  */
   while (prev->next_regno_use != use)
     prev = prev->next_regno_use;
   prev->next_regno_use = use->next_regno_use;
   next = use->next_insn_use;
   free (use);
 }
INSN_REG_USE_LIST (dbg)((&h_i_d[INSN_UID (dbg)])->reg_use_list) = NULLnullptr;

/* We delete rather than resolve these deps, otherwise we
  crash in sched_free_deps(), because forward deps are
  expected to be released before backward deps.  */
sd_delete_dep (sd_it);
    }

gcc_assert (QUEUE_INDEX (insn) == QUEUE_NOWHERE)((void)(!(((&h_i_d[INSN_UID (insn)])->queue_index) == (
-2)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4076, __FUNCTION__), 0 : 0));
QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index) = QUEUE_SCHEDULED(-3);

if (sched_pressure == SCHED_PRESSURE_MODEL
    && model_curr_point < model_num_insns
    && NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)))
  {
    if (model_index (insn) == model_curr_point)
do
 model_curr_point++;
while (model_curr_point < model_num_insns
      && (QUEUE_INDEX (MODEL_INSN (model_curr_point))((&h_i_d[INSN_UID ((model_schedule[model_curr_point]))])->
queue_index)
   == QUEUE_SCHEDULED(-3)));
    else
model_recompute (insn);
    model_update_limit_points ();
    update_register_pressure (insn);
    if (sched_verbose >= 2)
print_curr_reg_pressure ();
  }

gcc_assert (INSN_TICK (insn) >= MIN_TICK)((void)(!(((&h_i_d[INSN_UID (insn)])->tick) >= (-max_insn_queue_index
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4097, __FUNCTION__), 0 : 0));
if (INSN_TICK (insn)((&h_i_d[INSN_UID (insn)])->tick) > clock_var)
  /* INSN has been prematurely moved from the queue to the ready list.
     This is possible only if following flags are set.  */
  gcc_assert (flag_sched_stalled_insns || sched_fusion)((void)(!(global_options.x_flag_sched_stalled_insns || sched_fusion
) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4101, __FUNCTION__), 0 : 0));

/* ??? Probably, if INSN is scheduled prematurely, we should leave
   INSN_TICK untouched.  This is a machine-dependent issue, actually.  */
INSN_TICK (insn)((&h_i_d[INSN_UID (insn)])->tick) = clock_var;

check_clobbered_conditions (insn);

/* Update dependent instructions.  First, see if by scheduling this insn
   now we broke a dependence in a way that requires us to change another
   insn.  */
for (sd_it = sd_iterator_start (insn, SD_LIST_SPEC_BACK(2));
     sd_iterator_cond (&sd_it, &dep); sd_iterator_next (&sd_it))
  {
    struct dep_replacement *desc = DEP_REPLACE (dep)((dep)->replace);
    rtx_insn *pro = DEP_PRO (dep)((dep)->pro);
    if (QUEUE_INDEX (pro)((&h_i_d[INSN_UID (pro)])->queue_index) != QUEUE_SCHEDULED(-3)
 && desc != NULLnullptr && desc->insn == pro)
apply_replacement (dep, false);
  }

/* Go through and resolve forward dependencies.  */
for (sd_it = sd_iterator_start (insn, SD_LIST_FORW(4));
     sd_iterator_cond (&sd_it, &dep);)
  {
    rtx_insn *next = DEP_CON (dep)((dep)->con);
    bool cancelled = (DEP_STATUS (dep)((dep)->status) & DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1)) != 0;

    /* Resolve the dependence between INSN and NEXT.
sd_resolve_dep () moves current dep to another list thus
advancing the iterator.  */
    sd_resolve_dep (sd_it);

    if (cancelled)
{
 if (must_restore_pattern_p (next, dep))
   restore_pattern (dep, false);
 continue;
}

    /* Don't bother trying to mark next as ready if insn is a debug
insn.  If insn is the last hard dependency, it will have
already been discounted.  */
    if (DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN) && !DEBUG_INSN_P (next)(((enum rtx_code) (next)->code) == DEBUG_INSN))
continue;

    if (!IS_SPECULATION_BRANCHY_CHECK_P (insn)(((&h_i_d[INSN_UID (insn)])->recovery_block) != nullptr
 && ((&h_i_d[INSN_UID (insn)])->recovery_block
) != (((cfun + 0))->cfg->x_exit_block_ptr)))
{
 int effective_cost;

 effective_cost = try_ready (next);

 if (effective_cost >= 0
     && SCHED_GROUP_P (next)(__extension__ ({ __typeof ((next)) const _rtx = ((next)); if
 (((enum rtx_code) (_rtx)->code) != DEBUG_INSN && (
(enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != JUMP_INSN && ((enum rtx_code) (
_rtx)->code) != CALL_INSN) rtl_check_failed_flag ("SCHED_GROUP_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4154, __FUNCTION__); _rtx; })->in_struct)
     && advance < effective_cost)
   advance = effective_cost;
}
    else
/* Check always has only one forward dependence (to the first insn in
  the recovery block), therefore, this will be executed only once.  */
{
 gcc_assert (sd_lists_empty_p (insn, SD_LIST_FORW))((void)(!(sd_lists_empty_p (insn, (4))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4162, __FUNCTION__), 0 : 0));
 fix_recovery_deps (RECOVERY_BLOCK (insn)((&h_i_d[INSN_UID (insn)])->recovery_block));
}
  }

/* Annotate the instruction with issue information -- TImode
   indicates that the instruction is expected not to be able
   to issue on the same cycle as the previous insn.  A machine
   may use this information to decide how the instruction should
   be aligned.  */
if (issue_rate > 1
    && GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) != USE
    && GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) != CLOBBER
    && !DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN))
  {
    if (reload_completed)
PUT_MODE (insn, clock_var > last_clock_var ? TImode(scalar_int_mode ((scalar_int_mode::from_int) E_TImode)) : VOIDmode((void) 0, E_VOIDmode));
    last_clock_var = clock_var;
  }

if (nonscheduled_insns_begin != NULL_RTX(rtx) 0)
  /* Indicate to debug counters that INSN is scheduled.  */
  nonscheduled_insns_begin = insn;

return advance;
4187}

4189/* Functions for handling of notes.  */

4191/* Add note list that ends on FROM_END to the end of TO_ENDP.  */
4192void
4193concat_note_lists (rtx_insn *from_end, rtx_insn **to_endp)
4194{
rtx_insn *from_start;

/* It's easy when have nothing to concat.  */
if (from_end == NULLnullptr)
  return;

/* It's also easy when destination is empty.  */
if (*to_endp == NULLnullptr)
  {
    *to_endp = from_end;
    return;
  }

from_start = from_end;
while (PREV_INSN (from_start) != NULLnullptr)
  from_start = PREV_INSN (from_start);

SET_PREV_INSN (from_start) = *to_endp;
SET_NEXT_INSN (*to_endp) = from_start;
*to_endp = from_end;
4215}

4217/* Delete notes between HEAD and TAIL and put them in the chain
 of notes ended by NOTE_LIST.  */
4219void
4220remove_notes (rtx_insn *head, rtx_insn *tail)
4221{
rtx_insn *next_tail, *insn, *next;

note_list = 0;
if (head == tail && !INSN_P (head)(((((enum rtx_code) (head)->code) == INSN) || (((enum rtx_code
) (head)->code) == JUMP_INSN) || (((enum rtx_code) (head)->
code) == CALL_INSN)) || (((enum rtx_code) (head)->code) ==
 DEBUG_INSN)))
  return;

next_tail = NEXT_INSN (tail);
for (insn = head; insn != next_tail; insn = next)
  {
    next = NEXT_INSN (insn);
    if (!NOTE_P (insn)(((enum rtx_code) (insn)->code) == NOTE))
continue;

    switch (NOTE_KIND (insn)(((insn)->u.fld[4]).rt_int))
{
case NOTE_INSN_BASIC_BLOCK:
 continue;

case NOTE_INSN_EPILOGUE_BEG:
 if (insn != tail)
   {
     remove_insn (insn);
     /* If an insn was split just before the EPILOGUE_BEG note and
 that split created new basic blocks, we could have a
 BASIC_BLOCK note here.  Safely advance over it in that case
 and assert that we land on a real insn.  */
     if (NOTE_P (next)(((enum rtx_code) (next)->code) == NOTE)
  && NOTE_KIND (next)(((next)->u.fld[4]).rt_int) == NOTE_INSN_BASIC_BLOCK
  && next != next_tail)
next = NEXT_INSN (next);
     gcc_assert (INSN_P (next))((void)(!((((((enum rtx_code) (next)->code) == INSN) || ((
(enum rtx_code) (next)->code) == JUMP_INSN) || (((enum rtx_code
) (next)->code) == CALL_INSN)) || (((enum rtx_code) (next)
->code) == DEBUG_INSN))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4252, __FUNCTION__), 0 : 0));
     add_reg_note (next, REG_SAVE_NOTE,
	    GEN_INT (NOTE_INSN_EPILOGUE_BEG)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (NOTE_INSN_EPILOGUE_BEG
)));
     break;
   }
 /* FALLTHRU */

default:
 remove_insn (insn);

 /* Add the note to list that ends at NOTE_LIST.  */
 SET_PREV_INSN (insn) = note_list;
 SET_NEXT_INSN (insn) = NULL_RTX(rtx) 0;
 if (note_list)
   SET_NEXT_INSN (note_list) = insn;
 note_list = insn;
 break;
}

    gcc_assert ((sel_sched_p () || insn != tail) && insn != head)((void)(!((sel_sched_p () || insn != tail) && insn !=
 head) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4271, __FUNCTION__), 0 : 0));
  }
4273}

4275/* A structure to record enough data to allow us to backtrack the scheduler to
 a previous state.  */
4277struct haifa_saved_data
4278{
/* Next entry on the list.  */
struct haifa_saved_data *next;

/* Backtracking is associated with scheduling insns that have delay slots.
   DELAY_PAIR points to the structure that contains the insns involved, and
   the number of cycles between them.  */
struct delay_pair *delay_pair;

/* Data used by the frontend (e.g. sched-ebb or sched-rgn).  */
void *fe_saved_data;
/* Data used by the backend.  */
void *be_saved_data;

/* Copies of global state.  */
int clock_var, last_clock_var;
struct ready_list ready;
state_t curr_state;

rtx_insn *last_scheduled_insn;
rtx_insn *last_nondebug_scheduled_insn;
rtx_insn *nonscheduled_insns_begin;
int cycle_issued_insns;

/* Copies of state used in the inner loop of schedule_block.  */
struct sched_block_state sched_block;

/* We don't need to save q_ptr, as its value is arbitrary and we can set it
   to 0 when restoring.  */
int q_size;
rtx_insn_list **insn_queue;

/* Describe pattern replacements that occurred since this backtrack point
   was queued.  */
vec<dep_t> replacement_deps;
vec<int> replace_apply;

/* A copy of the next-cycle replacement vectors at the time of the backtrack
   point.  */
vec<dep_t> next_cycle_deps;
vec<int> next_cycle_apply;
4319};

4321/* A record, in reverse order, of all scheduled insns which have delay slots
 and may require backtracking.  */
4323static struct haifa_saved_data *backtrack_queue;

4325/* For every dependency of INSN, set the FEEDS_BACKTRACK_INSN bit according
 to SET_P.  */
4327static void
4328mark_backtrack_feeds (rtx_insn *insn, int set_p)
4329{
sd_iterator_def sd_it;
dep_t dep;
FOR_EACH_DEP (insn, SD_LIST_HARD_BACK, sd_it, dep)for ((sd_it) = sd_iterator_start ((insn), ((1))); sd_iterator_cond
 (&(sd_it), &(dep)); sd_iterator_next (&(sd_it)))
  {
    FEEDS_BACKTRACK_INSN (DEP_PRO (dep))((&h_i_d[INSN_UID (((dep)->pro))])->feeds_backtrack_insn
) = set_p;
  }
4336}

4338/* Save the current scheduler state so that we can backtrack to it
 later if necessary.  PAIR gives the insns that make it necessary to
 save this point.  SCHED_BLOCK is the local state of schedule_block
 that need to be saved.  */
4342static void
4343save_backtrack_point (struct delay_pair *pair,
      struct sched_block_state sched_block)
4345{
int i;
struct haifa_saved_data *save = XNEW (struct haifa_saved_data)((struct haifa_saved_data *) xmalloc (sizeof (struct haifa_saved_data
)));

save->curr_state = xmalloc (dfa_state_size);
memcpy (save->curr_state, curr_state, dfa_state_size);

save->ready.first = ready.first;
save->ready.n_ready = ready.n_ready;
save->ready.n_debug = ready.n_debug;
save->ready.veclen = ready.veclen;
save->ready.vec = XNEWVEC (rtx_insn *, ready.veclen)((rtx_insn * *) xmalloc (sizeof (rtx_insn *) * (ready.veclen)
));
memcpy (save->ready.vec, ready.vec, ready.veclen * sizeof (rtx));

save->insn_queue = XNEWVEC (rtx_insn_list *, max_insn_queue_index + 1)((rtx_insn_list * *) xmalloc (sizeof (rtx_insn_list *) * (max_insn_queue_index
 + 1)));
save->q_size = q_size;
for (i = 0; i <= max_insn_queue_index; i++)
  {
    int q = NEXT_Q_AFTER (q_ptr, i)(((q_ptr)+i) & max_insn_queue_index);
    save->insn_queue[i] = copy_INSN_LIST (insn_queue[q]);
  }

save->clock_var = clock_var;
save->last_clock_var = last_clock_var;
save->cycle_issued_insns = cycle_issued_insns;
save->last_scheduled_insn = last_scheduled_insn;
save->last_nondebug_scheduled_insn = last_nondebug_scheduled_insn;
save->nonscheduled_insns_begin = nonscheduled_insns_begin;

save->sched_block = sched_block;

save->replacement_deps.create (0);
save->replace_apply.create (0);
save->next_cycle_deps = next_cycle_replace_deps.copy ();
save->next_cycle_apply = next_cycle_apply.copy ();

if (current_sched_info->save_state)
  save->fe_saved_data = (*current_sched_info->save_state) ();

if (targetm.sched.alloc_sched_context)
  {
    save->be_saved_data = targetm.sched.alloc_sched_context ();
    targetm.sched.init_sched_context (save->be_saved_data, false);
  }
else
  save->be_saved_data = NULLnullptr;

save->delay_pair = pair;

save->next = backtrack_queue;
backtrack_queue = save;

while (pair)
  {
    mark_backtrack_feeds (pair->i2, 1);
    INSN_TICK (pair->i2)((&h_i_d[INSN_UID (pair->i2)])->tick) = INVALID_TICK(-(max_insn_queue_index + 1));
    INSN_EXACT_TICK (pair->i2)((&h_i_d[INSN_UID (pair->i2)])->exact_tick) = clock_var + pair_delay (pair);
    SHADOW_P (pair->i2)((&h_i_d[INSN_UID (pair->i2)])->shadow_p) = pair->stages == 0;
    pair = pair->next_same_i1;
  }
4405}

4407/* Walk the ready list and all queues. If any insns have unresolved backwards
 dependencies, these must be cancelled deps, broken by predication.  Set or
 clear (depending on SET) the DEP_CANCELLED bit in DEP_STATUS.  */

4411static void
4412toggle_cancelled_flags (bool set)
4413{
int i;
sd_iterator_def sd_it;
dep_t dep;

if (ready.n_ready > 0)
  {
    rtx_insn **first = ready_lastpos (&ready);
    for (i = 0; i < ready.n_ready; i++)
FOR_EACH_DEP (first[i], SD_LIST_BACK, sd_it, dep)for ((sd_it) = sd_iterator_start ((first[i]), (((1) | (2))));
 sd_iterator_cond (&(sd_it), &(dep)); sd_iterator_next
 (&(sd_it)))
 if (!DEBUG_INSN_P (DEP_PRO (dep))(((enum rtx_code) (((dep)->pro))->code) == DEBUG_INSN))
   {
     if (set)
DEP_STATUS (dep)((dep)->status) |= DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1);
     else
DEP_STATUS (dep)((dep)->status) &= ~DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1);
   }
  }
for (i = 0; i <= max_insn_queue_index; i++)
  {
    int q = NEXT_Q_AFTER (q_ptr, i)(((q_ptr)+i) & max_insn_queue_index);
    rtx_insn_list *link;
    for (link = insn_queue[q]; link; link = link->next ())
{
 rtx_insn *insn = link->insn ();
 FOR_EACH_DEP (insn, SD_LIST_BACK, sd_it, dep)for ((sd_it) = sd_iterator_start ((insn), (((1) | (2)))); sd_iterator_cond
 (&(sd_it), &(dep)); sd_iterator_next (&(sd_it)))
   if (!DEBUG_INSN_P (DEP_PRO (dep))(((enum rtx_code) (((dep)->pro))->code) == DEBUG_INSN))
     {
if (set)
  DEP_STATUS (dep)((dep)->status) |= DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1);
else
  DEP_STATUS (dep)((dep)->status) &= ~DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1);
     }
}
  }
4448}

4450/* Undo the replacements that have occurred after backtrack point SAVE
 was placed.  */
4452static void
4453undo_replacements_for_backtrack (struct haifa_saved_data *save)
4454{
while (!save->replacement_deps.is_empty ())
  {
    dep_t dep = save->replacement_deps.pop ();
    int apply_p = save->replace_apply.pop ();

    if (apply_p)
restore_pattern (dep, true);
    else
apply_replacement (dep, true);
  }
save->replacement_deps.release ();
save->replace_apply.release ();
4467}

4469/* Pop entries from the SCHEDULED_INSNS vector up to and including INSN.
 Restore their dependencies to an unresolved state, and mark them as
 queued nowhere.  */

4473static void
4474unschedule_insns_until (rtx_insn *insn)
4475{
auto_vec<rtx_insn *> recompute_vec;

/* Make two passes over the insns to be unscheduled.  First, we clear out
   dependencies and other trivial bookkeeping.  */
for (;;)
  {
    rtx_insn *last;
    sd_iterator_def sd_it;
    dep_t dep;

    last = scheduled_insns.pop ();

    /* This will be changed by restore_backtrack_point if the insn is in
any queue.  */
    QUEUE_INDEX (last)((&h_i_d[INSN_UID (last)])->queue_index) = QUEUE_NOWHERE(-2);
    if (last != insn)
INSN_TICK (last)((&h_i_d[INSN_UID (last)])->tick) = INVALID_TICK(-(max_insn_queue_index + 1));

    if (modulo_ii > 0 && INSN_UID (last) < modulo_iter0_max_uid)
modulo_insns_scheduled--;

    for (sd_it = sd_iterator_start (last, SD_LIST_RES_FORW(16));
  sd_iterator_cond (&sd_it, &dep);)
{
 rtx_insn *con = DEP_CON (dep)((dep)->con);
 sd_unresolve_dep (sd_it);
 if (!MUST_RECOMPUTE_SPEC_P (con)((&h_i_d[INSN_UID (con)])->must_recompute_spec))
   {
     MUST_RECOMPUTE_SPEC_P (con)((&h_i_d[INSN_UID (con)])->must_recompute_spec) = 1;
     recompute_vec.safe_push (con);
   }
}

    if (last == insn)
break;
  }

/* A second pass, to update ready and speculation status for insns
   depending on the unscheduled ones.  The first pass must have
   popped the scheduled_insns vector up to the point where we
   restart scheduling, as recompute_todo_spec requires it to be
   up-to-date.  */
while (!recompute_vec.is_empty ())
  {
    rtx_insn *con;

    con = recompute_vec.pop ();
    MUST_RECOMPUTE_SPEC_P (con)((&h_i_d[INSN_UID (con)])->must_recompute_spec) = 0;
    if (!sd_lists_empty_p (con, SD_LIST_HARD_BACK(1)))
{
 TODO_SPEC (con)((&h_i_d[INSN_UID (con)])->todo_spec) = HARD_DEP(((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) << 1);
 INSN_TICK (con)((&h_i_d[INSN_UID (con)])->tick) = INVALID_TICK(-(max_insn_queue_index + 1));
 if (PREDICATED_PAT (con)((&h_i_d[INSN_UID (con)])->predicated_pat) != NULL_RTX(rtx) 0)
   haifa_change_pattern (con, ORIG_PAT (con)((&h_i_d[INSN_UID (con)])->orig_pat));
}
    else if (QUEUE_INDEX (con)((&h_i_d[INSN_UID (con)])->queue_index) != QUEUE_SCHEDULED(-3))
TODO_SPEC (con)((&h_i_d[INSN_UID (con)])->todo_spec) = recompute_todo_spec (con, true);
  }
4534}

4536/* Restore scheduler state from the topmost entry on the backtracking queue.
 PSCHED_BLOCK_P points to the local data of schedule_block that we must
 overwrite with the saved data.
 The caller must already have called unschedule_insns_until.  */

4541static void
4542restore_last_backtrack_point (struct sched_block_state *psched_block)
4543{
int i;
struct haifa_saved_data *save = backtrack_queue;

backtrack_queue = save->next;

if (current_sched_info->restore_state)
  (*current_sched_info->restore_state) (save->fe_saved_data);

if (targetm.sched.alloc_sched_context)
  {
    targetm.sched.set_sched_context (save->be_saved_data);
    targetm.sched.free_sched_context (save->be_saved_data);
  }

/* Do this first since it clobbers INSN_TICK of the involved
   instructions.  */
undo_replacements_for_backtrack (save);

/* Clear the QUEUE_INDEX of everything in the ready list or one
   of the queues.  */
if (ready.n_ready > 0)
  {
    rtx_insn **first = ready_lastpos (&ready);
    for (i = 0; i < ready.n_ready; i++)
{
 rtx_insn *insn = first[i];
 QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index) = QUEUE_NOWHERE(-2);
 INSN_TICK (insn)((&h_i_d[INSN_UID (insn)])->tick) = INVALID_TICK(-(max_insn_queue_index + 1));
}
  }
for (i = 0; i <= max_insn_queue_index; i++)
  {
    int q = NEXT_Q_AFTER (q_ptr, i)(((q_ptr)+i) & max_insn_queue_index);

    for (rtx_insn_list *link = insn_queue[q]; link; link = link->next ())
{
 rtx_insn *x = link->insn ();
 QUEUE_INDEX (x)((&h_i_d[INSN_UID (x)])->queue_index) = QUEUE_NOWHERE(-2);
 INSN_TICK (x)((&h_i_d[INSN_UID (x)])->tick) = INVALID_TICK(-(max_insn_queue_index + 1));
}
    free_INSN_LIST_list (&insn_queue[q]);
  }

free (ready.vec);
ready = save->ready;

if (ready.n_ready > 0)
  {
    rtx_insn **first = ready_lastpos (&ready);
    for (i = 0; i < ready.n_ready; i++)
{
 rtx_insn *insn = first[i];
 QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index) = QUEUE_READY(-1);
 TODO_SPEC (insn)((&h_i_d[INSN_UID (insn)])->todo_spec) = recompute_todo_spec (insn, true);
 INSN_TICK (insn)((&h_i_d[INSN_UID (insn)])->tick) = save->clock_var;
}
  }

q_ptr = 0;
q_size = save->q_size;
for (i = 0; i <= max_insn_queue_index; i++)
  {
    int q = NEXT_Q_AFTER (q_ptr, i)(((q_ptr)+i) & max_insn_queue_index);

    insn_queue[q] = save->insn_queue[q];

    for (rtx_insn_list *link = insn_queue[q]; link; link = link->next ())
{
 rtx_insn *x = link->insn ();
 QUEUE_INDEX (x)((&h_i_d[INSN_UID (x)])->queue_index) = i;
 TODO_SPEC (x)((&h_i_d[INSN_UID (x)])->todo_spec) = recompute_todo_spec (x, true);
 INSN_TICK (x)((&h_i_d[INSN_UID (x)])->tick) = save->clock_var + i;
}
  }
free (save->insn_queue);

toggle_cancelled_flags (true);

clock_var = save->clock_var;
last_clock_var = save->last_clock_var;
cycle_issued_insns = save->cycle_issued_insns;
last_scheduled_insn = save->last_scheduled_insn;
last_nondebug_scheduled_insn = save->last_nondebug_scheduled_insn;
nonscheduled_insns_begin = save->nonscheduled_insns_begin;

*psched_block = save->sched_block;

memcpy (curr_state, save->curr_state, dfa_state_size);
free (save->curr_state);

mark_backtrack_feeds (save->delay_pair->i2, 0);

gcc_assert (next_cycle_replace_deps.is_empty ())((void)(!(next_cycle_replace_deps.is_empty ()) ? fancy_abort (
"/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4636, __FUNCTION__), 0 : 0));
next_cycle_replace_deps = save->next_cycle_deps.copy ();
next_cycle_apply = save->next_cycle_apply.copy ();

free (save);

for (save = backtrack_queue; save; save = save->next)
  {
    mark_backtrack_feeds (save->delay_pair->i2, 1);
  }
4646}

4648/* Discard all data associated with the topmost entry in the backtrack
 queue.  If RESET_TICK is false, we just want to free the data.  If true,
 we are doing this because we discovered a reason to backtrack.  In the
 latter case, also reset the INSN_TICK for the shadow insn.  */
4652static void
4653free_topmost_backtrack_point (bool reset_tick)
4654{
struct haifa_saved_data *save = backtrack_queue;
int i;

backtrack_queue = save->next;

if (reset_tick)
  {
    struct delay_pair *pair = save->delay_pair;
    while (pair)
{
 INSN_TICK (pair->i2)((&h_i_d[INSN_UID (pair->i2)])->tick) = INVALID_TICK(-(max_insn_queue_index + 1));
 INSN_EXACT_TICK (pair->i2)((&h_i_d[INSN_UID (pair->i2)])->exact_tick) = INVALID_TICK(-(max_insn_queue_index + 1));
 pair = pair->next_same_i1;
}
    undo_replacements_for_backtrack (save);
  }
else
  {
    save->replacement_deps.release ();
    save->replace_apply.release ();
  }

if (targetm.sched.free_sched_context)
  targetm.sched.free_sched_context (save->be_saved_data);
if (current_sched_info->restore_state)
  free (save->fe_saved_data);
for (i = 0; i <= max_insn_queue_index; i++)
  free_INSN_LIST_list (&save->insn_queue[i]);
free (save->insn_queue);
free (save->curr_state);
free (save->ready.vec);
free (save);
4687}

4689/* Free the entire backtrack queue.  */
4690static void
4691free_backtrack_queue (void)
4692{
while (backtrack_queue)
  free_topmost_backtrack_point (false);
4695}

4697/* Apply a replacement described by DESC.  If IMMEDIATELY is false, we
 may have to postpone the replacement until the start of the next cycle,
 at which point we will be called again with IMMEDIATELY true.  This is
 only done for machines which have instruction packets with explicit
 parallelism however.  */
4702static void
4703apply_replacement (dep_t dep, bool immediately)
4704{
struct dep_replacement *desc = DEP_REPLACE (dep)((dep)->replace);
if (!immediately && targetm.sched.exposed_pipeline && reload_completed)
  {
    next_cycle_replace_deps.safe_push (dep);
    next_cycle_apply.safe_push (1);
  }
else
  {
    bool success;

    if (QUEUE_INDEX (desc->insn)((&h_i_d[INSN_UID (desc->insn)])->queue_index) == QUEUE_SCHEDULED(-3))
return;

    if (sched_verbose >= 5)
fprintf (sched_dump, "applying replacement for insn %d\n",
 INSN_UID (desc->insn));

    success = validate_change (desc->insn, desc->loc, desc->newval, 0);
    gcc_assert (success)((void)(!(success) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4723, __FUNCTION__), 0 : 0));

    rtx_insn *insn = DEP_PRO (dep)((dep)->pro);

    /* Recompute priority since dependent priorities may have changed.  */
    priority (insn, true);
    update_insn_after_change (desc->insn);

    if ((TODO_SPEC (desc->insn)((&h_i_d[INSN_UID (desc->insn)])->todo_spec) & (HARD_DEP(((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) << 1) | DEP_POSTPONED((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1))) == 0)
fix_tick_ready (desc->insn);

    if (backtrack_queue != NULLnullptr)
{
 backtrack_queue->replacement_deps.safe_push (dep);
 backtrack_queue->replace_apply.safe_push (1);
}
  }
4740}

4742/* We have determined that a pattern involved in DEP must be restored.
 If IMMEDIATELY is false, we may have to postpone the replacement
 until the start of the next cycle, at which point we will be called
 again with IMMEDIATELY true.  */
4746static void
4747restore_pattern (dep_t dep, bool immediately)
4748{
rtx_insn *next = DEP_CON (dep)((dep)->con);
int tick = INSN_TICK (next)((&h_i_d[INSN_UID (next)])->tick);

/* If we already scheduled the insn, the modified version is
   correct.  */
if (QUEUE_INDEX (next)((&h_i_d[INSN_UID (next)])->queue_index) == QUEUE_SCHEDULED(-3))
  return;

if (!immediately && targetm.sched.exposed_pipeline && reload_completed)
  {
    next_cycle_replace_deps.safe_push (dep);
    next_cycle_apply.safe_push (0);
    return;
  }


if (DEP_TYPE (dep)((dep)->type) == REG_DEP_CONTROL)
  {
    if (sched_verbose >= 5)
fprintf (sched_dump, "restoring pattern for insn %d\n",
 INSN_UID (next));
    haifa_change_pattern (next, ORIG_PAT (next)((&h_i_d[INSN_UID (next)])->orig_pat));
  }
else
  {
    struct dep_replacement *desc = DEP_REPLACE (dep)((dep)->replace);
    bool success;

    if (sched_verbose >= 5)
fprintf (sched_dump, "restoring pattern for insn %d\n",
 INSN_UID (desc->insn));
    tick = INSN_TICK (desc->insn)((&h_i_d[INSN_UID (desc->insn)])->tick);

    success = validate_change (desc->insn, desc->loc, desc->orig, 0);
    gcc_assert (success)((void)(!(success) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4783, __FUNCTION__), 0 : 0));

    rtx_insn *insn = DEP_PRO (dep)((dep)->pro);

    if (QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index) != QUEUE_SCHEDULED(-3))
{
 /* Recompute priority since dependent priorities may have changed.  */
 priority (insn, true);
}

    update_insn_after_change (desc->insn);

    if (backtrack_queue != NULLnullptr)
{
 backtrack_queue->replacement_deps.safe_push (dep);
 backtrack_queue->replace_apply.safe_push (0);
}
  }
INSN_TICK (next)((&h_i_d[INSN_UID (next)])->tick) = tick;
if (TODO_SPEC (next)((&h_i_d[INSN_UID (next)])->todo_spec) == DEP_POSTPONED((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1))
  return;

if (sd_lists_empty_p (next, SD_LIST_BACK((1) | (2))))
  TODO_SPEC (next)((&h_i_d[INSN_UID (next)])->todo_spec) = 0;
else if (!sd_lists_empty_p (next, SD_LIST_HARD_BACK(1)))
  TODO_SPEC (next)((&h_i_d[INSN_UID (next)])->todo_spec) = HARD_DEP(((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 * 4
) - 8) / 4))) << 1) << 1) << 1) << 1);
4809}

4811/* Perform pattern replacements that were queued up until the next
 cycle.  */
4813static void
4814perform_replacements_new_cycle (void)
4815{
int i;
dep_t dep;
FOR_EACH_VEC_ELT (next_cycle_replace_deps, i, dep)for (i = 0; (next_cycle_replace_deps).iterate ((i), &(dep
)); ++(i))
  {
    int apply_p = next_cycle_apply[i];
    if (apply_p)
apply_replacement (dep, true);
    else
restore_pattern (dep, true);
  }
next_cycle_replace_deps.truncate (0);
next_cycle_apply.truncate (0);
4828}

4830/* Compute INSN_TICK_ESTIMATE for INSN.  PROCESSED is a bitmap of
 instructions we've previously encountered, a set bit prevents
 recursion.  BUDGET is a limit on how far ahead we look, it is
 reduced on recursive calls.  Return true if we produced a good
 estimate, or false if we exceeded the budget.  */
4835static bool
4836estimate_insn_tick (bitmap processed, rtx_insn *insn, int budget)
4837{
sd_iterator_def sd_it;
dep_t dep;
int earliest = INSN_TICK (insn)((&h_i_d[INSN_UID (insn)])->tick);

FOR_EACH_DEP (insn, SD_LIST_BACK, sd_it, dep)for ((sd_it) = sd_iterator_start ((insn), (((1) | (2)))); sd_iterator_cond
 (&(sd_it), &(dep)); sd_iterator_next (&(sd_it)))
  {
    rtx_insn *pro = DEP_PRO (dep)((dep)->pro);
    int t;

    if (DEP_STATUS (dep)((dep)->status) & DEP_CANCELLED(((((((((ds_t) 1) << (BE_IN_CONTROL_BITS_OFFSET + (((8 *
 4) - 8) / 4))) << 1) << 1) << 1) << 1
) << 1) << 1))
continue;

    if (QUEUE_INDEX (pro)((&h_i_d[INSN_UID (pro)])->queue_index) == QUEUE_SCHEDULED(-3))
gcc_assert (INSN_TICK (pro) + dep_cost (dep) <= INSN_TICK (insn))((void)(!(((&h_i_d[INSN_UID (pro)])->tick) + dep_cost (
dep) <= ((&h_i_d[INSN_UID (insn)])->tick)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4851, __FUNCTION__), 0 : 0));
    else
{
 int cost = dep_cost (dep);
 if (cost >= budget)
   return false;
 if (!bitmap_bit_p (processed, INSN_LUID (pro)(sched_luids[INSN_UID (pro)])))
   {
     if (!estimate_insn_tick (processed, pro, budget - cost))
return false;
   }
 gcc_assert (INSN_TICK_ESTIMATE (pro) != INVALID_TICK)((void)(!(((&h_i_d[INSN_UID (pro)])->tick_estimate) !=
 (-(max_insn_queue_index + 1))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4862, __FUNCTION__), 0 : 0));
 t = INSN_TICK_ESTIMATE (pro)((&h_i_d[INSN_UID (pro)])->tick_estimate) + cost;
 if (earliest == INVALID_TICK(-(max_insn_queue_index + 1)) || t > earliest)
   earliest = t;
}
  }
bitmap_set_bit (processed, INSN_LUID (insn)(sched_luids[INSN_UID (insn)]));
INSN_TICK_ESTIMATE (insn)((&h_i_d[INSN_UID (insn)])->tick_estimate) = earliest;
return true;
4871}

4873/* Examine the pair of insns in P, and estimate (optimistically, assuming
 infinite resources) the cycle in which the delayed shadow can be issued.
 Return the number of cycles that must pass before the real insn can be
 issued in order to meet this constraint.  */
4877static int
4878estimate_shadow_tick (struct delay_pair *p)
4879{
auto_bitmap processed;
int t;
bool cutoff;

cutoff = !estimate_insn_tick (processed, p->i2,
		max_insn_queue_index + pair_delay (p));
if (cutoff)
  return max_insn_queue_index;
t = INSN_TICK_ESTIMATE (p->i2)((&h_i_d[INSN_UID (p->i2)])->tick_estimate) - (clock_var + pair_delay (p) + 1);
if (t > 0)
  return t;
return 0;
4892}

4894/* If INSN has no unresolved backwards dependencies, add it to the schedule and
 recursively resolve all its forward dependencies.  */
4896static void
4897resolve_dependencies (rtx_insn *insn)
4898{
sd_iterator_def sd_it;
dep_t dep;

/* Don't use sd_lists_empty_p; it ignores debug insns.  */
if (DEPS_LIST_FIRST (INSN_HARD_BACK_DEPS (insn))((((&h_d_i_d[(sched_luids[INSN_UID (insn)])])->hard_back_deps
))->first) != NULLnullptr
    || DEPS_LIST_FIRST (INSN_SPEC_BACK_DEPS (insn))((((&h_d_i_d[(sched_luids[INSN_UID (insn)])])->spec_back_deps
))->first) != NULLnullptr)
  return;

if (sched_verbose >= 4)
  fprintf (sched_dump, ";;\tquickly resolving %d\n", INSN_UID (insn));

if (QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index) >= 0)
  queue_remove (insn);

scheduled_insns.safe_push (insn);

/* Update dependent instructions.  */
for (sd_it = sd_iterator_start (insn, SD_LIST_FORW(4));
     sd_iterator_cond (&sd_it, &dep);)
  {
    rtx_insn *next = DEP_CON (dep)((dep)->con);

    if (sched_verbose >= 4)
fprintf (sched_dump, ";;\t\tdep %d against %d\n", INSN_UID (insn),
 INSN_UID (next));

    /* Resolve the dependence between INSN and NEXT.
sd_resolve_dep () moves current dep to another list thus
advancing the iterator.  */
    sd_resolve_dep (sd_it);

    if (!IS_SPECULATION_BRANCHY_CHECK_P (insn)(((&h_i_d[INSN_UID (insn)])->recovery_block) != nullptr
 && ((&h_i_d[INSN_UID (insn)])->recovery_block
) != (((cfun + 0))->cfg->x_exit_block_ptr)))
{
 resolve_dependencies (next);
}
    else
/* Check always has only one forward dependence (to the first insn in
  the recovery block), therefore, this will be executed only once.  */
{
 gcc_assert (sd_lists_empty_p (insn, SD_LIST_FORW))((void)(!(sd_lists_empty_p (insn, (4))) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 4938, __FUNCTION__), 0 : 0));
}
  }
4941}


4944/* Return the head and tail pointers of ebb starting at BEG and ending
 at END.  */
4946void
4947get_ebb_head_tail (basic_block beg, basic_block end,
   rtx_insn **headp, rtx_insn **tailp)
4949{
rtx_insn *beg_head = BB_HEAD (beg)(beg)->il.x.head_;
rtx_insn * beg_tail = BB_END (beg)(beg)->il.x.rtl->end_;
rtx_insn * end_head = BB_HEAD (end)(end)->il.x.head_;
rtx_insn * end_tail = BB_END (end)(end)->il.x.rtl->end_;

/* Don't include any notes or labels at the beginning of the BEG
   basic block, or notes at the end of the END basic blocks.  */

if (LABEL_P (beg_head)(((enum rtx_code) (beg_head)->code) == CODE_LABEL))
  beg_head = NEXT_INSN (beg_head);

while (beg_head != beg_tail)
  if (NOTE_P (beg_head)(((enum rtx_code) (beg_head)->code) == NOTE))
    beg_head = NEXT_INSN (beg_head);
  else if (DEBUG_INSN_P (beg_head)(((enum rtx_code) (beg_head)->code) == DEBUG_INSN))
    {
rtx_insn * note, *next;

for (note = NEXT_INSN (beg_head);
    note != beg_tail;
    note = next)
 {
   next = NEXT_INSN (note);
   if (NOTE_P (note)(((enum rtx_code) (note)->code) == NOTE))
     {
if (sched_verbose >= 9)
  fprintf (sched_dump, "reorder %i\n", INSN_UID (note));

reorder_insns_nobb (note, note, PREV_INSN (beg_head));

if (BLOCK_FOR_INSN (note) != beg)
  df_insn_change_bb (note, beg);
     }
   else if (!DEBUG_INSN_P (note)(((enum rtx_code) (note)->code) == DEBUG_INSN))
     break;
 }

break;
    }
  else
    break;

*headp = beg_head;

if (beg == end)
  end_head = beg_head;
else if (LABEL_P (end_head)(((enum rtx_code) (end_head)->code) == CODE_LABEL))
  end_head = NEXT_INSN (end_head);

while (end_head != end_tail)
  if (NOTE_P (end_tail)(((enum rtx_code) (end_tail)->code) == NOTE))
    end_tail = PREV_INSN (end_tail);
  else if (DEBUG_INSN_P (end_tail)(((enum rtx_code) (end_tail)->code) == DEBUG_INSN))
    {
rtx_insn * note, *prev;

for (note = PREV_INSN (end_tail);
    note != end_head;
    note = prev)
 {
   prev = PREV_INSN (note);
   if (NOTE_P (note)(((enum rtx_code) (note)->code) == NOTE))
     {
if (sched_verbose >= 9)
  fprintf (sched_dump, "reorder %i\n", INSN_UID (note));

reorder_insns_nobb (note, note, end_tail);

if (end_tail == BB_END (end)(end)->il.x.rtl->end_)
  BB_END (end)(end)->il.x.rtl->end_ = note;

if (BLOCK_FOR_INSN (note) != end)
  df_insn_change_bb (note, end);
     }
   else if (!DEBUG_INSN_P (note)(((enum rtx_code) (note)->code) == DEBUG_INSN))
     break;
 }

break;
    }
  else
    break;

*tailp = end_tail;
5034}

5036/* Return nonzero if there are no real insns in the range [ HEAD, TAIL ].  */

5038int
5039no_real_insns_p (const rtx_insn *head, const rtx_insn *tail)
5040{
while (head != NEXT_INSN (tail))
  {
    if (!NOTE_P (head)(((enum rtx_code) (head)->code) == NOTE) && !LABEL_P (head)(((enum rtx_code) (head)->code) == CODE_LABEL))
return 0;
    head = NEXT_INSN (head);
  }
return 1;
5048}

5050/* Restore-other-notes: NOTE_LIST is the end of a chain of notes
 previously found among the insns.  Insert them just before HEAD.  */
5052rtx_insn *
5053restore_other_notes (rtx_insn *head, basic_block head_bb)
5054{
if (note_list != 0)
  {
    rtx_insn *note_head = note_list;

    if (head)
head_bb = BLOCK_FOR_INSN (head);
    else
head = NEXT_INSN (bb_note (head_bb));

    while (PREV_INSN (note_head))
{
 set_block_for_insn (note_head, head_bb);
 note_head = PREV_INSN (note_head);
}
    /* In the above cycle we've missed this note.  */
    set_block_for_insn (note_head, head_bb);

    SET_PREV_INSN (note_head) = PREV_INSN (head);
    SET_NEXT_INSN (PREV_INSN (head)) = note_head;
    SET_PREV_INSN (head) = note_list;
    SET_NEXT_INSN (note_list) = head;

    if (BLOCK_FOR_INSN (head) != head_bb)
BB_END (head_bb)(head_bb)->il.x.rtl->end_ = note_list;

    head = note_head;
  }

return head;
5084}

5086/* When we know we are going to discard the schedule due to a failed attempt
 at modulo scheduling, undo all replacements.  */
5088static void
5089undo_all_replacements (void)
5090{
rtx_insn *insn;
int i;

FOR_EACH_VEC_ELT (scheduled_insns, i, insn)for (i = 0; (scheduled_insns).iterate ((i), &(insn)); ++(
i))
  {
    sd_iterator_def sd_it;
    dep_t dep;

    /* See if we must undo a replacement.  */
    for (sd_it = sd_iterator_start (insn, SD_LIST_RES_FORW(16));
  sd_iterator_cond (&sd_it, &dep); sd_iterator_next (&sd_it))
{
 struct dep_replacement *desc = DEP_REPLACE (dep)((dep)->replace);
 if (desc != NULLnullptr)
   validate_change (desc->insn, desc->loc, desc->orig, 0);
}
  }
5108}

5110/* Return first non-scheduled insn in the current scheduling block.
 This is mostly used for debug-counter purposes.  */
5112static rtx_insn *
5113first_nonscheduled_insn (void)
5114{
rtx_insn *insn = (nonscheduled_insns_begin != NULL_RTX(rtx) 0
    ? nonscheduled_insns_begin
    : current_sched_info->prev_head);

do
  {
    insn = next_nonnote_nondebug_insn (insn);
  }
while (QUEUE_INDEX (insn)((&h_i_d[INSN_UID (insn)])->queue_index) == QUEUE_SCHEDULED(-3));

return insn;
5126}

5128/* Move insns that became ready to fire from queue to ready list.  */

5130static void
5131queue_to_ready (struct ready_list *ready)
5132{
rtx_insn *insn;
rtx_insn_list *link;
rtx_insn *skip_insn;

q_ptr = NEXT_Q (q_ptr)(((q_ptr)+1) & max_insn_queue_index);

if (dbg_cnt (sched_insn) == false)
  /* If debug counter is activated do not requeue the first
     nonscheduled insn.  */
  skip_insn = first_nonscheduled_insn ();
else
  skip_insn = NULLnullptr;

/* Add all pending insns that can be scheduled without stalls to the
   ready list.  */
for (link = insn_queue[q_ptr]; link; link = link->next ())
  {
    insn = link->insn ();
    q_size -= 1;

    if (sched_verbose >= 2)
fprintf (sched_dump, ";;\t\tQ-->Ready: insn %s: ",
 (*current_sched_info->print_insn) (insn, 0));

    /* If the ready list is full, delay the insn for 1 cycle.
See the comment in schedule_block for the rationale.  */
    if (!reload_completed
 && (ready->n_ready - ready->n_debug > param_max_sched_ready_insnsglobal_options.x_param_max_sched_ready_insns
     || (sched_pressure == SCHED_PRESSURE_MODEL
  /* Limit pressure recalculations to
     param_max_sched_ready_insns instructions too.  */
  && model_index (insn) > (model_curr_point
			   + param_max_sched_ready_insnsglobal_options.x_param_max_sched_ready_insns)))
 && !(sched_pressure == SCHED_PRESSURE_MODEL
      && model_curr_point < model_num_insns
      /* Always allow the next model instruction to issue.  */
      && model_index (insn) == model_curr_point)
 && !SCHED_GROUP_P (insn)(__extension__ ({ __typeof ((insn)) const _rtx = ((insn)); if
 (((enum rtx_code) (_rtx)->code) != DEBUG_INSN && (
(enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != JUMP_INSN && ((enum rtx_code) (
_rtx)->code) != CALL_INSN) rtl_check_failed_flag ("SCHED_GROUP_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5170, __FUNCTION__); _rtx; })->in_struct)
 && insn != skip_insn)
{
 if (sched_verbose >= 2)
   fprintf (sched_dump, "keeping in queue, ready full\n");
 queue_insn (insn, 1, "ready full");
}
    else
{
 ready_add (ready, insn, false);
 if (sched_verbose >= 2)
   fprintf (sched_dump, "moving to ready without stalls\n");
      }
  }
free_INSN_LIST_list (&insn_queue[q_ptr]);

/* If there are no ready insns, stall until one is ready and add all
   of the pending insns at that point to the ready list.  */
if (ready->n_ready == 0)
  {
    int stalls;

    for (stalls = 1; stalls <= max_insn_queue_index; stalls++)
{
 if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)(((q_ptr)+stalls) & max_insn_queue_index)]))
   {
     for (; link; link = link->next ())
{
  insn = link->insn ();
  q_size -= 1;

  if (sched_verbose >= 2)
    fprintf (sched_dump, ";;\t\tQ-->Ready: insn %s: ",
	     (*current_sched_info->print_insn) (insn, 0));

  ready_add (ready, insn, false);
  if (sched_verbose >= 2)
    fprintf (sched_dump, "moving to ready with %d stalls\n", stalls);
}
     free_INSN_LIST_list (&insn_queue[NEXT_Q_AFTER (q_ptr, stalls)(((q_ptr)+stalls) & max_insn_queue_index)]);

     advance_one_cycle ();

     break;
   }

 advance_one_cycle ();
}

    q_ptr = NEXT_Q_AFTER (q_ptr, stalls)(((q_ptr)+stalls) & max_insn_queue_index);
    clock_var += stalls;
    if (sched_verbose >= 2)
fprintf (sched_dump, ";;\tAdvancing clock by %d cycle[s] to %d\n",
 stalls, clock_var);
  }
5225}

5227/* Used by early_queue_to_ready.  Determines whether it is "ok" to
 prematurely move INSN from the queue to the ready list.  Currently,
 if a target defines the hook 'is_costly_dependence', this function
 uses the hook to check whether there exist any dependences which are
 considered costly by the target, between INSN and other insns that
 have already been scheduled.  Dependences are checked up to Y cycles
 back, with default Y=1; The flag -fsched-stalled-insns-dep=Y allows
 controlling this value.
 (Other considerations could be taken into account instead (or in
 addition) depending on user flags and target hooks.  */

5238static bool
5239ok_for_early_queue_removal (rtx_insn *insn)
5240{
if (targetm.sched.is_costly_dependence)
  {
    int n_cycles;
    int i = scheduled_insns.length ();
    for (n_cycles = flag_sched_stalled_insns_depglobal_options.x_flag_sched_stalled_insns_dep; n_cycles; n_cycles--)
{
 while (i-- > 0)
   {
     int cost;

     rtx_insn *prev_insn = scheduled_insns[i];

     if (!NOTE_P (prev_insn)(((enum rtx_code) (prev_insn)->code) == NOTE))
{
  dep_t dep;

  dep = sd_find_dep_between (prev_insn, insn, true);

  if (dep != NULLnullptr)
    {
      cost = dep_cost (dep);

      if (targetm.sched.is_costly_dependence (dep, cost,
		flag_sched_stalled_insns_depglobal_options.x_flag_sched_stalled_insns_dep - n_cycles))
	return false;
    }
}

     if (GET_MODE (prev_insn)((machine_mode) (prev_insn)->mode) == TImode(scalar_int_mode ((scalar_int_mode::from_int) E_TImode))) /* end of dispatch group */
break;
   }

 if (i == 0)
   break;
}
  }

return true;
5279}


5282/* Remove insns from the queue, before they become "ready" with respect
 to FU latency considerations.  */

5285static int
5286early_queue_to_ready (state_t state, struct ready_list *ready)
5287{
rtx_insn *insn;
rtx_insn_list *link;
rtx_insn_list *next_link;
rtx_insn_list *prev_link;
bool move_to_ready;
int cost;
state_t temp_state = alloca (dfa_state_size)__builtin_alloca(dfa_state_size);
int stalls;
int insns_removed = 0;

/*
   Flag '-fsched-stalled-insns=X' determines the aggressiveness of this
   function:

   X == 0: There is no limit on how many queued insns can be removed
           prematurely.  (flag_sched_stalled_insns = -1).

   X >= 1: Only X queued insns can be removed prematurely in each
    invocation.  (flag_sched_stalled_insns = X).

   Otherwise: Early queue removal is disabled.
       (flag_sched_stalled_insns = 0)
*/

if (! flag_sched_stalled_insnsglobal_options.x_flag_sched_stalled_insns)
  return 0;

for (stalls = 0; stalls <= max_insn_queue_index; stalls++)
  {
    if ((link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)(((q_ptr)+stalls) & max_insn_queue_index)]))
{
 if (sched_verbose > 6)
   fprintf (sched_dump, ";; look at index %d + %d\n", q_ptr, stalls);

 prev_link = 0;
 while (link)
   {
     next_link = link->next ();
     insn = link->insn ();
     if (insn && sched_verbose > 6)
print_rtl_single (sched_dump, insn);

     memcpy (temp_state, state, dfa_state_size);
     if (recog_memoized (insn) < 0)
/* non-negative to indicate that it's not ready
   to avoid infinite Q->R->Q->R... */
cost = 0;
     else
cost = state_transition (temp_state, insn);

     if (sched_verbose >= 6)
fprintf (sched_dump, "transition cost = %d\n", cost);

     move_to_ready = false;
     if (cost < 0)
{
  move_to_ready = ok_for_early_queue_removal (insn);
  if (move_to_ready == true)
    {
      /* move from Q to R */
      q_size -= 1;
      ready_add (ready, insn, false);

      if (prev_link)
	XEXP (prev_link, 1)(((prev_link)->u.fld[1]).rt_rtx) = next_link;
      else
	insn_queue[NEXT_Q_AFTER (q_ptr, stalls)(((q_ptr)+stalls) & max_insn_queue_index)] = next_link;

      free_INSN_LIST_node (link);

      if (sched_verbose >= 2)
	fprintf (sched_dump, ";;\t\tEarly Q-->Ready: insn %s\n",
		 (*current_sched_info->print_insn) (insn, 0));

      insns_removed++;
      if (insns_removed == flag_sched_stalled_insnsglobal_options.x_flag_sched_stalled_insns)
	/* Remove no more than flag_sched_stalled_insns insns
	   from Q at a time.  */
	return insns_removed;
    }
}

     if (move_to_ready == false)
prev_link = link;

     link = next_link;
   } /* while link */
} /* if link */

  } /* for stalls.. */

return insns_removed;
5380}


5383/* Print the ready list for debugging purposes.
 If READY_TRY is non-zero then only print insns that max_issue
 will consider.  */
5386static void
5387debug_ready_list_1 (struct ready_list *ready, signed char *ready_try)
5388{
rtx_insn **p;
int i;

if (ready->n_ready == 0)
  {
    fprintf (sched_dump, "\n");
    return;
  }

p = ready_lastpos (ready);
for (i = 0; i < ready->n_ready; i++)
  {
    if (ready_try != NULLnullptr && ready_try[ready->n_ready - i - 1])
continue;

    fprintf (sched_dump, "  %s:%d",
      (*current_sched_info->print_insn) (p[i], 0),
      INSN_LUID (p[i])(sched_luids[INSN_UID (p[i])]));
    if (sched_pressure != SCHED_PRESSURE_NONE)
fprintf (sched_dump, "(cost=%d",
 INSN_REG_PRESSURE_EXCESS_COST_CHANGE (p[i])((&h_i_d[INSN_UID (p[i])])->reg_pressure_excess_cost_change
));
    fprintf (sched_dump, ":prio=%d", INSN_PRIORITY (p[i])((&h_i_d[INSN_UID (p[i])])->priority));
    if (INSN_TICK (p[i])((&h_i_d[INSN_UID (p[i])])->tick) > clock_var)
fprintf (sched_dump, ":delay=%d", INSN_TICK (p[i])((&h_i_d[INSN_UID (p[i])])->tick) - clock_var);
    if (sched_pressure == SCHED_PRESSURE_MODEL)
fprintf (sched_dump, ":idx=%d",
 model_index (p[i]));
    if (sched_pressure != SCHED_PRESSURE_NONE)
fprintf (sched_dump, ")");
  }
fprintf (sched_dump, "\n");
5420}

5422/* Print the ready list.  Callable from debugger.  */
5423static void
5424debug_ready_list (struct ready_list *ready)
5425{
debug_ready_list_1 (ready, NULLnullptr);
5427}

5429/* Search INSN for REG_SAVE_NOTE notes and convert them back into insn
 NOTEs.  This is used for NOTE_INSN_EPILOGUE_BEG, so that sched-ebb
 replaces the epilogue note in the correct basic block.  */
5432void
5433reemit_notes (rtx_insn *insn)
5434{
rtx note;
rtx_insn *last = insn;

for (note = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); note; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
  {
    if (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_SAVE_NOTE)
{
 enum insn_note note_type = (enum insn_note) INTVAL (XEXP (note, 0))(((((note)->u.fld[0]).rt_rtx))->u.hwint[0]);

 last = emit_note_before (note_type, last);
 remove_note (insn, note);
 df_insn_create_insn_record (last);
}
  }
5449}

5451/* Move INSN.  Reemit notes if needed.  Update CFG, if needed.  */
5452static void
5453move_insn (rtx_insn *insn, rtx_insn *last, rtx nt)
5454{
if (PREV_INSN (insn) != last)
  {
    basic_block bb;
    rtx_insn *note;
    int jump_p = 0;

    bb = BLOCK_FOR_INSN (insn);

    /* BB_HEAD is either LABEL or NOTE.  */
    gcc_assert (BB_HEAD (bb) != insn)((void)(!((bb)->il.x.head_ != insn) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5464, __FUNCTION__), 0 : 0));

    if (BB_END (bb)(bb)->il.x.rtl->end_ == insn)
/* If this is last instruction in BB, move end marker one
  instruction up.  */
{
 /* Jumps are always placed at the end of basic block.  */
 jump_p = control_flow_insn_p (insn);

 gcc_assert (!jump_p((void)(!(!jump_p || ((common_sched_info->sched_pass_id ==
 SCHED_RGN_PASS) && (((&h_i_d[INSN_UID (insn)])->
recovery_block) != nullptr && ((&h_i_d[INSN_UID (
insn)])->recovery_block) != (((cfun + 0))->cfg->x_exit_block_ptr
))) || (common_sched_info->sched_pass_id == SCHED_EBB_PASS
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5477, __FUNCTION__), 0 : 0))
      || ((common_sched_info->sched_pass_id == SCHED_RGN_PASS)((void)(!(!jump_p || ((common_sched_info->sched_pass_id ==
 SCHED_RGN_PASS) && (((&h_i_d[INSN_UID (insn)])->
recovery_block) != nullptr && ((&h_i_d[INSN_UID (
insn)])->recovery_block) != (((cfun + 0))->cfg->x_exit_block_ptr
))) || (common_sched_info->sched_pass_id == SCHED_EBB_PASS
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5477, __FUNCTION__), 0 : 0))
	  && IS_SPECULATION_BRANCHY_CHECK_P (insn))((void)(!(!jump_p || ((common_sched_info->sched_pass_id ==
 SCHED_RGN_PASS) && (((&h_i_d[INSN_UID (insn)])->
recovery_block) != nullptr && ((&h_i_d[INSN_UID (
insn)])->recovery_block) != (((cfun + 0))->cfg->x_exit_block_ptr
))) || (common_sched_info->sched_pass_id == SCHED_EBB_PASS
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5477, __FUNCTION__), 0 : 0))
      || (common_sched_info->sched_pass_id((void)(!(!jump_p || ((common_sched_info->sched_pass_id ==
 SCHED_RGN_PASS) && (((&h_i_d[INSN_UID (insn)])->
recovery_block) != nullptr && ((&h_i_d[INSN_UID (
insn)])->recovery_block) != (((cfun + 0))->cfg->x_exit_block_ptr
))) || (common_sched_info->sched_pass_id == SCHED_EBB_PASS
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5477, __FUNCTION__), 0 : 0))
	  == SCHED_EBB_PASS))((void)(!(!jump_p || ((common_sched_info->sched_pass_id ==
 SCHED_RGN_PASS) && (((&h_i_d[INSN_UID (insn)])->
recovery_block) != nullptr && ((&h_i_d[INSN_UID (
insn)])->recovery_block) != (((cfun + 0))->cfg->x_exit_block_ptr
))) || (common_sched_info->sched_pass_id == SCHED_EBB_PASS
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5477, __FUNCTION__), 0 : 0));

 gcc_assert (BLOCK_FOR_INSN (PREV_INSN (insn)) == bb)((void)(!(BLOCK_FOR_INSN (PREV_INSN (insn)) == bb) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5479, __FUNCTION__), 0 : 0));

 BB_END (bb)(bb)->il.x.rtl->end_ = PREV_INSN (insn);
}

    gcc_assert (BB_END (bb) != last)((void)(!((bb)->il.x.rtl->end_ != last) ? fancy_abort (
"/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5484, __FUNCTION__), 0 : 0));

    if (jump_p)
/* We move the block note along with jump.  */
{
 gcc_assert (nt)((void)(!(nt) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5489, __FUNCTION__), 0 : 0));

 note = NEXT_INSN (insn);
 while (NOTE_NOT_BB_P (note)((((enum rtx_code) (note)->code) == NOTE) && ((((note
)->u.fld[4]).rt_int) != NOTE_INSN_BASIC_BLOCK)) && note != nt)
   note = NEXT_INSN (note);

 if (note != nt
     && (LABEL_P (note)(((enum rtx_code) (note)->code) == CODE_LABEL)
  || BARRIER_P (note)(((enum rtx_code) (note)->code) == BARRIER)))
   note = NEXT_INSN (note);

 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (note))((void)(!(((((enum rtx_code) (note)->code) == NOTE) &&
 (((note)->u.fld[4]).rt_int) == NOTE_INSN_BASIC_BLOCK)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5500, __FUNCTION__), 0 : 0));
}
    else
note = insn;

    SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (note);
    SET_PREV_INSN (NEXT_INSN (note)) = PREV_INSN (insn);

    SET_NEXT_INSN (note) = NEXT_INSN (last);
    SET_PREV_INSN (NEXT_INSN (last)) = note;

    SET_NEXT_INSN (last) = insn;
    SET_PREV_INSN (insn) = last;

    bb = BLOCK_FOR_INSN (last);

    if (jump_p)
{
 fix_jump_move (insn);

 if (BLOCK_FOR_INSN (insn) != bb)
   move_block_after_check (insn);

 gcc_assert (BB_END (bb) == last)((void)(!((bb)->il.x.rtl->end_ == last) ? fancy_abort (
"/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5523, __FUNCTION__), 0 : 0));
}

    df_insn_change_bb (insn, bb);

    /* Update BB_END, if needed.  */
    if (BB_END (bb)(bb)->il.x.rtl->end_ == last)
BB_END (bb)(bb)->il.x.rtl->end_ = insn;
  }

SCHED_GROUP_P (insn)(__extension__ ({ __typeof ((insn)) const _rtx = ((insn)); if
 (((enum rtx_code) (_rtx)->code) != DEBUG_INSN && (
(enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != JUMP_INSN && ((enum rtx_code) (
_rtx)->code) != CALL_INSN) rtl_check_failed_flag ("SCHED_GROUP_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5533, __FUNCTION__); _rtx; })->in_struct) = 0;
5534}

5536/* Return true if scheduling INSN will finish current clock cycle.  */
5537static bool
5538insn_finishes_cycle_p (rtx_insn *insn)
5539{
if (SCHED_GROUP_P (insn)(__extension__ ({ __typeof ((insn)) const _rtx = ((insn)); if
 (((enum rtx_code) (_rtx)->code) != DEBUG_INSN && (
(enum rtx_code) (_rtx)->code) != INSN && ((enum rtx_code
) (_rtx)->code) != JUMP_INSN && ((enum rtx_code) (
_rtx)->code) != CALL_INSN) rtl_check_failed_flag ("SCHED_GROUP_P"
, _rtx, "/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5540, __FUNCTION__); _rtx; })->in_struct))
  /* After issuing INSN, rest of the sched_group will be forced to issue
     in order.  Don't make any plans for the rest of cycle.  */
  return true;

/* Finishing the block will, apparently, finish the cycle.  */
if (current_sched_info->insn_finishes_block_p
    && current_sched_info->insn_finishes_block_p (insn))
  return true;

return false;
5551}

5553/* Helper for autopref_multipass_init.  Given a SET in PAT and whether
 we're expecting a memory WRITE or not, check that the insn is relevant to
 the autoprefetcher modelling code.  Return true iff that is the case.
 If it is relevant, record the base register of the memory op in BASE and
 the offset in OFFSET.  */

5559static bool
5560analyze_set_insn_for_autopref (rtx pat, bool write, rtx *base, int *offset)
5561{
if (GET_CODE (pat)((enum rtx_code) (pat)->code) != SET)
  return false;

rtx mem = write ? SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx) : SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx);
if (!MEM_P (mem)(((enum rtx_code) (mem)->code) == MEM))
  return false;

struct address_info info;
decompose_mem_address (&info, mem);

/* TODO: Currently only (base+const) addressing is supported.  */
if (info.base == NULLnullptr || !REG_P (*info.base)(((enum rtx_code) (*info.base)->code) == REG)
    || (info.disp != NULLnullptr && !CONST_INT_P (*info.disp)(((enum rtx_code) (*info.disp)->code) == CONST_INT)))
  return false;

*base = *info.base;
*offset = info.disp ? INTVAL (*info.disp)((*info.disp)->u.hwint[0]) : 0;
return true;
5580}

5582/* Functions to model cache auto-prefetcher.

 Some of the CPUs have cache auto-prefetcher, which /seems/ to initiate
 memory prefetches if it sees instructions with consequitive memory accesses
 in the instruction stream.  Details of such hardware units are not published,
 so we can only guess what exactly is going on there.
 In the scheduler, we model abstract auto-prefetcher.  If there are memory
 insns in the ready list (or the queue) that have same memory base, but
 different offsets, then we delay the insns with larger offsets until insns
 with smaller offsets get scheduled.  If PARAM_SCHED_AUTOPREF_QUEUE_DEPTH
 is "1", then we look at the ready list; if it is N>1, then we also look
 through N-1 queue entries.
 If the param is N>=0, then rank_for_schedule will consider auto-prefetching
 among its heuristics.
 Param value of "-1" disables modelling of the auto-prefetcher.  */

5598/* Initialize autoprefetcher model data for INSN.  */
5599static void
5600autopref_multipass_init (const rtx_insn *insn, int write)
5601{
autopref_multipass_data_t data = &INSN_AUTOPREF_MULTIPASS_DATA (insn)((&h_i_d[INSN_UID (insn)])->autopref_multipass_data)[write];

gcc_assert (data->status == AUTOPREF_MULTIPASS_DATA_UNINITIALIZED)((void)(!(data->status == AUTOPREF_MULTIPASS_DATA_UNINITIALIZED
) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5604, __FUNCTION__), 0 : 0));
data->base = NULL_RTX(rtx) 0;
data->offset = 0;
/* Set insn entry initialized, but not relevant for auto-prefetcher.  */
data->status = AUTOPREF_MULTIPASS_DATA_IRRELEVANT;

rtx pat = PATTERN (insn);

/* We have a multi-set insn like a load-multiple or store-multiple.
   We care about these as long as all the memory ops inside the PARALLEL
   have the same base register.  We care about the minimum and maximum
   offsets from that base but don't check for the order of those offsets
   within the PARALLEL insn itself.  */
if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
  {
    int n_elems = XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem);

    int i, offset;
    rtx base, prev_base = NULL_RTX(rtx) 0;
    int min_offset = INT_MAX2147483647;

    for (i = 0; i < n_elems; i++)
{
 rtx set = XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]);
 if (GET_CODE (set)((enum rtx_code) (set)->code) != SET)
   return;

 if (!analyze_set_insn_for_autopref (set, write, &base, &offset))
   return;

 /* Ensure that all memory operations in the PARALLEL use the same
    base register.  */
 if (i > 0 && REGNO (base)(rhs_regno(base)) != REGNO (prev_base)(rhs_regno(prev_base)))
   return;
 prev_base = base;
 min_offset = MIN (min_offset, offset)((min_offset) < (offset) ? (min_offset) : (offset));
}

    /* If we reached here then we have a valid PARALLEL of multiple memory ops
with prev_base as the base and min_offset containing the offset.  */
    gcc_assert (prev_base)((void)(!(prev_base) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5644, __FUNCTION__), 0 : 0));
    data->base = prev_base;
    data->offset = min_offset;
    data->status = AUTOPREF_MULTIPASS_DATA_NORMAL;
    return;
  }

/* Otherwise this is a single set memory operation.  */
rtx set = single_set (insn);
if (set == NULL_RTX(rtx) 0)
  return;

if (!analyze_set_insn_for_autopref (set, write, &data->base,
		       &data->offset))
  return;

/* This insn is relevant for the auto-prefetcher.
   The base and offset fields will have been filled in the
   analyze_set_insn_for_autopref call above.  */
data->status = AUTOPREF_MULTIPASS_DATA_NORMAL;
5664}

5666/* Helper function for rank_for_schedule sorting.  */
5667static int
5668autopref_rank_for_schedule (const rtx_insn *insn1, const rtx_insn *insn2)
5669{
int r = 0;
for (int write = 0; write < 2 && !r; ++write)
  {
    autopref_multipass_data_t data1
= &INSN_AUTOPREF_MULTIPASS_DATA (insn1)((&h_i_d[INSN_UID (insn1)])->autopref_multipass_data)[write];
    autopref_multipass_data_t data2
= &INSN_AUTOPREF_MULTIPASS_DATA (insn2)((&h_i_d[INSN_UID (insn2)])->autopref_multipass_data)[write];

    if (data1->status == AUTOPREF_MULTIPASS_DATA_UNINITIALIZED)
autopref_multipass_init (insn1, write);

    if (data2->status == AUTOPREF_MULTIPASS_DATA_UNINITIALIZED)
autopref_multipass_init (insn2, write);

    int irrel1 = data1->status == AUTOPREF_MULTIPASS_DATA_IRRELEVANT;
    int irrel2 = data2->status == AUTOPREF_MULTIPASS_DATA_IRRELEVANT;

    if (!irrel1 && !irrel2)
/* Sort memory references from lowest offset to the largest.  */
r = data1->offset - data2->offset;
    else if (write)
/* Schedule "irrelevant" insns before memory stores to resolve
  as many producer dependencies of stores as possible.  */
r = irrel2 - irrel1;
    else
/* Schedule "irrelevant" insns after memory reads to avoid breaking
  memory read sequences.  */
r = irrel1 - irrel2;
  }

return r;
5701}

5703/* True if header of debug dump was printed.  */
5704static bool autopref_multipass_dfa_lookahead_guard_started_dump_p;

5706/* Helper for autopref_multipass_dfa_lookahead_guard.
 Return "1" if INSN1 should be delayed in favor of INSN2.  */
5708static int
5709autopref_multipass_dfa_lookahead_guard_1 (const rtx_insn *insn1,
			  const rtx_insn *insn2, int write)
5711{
autopref_multipass_data_t data1
  = &INSN_AUTOPREF_MULTIPASS_DATA (insn1)((&h_i_d[INSN_UID (insn1)])->autopref_multipass_data)[write];
autopref_multipass_data_t data2
  = &INSN_AUTOPREF_MULTIPASS_DATA (insn2)((&h_i_d[INSN_UID (insn2)])->autopref_multipass_data)[write];

if (data2->status == AUTOPREF_MULTIPASS_DATA_UNINITIALIZED)
  autopref_multipass_init (insn2, write);
if (data2->status == AUTOPREF_MULTIPASS_DATA_IRRELEVANT)
  return 0;

if (rtx_equal_p (data1->base, data2->base)
    && data1->offset > data2->offset)
  {
    if (sched_verbose >= 2)
{
        if (!autopref_multipass_dfa_lookahead_guard_started_dump_p)
   {
     fprintf (sched_dump,
       ";;\t\tnot trying in max_issue due to autoprefetch "
       "model: ");
     autopref_multipass_dfa_lookahead_guard_started_dump_p = true;
   }

 fprintf (sched_dump, " %d(%d)", INSN_UID (insn1), INSN_UID (insn2));
}

    return 1;
  }

return 0;
5742}

5744/* General note:

 We could have also hooked autoprefetcher model into
 first_cycle_multipass_backtrack / first_cycle_multipass_issue hooks
 to enable intelligent selection of "[r1+0]=r2; [r1+4]=r3" on the same cycle
 (e.g., once "[r1+0]=r2" is issued in max_issue(), "[r1+4]=r3" gets
 unblocked).  We don't bother about this yet because target of interest
 (ARM Cortex-A15) can issue only 1 memory operation per cycle.  */

5753/* Implementation of first_cycle_multipass_dfa_lookahead_guard hook.
 Return "1" if INSN1 should not be considered in max_issue due to
 auto-prefetcher considerations.  */
5756int
5757autopref_multipass_dfa_lookahead_guard (rtx_insn *insn1, int ready_index)
5758{
int r = 0;

/* Exit early if the param forbids this or if we're not entering here through
   normal haifa scheduling.  This can happen if selective scheduling is
   explicitly enabled.  */
if (!insn_queue || param_sched_autopref_queue_depthglobal_options.x_param_sched_autopref_queue_depth <= 0)
  return 0;

if (sched_verbose >= 2 && ready_index == 0)
  autopref_multipass_dfa_lookahead_guard_started_dump_p = false;

for (int write = 0; write < 2; ++write)
  {
    autopref_multipass_data_t data1
= &INSN_AUTOPREF_MULTIPASS_DATA (insn1)((&h_i_d[INSN_UID (insn1)])->autopref_multipass_data)[write];

    if (data1->status == AUTOPREF_MULTIPASS_DATA_UNINITIALIZED)
autopref_multipass_init (insn1, write);
    if (data1->status == AUTOPREF_MULTIPASS_DATA_IRRELEVANT)
continue;

    if (ready_index == 0
 && data1->status == AUTOPREF_MULTIPASS_DATA_DONT_DELAY)
/* We allow only a single delay on priviledged instructions.
  Doing otherwise would cause infinite loop.  */
{
 if (sched_verbose >= 2)
   {
     if (!autopref_multipass_dfa_lookahead_guard_started_dump_p)
{
  fprintf (sched_dump,
	   ";;\t\tnot trying in max_issue due to autoprefetch "
	   "model: ");
  autopref_multipass_dfa_lookahead_guard_started_dump_p = true;
}

     fprintf (sched_dump, " *%d*", INSN_UID (insn1));
   }
 continue;
}

    for (int i2 = 0; i2 < ready.n_ready; ++i2)
{
 rtx_insn *insn2 = get_ready_element (i2);
 if (insn1 == insn2)
   continue;
 r = autopref_multipass_dfa_lookahead_guard_1 (insn1, insn2, write);
 if (r)
   {
     if (ready_index == 0)
{
  r = -1;
  data1->status = AUTOPREF_MULTIPASS_DATA_DONT_DELAY;
}
     goto finish;
   }
}

    if (param_sched_autopref_queue_depthglobal_options.x_param_sched_autopref_queue_depth == 1)
continue;

    /* Everything from the current queue slot should have been moved to
the ready list.  */
    gcc_assert (insn_queue[NEXT_Q_AFTER (q_ptr, 0)] == NULL_RTX)((void)(!(insn_queue[(((q_ptr)+0) & max_insn_queue_index)
] == (rtx) 0) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/haifa-sched.cc"
, 5822, __FUNCTION__), 0 : 0));

    int n_stalls = param_sched_autopref_queue_depthglobal_options.x_param_sched_autopref_queue_depth - 1;
    if (n_stalls > max_insn_queue_index)
n_stalls = max_insn_queue_index;

    for (int stalls = 1; stalls <= n_stalls; ++stalls)
{
 for (rtx_insn_list *link = insn_queue[NEXT_Q_AFTER (q_ptr, stalls)(((q_ptr)+stalls) & max_insn_queue_index)];
      link != NULL_RTX(rtx) 0;
      link = link->next ())
   {
     rtx_insn *insn2 = link->insn ();
     r = autopref_multipass_dfa_lookahead_guard_1 (insn1, insn2,
					    write);
     if (r)
{
  /* Queue INSN1 until INSN2 can issue.  */
  r = -stalls;