/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc

Bug Summary

File:	build/gcc/loop-iv.cc
Warning:	line 517, column 19 The left operand of '==' is a garbage value
Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-suse-linux -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name loop-iv.cc -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -resource-dir /usr/lib64/clang/15.0.7 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../include/c++/13/backward -internal-isystem /usr/lib64/clang/15.0.7/include -internal-isystem /usr/local/include -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/13/../../../../x86_64-suse-linux/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir=/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2023-03-27-141847-20772-1/report-XW2GA9.plist -x c++ /buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc
1/* Rtl-level induction variable analysis.
 Copyright (C) 2004-2023 Free Software Foundation, Inc.

4This file is part of GCC.

6GCC is free software; you can redistribute it and/or modify it
7under the terms of the GNU General Public License as published by the
8Free Software Foundation; either version 3, or (at your option) any
9later version.

11GCC is distributed in the hope that it will be useful, but WITHOUT
12ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14for more details.

16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3.  If not see
18<http://www.gnu.org/licenses/>.  */

20/* This is a simple analysis of induction variables of the loop.  The major use
 is for determining the number of iterations of a loop for loop unrolling,
 doloop optimization and branch prediction.  The iv information is computed
 on demand.

 Induction variables are analyzed by walking the use-def chains.  When
 a basic induction variable (biv) is found, it is cached in the bivs
 hash table.  When register is proved to be a biv, its description
 is stored to DF_REF_DATA of the def reference.

 The analysis works always with one loop -- you must call
 iv_analysis_loop_init (loop) for it.  All the other functions then work with
 this loop.   When you need to work with another loop, just call
 iv_analysis_loop_init for it.  When you no longer need iv analysis, call
 iv_analysis_done () to clean up the memory.

 The available functions are:

 iv_analyze (insn, mode, reg, iv): Stores the description of the induction
   variable corresponding to the use of register REG in INSN to IV, given
   that REG has mode MODE.  Returns true if REG is an induction variable
   in INSN. false otherwise.  If a use of REG is not found in INSN,
   the following insns are scanned (so that we may call this function
   on insns returned by get_condition).
 iv_analyze_result (insn, def, iv):  Stores to IV the description of the iv
   corresponding to DEF, which is a register defined in INSN.
 iv_analyze_expr (insn, mode, expr, iv):  Stores to IV the description of iv
   corresponding to expression EXPR evaluated at INSN.  All registers used by
   EXPR must also be used in INSN.  MODE is the mode of EXPR.
49*/

51#include "config.h"
52#include "system.h"
53#include "coretypes.h"
54#include "backend.h"
55#include "rtl.h"
56#include "df.h"
57#include "memmodel.h"
58#include "emit-rtl.h"
59#include "diagnostic-core.h"
60#include "cfgloop.h"
61#include "intl.h"
62#include "dumpfile.h"
63#include "rtl-iter.h"
64#include "tree-ssa-loop-niter.h"
65#include "regs.h"
66#include "function-abi.h"

68/* Possible return values of iv_get_reaching_def.  */

70enum iv_grd_result
71{
/* More than one reaching def, or reaching def that does not
   dominate the use.  */
GRD_INVALID,

/* The use is trivial invariant of the loop, i.e. is not changed
   inside the loop.  */
GRD_INVARIANT,

/* The use is reached by initial value and a value from the
   previous iteration.  */
GRD_MAYBE_BIV,

/* The use has single dominating def.  */
GRD_SINGLE_DOM
86};

88/* Information about a biv.  */

90class biv_entry
91{
92public:
unsigned regno;	/* The register of the biv.  */
class rtx_iv iv;	/* Value of the biv.  */
95};

97static bool clean_slate = true;

99static unsigned int iv_ref_table_size = 0;

101/* Table of rtx_ivs indexed by the df_ref uid field.  */
102static class rtx_iv ** iv_ref_table;

104/* Induction variable stored at the reference.  */
105#define DF_REF_IV(REF)iv_ref_table[((REF)->base.id)] iv_ref_table[DF_REF_ID (REF)((REF)->base.id)]
106#define DF_REF_IV_SET(REF, IV)iv_ref_table[((REF)->base.id)] = (IV) iv_ref_table[DF_REF_ID (REF)((REF)->base.id)] = (IV)

108/* The current loop.  */

110static class loop *current_loop;

112/* Hashtable helper.  */

114struct biv_entry_hasher : free_ptr_hash <biv_entry>
115{
typedef rtx_def *compare_type;
static inline hashval_t hash (const biv_entry *);
static inline bool equal (const biv_entry *, const rtx_def *);
119};

121/* Returns hash value for biv B.  */

123inline hashval_t
124biv_entry_hasher::hash (const biv_entry *b)
125{
return b->regno;
127}

129/* Compares biv B and register R.  */

131inline bool
132biv_entry_hasher::equal (const biv_entry *b, const rtx_def *r)
133{
return b->regno == REGNO (r)(rhs_regno(r));
135}

137/* Bivs of the current loop.  */

139static hash_table<biv_entry_hasher> *bivs;

141static bool iv_analyze_op (rtx_insn *, scalar_int_mode, rtx, class rtx_iv *);

143/* Return the RTX code corresponding to the IV extend code EXTEND.  */
144static inline enum rtx_code
145iv_extend_to_rtx_code (enum iv_extend_code extend)
146{
switch (extend)
  {
  case IV_SIGN_EXTEND:
    return SIGN_EXTEND;
  case IV_ZERO_EXTEND:
    return ZERO_EXTEND;
  case IV_UNKNOWN_EXTEND:
    return UNKNOWN;
  }
gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 156, __FUNCTION__));
157}

159/* Dumps information about IV to FILE.  */

161extern void dump_iv_info (FILE *, class rtx_iv *);
162void
163dump_iv_info (FILE *file, class rtx_iv *iv)
164{
if (!iv->base)
  {
    fprintf (file, "not simple");
    return;
  }

if (iv->step == const0_rtx(const_int_rtx[64])
    && !iv->first_special)
  fprintf (file, "invariant ");

print_rtl (file, iv->base);
if (iv->step != const0_rtx(const_int_rtx[64]))
  {
    fprintf (file, " + ");
    print_rtl (file, iv->step);
    fprintf (file, " * iteration");
  }
fprintf (file, " (in %s)", GET_MODE_NAME (iv->mode)mode_name[iv->mode]);

if (iv->mode != iv->extend_mode)
  fprintf (file, " %s to %s",
    rtx_name[iv_extend_to_rtx_code (iv->extend)],
    GET_MODE_NAME (iv->extend_mode)mode_name[iv->extend_mode]);

if (iv->mult != const1_rtx(const_int_rtx[64 +1]))
  {
    fprintf (file, " * ");
    print_rtl (file, iv->mult);
  }
if (iv->delta != const0_rtx(const_int_rtx[64]))
  {
    fprintf (file, " + ");
    print_rtl (file, iv->delta);
  }
if (iv->first_special)
  fprintf (file, " (first special)");
201}

203static void
204check_iv_ref_table_size (void)
205{
if (iv_ref_table_size < DF_DEFS_TABLE_SIZE ()(df->def_info.table_size))
  {
    unsigned int new_size = DF_DEFS_TABLE_SIZE ()(df->def_info.table_size) + (DF_DEFS_TABLE_SIZE ()(df->def_info.table_size) / 4);
    iv_ref_table = XRESIZEVEC (class rtx_iv *, iv_ref_table, new_size)((class rtx_iv * *) xrealloc ((void *) (iv_ref_table), sizeof
 (class rtx_iv *) * (new_size)));
    memset (&iv_ref_table[iv_ref_table_size], 0,
     (new_size - iv_ref_table_size) * sizeof (class rtx_iv *));
    iv_ref_table_size = new_size;
  }
214}


217/* Checks whether REG is a well-behaved register.  */

219static bool
220simple_reg_p (rtx reg)
221{
unsigned r;

if (GET_CODE (reg)((enum rtx_code) (reg)->code) == SUBREG)
  {
    if (!subreg_lowpart_p (reg))
return false;
    reg = SUBREG_REG (reg)(((reg)->u.fld[0]).rt_rtx);
  }

if (!REG_P (reg)(((enum rtx_code) (reg)->code) == REG))
  return false;

r = REGNO (reg)(rhs_regno(reg));
if (HARD_REGISTER_NUM_P (r)((r) < 76))
  return false;

if (GET_MODE_CLASS (GET_MODE (reg))((enum mode_class) mode_class[((machine_mode) (reg)->mode)
]) != MODE_INT)
  return false;

return true;
242}

244/* Clears the information about ivs stored in df.  */

246static void
247clear_iv_info (void)
248{
unsigned i, n_defs = DF_DEFS_TABLE_SIZE ()(df->def_info.table_size);
class rtx_iv *iv;

check_iv_ref_table_size ();
for (i = 0; i < n_defs; i++)
  {
    iv = iv_ref_table[i];
    if (iv)
{
 free (iv);
 iv_ref_table[i] = NULL__null;
}
  }

bivs->empty ();
264}


267/* Prepare the data for an induction variable analysis of a LOOP.  */

269void
270iv_analysis_loop_init (class loop *loop)
271{
current_loop = loop;

/* Clear the information from the analysis of the previous loop.  */
if (clean_slate)
  {
    df_set_flags (DF_EQ_NOTES + DF_DEFER_INSN_RESCAN);
    bivs = new hash_table<biv_entry_hasher> (10);
    clean_slate = false;
  }
else
  clear_iv_info ();

/* Get rid of the ud chains before processing the rescans.  Then add
   the problem back.  */
df_remove_problem (df_chain(df->problems_by_index[DF_CHAIN]));
df_process_deferred_rescans ();
df_set_flags (DF_RD_PRUNE_DEAD_DEFS);
df_chain_add_problem (DF_UD_CHAIN);
df_note_add_problem ();
df_analyze_loop (loop);
if (dump_file)
  df_dump_region (dump_file);

check_iv_ref_table_size ();
296}

298/* Finds the definition of REG that dominates loop latch and stores
 it to DEF.  Returns false if there is not a single definition
 dominating the latch.  If REG has no definition in loop, DEF
 is set to NULL and true is returned.  */

303static bool
304latch_dominating_def (rtx reg, df_ref *def)
305{
df_ref single_rd = NULL__null, adef;
unsigned regno = REGNO (reg)(rhs_regno(reg));
class df_rd_bb_info *bb_info = DF_RD_BB_INFO (current_loop->latch)(df_rd_get_bb_info ((current_loop->latch)->index));

for (adef = DF_REG_DEF_CHAIN (regno)(df->def_regs[(regno)]->reg_chain); adef; adef = DF_REF_NEXT_REG (adef)((adef)->base.next_reg))
  {
    if (!bitmap_bit_p (df->blocks_to_analyze, DF_REF_BBNO (adef)(((((adef)->base.cl) == DF_REF_ARTIFICIAL) ? (adef)->artificial_ref
.bb : BLOCK_FOR_INSN (((adef)->base.insn_info->insn)))->
index))
 || !bitmap_bit_p (&bb_info->out, DF_REF_ID (adef)((adef)->base.id)))
continue;

    /* More than one reaching definition.  */
    if (single_rd)
return false;

    if (!just_once_each_iteration_p (current_loop, DF_REF_BB (adef)((((adef)->base.cl) == DF_REF_ARTIFICIAL) ? (adef)->artificial_ref
.bb : BLOCK_FOR_INSN (((adef)->base.insn_info->insn)))))
return false;

    single_rd = adef;
  }

*def = single_rd;
return true;
328}

330/* Gets definition of REG reaching its use in INSN and stores it to DEF.  */

332static enum iv_grd_result
333iv_get_reaching_def (rtx_insn *insn, rtx reg, df_ref *def)
334{
df_ref use, adef;
basic_block def_bb, use_bb;
rtx_insn *def_insn;
bool dom_p;

*def = NULL__null;
if (!simple_reg_p (reg))
  return GRD_INVALID;
if (GET_CODE (reg)((enum rtx_code) (reg)->code) == SUBREG)
  reg = SUBREG_REG (reg)(((reg)->u.fld[0]).rt_rtx);
gcc_assert (REG_P (reg))((void)(!((((enum rtx_code) (reg)->code) == REG)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 345, __FUNCTION__), 0 : 0));

use = df_find_use (insn, reg);
gcc_assert (use != NULL)((void)(!(use != __null) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 348, __FUNCTION__), 0 : 0));

if (!DF_REF_CHAIN (use)((use)->base.chain))
  return GRD_INVARIANT;

/* More than one reaching def.  */
if (DF_REF_CHAIN (use)((use)->base.chain)->next)
  return GRD_INVALID;

adef = DF_REF_CHAIN (use)((use)->base.chain)->ref;

/* We do not handle setting only part of the register.  */
if (DF_REF_FLAGS (adef)((adef)->base.flags) & DF_REF_READ_WRITE)
  return GRD_INVALID;

def_insn = DF_REF_INSN (adef)((adef)->base.insn_info->insn);
def_bb = DF_REF_BB (adef)((((adef)->base.cl) == DF_REF_ARTIFICIAL) ? (adef)->artificial_ref
.bb : BLOCK_FOR_INSN (((adef)->base.insn_info->insn)));
use_bb = BLOCK_FOR_INSN (insn);

if (use_bb == def_bb)
  dom_p = (DF_INSN_LUID (def_insn)((((df->insns[(INSN_UID (def_insn))]))->luid)) < DF_INSN_LUID (insn)((((df->insns[(INSN_UID (insn))]))->luid)));
else
  dom_p = dominated_by_p (CDI_DOMINATORS, use_bb, def_bb);

if (dom_p)
  {
    *def = adef;
    return GRD_SINGLE_DOM;
  }

/* The definition does not dominate the use.  This is still OK if
   this may be a use of a biv, i.e. if the def_bb dominates loop
   latch.  */
if (just_once_each_iteration_p (current_loop, def_bb))
  return GRD_MAYBE_BIV;

return GRD_INVALID;
385}

387/* Sets IV to invariant CST in MODE.  Always returns true (just for
 consistency with other iv manipulation functions that may fail).  */

390static bool
391iv_constant (class rtx_iv *iv, scalar_int_mode mode, rtx cst)
392{
iv->mode = mode;
iv->base = cst;
iv->step = const0_rtx(const_int_rtx[64]);
iv->first_special = false;
iv->extend = IV_UNKNOWN_EXTEND;
iv->extend_mode = iv->mode;
iv->delta = const0_rtx(const_int_rtx[64]);
iv->mult = const1_rtx(const_int_rtx[64 +1]);

return true;
403}

405/* Evaluates application of subreg to MODE on IV.  */

407static bool
408iv_subreg (class rtx_iv *iv, scalar_int_mode mode)
409{
/* If iv is invariant, just calculate the new value.  */
if (iv->step == const0_rtx(const_int_rtx[64])
    && !iv->first_special)
  {
    rtx val = get_iv_value (iv, const0_rtx(const_int_rtx[64]));
    val = lowpart_subreg (mode, val,
	    iv->extend == IV_UNKNOWN_EXTEND
	    ? iv->mode : iv->extend_mode);

    iv->base = val;
    iv->extend = IV_UNKNOWN_EXTEND;
    iv->mode = iv->extend_mode = mode;
    iv->delta = const0_rtx(const_int_rtx[64]);
    iv->mult = const1_rtx(const_int_rtx[64 +1]);
    return true;
  }

if (iv->extend_mode == mode)
  return true;

if (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (iv->mode))
  return false;

iv->extend = IV_UNKNOWN_EXTEND;
iv->mode = mode;

iv->base = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta,
		  simplify_gen_binary (MULT, iv->extend_mode,
				       iv->base, iv->mult));
iv->step = simplify_gen_binary (MULT, iv->extend_mode, iv->step, iv->mult);
iv->mult = const1_rtx(const_int_rtx[64 +1]);
iv->delta = const0_rtx(const_int_rtx[64]);
iv->first_special = false;

return true;
445}

447/* Evaluates application of EXTEND to MODE on IV.  */

449static bool
450iv_extend (class rtx_iv *iv, enum iv_extend_code extend, scalar_int_mode mode)
451{
/* If iv is invariant, just calculate the new value.  */
if (iv->step == const0_rtx(const_int_rtx[64])
    && !iv->first_special)
  {
    rtx val = get_iv_value (iv, const0_rtx(const_int_rtx[64]));
    if (iv->extend_mode != iv->mode
 && iv->extend != IV_UNKNOWN_EXTEND
 && iv->extend != extend)
val = lowpart_subreg (iv->mode, val, iv->extend_mode);
    val = simplify_gen_unary (iv_extend_to_rtx_code (extend), mode,
		val,
		iv->extend == extend
		? iv->extend_mode : iv->mode);
    iv->base = val;
    iv->extend = IV_UNKNOWN_EXTEND;
    iv->mode = iv->extend_mode = mode;
    iv->delta = const0_rtx(const_int_rtx[64]);
    iv->mult = const1_rtx(const_int_rtx[64 +1]);
    return true;
  }

if (mode != iv->extend_mode)
  return false;

if (iv->extend != IV_UNKNOWN_EXTEND
    && iv->extend != extend)
  return false;

iv->extend = extend;

return true;
483}

485/* Evaluates negation of IV.  */

487static bool
488iv_neg (class rtx_iv *iv)
489{
if (iv->extend == IV_UNKNOWN_EXTEND)
  {
    iv->base = simplify_gen_unary (NEG, iv->extend_mode,
		     iv->base, iv->extend_mode);
    iv->step = simplify_gen_unary (NEG, iv->extend_mode,
		     iv->step, iv->extend_mode);
  }
else
  {
    iv->delta = simplify_gen_unary (NEG, iv->extend_mode,
		      iv->delta, iv->extend_mode);
    iv->mult = simplify_gen_unary (NEG, iv->extend_mode,
		     iv->mult, iv->extend_mode);
  }

return true;
506}

508/* Evaluates addition or subtraction (according to OP) of IV1 to IV0.  */

510static bool
511iv_add (class rtx_iv *iv0, class rtx_iv *iv1, enum rtx_code op)
512{
scalar_int_mode mode;
rtx arg;

/* Extend the constant to extend_mode of the other operand if necessary.  */
if (iv0->extend == IV_UNKNOWN_EXTEND
30
←
The left operand of '==' is a garbage value
    && iv0->mode == iv0->extend_mode
    && iv0->step == const0_rtx(const_int_rtx[64])
    && GET_MODE_SIZE (iv0->extend_mode) < GET_MODE_SIZE (iv1->extend_mode))
  {
    iv0->extend_mode = iv1->extend_mode;
    iv0->base = simplify_gen_unary (ZERO_EXTEND, iv0->extend_mode,
		      iv0->base, iv0->mode);
  }
if (iv1->extend == IV_UNKNOWN_EXTEND
    && iv1->mode == iv1->extend_mode
    && iv1->step == const0_rtx(const_int_rtx[64])
    && GET_MODE_SIZE (iv1->extend_mode) < GET_MODE_SIZE (iv0->extend_mode))
  {
    iv1->extend_mode = iv0->extend_mode;
    iv1->base = simplify_gen_unary (ZERO_EXTEND, iv1->extend_mode,
		      iv1->base, iv1->mode);
  }

mode = iv0->extend_mode;
if (mode != iv1->extend_mode)
  return false;

if (iv0->extend == IV_UNKNOWN_EXTEND
    && iv1->extend == IV_UNKNOWN_EXTEND)
  {
    if (iv0->mode != iv1->mode)
return false;

    iv0->base = simplify_gen_binary (op, mode, iv0->base, iv1->base);
    iv0->step = simplify_gen_binary (op, mode, iv0->step, iv1->step);

    return true;
  }

/* Handle addition of constant.  */
if (iv1->extend == IV_UNKNOWN_EXTEND
    && iv1->mode == mode
    && iv1->step == const0_rtx(const_int_rtx[64]))
  {
    iv0->delta = simplify_gen_binary (op, mode, iv0->delta, iv1->base);
    return true;
  }

if (iv0->extend == IV_UNKNOWN_EXTEND
    && iv0->mode == mode
    && iv0->step == const0_rtx(const_int_rtx[64]))
  {
    arg = iv0->base;
    *iv0 = *iv1;
    if (op == MINUS
 && !iv_neg (iv0))
return false;

    iv0->delta = simplify_gen_binary (PLUS, mode, iv0->delta, arg);
    return true;
  }

return false;
576}

578/* Evaluates multiplication of IV by constant CST.  */

580static bool
581iv_mult (class rtx_iv *iv, rtx mby)
582{
scalar_int_mode mode = iv->extend_mode;

if (GET_MODE (mby)((machine_mode) (mby)->mode) != VOIDmode((void) 0, E_VOIDmode)
    && GET_MODE (mby)((machine_mode) (mby)->mode) != mode)
  return false;

if (iv->extend == IV_UNKNOWN_EXTEND)
  {
    iv->base = simplify_gen_binary (MULT, mode, iv->base, mby);
    iv->step = simplify_gen_binary (MULT, mode, iv->step, mby);
  }
else
  {
    iv->delta = simplify_gen_binary (MULT, mode, iv->delta, mby);
    iv->mult = simplify_gen_binary (MULT, mode, iv->mult, mby);
  }

return true;
601}

603/* Evaluates shift of IV by constant CST.  */

605static bool
606iv_shift (class rtx_iv *iv, rtx mby)
607{
scalar_int_mode mode = iv->extend_mode;

if (GET_MODE (mby)((machine_mode) (mby)->mode) != VOIDmode((void) 0, E_VOIDmode)
    && GET_MODE (mby)((machine_mode) (mby)->mode) != mode)
  return false;

if (iv->extend == IV_UNKNOWN_EXTEND)
  {
    iv->base = simplify_gen_binary (ASHIFT, mode, iv->base, mby);
    iv->step = simplify_gen_binary (ASHIFT, mode, iv->step, mby);
  }
else
  {
    iv->delta = simplify_gen_binary (ASHIFT, mode, iv->delta, mby);
    iv->mult = simplify_gen_binary (ASHIFT, mode, iv->mult, mby);
  }

return true;
626}

628/* The recursive part of get_biv_step.  Gets the value of the single value
 defined by DEF wrto initial value of REG inside loop, in shape described
 at get_biv_step.  */

632static bool
633get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
rtx *inner_step, scalar_int_mode *inner_mode,
enum iv_extend_code *extend,
rtx *outer_step)
637{
rtx set, rhs, op0 = NULL_RTX(rtx) 0, op1 = NULL_RTX(rtx) 0;
rtx next, nextr;
enum rtx_code code;
rtx_insn *insn = DF_REF_INSN (def)((def)->base.insn_info->insn);
df_ref next_def;
enum iv_grd_result res;

set = single_set (insn);
if (!set)
  return false;

rhs = find_reg_equal_equiv_note (insn);
if (rhs)
  rhs = XEXP (rhs, 0)(((rhs)->u.fld[0]).rt_rtx);
else
  rhs = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);

code = GET_CODE (rhs)((enum rtx_code) (rhs)->code);
switch (code)
  {
  case SUBREG:
  case REG:
    next = rhs;
    break;

  case PLUS:
  case MINUS:
    op0 = XEXP (rhs, 0)(((rhs)->u.fld[0]).rt_rtx);
    op1 = XEXP (rhs, 1)(((rhs)->u.fld[1]).rt_rtx);

    if (code == PLUS && CONSTANT_P (op0)((rtx_class[(int) (((enum rtx_code) (op0)->code))]) == RTX_CONST_OBJ
))
std::swap (op0, op1);

    if (!simple_reg_p (op0)
 || !CONSTANT_P (op1)((rtx_class[(int) (((enum rtx_code) (op1)->code))]) == RTX_CONST_OBJ
))
return false;

    if (GET_MODE (rhs)((machine_mode) (rhs)->mode) != outer_mode)
{
 /* ppc64 uses expressions like

    (set x:SI (plus:SI (subreg:SI y:DI) 1)).

    this is equivalent to

    (set x':DI (plus:DI y:DI 1))
    (set x:SI (subreg:SI (x':DI)).  */
 if (GET_CODE (op0)((enum rtx_code) (op0)->code) != SUBREG)
   return false;
 if (GET_MODE (SUBREG_REG (op0))((machine_mode) ((((op0)->u.fld[0]).rt_rtx))->mode) != outer_mode)
   return false;
}

    next = op0;
    break;

  case SIGN_EXTEND:
  case ZERO_EXTEND:
    if (GET_MODE (rhs)((machine_mode) (rhs)->mode) != outer_mode)
return false;

    op0 = XEXP (rhs, 0)(((rhs)->u.fld[0]).rt_rtx);
    if (!simple_reg_p (op0))
return false;

    next = op0;
    break;

  default:
    return false;
  }

if (GET_CODE (next)((enum rtx_code) (next)->code) == SUBREG)
  {
    if (!subreg_lowpart_p (next))
return false;

    nextr = SUBREG_REG (next)(((next)->u.fld[0]).rt_rtx);
    if (GET_MODE (nextr)((machine_mode) (nextr)->mode) != outer_mode)
return false;
  }
else
  nextr = next;

res = iv_get_reaching_def (insn, nextr, &next_def);

if (res == GRD_INVALID || res == GRD_INVARIANT)
  return false;

if (res == GRD_MAYBE_BIV)
  {
    if (!rtx_equal_p (nextr, reg))
return false;

    *inner_step = const0_rtx(const_int_rtx[64]);
    *extend = IV_UNKNOWN_EXTEND;
    *inner_mode = outer_mode;
    *outer_step = const0_rtx(const_int_rtx[64]);
  }
else if (!get_biv_step_1 (next_def, outer_mode, reg,
	    inner_step, inner_mode, extend,
	    outer_step))
  return false;

if (GET_CODE (next)((enum rtx_code) (next)->code) == SUBREG)
  {
    scalar_int_mode amode;
    if (!is_a <scalar_int_mode> (GET_MODE (next)((machine_mode) (next)->mode), &amode)
 || GET_MODE_SIZE (amode) > GET_MODE_SIZE (*inner_mode))
return false;

    *inner_mode = amode;
    *inner_step = simplify_gen_binary (PLUS, outer_mode,
			 *inner_step, *outer_step);
    *outer_step = const0_rtx(const_int_rtx[64]);
    *extend = IV_UNKNOWN_EXTEND;
  }

switch (code)
  {
  case REG:
  case SUBREG:
    break;

  case PLUS:
  case MINUS:
    if (*inner_mode == outer_mode
 /* See comment in previous switch.  */
 || GET_MODE (rhs)((machine_mode) (rhs)->mode) != outer_mode)
*inner_step = simplify_gen_binary (code, outer_mode,
			   *inner_step, op1);
    else
*outer_step = simplify_gen_binary (code, outer_mode,
			   *outer_step, op1);
    break;

  case SIGN_EXTEND:
  case ZERO_EXTEND:
    gcc_assert (GET_MODE (op0) == *inner_mode((void)(!(((machine_mode) (op0)->mode) == *inner_mode &&
 *extend == IV_UNKNOWN_EXTEND && *outer_step == (const_int_rtx
[64])) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 778, __FUNCTION__), 0 : 0))
  && *extend == IV_UNKNOWN_EXTEND((void)(!(((machine_mode) (op0)->mode) == *inner_mode &&
 *extend == IV_UNKNOWN_EXTEND && *outer_step == (const_int_rtx
[64])) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 778, __FUNCTION__), 0 : 0))
  && *outer_step == const0_rtx)((void)(!(((machine_mode) (op0)->mode) == *inner_mode &&
 *extend == IV_UNKNOWN_EXTEND && *outer_step == (const_int_rtx
[64])) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 778, __FUNCTION__), 0 : 0));

    *extend = (code == SIGN_EXTEND) ? IV_SIGN_EXTEND : IV_ZERO_EXTEND;
    break;

  default:
    return false;
  }

return true;
788}

790/* Gets the operation on register REG inside loop, in shape

 OUTER_STEP + EXTEND_{OUTER_MODE} (SUBREG_{INNER_MODE} (REG + INNER_STEP))

 If the operation cannot be described in this shape, return false.
 LAST_DEF is the definition of REG that dominates loop latch.  */

797static bool
798get_biv_step (df_ref last_def, scalar_int_mode outer_mode, rtx reg,
     rtx *inner_step, scalar_int_mode *inner_mode,
     enum iv_extend_code *extend, rtx *outer_step)
801{
if (!get_biv_step_1 (last_def, outer_mode, reg,
       inner_step, inner_mode, extend,
       outer_step))
  return false;

gcc_assert ((*inner_mode == outer_mode) != (*extend != IV_UNKNOWN_EXTEND))((void)(!((*inner_mode == outer_mode) != (*extend != IV_UNKNOWN_EXTEND
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 807, __FUNCTION__), 0 : 0));
gcc_assert (*inner_mode != outer_mode || *outer_step == const0_rtx)((void)(!(*inner_mode != outer_mode || *outer_step == (const_int_rtx
[64])) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 808, __FUNCTION__), 0 : 0));

return true;
811}

813/* Records information that DEF is induction variable IV.  */

815static void
816record_iv (df_ref def, class rtx_iv *iv)
817{
class rtx_iv *recorded_iv = XNEW (class rtx_iv)((class rtx_iv *) xmalloc (sizeof (class rtx_iv)));

*recorded_iv = *iv;
check_iv_ref_table_size ();
DF_REF_IV_SET (def, recorded_iv)iv_ref_table[((def)->base.id)] = (recorded_iv);
823}

825/* If DEF was already analyzed for bivness, store the description of the biv to
 IV and return true.  Otherwise return false.  */

828static bool
829analyzed_for_bivness_p (rtx def, class rtx_iv *iv)
830{
class biv_entry *biv = bivs->find_with_hash (def, REGNO (def)(rhs_regno(def)));

if (!biv)
  return false;

*iv = biv->iv;
return true;
838}

840static void
841record_biv (rtx def, class rtx_iv *iv)
842{
class biv_entry *biv = XNEW (class biv_entry)((class biv_entry *) xmalloc (sizeof (class biv_entry)));
biv_entry **slot = bivs->find_slot_with_hash (def, REGNO (def)(rhs_regno(def)), INSERT);

biv->regno = REGNO (def)(rhs_regno(def));
biv->iv = *iv;
gcc_assert (!*slot)((void)(!(!*slot) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 848, __FUNCTION__), 0 : 0));
*slot = biv;
850}

852/* Determines whether DEF is a biv and if so, stores its description
 to *IV.  OUTER_MODE is the mode of DEF.  */

855static bool
856iv_analyze_biv (scalar_int_mode outer_mode, rtx def, class rtx_iv *iv)
857{
rtx inner_step, outer_step;
scalar_int_mode inner_mode;
enum iv_extend_code extend;
df_ref last_def;

if (dump_file)
  {
    fprintf (dump_file, "Analyzing ");
    print_rtl (dump_file, def);
    fprintf (dump_file, " for bivness.\n");
  }

if (!REG_P (def)(((enum rtx_code) (def)->code) == REG))
  {
    if (!CONSTANT_P (def)((rtx_class[(int) (((enum rtx_code) (def)->code))]) == RTX_CONST_OBJ
))
return false;

    return iv_constant (iv, outer_mode, def);
  }

if (!latch_dominating_def (def, &last_def))
  {
    if (dump_file)
fprintf (dump_file, "  not simple.\n");
    return false;
  }

if (!last_def)
  return iv_constant (iv, outer_mode, def);

if (analyzed_for_bivness_p (def, iv))
  {
    if (dump_file)
fprintf (dump_file, "  already analysed.\n");
    return iv->base != NULL_RTX(rtx) 0;
  }

if (!get_biv_step (last_def, outer_mode, def, &inner_step, &inner_mode,
     &extend, &outer_step))
  {
    iv->base = NULL_RTX(rtx) 0;
    goto end;
  }

/* Loop transforms base to es (base + inner_step) + outer_step,
   where es means extend of subreg between inner_mode and outer_mode.
   The corresponding induction variable is

   es ((base - outer_step) + i * (inner_step + outer_step)) + outer_step  */

iv->base = simplify_gen_binary (MINUS, outer_mode, def, outer_step);
iv->step = simplify_gen_binary (PLUS, outer_mode, inner_step, outer_step);
iv->mode = inner_mode;
iv->extend_mode = outer_mode;
iv->extend = extend;
iv->mult = const1_rtx(const_int_rtx[64 +1]);
iv->delta = outer_step;
iv->first_special = inner_mode != outer_mode;

end:
if (dump_file)
  {
    fprintf (dump_file, "  ");
    dump_iv_info (dump_file, iv);
    fprintf (dump_file, "\n");
  }

record_biv (def, iv);
return iv->base != NULL_RTX(rtx) 0;
927}

929/* Analyzes expression RHS used at INSN and stores the result to *IV.
 The mode of the induction variable is MODE.  */

932bool
933iv_analyze_expr (rtx_insn *insn, scalar_int_mode mode, rtx rhs,
 class rtx_iv *iv)
935{
rtx mby = NULL_RTX(rtx) 0;
rtx op0 = NULL_RTX(rtx) 0, op1 = NULL_RTX(rtx) 0;
class rtx_iv iv0, iv1;
enum rtx_code code = GET_CODE (rhs)((enum rtx_code) (rhs)->code);
scalar_int_mode omode = mode;

iv->base = NULL_RTX(rtx) 0;
iv->step = NULL_RTX(rtx) 0;

gcc_assert (GET_MODE (rhs) == mode || GET_MODE (rhs) == VOIDmode)((void)(!(((machine_mode) (rhs)->mode) == mode || ((machine_mode
) (rhs)->mode) == ((void) 0, E_VOIDmode)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 945, __FUNCTION__), 0 : 0));
19
←
Assuming the condition is true→
20
←
'?' condition is false→

if (CONSTANT_P (rhs)((rtx_class[(int) (((enum rtx_code) (rhs)->code))]) == RTX_CONST_OBJ
)
21
←
Assuming the condition is false→
24
←
Taking false branch→
    || REG_P (rhs)(((enum rtx_code) (rhs)->code) == REG)
22
←
Assuming field 'code' is not equal to REG→
    || code == SUBREG)
23
←
Assuming 'code' is not equal to SUBREG→
  return iv_analyze_op (insn, mode, rhs, iv);

switch (code)
25
←
Control jumps to 'case MINUS:'  at line 968→
  {
  case REG:
    op0 = rhs;
    break;

  case SIGN_EXTEND:
  case ZERO_EXTEND:
  case NEG:
    op0 = XEXP (rhs, 0)(((rhs)->u.fld[0]).rt_rtx);
    /* We don't know how many bits there are in a sign-extended constant.  */
    if (!is_a <scalar_int_mode> (GET_MODE (op0)((machine_mode) (op0)->mode), &omode))
return false;
    break;

  case PLUS:
  case MINUS:
    op0 = XEXP (rhs, 0)(((rhs)->u.fld[0]).rt_rtx);
    op1 = XEXP (rhs, 1)(((rhs)->u.fld[1]).rt_rtx);
    break;

  case MULT:
    op0 = XEXP (rhs, 0)(((rhs)->u.fld[0]).rt_rtx);
    mby = XEXP (rhs, 1)(((rhs)->u.fld[1]).rt_rtx);
    if (!CONSTANT_P (mby)((rtx_class[(int) (((enum rtx_code) (mby)->code))]) == RTX_CONST_OBJ
))
std::swap (op0, mby);
    if (!CONSTANT_P (mby)((rtx_class[(int) (((enum rtx_code) (mby)->code))]) == RTX_CONST_OBJ
))
return false;
    break;

  case ASHIFT:
    op0 = XEXP (rhs, 0)(((rhs)->u.fld[0]).rt_rtx);
    mby = XEXP (rhs, 1)(((rhs)->u.fld[1]).rt_rtx);
    if (!CONSTANT_P (mby)((rtx_class[(int) (((enum rtx_code) (mby)->code))]) == RTX_CONST_OBJ
))
return false;
    break;

  default:
    return false;
  }

if (op0
26
←
Assuming 'op0' is null→
    && !iv_analyze_expr (insn, omode, op0, &iv0))
  return false;

if (op1
27
←
Assuming 'op1' is null→
    && !iv_analyze_expr (insn, omode, op1, &iv1))
  return false;

switch (code)
28
←
Control jumps to 'case MINUS:'  at line 1019→
  {
  case SIGN_EXTEND:
    if (!iv_extend (&iv0, IV_SIGN_EXTEND, mode))
return false;
    break;

  case ZERO_EXTEND:
    if (!iv_extend (&iv0, IV_ZERO_EXTEND, mode))
return false;
    break;

  case NEG:
    if (!iv_neg (&iv0))
return false;
    break;

  case PLUS:
  case MINUS:
    if (!iv_add (&iv0, &iv1, code))
29
←
Calling 'iv_add'→
return false;
    break;

  case MULT:
    if (!iv_mult (&iv0, mby))
return false;
    break;

  case ASHIFT:
    if (!iv_shift (&iv0, mby))
return false;
    break;

  default:
    break;
  }

*iv = iv0;
return iv->base != NULL_RTX(rtx) 0;
1040}

1042/* Analyzes iv DEF and stores the result to *IV.  */

1044static bool
1045iv_analyze_def (df_ref def, class rtx_iv *iv)
1046{
rtx_insn *insn = DF_REF_INSN (def)((def)->base.insn_info->insn);
rtx reg = DF_REF_REG (def)((def)->base.reg);
rtx set, rhs;

if (dump_file)
4
←
Assuming 'dump_file' is null→
5
←
Taking false branch→
  {
    fprintf (dump_file, "Analyzing def of ");
    print_rtl (dump_file, reg);
    fprintf (dump_file, " in insn ");
    print_rtl_single (dump_file, insn);
  }

check_iv_ref_table_size ();
if (DF_REF_IV (def)iv_ref_table[((def)->base.id)])
6
←
Assuming the condition is false→
7
←
Taking false branch→
  {
    if (dump_file)
fprintf (dump_file, "  already analysed.\n");
    *iv = *DF_REF_IV (def)iv_ref_table[((def)->base.id)];
    return iv->base != NULL_RTX(rtx) 0;
  }

iv->base = NULL_RTX(rtx) 0;
iv->step = NULL_RTX(rtx) 0;

scalar_int_mode mode;
if (!REG_P (reg)(((enum rtx_code) (reg)->code) == REG) || !is_a <scalar_int_mode> (GET_MODE (reg)((machine_mode) (reg)->mode), &mode))
8
←
Assuming field 'code' is equal to REG→
9
←
Taking false branch→
  return false;

set = single_set (insn);
if (!set)
10
←
Assuming 'set' is non-null→
11
←
Taking false branch→
  return false;

if (!REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
 REG))
12
←
Assuming field 'code' is equal to REG→
13
←
Taking false branch→
  return false;

gcc_assert (SET_DEST (set) == reg)((void)(!((((set)->u.fld[0]).rt_rtx) == reg) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 1082, __FUNCTION__), 0 : 0));
14
←
Assuming 'reg' is equal to field 'rt_rtx'→
15
←
'?' condition is false→
rhs = find_reg_equal_equiv_note (insn);
if (rhs)
16
←
Assuming 'rhs' is null→
17
←
Taking false branch→
  rhs = XEXP (rhs, 0)(((rhs)->u.fld[0]).rt_rtx);
else
  rhs = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);

iv_analyze_expr (insn, mode, rhs, iv);
18
←
Calling 'iv_analyze_expr'→
record_iv (def, iv);

if (dump_file)
  {
    print_rtl (dump_file, reg);
    fprintf (dump_file, " in insn ");
    print_rtl_single (dump_file, insn);
    fprintf (dump_file, "  is ");
    dump_iv_info (dump_file, iv);
    fprintf (dump_file, "\n");
  }

return iv->base != NULL_RTX(rtx) 0;
1103}

1105/* Analyzes operand OP of INSN and stores the result to *IV.  MODE is the
 mode of OP.  */

1108static bool
1109iv_analyze_op (rtx_insn *insn, scalar_int_mode mode, rtx op, class rtx_iv *iv)
1110{
df_ref def = NULL__null;
enum iv_grd_result res;

if (dump_file)
  {
    fprintf (dump_file, "Analyzing operand ");
    print_rtl (dump_file, op);
    fprintf (dump_file, " of insn ");
    print_rtl_single (dump_file, insn);
  }

if (function_invariant_p (op))
  res = GRD_INVARIANT;
else if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG)
  {
    scalar_int_mode inner_mode;
    if (!subreg_lowpart_p (op)
 || !is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op))((machine_mode) ((((op)->u.fld[0]).rt_rtx))->mode), &inner_mode))
return false;

    if (!iv_analyze_op (insn, inner_mode, SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx), iv))
return false;

    return iv_subreg (iv, mode);
  }
else
  {
    res = iv_get_reaching_def (insn, op, &def);
    if (res == GRD_INVALID)
{
 if (dump_file)
   fprintf (dump_file, "  not simple.\n");
 return false;
}
  }

if (res == GRD_INVARIANT)
  {
    iv_constant (iv, mode, op);

    if (dump_file)
{
 fprintf (dump_file, "  ");
 dump_iv_info (dump_file, iv);
 fprintf (dump_file, "\n");
}
    return true;
  }

if (res == GRD_MAYBE_BIV)
  return iv_analyze_biv (mode, op, iv);

return iv_analyze_def (def, iv);
1164}

1166/* Analyzes value VAL at INSN and stores the result to *IV.  MODE is the
 mode of VAL.  */

1169bool
1170iv_analyze (rtx_insn *insn, scalar_int_mode mode, rtx val, class rtx_iv *iv)
1171{
rtx reg;

/* We must find the insn in that val is used, so that we get to UD chains.
   Since the function is sometimes called on result of get_condition,
   this does not necessarily have to be directly INSN; scan also the
   following insns.  */
if (simple_reg_p (val))
  {
    if (GET_CODE (val)((enum rtx_code) (val)->code) == SUBREG)
reg = SUBREG_REG (val)(((val)->u.fld[0]).rt_rtx);
    else
reg = val;

    while (!df_find_use (insn, reg))
insn = NEXT_INSN (insn);
  }

return iv_analyze_op (insn, mode, val, iv);
1190}

1192/* Analyzes definition of DEF in INSN and stores the result to IV.  */

1194bool
1195iv_analyze_result (rtx_insn *insn, rtx def, class rtx_iv *iv)
1196{
df_ref adef;

adef = df_find_def (insn, def);
if (!adef)
1
Assuming 'adef' is non-null→
2
←
Taking false branch→
  return false;

return iv_analyze_def (adef, iv);
3
←
Calling 'iv_analyze_def'→
1204}

1206/* Checks whether definition of register REG in INSN is a basic induction
 variable.  MODE is the mode of REG.

 IV analysis must have been initialized (via a call to
 iv_analysis_loop_init) for this function to produce a result.  */

1212bool
1213biv_p (rtx_insn *insn, scalar_int_mode mode, rtx reg)
1214{
class rtx_iv iv;
df_ref def, last_def;

if (!simple_reg_p (reg))
  return false;

def = df_find_def (insn, reg);
gcc_assert (def != NULL)((void)(!(def != __null) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 1222, __FUNCTION__), 0 : 0));
if (!latch_dominating_def (reg, &last_def))
  return false;
if (last_def != def)
  return false;

if (!iv_analyze_biv (mode, reg, &iv))
  return false;

return iv.step != const0_rtx(const_int_rtx[64]);
1232}

1234/* Calculates value of IV at ITERATION-th iteration.  */

1236rtx
1237get_iv_value (class rtx_iv *iv, rtx iteration)
1238{
rtx val;

/* We would need to generate some if_then_else patterns, and so far
   it is not needed anywhere.  */
gcc_assert (!iv->first_special)((void)(!(!iv->first_special) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 1243, __FUNCTION__), 0 : 0));

if (iv->step != const0_rtx(const_int_rtx[64]) && iteration != const0_rtx(const_int_rtx[64]))
  val = simplify_gen_binary (PLUS, iv->extend_mode, iv->base,
	       simplify_gen_binary (MULT, iv->extend_mode,
				    iv->step, iteration));
else
  val = iv->base;

if (iv->extend_mode == iv->mode)
  return val;

val = lowpart_subreg (iv->mode, val, iv->extend_mode);

if (iv->extend == IV_UNKNOWN_EXTEND)
  return val;

val = simplify_gen_unary (iv_extend_to_rtx_code (iv->extend),
	    iv->extend_mode, val, iv->mode);
val = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta,
	     simplify_gen_binary (MULT, iv->extend_mode,
				  iv->mult, val));

return val;
1267}

1269/* Free the data for an induction variable analysis.  */

1271void
1272iv_analysis_done (void)
1273{
if (!clean_slate)
  {
    clear_iv_info ();
    clean_slate = true;
    df_finish_pass (true);
    delete bivs;
    bivs = NULL__null;
    free (iv_ref_table);
    iv_ref_table = NULL__null;
    iv_ref_table_size = 0;
  }
1285}

1287/* Computes inverse to X modulo (1 << MOD).  */

1289static uint64_t
1290inverse (uint64_t x, int mod)
1291{
uint64_t mask =
 ((uint64_t) 1 << (mod - 1) << 1) - 1;
uint64_t rslt = 1;
int i;

for (i = 0; i < mod - 1; i++)
  {
    rslt = (rslt * x) & mask;
    x = (x * x) & mask;
  }

return rslt;
1304}

1306/* Checks whether any register in X is in set ALT.  */

1308static bool
1309altered_reg_used (const_rtx x, bitmap alt)
1310{
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, NONCONST)for (subrtx_iterator iter (array, x, rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
  {
    const_rtx x = *iter;
    if (REG_P (x)(((enum rtx_code) (x)->code) == REG) && REGNO_REG_SET_P (alt, REGNO (x))bitmap_bit_p (alt, (rhs_regno(x))))
return true;
  }
return false;
1319}

1321/* Marks registers altered by EXPR in set ALT.  */

1323static void
1324mark_altered (rtx expr, const_rtx by ATTRIBUTE_UNUSED__attribute__ ((__unused__)), void *alt)
1325{
if (GET_CODE (expr)((enum rtx_code) (expr)->code) == SUBREG)
  expr = SUBREG_REG (expr)(((expr)->u.fld[0]).rt_rtx);
if (!REG_P (expr)(((enum rtx_code) (expr)->code) == REG))
  return;

SET_REGNO_REG_SET ((bitmap) alt, REGNO (expr))bitmap_set_bit ((bitmap) alt, (rhs_regno(expr)));
1332}

1334/* Checks whether RHS is simple enough to process.  */

1336static bool
1337simple_rhs_p (rtx rhs)
1338{
rtx op0, op1;

if (function_invariant_p (rhs)
    || (REG_P (rhs)(((enum rtx_code) (rhs)->code) == REG) && !HARD_REGISTER_P (rhs)((((rhs_regno(rhs))) < 76))))
  return true;

switch (GET_CODE (rhs)((enum rtx_code) (rhs)->code))
  {
  case PLUS:
  case MINUS:
  case AND:
    op0 = XEXP (rhs, 0)(((rhs)->u.fld[0]).rt_rtx);
    op1 = XEXP (rhs, 1)(((rhs)->u.fld[1]).rt_rtx);
    /* Allow reg OP const and reg OP reg.  */
    if (!(REG_P (op0)(((enum rtx_code) (op0)->code) == REG) && !HARD_REGISTER_P (op0)((((rhs_regno(op0))) < 76)))
 && !function_invariant_p (op0))
return false;
    if (!(REG_P (op1)(((enum rtx_code) (op1)->code) == REG) && !HARD_REGISTER_P (op1)((((rhs_regno(op1))) < 76)))
 && !function_invariant_p (op1))
return false;

    return true;

  case ASHIFT:
  case ASHIFTRT:
  case LSHIFTRT:
  case MULT:
    op0 = XEXP (rhs, 0)(((rhs)->u.fld[0]).rt_rtx);
    op1 = XEXP (rhs, 1)(((rhs)->u.fld[1]).rt_rtx);
    /* Allow reg OP const.  */
    if (!(REG_P (op0)(((enum rtx_code) (op0)->code) == REG) && !HARD_REGISTER_P (op0)((((rhs_regno(op0))) < 76))))
return false;
    if (!function_invariant_p (op1))
return false;

    return true;

  default:
    return false;
  }
1379}

1381/* If any registers in *EXPR that have a single definition, try to replace
 them with the known-equivalent values.  */

1384static void
1385replace_single_def_regs (rtx *expr)
1386{
subrtx_var_iterator::array_type array;
repeat:
FOR_EACH_SUBRTX_VAR (iter, array, *expr, NONCONST)for (subrtx_var_iterator iter (array, *expr, rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
  {
    rtx x = *iter;
    if (REG_P (x)(((enum rtx_code) (x)->code) == REG))
if (rtx new_x = df_find_single_def_src (x))
 {
   *expr = simplify_replace_rtx (*expr, x, new_x);
   goto repeat;
 }
  }
1399}

1401/* A subroutine of simplify_using_initial_values, this function examines INSN
 to see if it contains a suitable set that we can use to make a replacement.
 If it is suitable, return true and set DEST and SRC to the lhs and rhs of
 the set; return false otherwise.  */

1406static bool
1407suitable_set_for_replacement (rtx_insn *insn, rtx *dest, rtx *src)
1408{
rtx set = single_set (insn);
rtx lhs = NULL_RTX(rtx) 0, rhs;

if (!set)
  return false;

lhs = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);
if (!REG_P (lhs)(((enum rtx_code) (lhs)->code) == REG))
  return false;

rhs = find_reg_equal_equiv_note (insn);
if (rhs)
  rhs = XEXP (rhs, 0)(((rhs)->u.fld[0]).rt_rtx);
else
  rhs = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);

if (!simple_rhs_p (rhs))
  return false;

*dest = lhs;
*src = rhs;
return true;
1431}

1433/* Using the data returned by suitable_set_for_replacement, replace DEST
 with SRC in *EXPR and return the new expression.  Also call
 replace_single_def_regs if the replacement changed something.  */
1436static void
1437replace_in_expr (rtx *expr, rtx dest, rtx src)
1438{
rtx old = *expr;
*expr = simplify_replace_rtx (*expr, dest, src);
if (old == *expr)
  return;
replace_single_def_regs (expr);
1444}

1446/* Checks whether A implies B.  */

1448static bool
1449implies_p (rtx a, rtx b)
1450{
rtx op0, op1, opb0, opb1;
machine_mode mode;

if (rtx_equal_p (a, b))
  return true;

if (GET_CODE (a)((enum rtx_code) (a)->code) == EQ)
  {
    op0 = XEXP (a, 0)(((a)->u.fld[0]).rt_rtx);
    op1 = XEXP (a, 1)(((a)->u.fld[1]).rt_rtx);

    if (REG_P (op0)(((enum rtx_code) (op0)->code) == REG)
 || (GET_CODE (op0)((enum rtx_code) (op0)->code) == SUBREG
     && REG_P (SUBREG_REG (op0))(((enum rtx_code) ((((op0)->u.fld[0]).rt_rtx))->code) ==
 REG)))
{
 rtx r = simplify_replace_rtx (b, op0, op1);
 if (r == const_true_rtx)
   return true;
}

    if (REG_P (op1)(((enum rtx_code) (op1)->code) == REG)
 || (GET_CODE (op1)((enum rtx_code) (op1)->code) == SUBREG
     && REG_P (SUBREG_REG (op1))(((enum rtx_code) ((((op1)->u.fld[0]).rt_rtx))->code) ==
 REG)))
{
 rtx r = simplify_replace_rtx (b, op1, op0);
 if (r == const_true_rtx)
   return true;
}
  }

if (b == const_true_rtx)
  return true;

if ((GET_RTX_CLASS (GET_CODE (a))(rtx_class[(int) (((enum rtx_code) (a)->code))]) != RTX_COMM_COMPARE
     && GET_RTX_CLASS (GET_CODE (a))(rtx_class[(int) (((enum rtx_code) (a)->code))]) != RTX_COMPARE)
    || (GET_RTX_CLASS (GET_CODE (b))(rtx_class[(int) (((enum rtx_code) (b)->code))]) != RTX_COMM_COMPARE
 && GET_RTX_CLASS (GET_CODE (b))(rtx_class[(int) (((enum rtx_code) (b)->code))]) != RTX_COMPARE))
  return false;

op0 = XEXP (a, 0)(((a)->u.fld[0]).rt_rtx);
op1 = XEXP (a, 1)(((a)->u.fld[1]).rt_rtx);
opb0 = XEXP (b, 0)(((b)->u.fld[0]).rt_rtx);
opb1 = XEXP (b, 1)(((b)->u.fld[1]).rt_rtx);

mode = GET_MODE (op0)((machine_mode) (op0)->mode);
if (mode != GET_MODE (opb0)((machine_mode) (opb0)->mode))
  mode = VOIDmode((void) 0, E_VOIDmode);
else if (mode == VOIDmode((void) 0, E_VOIDmode))
  {
    mode = GET_MODE (op1)((machine_mode) (op1)->mode);
    if (mode != GET_MODE (opb1)((machine_mode) (opb1)->mode))
mode = VOIDmode((void) 0, E_VOIDmode);
  }

/* A < B implies A + 1 <= B.  */
if ((GET_CODE (a)((enum rtx_code) (a)->code) == GT || GET_CODE (a)((enum rtx_code) (a)->code) == LT)
    && (GET_CODE (b)((enum rtx_code) (b)->code) == GE || GET_CODE (b)((enum rtx_code) (b)->code) == LE))
  {

    if (GET_CODE (a)((enum rtx_code) (a)->code) == GT)
std::swap (op0, op1);

    if (GET_CODE (b)((enum rtx_code) (b)->code) == GE)
std::swap (opb0, opb1);

    if (SCALAR_INT_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_INT || ((enum mode_class
) mode_class[mode]) == MODE_PARTIAL_INT)
 && rtx_equal_p (op1, opb1)
 && simplify_gen_binary (MINUS, mode, opb0, op0) == const1_rtx(const_int_rtx[64 +1]))
return true;
    return false;
  }

/* A < B or A > B imply A != B.  TODO: Likewise
   A + n < B implies A != B + n if neither wraps.  */
if (GET_CODE (b)((enum rtx_code) (b)->code) == NE
    && (GET_CODE (a)((enum rtx_code) (a)->code) == GT || GET_CODE (a)((enum rtx_code) (a)->code) == GTU
 || GET_CODE (a)((enum rtx_code) (a)->code) == LT || GET_CODE (a)((enum rtx_code) (a)->code) == LTU))
  {
    if (rtx_equal_p (op0, opb0)
 && rtx_equal_p (op1, opb1))
return true;
  }

/* For unsigned comparisons, A != 0 implies A > 0 and A >= 1.  */
if (GET_CODE (a)((enum rtx_code) (a)->code) == NE
    && op1 == const0_rtx(const_int_rtx[64]))
  {
    if ((GET_CODE (b)((enum rtx_code) (b)->code) == GTU
  && opb1 == const0_rtx(const_int_rtx[64]))
 || (GET_CODE (b)((enum rtx_code) (b)->code) == GEU
     && opb1 == const1_rtx(const_int_rtx[64 +1])))
return rtx_equal_p (op0, opb0);
  }

/* A != N is equivalent to A - (N + 1) <u -1.  */
if (GET_CODE (a)((enum rtx_code) (a)->code) == NE
    && CONST_INT_P (op1)(((enum rtx_code) (op1)->code) == CONST_INT)
    && GET_CODE (b)((enum rtx_code) (b)->code) == LTU
    && opb1 == constm1_rtx(const_int_rtx[64 -1])
    && GET_CODE (opb0)((enum rtx_code) (opb0)->code) == PLUS
    && CONST_INT_P (XEXP (opb0, 1))(((enum rtx_code) ((((opb0)->u.fld[1]).rt_rtx))->code) ==
 CONST_INT)
    /* Avoid overflows.  */
    && ((unsigned HOST_WIDE_INTlong) INTVAL (XEXP (opb0, 1))(((((opb0)->u.fld[1]).rt_rtx))->u.hwint[0])
 != ((unsigned HOST_WIDE_INTlong)1
     << (HOST_BITS_PER_WIDE_INT64 - 1)) - 1)
    && INTVAL (XEXP (opb0, 1))(((((opb0)->u.fld[1]).rt_rtx))->u.hwint[0]) + 1 == -INTVAL (op1)((op1)->u.hwint[0]))
  return rtx_equal_p (op0, XEXP (opb0, 0)(((opb0)->u.fld[0]).rt_rtx));

/* Likewise, A != N implies A - N > 0.  */
if (GET_CODE (a)((enum rtx_code) (a)->code) == NE
    && CONST_INT_P (op1)(((enum rtx_code) (op1)->code) == CONST_INT))
  {
    if (GET_CODE (b)((enum rtx_code) (b)->code) == GTU
 && GET_CODE (opb0)((enum rtx_code) (opb0)->code) == PLUS
 && opb1 == const0_rtx(const_int_rtx[64])
 && CONST_INT_P (XEXP (opb0, 1))(((enum rtx_code) ((((opb0)->u.fld[1]).rt_rtx))->code) ==
 CONST_INT)
 /* Avoid overflows.  */
 && ((unsigned HOST_WIDE_INTlong) INTVAL (XEXP (opb0, 1))(((((opb0)->u.fld[1]).rt_rtx))->u.hwint[0])
     != (HOST_WIDE_INT_1U1UL << (HOST_BITS_PER_WIDE_INT64 - 1)))
 && rtx_equal_p (XEXP (opb0, 0)(((opb0)->u.fld[0]).rt_rtx), op0))
return INTVAL (op1)((op1)->u.hwint[0]) == -INTVAL (XEXP (opb0, 1))(((((opb0)->u.fld[1]).rt_rtx))->u.hwint[0]);
    if (GET_CODE (b)((enum rtx_code) (b)->code) == GEU
 && GET_CODE (opb0)((enum rtx_code) (opb0)->code) == PLUS
 && opb1 == const1_rtx(const_int_rtx[64 +1])
 && CONST_INT_P (XEXP (opb0, 1))(((enum rtx_code) ((((opb0)->u.fld[1]).rt_rtx))->code) ==
 CONST_INT)
 /* Avoid overflows.  */
 && ((unsigned HOST_WIDE_INTlong) INTVAL (XEXP (opb0, 1))(((((opb0)->u.fld[1]).rt_rtx))->u.hwint[0])
     != (HOST_WIDE_INT_1U1UL << (HOST_BITS_PER_WIDE_INT64 - 1)))
 && rtx_equal_p (XEXP (opb0, 0)(((opb0)->u.fld[0]).rt_rtx), op0))
return INTVAL (op1)((op1)->u.hwint[0]) == -INTVAL (XEXP (opb0, 1))(((((opb0)->u.fld[1]).rt_rtx))->u.hwint[0]);
  }

/* A >s X, where X is positive, implies A <u Y, if Y is negative.  */
if ((GET_CODE (a)((enum rtx_code) (a)->code) == GT || GET_CODE (a)((enum rtx_code) (a)->code) == GE)
    && CONST_INT_P (op1)(((enum rtx_code) (op1)->code) == CONST_INT)
    && ((GET_CODE (a)((enum rtx_code) (a)->code) == GT && op1 == constm1_rtx(const_int_rtx[64 -1]))
 || INTVAL (op1)((op1)->u.hwint[0]) >= 0)
    && GET_CODE (b)((enum rtx_code) (b)->code) == LTU
    && CONST_INT_P (opb1)(((enum rtx_code) (opb1)->code) == CONST_INT)
    && rtx_equal_p (op0, opb0))
  return INTVAL (opb1)((opb1)->u.hwint[0]) < 0;

return false;
1594}

1596/* Canonicalizes COND so that

 (1) Ensure that operands are ordered according to
     swap_commutative_operands_p.
 (2) (LE x const) will be replaced with (LT x <const+1>) and similarly
     for GE, GEU, and LEU.  */

1603rtx
1604canon_condition (rtx cond)
1605{
rtx op0, op1;
enum rtx_code code;
machine_mode mode;

code = GET_CODE (cond)((enum rtx_code) (cond)->code);
op0 = XEXP (cond, 0)(((cond)->u.fld[0]).rt_rtx);
op1 = XEXP (cond, 1)(((cond)->u.fld[1]).rt_rtx);

if (swap_commutative_operands_p (op0, op1))
  {
    code = swap_condition (code);
    std::swap (op0, op1);
  }

mode = GET_MODE (op0)((machine_mode) (op0)->mode);
if (mode == VOIDmode((void) 0, E_VOIDmode))
  mode = GET_MODE (op1)((machine_mode) (op1)->mode);
gcc_assert (mode != VOIDmode)((void)(!(mode != ((void) 0, E_VOIDmode)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 1623, __FUNCTION__), 0 : 0));

if (CONST_SCALAR_INT_P (op1)((((enum rtx_code) (op1)->code) == CONST_INT) || (((enum rtx_code
) (op1)->code) == CONST_WIDE_INT)) && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) != MODE_CC)
  {
    rtx_mode_t const_val (op1, mode);

    switch (code)
{
case LE:
 if (wi::ne_p (const_val, wi::max_value (mode, SIGNED)))
   {
     code = LT;
     op1 = immed_wide_int_const (wi::add (const_val, 1),  mode);
   }
 break;

case GE:
 if (wi::ne_p (const_val, wi::min_value (mode, SIGNED)))
   {
     code = GT;
     op1 = immed_wide_int_const (wi::sub (const_val, 1), mode);
   }
 break;

case LEU:
 if (wi::ne_p (const_val, -1))
   {
     code = LTU;
     op1 = immed_wide_int_const (wi::add (const_val, 1), mode);
   }
 break;

case GEU:
 if (wi::ne_p (const_val, 0))
   {
     code = GTU;
     op1 = immed_wide_int_const (wi::sub (const_val, 1), mode);
   }
 break;

default:
 break;
}
  }

if (op0 != XEXP (cond, 0)(((cond)->u.fld[0]).rt_rtx)
    || op1 != XEXP (cond, 1)(((cond)->u.fld[1]).rt_rtx)
    || code != GET_CODE (cond)((enum rtx_code) (cond)->code)
    || GET_MODE (cond)((machine_mode) (cond)->mode) != SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)))
  cond = gen_rtx_fmt_ee (code, SImode, op0, op1)gen_rtx_fmt_ee_stat ((code), ((scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), (op0), (op1) );

return cond;
1675}

1677/* Reverses CONDition; returns NULL if we cannot.  */

1679static rtx
1680reversed_condition (rtx cond)
1681{
enum rtx_code reversed;
reversed = reversed_comparison_code (cond, NULL__null);
if (reversed == UNKNOWN)
  return NULL_RTX(rtx) 0;
else
  return gen_rtx_fmt_ee (reversed,gen_rtx_fmt_ee_stat ((reversed), (((machine_mode) (cond)->
mode)), ((((cond)->u.fld[0]).rt_rtx)), ((((cond)->u.fld
[1]).rt_rtx)) )
	   GET_MODE (cond), XEXP (cond, 0),gen_rtx_fmt_ee_stat ((reversed), (((machine_mode) (cond)->
mode)), ((((cond)->u.fld[0]).rt_rtx)), ((((cond)->u.fld
[1]).rt_rtx)) )
	   XEXP (cond, 1))gen_rtx_fmt_ee_stat ((reversed), (((machine_mode) (cond)->
mode)), ((((cond)->u.fld[0]).rt_rtx)), ((((cond)->u.fld
[1]).rt_rtx)) );
1690}

1692/* Tries to use the fact that COND holds to simplify EXPR.  ALTERED is the
 set of altered regs.  */

1695void
1696simplify_using_condition (rtx cond, rtx *expr, regset altered)
1697{
rtx rev, reve, exp = *expr;

/* If some register gets altered later, we do not really speak about its
   value at the time of comparison.  */
if (altered && altered_reg_used (cond, altered))
  return;

if (GET_CODE (cond)((enum rtx_code) (cond)->code) == EQ
    && REG_P (XEXP (cond, 0))(((enum rtx_code) ((((cond)->u.fld[0]).rt_rtx))->code) ==
 REG) && CONSTANT_P (XEXP (cond, 1))((rtx_class[(int) (((enum rtx_code) ((((cond)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
  {
    *expr = simplify_replace_rtx (*expr, XEXP (cond, 0)(((cond)->u.fld[0]).rt_rtx), XEXP (cond, 1)(((cond)->u.fld[1]).rt_rtx));
    return;
  }

if (!COMPARISON_P (exp)(((rtx_class[(int) (((enum rtx_code) (exp)->code))]) &
 (~1)) == (RTX_COMPARE & (~1))))
  return;

rev = reversed_condition (cond);
reve = reversed_condition (exp);

cond = canon_condition (cond);
exp = canon_condition (exp);
if (rev)
  rev = canon_condition (rev);
if (reve)
  reve = canon_condition (reve);

if (rtx_equal_p (exp, cond))
  {
    *expr = const_true_rtx;
    return;
  }

if (rev && rtx_equal_p (exp, rev))
  {
    *expr = const0_rtx(const_int_rtx[64]);
    return;
  }

if (implies_p (cond, exp))
  {
    *expr = const_true_rtx;
    return;
  }

if (reve && implies_p (cond, reve))
  {
    *expr = const0_rtx(const_int_rtx[64]);
    return;
  }

/* A proof by contradiction.  If *EXPR implies (not cond), *EXPR must
   be false.  */
if (rev && implies_p (exp, rev))
  {
    *expr = const0_rtx(const_int_rtx[64]);
    return;
  }

/* Similarly, If (not *EXPR) implies (not cond), *EXPR must be true.  */
if (rev && reve && implies_p (reve, rev))
  {
    *expr = const_true_rtx;
    return;
  }

/* We would like to have some other tests here.  TODO.  */

return;
1767}

1769/* Use relationship between A and *B to eventually eliminate *B.
 OP is the operation we consider.  */

1772static void
1773eliminate_implied_condition (enum rtx_code op, rtx a, rtx *b)
1774{
switch (op)
  {
  case AND:
    /* If A implies *B, we may replace *B by true.  */
    if (implies_p (a, *b))
*b = const_true_rtx;
    break;

  case IOR:
    /* If *B implies A, we may replace *B by false.  */
    if (implies_p (*b, a))
*b = const0_rtx(const_int_rtx[64]);
    break;

  default:
    gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 1790, __FUNCTION__));
  }
1792}

1794/* Eliminates the conditions in TAIL that are implied by HEAD.  OP is the
 operation we consider.  */

1797static void
1798eliminate_implied_conditions (enum rtx_code op, rtx *head, rtx tail)
1799{
rtx elt;

for (elt = tail; elt; elt = XEXP (elt, 1)(((elt)->u.fld[1]).rt_rtx))
  eliminate_implied_condition (op, *head, &XEXP (elt, 0)(((elt)->u.fld[0]).rt_rtx));
for (elt = tail; elt; elt = XEXP (elt, 1)(((elt)->u.fld[1]).rt_rtx))
  eliminate_implied_condition (op, XEXP (elt, 0)(((elt)->u.fld[0]).rt_rtx), head);
1806}

1808/* Simplifies *EXPR using initial values at the start of the LOOP.  If *EXPR
 is a list, its elements are assumed to be combined using OP.  */

1811static void
1812simplify_using_initial_values (class loop *loop, enum rtx_code op, rtx *expr)
1813{
bool expression_valid;
rtx head, tail, last_valid_expr;
rtx_expr_list *cond_list;
rtx_insn *insn;
rtx neutral, aggr;
regset altered, this_altered;
edge e;

if (!*expr)
  return;

if (CONSTANT_P (*expr)((rtx_class[(int) (((enum rtx_code) (*expr)->code))]) == RTX_CONST_OBJ
))
  return;

if (GET_CODE (*expr)((enum rtx_code) (*expr)->code) == EXPR_LIST)
  {
    head = XEXP (*expr, 0)(((*expr)->u.fld[0]).rt_rtx);
    tail = XEXP (*expr, 1)(((*expr)->u.fld[1]).rt_rtx);

    eliminate_implied_conditions (op, &head, tail);

    switch (op)
{
case AND:
 neutral = const_true_rtx;
 aggr = const0_rtx(const_int_rtx[64]);
 break;

case IOR:
 neutral = const0_rtx(const_int_rtx[64]);
 aggr = const_true_rtx;
 break;

default:
 gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 1848, __FUNCTION__));
}

    simplify_using_initial_values (loop, UNKNOWN, &head);
    if (head == aggr)
{
 XEXP (*expr, 0)(((*expr)->u.fld[0]).rt_rtx) = aggr;
 XEXP (*expr, 1)(((*expr)->u.fld[1]).rt_rtx) = NULL_RTX(rtx) 0;
 return;
}
    else if (head == neutral)
{
 *expr = tail;
 simplify_using_initial_values (loop, op, expr);
 return;
}
    simplify_using_initial_values (loop, op, &tail);

    if (tail && XEXP (tail, 0)(((tail)->u.fld[0]).rt_rtx) == aggr)
{
 *expr = tail;
 return;
}

    XEXP (*expr, 0)(((*expr)->u.fld[0]).rt_rtx) = head;
    XEXP (*expr, 1)(((*expr)->u.fld[1]).rt_rtx) = tail;
    return;
  }

gcc_assert (op == UNKNOWN)((void)(!(op == UNKNOWN) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 1877, __FUNCTION__), 0 : 0));

replace_single_def_regs (expr);
if (CONSTANT_P (*expr)((rtx_class[(int) (((enum rtx_code) (*expr)->code))]) == RTX_CONST_OBJ
))
  return;

e = loop_preheader_edge (loop);
if (e->src == ENTRY_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_entry_block_ptr))
  return;

altered = ALLOC_REG_SET (&reg_obstack)bitmap_alloc (&reg_obstack);
this_altered = ALLOC_REG_SET (&reg_obstack)bitmap_alloc (&reg_obstack);

expression_valid = true;
last_valid_expr = *expr;
cond_list = NULL__null;
while (1)
  {
    insn = BB_END (e->src)(e->src)->il.x.rtl->end_;
    if (any_condjump_p (insn) && onlyjump_p (insn))
{
 rtx cond = get_condition (BB_END (e->src)(e->src)->il.x.rtl->end_, NULL__null, false, true);

 if (cond && (e->flags & EDGE_FALLTHRU))
   cond = reversed_condition (cond);
 if (cond)
   {
     rtx old = *expr;
     simplify_using_condition (cond, expr, altered);
     if (old != *expr)
{
  rtx note;
  if (CONSTANT_P (*expr)((rtx_class[(int) (((enum rtx_code) (*expr)->code))]) == RTX_CONST_OBJ
))
    goto out;
  for (note = cond_list; note; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
    {
      simplify_using_condition (XEXP (note, 0)(((note)->u.fld[0]).rt_rtx), expr, altered);
      if (CONSTANT_P (*expr)((rtx_class[(int) (((enum rtx_code) (*expr)->code))]) == RTX_CONST_OBJ
))
	goto out;
    }
}
     cond_list = alloc_EXPR_LIST (0, cond, cond_list);
   }
}

    FOR_BB_INSNS_REVERSE (e->src, insn)for ((insn) = (e->src)->il.x.rtl->end_; (insn) &&
 (insn) != PREV_INSN ((e->src)->il.x.head_); (insn) = PREV_INSN
 (insn))
{
 rtx src, dest;
 rtx old = *expr;

 if (!INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
 DEBUG_INSN)))
   continue;

 CLEAR_REG_SET (this_altered)bitmap_clear (this_altered);
 note_stores (insn, mark_altered, this_altered);
 if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
   {
     /* Kill all registers that might be clobbered by the call.
 We don't track modes of hard registers, so we need to be
 conservative and assume that partial kills are full kills.  */
     function_abi callee_abi = insn_callee_abi (insn);
     IOR_REG_SET_HRS (this_altered,bitmap_ior_into (this_altered, bitmap_view<HARD_REG_SET>
 (callee_abi.full_and_partial_reg_clobbers ()))
	       callee_abi.full_and_partial_reg_clobbers ())bitmap_ior_into (this_altered, bitmap_view<HARD_REG_SET>
 (callee_abi.full_and_partial_reg_clobbers ()));
   }

 if (suitable_set_for_replacement (insn, &dest, &src))
   {
     rtx_expr_list **pnote, **pnote_next;

     replace_in_expr (expr, dest, src);
     if (CONSTANT_P (*expr)((rtx_class[(int) (((enum rtx_code) (*expr)->code))]) == RTX_CONST_OBJ
))
goto out;

     for (pnote = &cond_list; *pnote; pnote = pnote_next)
{
  rtx_expr_list *note = *pnote;
  rtx old_cond = XEXP (note, 0)(((note)->u.fld[0]).rt_rtx);

  pnote_next = (rtx_expr_list **)&XEXP (note, 1)(((note)->u.fld[1]).rt_rtx);
  replace_in_expr (&XEXP (note, 0)(((note)->u.fld[0]).rt_rtx), dest, src);

  /* We can no longer use a condition that has been simplified
     to a constant, and simplify_using_condition will abort if
     we try.  */
  if (CONSTANT_P (XEXP (note, 0))((rtx_class[(int) (((enum rtx_code) ((((note)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ))
    {
      *pnote = *pnote_next;
      pnote_next = pnote;
      free_EXPR_LIST_node (note);
    }
  /* Retry simplifications with this condition if either the
     expression or the condition changed.  */
  else if (old_cond != XEXP (note, 0)(((note)->u.fld[0]).rt_rtx) || old != *expr)
    simplify_using_condition (XEXP (note, 0)(((note)->u.fld[0]).rt_rtx), expr, altered);
}
   }
 else
   {
     rtx_expr_list **pnote, **pnote_next;

     /* If we did not use this insn to make a replacement, any overlap
 between stores in this insn and our expression will cause the
 expression to become invalid.  */
     if (altered_reg_used (*expr, this_altered))
goto out;

     /* Likewise for the conditions.  */
     for (pnote = &cond_list; *pnote; pnote = pnote_next)
{
  rtx_expr_list *note = *pnote;
  rtx old_cond = XEXP (note, 0)(((note)->u.fld[0]).rt_rtx);

  pnote_next = (rtx_expr_list **)&XEXP (note, 1)(((note)->u.fld[1]).rt_rtx);
  if (altered_reg_used (old_cond, this_altered))
    {
      *pnote = *pnote_next;
      pnote_next = pnote;
      free_EXPR_LIST_node (note);
    }
}
   }

 if (CONSTANT_P (*expr)((rtx_class[(int) (((enum rtx_code) (*expr)->code))]) == RTX_CONST_OBJ
))
   goto out;

 IOR_REG_SET (altered, this_altered)bitmap_ior_into (altered, this_altered);

 /* If the expression now contains regs that have been altered, we
    can't return it to the caller.  However, it is still valid for
    further simplification, so keep searching to see if we can
    eventually turn it into a constant.  */
 if (altered_reg_used (*expr, altered))
   expression_valid = false;
 if (expression_valid)
   last_valid_expr = *expr;
}

    if (!single_pred_p (e->src)
 || single_pred (e->src) == ENTRY_BLOCK_PTR_FOR_FN (cfun)(((cfun + 0))->cfg->x_entry_block_ptr))
break;
    e = single_pred_edge (e->src);
  }

out:
free_EXPR_LIST_list (&cond_list);
if (!CONSTANT_P (*expr)((rtx_class[(int) (((enum rtx_code) (*expr)->code))]) == RTX_CONST_OBJ
))
  *expr = last_valid_expr;
FREE_REG_SET (altered)((void) (bitmap_obstack_free ((bitmap) altered), (altered) = (
bitmap) __null));
FREE_REG_SET (this_altered)((void) (bitmap_obstack_free ((bitmap) this_altered), (this_altered
) = (bitmap) __null));
2026}

2028/* Transforms invariant IV into MODE.  Adds assumptions based on the fact
 that IV occurs as left operands of comparison COND and its signedness
 is SIGNED_P to DESC.  */

2032static void
2033shorten_into_mode (class rtx_iv *iv, scalar_int_mode mode,
   enum rtx_code cond, bool signed_p, class niter_desc *desc)
2035{
rtx mmin, mmax, cond_over, cond_under;

get_mode_bounds (mode, signed_p, iv->extend_mode, &mmin, &mmax);
cond_under = simplify_gen_relational (LT, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), iv->extend_mode,
			iv->base, mmin);
cond_over = simplify_gen_relational (GT, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), iv->extend_mode,
		       iv->base, mmax);

switch (cond)
  {
    case LE:
    case LT:
    case LEU:
    case LTU:
if (cond_under != const0_rtx(const_int_rtx[64]))
 desc->infinite =
  alloc_EXPR_LIST (0, cond_under, desc->infinite);
if (cond_over != const0_rtx(const_int_rtx[64]))
 desc->noloop_assumptions =
  alloc_EXPR_LIST (0, cond_over, desc->noloop_assumptions);
break;

    case GE:
    case GT:
    case GEU:
    case GTU:
if (cond_over != const0_rtx(const_int_rtx[64]))
 desc->infinite =
  alloc_EXPR_LIST (0, cond_over, desc->infinite);
if (cond_under != const0_rtx(const_int_rtx[64]))
 desc->noloop_assumptions =
  alloc_EXPR_LIST (0, cond_under, desc->noloop_assumptions);
break;

    case NE:
if (cond_over != const0_rtx(const_int_rtx[64]))
 desc->infinite =
  alloc_EXPR_LIST (0, cond_over, desc->infinite);
if (cond_under != const0_rtx(const_int_rtx[64]))
 desc->infinite =
  alloc_EXPR_LIST (0, cond_under, desc->infinite);
break;

    default:
gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 2080, __FUNCTION__));
  }

iv->mode = mode;
iv->extend = signed_p ? IV_SIGN_EXTEND : IV_ZERO_EXTEND;
2085}

2087/* Transforms IV0 and IV1 compared by COND so that they are both compared as
 subregs of the same mode if possible (sometimes it is necessary to add
 some assumptions to DESC).  */

2091static bool
2092canonicalize_iv_subregs (class rtx_iv *iv0, class rtx_iv *iv1,
	 enum rtx_code cond, class niter_desc *desc)
2094{
scalar_int_mode comp_mode;
bool signed_p;

/* If the ivs behave specially in the first iteration, or are
   added/multiplied after extending, we ignore them.  */
if (iv0->first_special || iv0->mult != const1_rtx(const_int_rtx[64 +1]) || iv0->delta != const0_rtx(const_int_rtx[64]))
  return false;
if (iv1->first_special || iv1->mult != const1_rtx(const_int_rtx[64 +1]) || iv1->delta != const0_rtx(const_int_rtx[64]))
  return false;

/* If there is some extend, it must match signedness of the comparison.  */
switch (cond)
  {
    case LE:
    case LT:
if (iv0->extend == IV_ZERO_EXTEND
   || iv1->extend == IV_ZERO_EXTEND)
 return false;
signed_p = true;
break;

    case LEU:
    case LTU:
if (iv0->extend == IV_SIGN_EXTEND
   || iv1->extend == IV_SIGN_EXTEND)
 return false;
signed_p = false;
break;

    case NE:
if (iv0->extend != IV_UNKNOWN_EXTEND
   && iv1->extend != IV_UNKNOWN_EXTEND
   && iv0->extend != iv1->extend)
 return false;

signed_p = false;
if (iv0->extend != IV_UNKNOWN_EXTEND)
 signed_p = iv0->extend == IV_SIGN_EXTEND;
if (iv1->extend != IV_UNKNOWN_EXTEND)
 signed_p = iv1->extend == IV_SIGN_EXTEND;
break;

    default:
gcc_unreachable ()(fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 2138, __FUNCTION__));
  }

/* Values of both variables should be computed in the same mode.  These
   might indeed be different, if we have comparison like

   (compare (subreg:SI (iv0)) (subreg:SI (iv1)))

   and iv0 and iv1 are both ivs iterating in SI mode, but calculated
   in different modes.  This does not seem impossible to handle, but
   it hardly ever occurs in practice.

   The only exception is the case when one of operands is invariant.
   For example pentium 3 generates comparisons like
   (lt (subreg:HI (reg:SI)) 100).  Here we assign HImode to 100, but we
   definitely do not want this prevent the optimization.  */
comp_mode = iv0->extend_mode;
if (GET_MODE_BITSIZE (comp_mode) < GET_MODE_BITSIZE (iv1->extend_mode))
  comp_mode = iv1->extend_mode;

if (iv0->extend_mode != comp_mode)
  {
    if (iv0->mode != iv0->extend_mode
 || iv0->step != const0_rtx(const_int_rtx[64]))
return false;

    iv0->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND,
		      comp_mode, iv0->base, iv0->mode);
    iv0->extend_mode = comp_mode;
  }

if (iv1->extend_mode != comp_mode)
  {
    if (iv1->mode != iv1->extend_mode
 || iv1->step != const0_rtx(const_int_rtx[64]))
return false;

    iv1->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND,
		      comp_mode, iv1->base, iv1->mode);
    iv1->extend_mode = comp_mode;
  }

/* Check that both ivs belong to a range of a single mode.  If one of the
   operands is an invariant, we may need to shorten it into the common
   mode.  */
if (iv0->mode == iv0->extend_mode
    && iv0->step == const0_rtx(const_int_rtx[64])
    && iv0->mode != iv1->mode)
  shorten_into_mode (iv0, iv1->mode, cond, signed_p, desc);

if (iv1->mode == iv1->extend_mode
    && iv1->step == const0_rtx(const_int_rtx[64])
    && iv0->mode != iv1->mode)
  shorten_into_mode (iv1, iv0->mode, swap_condition (cond), signed_p, desc);

if (iv0->mode != iv1->mode)
  return false;

desc->mode = iv0->mode;
desc->signed_p = signed_p;

return true;
2200}

2202/* Tries to estimate the maximum number of iterations in LOOP, and return the
 result.  This function is called from iv_number_of_iterations with
 a number of fields in DESC already filled in.  OLD_NITER is the original
 expression for the number of iterations, before we tried to simplify it.  */

2207static uint64_t
2208determine_max_iter (class loop *loop, class niter_desc *desc, rtx old_niter)
2209{
rtx niter = desc->niter_expr;
rtx mmin, mmax, cmp;
uint64_t nmax, inc;
uint64_t andmax = 0;

/* We used to look for constant operand 0 of AND,
   but canonicalization should always make this impossible.  */
gcc_checking_assert (GET_CODE (niter) != AND((void)(!(((enum rtx_code) (niter)->code) != AND || !(((enum
 rtx_code) ((((niter)->u.fld[0]).rt_rtx))->code) == CONST_INT
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 2218, __FUNCTION__), 0 : 0))
              || !CONST_INT_P (XEXP (niter, 0)))((void)(!(((enum rtx_code) (niter)->code) != AND || !(((enum
 rtx_code) ((((niter)->u.fld[0]).rt_rtx))->code) == CONST_INT
)) ? fancy_abort ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 2218, __FUNCTION__), 0 : 0));

if (GET_CODE (niter)((enum rtx_code) (niter)->code) == AND
    && CONST_INT_P (XEXP (niter, 1))(((enum rtx_code) ((((niter)->u.fld[1]).rt_rtx))->code)
 == CONST_INT))
  {
    andmax = UINTVAL (XEXP (niter, 1))((unsigned long) (((((niter)->u.fld[1]).rt_rtx))->u.hwint
[0]));
    niter = XEXP (niter, 0)(((niter)->u.fld[0]).rt_rtx);
  }

get_mode_bounds (desc->mode, desc->signed_p, desc->mode, &mmin, &mmax);
nmax = UINTVAL (mmax)((unsigned long) ((mmax)->u.hwint[0])) - UINTVAL (mmin)((unsigned long) ((mmin)->u.hwint[0]));

if (GET_CODE (niter)((enum rtx_code) (niter)->code) == UDIV)
  {
    if (!CONST_INT_P (XEXP (niter, 1))(((enum rtx_code) ((((niter)->u.fld[1]).rt_rtx))->code)
 == CONST_INT))
return nmax;
    inc = INTVAL (XEXP (niter, 1))(((((niter)->u.fld[1]).rt_rtx))->u.hwint[0]);
    niter = XEXP (niter, 0)(((niter)->u.fld[0]).rt_rtx);
  }
else
  inc = 1;

/* We could use a binary search here, but for now improving the upper
   bound by just one eliminates one important corner case.  */
cmp = simplify_gen_relational (desc->signed_p ? LT : LTU, VOIDmode((void) 0, E_VOIDmode),
		 desc->mode, old_niter, mmax);
simplify_using_initial_values (loop, UNKNOWN, &cmp);
if (cmp == const_true_rtx)
  {
    nmax--;

    if (dump_file)
fprintf (dump_file, ";; improved upper bound by one.\n");
  }
nmax /= inc;
if (andmax)
  nmax = MIN (nmax, andmax)((nmax) < (andmax) ? (nmax) : (andmax));
if (dump_file)
  fprintf (dump_file, ";; Determined upper bound %" PRId64"l" "d"".\n",
    nmax);
return nmax;
2259}

2261/* Computes number of iterations of the CONDITION in INSN in LOOP and stores
 the result into DESC.  Very similar to determine_number_of_iterations
 (basically its rtl version), complicated by things like subregs.  */

2265static void
2266iv_number_of_iterations (class loop *loop, rtx_insn *insn, rtx condition,
	 class niter_desc *desc)
2268{
rtx op0, op1, delta, step, bound, may_xform, tmp, tmp0, tmp1;
class rtx_iv iv0, iv1;
rtx assumption, may_not_xform;
enum rtx_code cond;
machine_mode nonvoid_mode;
scalar_int_mode comp_mode;
rtx mmin, mmax, mode_mmin, mode_mmax;
uint64_t s, size, d, inv, max, up, down;
int64_t inc, step_val;
int was_sharp = false;
rtx old_niter;
bool step_is_pow2;

/* The meaning of these assumptions is this:
   if !assumptions
     then the rest of information does not have to be valid
   if noloop_assumptions then the loop does not roll
   if infinite then this exit is never used */

desc->assumptions = NULL_RTX(rtx) 0;
desc->noloop_assumptions = NULL_RTX(rtx) 0;
desc->infinite = NULL_RTX(rtx) 0;
desc->simple_p = true;

desc->const_iter = false;
desc->niter_expr = NULL_RTX(rtx) 0;

cond = GET_CODE (condition)((enum rtx_code) (condition)->code);
gcc_assert (COMPARISON_P (condition))((void)(!((((rtx_class[(int) (((enum rtx_code) (condition)->
code))]) & (~1)) == (RTX_COMPARE & (~1)))) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 2297, __FUNCTION__), 0 : 0));

nonvoid_mode = GET_MODE (XEXP (condition, 0))((machine_mode) ((((condition)->u.fld[0]).rt_rtx))->mode
);
if (nonvoid_mode == VOIDmode((void) 0, E_VOIDmode))
  nonvoid_mode = GET_MODE (XEXP (condition, 1))((machine_mode) ((((condition)->u.fld[1]).rt_rtx))->mode
);
/* The constant comparisons should be folded.  */
gcc_assert (nonvoid_mode != VOIDmode)((void)(!(nonvoid_mode != ((void) 0, E_VOIDmode)) ? fancy_abort
 ("/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/loop-iv.cc"
, 2303, __FUNCTION__), 0 : 0));

/* We only handle integers or pointers.  */
scalar_int_mode mode;
if (!is_a <scalar_int_mode> (nonvoid_mode, &mode))
  goto fail;

op0 = XEXP (condition, 0)(((condition)->u.fld[0]).rt_rtx);
if (!iv_analyze (insn, mode, op0, &iv0))
  goto fail;

op1 = XEXP (condition, 1)(((condition)->u.fld[1]).rt_rtx);
if (!iv_analyze (insn, mode, op1, &iv1))
  goto fail;

if (GET_MODE_BITSIZE (iv0.extend_mode) > HOST_BITS_PER_WIDE_INT64
    || GET_MODE_BITSIZE (iv1.extend_mode) > HOST_BITS_PER_WIDE_INT64)
  goto fail;

/* Check condition and normalize it.  */

switch (cond)
  {
    case GE:
    case GT:
    case GEU:
    case GTU:
std::swap (iv0, iv1);
cond = swap_condition (cond);
break;
    case NE:
    case LE:
    case LEU:
    case LT:
    case LTU:
break;
    default:
goto fail;
  }

/* Handle extends.  This is relatively nontrivial, so we only try in some
   easy cases, when we can canonicalize the ivs (possibly by adding some
   assumptions) to shape subreg (base + i * step).  This function also fills
   in desc->mode and desc->signed_p.  */

if (!canonicalize_iv_subregs (&iv0, &iv1, cond, desc))
  goto fail;

comp_mode = iv0.extend_mode;
mode = iv0.mode;
size = GET_MODE_PRECISION (mode);
get_mode_bounds (mode, (cond == LE || cond == LT), comp_mode, &mmin, &mmax);
mode_mmin = lowpart_subreg (mode, mmin, comp_mode);
mode_mmax = lowpart_subreg (mode, mmax, comp_mode);

if (!CONST_INT_P (iv0.step)(((enum rtx_code) (iv0.step)->code) == CONST_INT) || !CONST_INT_P (iv1.step)(((enum rtx_code) (iv1.step)->code) == CONST_INT))
  goto fail;

/* We can take care of the case of two induction variables chasing each other
   if the test is NE. I have never seen a loop using it, but still it is
   cool.  */
if (iv0.step != const0_rtx(const_int_rtx[64]) && iv1.step != const0_rtx(const_int_rtx[64]))
  {
    if (cond != NE)
goto fail;

    iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step);
    iv1.step = const0_rtx(const_int_rtx[64]);
  }

iv0.step = lowpart_subreg (mode, iv0.step, comp_mode);
iv1.step = lowpart_subreg (mode, iv1.step, comp_mode);

/* This is either infinite loop or the one that ends immediately, depending
   on initial values.  Unswitching should remove this kind of conditions.  */
if (iv0.step == const0_rtx(const_int_rtx[64]) && iv1.step == const0_rtx(const_int_rtx[64]))
  goto fail;

if (cond != NE)
  {
    if (iv0.step == const0_rtx(const_int_rtx[64]))
step_val = -INTVAL (iv1.step)((iv1.step)->u.hwint[0]);
    else
step_val = INTVAL (iv0.step)((iv0.step)->u.hwint[0]);

    /* Ignore loops of while (i-- < 10) type.  */
    if (step_val < 0)
goto fail;

    step_is_pow2 = !(step_val & (step_val - 1));
  }
else
  {
    /* We do not care about whether the step is power of two in this
case.  */
    step_is_pow2 = false;
    step_val = 0;
  }

/* Some more condition normalization.  We must record some assumptions
   due to overflows.  */
switch (cond)
  {
    case LT:
    case LTU:
/* We want to take care only of non-sharp relationals; this is easy,
  as in cases the overflow would make the transformation unsafe
  the loop does not roll.  Seemingly it would make more sense to want
  to take care of sharp relationals instead, as NE is more similar to
  them, but the problem is that here the transformation would be more
  difficult due to possibly infinite loops.  */
if (iv0.step == const0_rtx(const_int_rtx[64]))
 {
   tmp = lowpart_subreg (mode, iv0.base, comp_mode);
   assumption = simplify_gen_relational (EQ, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode, tmp,
				  mode_mmax);
   if (assumption == const_true_rtx)
     goto zero_iter_simplify;
   iv0.base = simplify_gen_binary (PLUS, comp_mode,
			    iv0.base, const1_rtx(const_int_rtx[64 +1]));
 }
else
 {
   tmp = lowpart_subreg (mode, iv1.base, comp_mode);
   assumption = simplify_gen_relational (EQ, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode, tmp,
				  mode_mmin);
   if (assumption == const_true_rtx)
     goto zero_iter_simplify;
   iv1.base = simplify_gen_binary (PLUS, comp_mode,
			    iv1.base, constm1_rtx(const_int_rtx[64 -1]));
 }

if (assumption != const0_rtx(const_int_rtx[64]))
 desc->noloop_assumptions =
  alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions);
cond = (cond == LT) ? LE : LEU;

/* It will be useful to be able to tell the difference once more in
  LE -> NE reduction.  */
was_sharp = true;
break;
    default: ;
  }

/* Take care of trivially infinite loops.  */
if (cond != NE)
  {
    if (iv0.step == const0_rtx(const_int_rtx[64]))
{
 tmp = lowpart_subreg (mode, iv0.base, comp_mode);
 if (rtx_equal_p (tmp, mode_mmin))
   {
     desc->infinite =
      alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX(rtx) 0);
     /* Fill in the remaining fields somehow.  */
     goto zero_iter_simplify;
   }
}
    else
{
 tmp = lowpart_subreg (mode, iv1.base, comp_mode);
 if (rtx_equal_p (tmp, mode_mmax))
   {
     desc->infinite =
      alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX(rtx) 0);
     /* Fill in the remaining fields somehow.  */
     goto zero_iter_simplify;
   }
}
  }

/* If we can we want to take care of NE conditions instead of size
   comparisons, as they are much more friendly (most importantly
   this takes care of special handling of loops with step 1).  We can
   do it if we first check that upper bound is greater or equal to
   lower bound, their difference is constant c modulo step and that
   there is not an overflow.  */
if (cond != NE)
  {
    if (iv0.step == const0_rtx(const_int_rtx[64]))
step = simplify_gen_unary (NEG, comp_mode, iv1.step, comp_mode);
    else
step = iv0.step;
    step = lowpart_subreg (mode, step, comp_mode);
    delta = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base);
    delta = lowpart_subreg (mode, delta, comp_mode);
    delta = simplify_gen_binary (UMOD, mode, delta, step);
    may_xform = const0_rtx(const_int_rtx[64]);
    may_not_xform = const_true_rtx;

    if (CONST_INT_P (delta)(((enum rtx_code) (delta)->code) == CONST_INT))
{
 if (was_sharp && INTVAL (delta)((delta)->u.hwint[0]) == INTVAL (step)((step)->u.hwint[0]) - 1)
   {
     /* A special case.  We have transformed condition of type
 for (i = 0; i < 4; i += 4)
 into
 for (i = 0; i <= 3; i += 4)
 obviously if the test for overflow during that transformation
 passed, we cannot overflow here.  Most importantly any
 loop with sharp end condition and step 1 falls into this
 category, so handling this case specially is definitely
 worth the troubles.  */
     may_xform = const_true_rtx;
   }
 else if (iv0.step == const0_rtx(const_int_rtx[64]))
   {
     bound = simplify_gen_binary (PLUS, comp_mode, mmin, step);
     bound = simplify_gen_binary (MINUS, comp_mode, bound, delta);
     bound = lowpart_subreg (mode, bound, comp_mode);
     tmp = lowpart_subreg (mode, iv0.base, comp_mode);
     may_xform = simplify_gen_relational (cond, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode,
				   bound, tmp);
     may_not_xform = simplify_gen_relational (reverse_condition (cond),
				       SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode,
				       bound, tmp);
   }
 else
   {
     bound = simplify_gen_binary (MINUS, comp_mode, mmax, step);
     bound = simplify_gen_binary (PLUS, comp_mode, bound, delta);
     bound = lowpart_subreg (mode, bound, comp_mode);
     tmp = lowpart_subreg (mode, iv1.base, comp_mode);
     may_xform = simplify_gen_relational (cond, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode,
				   tmp, bound);
     may_not_xform = simplify_gen_relational (reverse_condition (cond),
				       SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode,
				       tmp, bound);
   }
}

    if (may_xform != const0_rtx(const_int_rtx[64]))
{
 /* We perform the transformation always provided that it is not
    completely senseless.  This is OK, as we would need this assumption
    to determine the number of iterations anyway.  */
 if (may_xform != const_true_rtx)
   {
     /* If the step is a power of two and the final value we have
 computed overflows, the cycle is infinite.  Otherwise it
 is nontrivial to compute the number of iterations.  */
     if (step_is_pow2)
desc->infinite = alloc_EXPR_LIST (0, may_not_xform,
				  desc->infinite);
     else
desc->assumptions = alloc_EXPR_LIST (0, may_xform,
				     desc->assumptions);
   }

 /* We are going to lose some information about upper bound on
    number of iterations in this step, so record the information
    here.  */
 inc = INTVAL (iv0.step)((iv0.step)->u.hwint[0]) - INTVAL (iv1.step)((iv1.step)->u.hwint[0]);
 if (CONST_INT_P (iv1.base)(((enum rtx_code) (iv1.base)->code) == CONST_INT))
   up = INTVAL (iv1.base)((iv1.base)->u.hwint[0]);
 else
   up = INTVAL (mode_mmax)((mode_mmax)->u.hwint[0]) - inc;
 down = INTVAL (CONST_INT_P (iv0.base)(((((enum rtx_code) (iv0.base)->code) == CONST_INT) ? iv0.
base : mode_mmin)->u.hwint[0])
	 ? iv0.base(((((enum rtx_code) (iv0.base)->code) == CONST_INT) ? iv0.
base : mode_mmin)->u.hwint[0])
	 : mode_mmin)(((((enum rtx_code) (iv0.base)->code) == CONST_INT) ? iv0.
base : mode_mmin)->u.hwint[0]);
 max = (up - down) / inc + 1;
 if (!desc->infinite
     && !desc->assumptions)
   record_niter_bound (loop, max, false, true);

 if (iv0.step == const0_rtx(const_int_rtx[64]))
   {
     iv0.base = simplify_gen_binary (PLUS, comp_mode, iv0.base, delta);
     iv0.base = simplify_gen_binary (MINUS, comp_mode, iv0.base, step);
   }
 else
   {
     iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, delta);
     iv1.base = simplify_gen_binary (PLUS, comp_mode, iv1.base, step);
   }

 tmp0 = lowpart_subreg (mode, iv0.base, comp_mode);
 tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
 assumption = simplify_gen_relational (reverse_condition (cond),
				SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode, tmp0, tmp1);
 if (assumption == const_true_rtx)
   goto zero_iter_simplify;
 else if (assumption != const0_rtx(const_int_rtx[64]))
   desc->noloop_assumptions =
    alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions);
 cond = NE;
}
  }

/* Count the number of iterations.  */
if (cond == NE)
  {
    /* Everything we do here is just arithmetics modulo size of mode.  This
makes us able to do more involved computations of number of iterations
than in other cases.  First transform the condition into shape
s * i <> c, with s positive.  */
    iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base);
    iv0.base = const0_rtx(const_int_rtx[64]);
    iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step);
    iv1.step = const0_rtx(const_int_rtx[64]);
    if (INTVAL (iv0.step)((iv0.step)->u.hwint[0]) < 0)
{
 iv0.step = simplify_gen_unary (NEG, comp_mode, iv0.step, comp_mode);
 iv1.base = simplify_gen_unary (NEG, comp_mode, iv1.base, comp_mode);
}
    iv0.step = lowpart_subreg (mode, iv0.step, comp_mode);

    /* Let nsd (s, size of mode) = d.  If d does not divide c, the loop
is infinite.  Otherwise, the number of iterations is
(inverse(s/d) * (c/d)) mod (size of mode/d).  */
    s = INTVAL (iv0.step)((iv0.step)->u.hwint[0]); d = 1;
    while (s % 2 != 1)
{
 s /= 2;
 d *= 2;
 size--;
}
    bound = GEN_INT (((uint64_t) 1 << (size - 1 ) << 1) - 1)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (((uint64_t) 1 <<
 (size - 1 ) << 1) - 1));

    tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
    tmp = simplify_gen_binary (UMOD, mode, tmp1, gen_int_mode (d, mode));
    assumption = simplify_gen_relational (NE, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode, tmp, const0_rtx(const_int_rtx[64]));
    desc->infinite = alloc_EXPR_LIST (0, assumption, desc->infinite);

    tmp = simplify_gen_binary (UDIV, mode, tmp1, gen_int_mode (d, mode));
    inv = inverse (s, size);
    tmp = simplify_gen_binary (MULT, mode, tmp, gen_int_mode (inv, mode));
    desc->niter_expr = simplify_gen_binary (AND, mode, tmp, bound);
  }
else
  {
    if (iv1.step == const0_rtx(const_int_rtx[64]))
/* Condition in shape a + s * i <= b
  We must know that b + s does not overflow and a <= b + s and then we
  can compute number of iterations as (b + s - a) / s.  (It might
  seem that we in fact could be more clever about testing the b + s
  overflow condition using some information about b - a mod s,
  but it was already taken into account during LE -> NE transform).  */
{
 step = iv0.step;
 tmp0 = lowpart_subreg (mode, iv0.base, comp_mode);
 tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);

 bound = simplify_gen_binary (MINUS, mode, mode_mmax,
		       lowpart_subreg (mode, step,
				       comp_mode));
 if (step_is_pow2)
   {
     rtx t0, t1;

     /* If s is power of 2, we know that the loop is infinite if
 a % s <= b % s and b + s overflows.  */
     assumption = simplify_gen_relational (reverse_condition (cond),
				    SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode,
				    tmp1, bound);

     t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step);
     t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step);
     tmp = simplify_gen_relational (cond, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode, t0, t1);
     assumption = simplify_gen_binary (AND, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), assumption, tmp);
     desc->infinite =
      alloc_EXPR_LIST (0, assumption, desc->infinite);
   }
 else
   {
     assumption = simplify_gen_relational (cond, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode,
				    tmp1, bound);
     desc->assumptions =
      alloc_EXPR_LIST (0, assumption, desc->assumptions);
   }

 tmp = simplify_gen_binary (PLUS, comp_mode, iv1.base, iv0.step);
 tmp = lowpart_subreg (mode, tmp, comp_mode);
 assumption = simplify_gen_relational (reverse_condition (cond),
				SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode, tmp0, tmp);

 delta = simplify_gen_binary (PLUS, mode, tmp1, step);
 delta = simplify_gen_binary (MINUS, mode, delta, tmp0);
}
    else
{
 /* Condition in shape a <= b - s * i
    We must know that a - s does not overflow and a - s <= b and then
    we can again compute number of iterations as (b - (a - s)) / s.  */
 step = simplify_gen_unary (NEG, mode, iv1.step, mode);
 tmp0 = lowpart_subreg (mode, iv0.base, comp_mode);
 tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);

 bound = simplify_gen_binary (PLUS, mode, mode_mmin,
		       lowpart_subreg (mode, step, comp_mode));
 if (step_is_pow2)
   {
     rtx t0, t1;

     /* If s is power of 2, we know that the loop is infinite if
 a % s <= b % s and a - s overflows.  */
     assumption = simplify_gen_relational (reverse_condition (cond),
				    SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode,
				    bound, tmp0);

     t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step);
     t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step);
     tmp = simplify_gen_relational (cond, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode, t0, t1);
     assumption = simplify_gen_binary (AND, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), assumption, tmp);
     desc->infinite =
      alloc_EXPR_LIST (0, assumption, desc->infinite);
   }
 else
   {
     assumption = simplify_gen_relational (cond, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode,
				    bound, tmp0);
     desc->assumptions =
      alloc_EXPR_LIST (0, assumption, desc->assumptions);
   }

 tmp = simplify_gen_binary (PLUS, comp_mode, iv0.base, iv1.step);
 tmp = lowpart_subreg (mode, tmp, comp_mode);
 assumption = simplify_gen_relational (reverse_condition (cond),
				SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), mode,
				tmp, tmp1);
 delta = simplify_gen_binary (MINUS, mode, tmp0, step);
 delta = simplify_gen_binary (MINUS, mode, tmp1, delta);
}
    if (assumption == const_true_rtx)
goto zero_iter_simplify;
    else if (assumption != const0_rtx(const_int_rtx[64]))
desc->noloop_assumptions =
alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions);
    delta = simplify_gen_binary (UDIV, mode, delta, step);
    desc->niter_expr = delta;
  }

old_niter = desc->niter_expr;

simplify_using_initial_values (loop, AND, &desc->assumptions);
if (desc->assumptions
    && XEXP (desc->assumptions, 0)(((desc->assumptions)->u.fld[0]).rt_rtx) == const0_rtx(const_int_rtx[64]))
  goto fail;
simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions);
simplify_using_initial_values (loop, IOR, &desc->infinite);
simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr);

/* Rerun the simplification.  Consider code (created by copying loop headers)

   i = 0;

   if (0 < n)
     {
       do
  {
    i++;
  } while (i < n);
     }

  The first pass determines that i = 0, the second pass uses it to eliminate
  noloop assumption.  */

simplify_using_initial_values (loop, AND, &desc->assumptions);
if (desc->assumptions
    && XEXP (desc->assumptions, 0)(((desc->assumptions)->u.fld[0]).rt_rtx) == const0_rtx(const_int_rtx[64]))
  goto fail;
simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions);
simplify_using_initial_values (loop, IOR, &desc->infinite);
simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr);

if (desc->noloop_assumptions
    && XEXP (desc->noloop_assumptions, 0)(((desc->noloop_assumptions)->u.fld[0]).rt_rtx) == const_true_rtx)
  goto zero_iter;

if (CONST_INT_P (desc->niter_expr)(((enum rtx_code) (desc->niter_expr)->code) == CONST_INT
))
  {
    uint64_t val = INTVAL (desc->niter_expr)((desc->niter_expr)->u.hwint[0]);

    desc->const_iter = true;
    desc->niter = val & GET_MODE_MASK (desc->mode)mode_mask_array[desc->mode];
    if (!desc->infinite
 && !desc->assumptions)
      record_niter_bound (loop, desc->niter, false, true);
  }
else
  {
    max = determine_max_iter (loop, desc, old_niter);
    if (!max)
goto zero_iter_simplify;
    if (!desc->infinite
 && !desc->assumptions)
record_niter_bound (loop, max, false, true);

    /* simplify_using_initial_values does a copy propagation on the registers
in the expression for the number of iterations.  This prolongs life
ranges of registers and increases register pressure, and usually
brings no gain (and if it happens to do, the cse pass will take care
of it anyway).  So prevent this behavior, unless it enabled us to
derive that the number of iterations is a constant.  */
    desc->niter_expr = old_niter;
  }

return;

2802zero_iter_simplify:
/* Simplify the assumptions.  */
simplify_using_initial_values (loop, AND, &desc->assumptions);
if (desc->assumptions
    && XEXP (desc->assumptions, 0)(((desc->assumptions)->u.fld[0]).rt_rtx) == const0_rtx(const_int_rtx[64]))
  goto fail;
simplify_using_initial_values (loop, IOR, &desc->infinite);

/* Fallthru.  */
2811zero_iter:
desc->const_iter = true;
desc->niter = 0;
record_niter_bound (loop, 0, true, true);
desc->noloop_assumptions = NULL_RTX(rtx) 0;
desc->niter_expr = const0_rtx(const_int_rtx[64]);
return;

2819fail:
desc->simple_p = false;
return;
2822}

2824/* Checks whether E is a simple exit from LOOP and stores its description
 into DESC.  */

2827static void
2828check_simple_exit (class loop *loop, edge e, class niter_desc *desc)
2829{
basic_block exit_bb;
rtx condition;
rtx_insn *at;
edge ein;

exit_bb = e->src;
desc->simple_p = false;

/* It must belong directly to the loop.  */
if (exit_bb->loop_father != loop)
  return;

/* It must be tested (at least) once during any iteration.  */
if (!dominated_by_p (CDI_DOMINATORS, loop->latch, exit_bb))
  return;

/* It must end in a simple conditional jump.  */
if (!any_condjump_p (BB_END (exit_bb)(exit_bb)->il.x.rtl->end_) || !onlyjump_p (BB_END (exit_bb)(exit_bb)->il.x.rtl->end_))
  return;

ein = EDGE_SUCC (exit_bb, 0)(*(exit_bb)->succs)[(0)];
if (ein == e)
  ein = EDGE_SUCC (exit_bb, 1)(*(exit_bb)->succs)[(1)];

desc->out_edge = e;
desc->in_edge = ein;

/* Test whether the condition is suitable.  */
if (!(condition = get_condition (BB_END (ein->src)(ein->src)->il.x.rtl->end_, &at, false, false)))
  return;

if (ein->flags & EDGE_FALLTHRU)
  {
    condition = reversed_condition (condition);
    if (!condition)
return;
  }

/* Check that we are able to determine number of iterations and fill
   in information about it.  */
iv_number_of_iterations (loop, at, condition, desc);
2871}

2873/* Finds a simple exit of LOOP and stores its description into DESC.  */

2875static void
2876find_simple_exit (class loop *loop, class niter_desc *desc)
2877{
unsigned i;
basic_block *body;
edge e;
class niter_desc act;
bool any = false;
edge_iterator ei;

desc->simple_p = false;
body = get_loop_body (loop);

for (i = 0; i < loop->num_nodes; i++)
  {
    FOR_EACH_EDGE (e, ei, body[i]->succs)for ((ei) = ei_start_1 (&((body[i]->succs))); ei_cond (
(ei), &(e)); ei_next (&(ei)))
{
 if (flow_bb_inside_loop_p (loop, e->dest))
   continue;

 check_simple_exit (loop, e, &act);
 if (!act.simple_p)
   continue;

 if (!any)
   any = true;
 else
   {
     /* Prefer constant iterations; the less the better.  */
     if (!act.const_iter
  || (desc->const_iter && act.niter >= desc->niter))
continue;

     /* Also if the actual exit may be infinite, while the old one
 not, prefer the old one.  */
     if (act.infinite && !desc->infinite)
continue;
   }

 *desc = act;
}
  }

if (dump_file)
  {
    if (desc->simple_p)
{
 fprintf (dump_file, "Loop %d is simple:\n", loop->num);
 fprintf (dump_file, "  simple exit %d -> %d\n",
   desc->out_edge->src->index,
   desc->out_edge->dest->index);
 if (desc->assumptions)
   {
     fprintf (dump_file, "  assumptions: ");
     print_rtl (dump_file, desc->assumptions);
     fprintf (dump_file, "\n");
   }
 if (desc->noloop_assumptions)
   {
     fprintf (dump_file, "  does not roll if: ");
     print_rtl (dump_file, desc->noloop_assumptions);
     fprintf (dump_file, "\n");
   }
 if (desc->infinite)
   {
     fprintf (dump_file, "  infinite if: ");
     print_rtl (dump_file, desc->infinite);
     fprintf (dump_file, "\n");
   }

 fprintf (dump_file, "  number of iterations: ");
 print_rtl (dump_file, desc->niter_expr);
    	  fprintf (dump_file, "\n");

 fprintf (dump_file, "  upper bound: %li\n",
   (long)get_max_loop_iterations_int (loop));
 fprintf (dump_file, "  likely upper bound: %li\n",
   (long)get_likely_max_loop_iterations_int (loop));
 fprintf (dump_file, "  realistic bound: %li\n",
   (long)get_estimated_loop_iterations_int (loop));
}
    else
fprintf (dump_file, "Loop %d is not simple.\n", loop->num);
  }

/* Fix up the finiteness if possible.  We can only do it for single exit,
   since the loop is finite, but it's possible that we predicate one loop
   exit to be finite which can not be determined as finite in middle-end as
   well.  It results in incorrect predicate information on the exit condition
   expression.  For example, if says [(int) _1 + -8, + , -8] != 0 finite,
   it means _1 can exactly divide -8.  */
if (desc->infinite && single_exit (loop) && finite_loop_p (loop))
  {
    desc->infinite = NULL_RTX(rtx) 0;
    if (dump_file)
fprintf (dump_file, "  infinite updated to finite.\n");
  }

free (body);
2974}

2976/* Creates a simple loop description of LOOP if it was not computed
 already.  */

2979class niter_desc *
2980get_simple_loop_desc (class loop *loop)
2981{
class niter_desc *desc = simple_loop_desc (loop);

if (desc)
  return desc;

/* At least desc->infinite is not always initialized by
   find_simple_loop_exit.  */
desc = ggc_cleared_alloc<niter_desc> ();
iv_analysis_loop_init (loop);
find_simple_exit (loop, desc);
loop->simple_loop_desc = desc;
return desc;
2994}

2996/* Releases simple loop description for LOOP.  */

2998void
2999free_simple_loop_desc (class loop *loop)
3000{
class niter_desc *desc = simple_loop_desc (loop);

if (!desc)
  return;

ggc_free (desc);
loop->simple_loop_desc = NULL__null;
3008}