Bug Summary

File:build/gcc/lra-constraints.c
Warning:line 4966, column 3
Value stored to 'changed_p' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-unknown-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name lra-constraints.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -resource-dir /usr/lib64/clang/13.0.0 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../include/c++/11 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../include/c++/11/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../include/c++/11/backward -internal-isystem /usr/lib64/clang/13.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/11/../../../../x86_64-suse-linux/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-error=format-diag -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir=/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2021-11-20-133755-20252-1/report-ASxjGX.plist -x c++ /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c
1/* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2021 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21
22/* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
24 split.
25
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
33
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
37 allocations;
38 o some heuristics to choose insn alternative to improve the
39 inheritance;
40 o early clobbers etc.
41
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
45 changed.
46
47 There is special code for preventing all LRA and this pass cycling
48 in case of bugs.
49
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
54
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
57 traversal of EBBs.
58
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
62
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
65 ... => ...
66 reload_p2 <- p reload_p2 <- new_p
67
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
70 pseudo*.
71
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
75
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
82 insns.
83
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
86
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
89 ... =>
90 ... r <- s (new insn -- restore)
91 ... <- r ... <- r
92
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
95
96 Splitting is done:
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
101
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
106
107#undef REG_OK_STRICT
108
109#include "config.h"
110#include "system.h"
111#include "coretypes.h"
112#include "backend.h"
113#include "target.h"
114#include "rtl.h"
115#include "tree.h"
116#include "predict.h"
117#include "df.h"
118#include "memmodel.h"
119#include "tm_p.h"
120#include "expmed.h"
121#include "optabs.h"
122#include "regs.h"
123#include "ira.h"
124#include "recog.h"
125#include "output.h"
126#include "addresses.h"
127#include "expr.h"
128#include "cfgrtl.h"
129#include "rtl-error.h"
130#include "lra.h"
131#include "lra-int.h"
132#include "print-rtl.h"
133#include "function-abi.h"
134#include "rtl-iter.h"
135
136/* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
137 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
138 reload insns. */
139static int bb_reload_num;
140
141/* The current insn being processed and corresponding its single set
142 (NULL otherwise), its data (basic block, the insn data, the insn
143 static data, and the mode of each operand). */
144static rtx_insn *curr_insn;
145static rtx curr_insn_set;
146static basic_block curr_bb;
147static lra_insn_recog_data_t curr_id;
148static struct lra_static_insn_data *curr_static_id;
149static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS30];
150/* Mode of the register substituted by its equivalence with VOIDmode
151 (e.g. constant) and whose subreg is given operand of the current
152 insn. VOIDmode in all other cases. */
153static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS30];
154
155
156
157/* Start numbers for new registers and insns at the current constraints
158 pass start. */
159static int new_regno_start;
160static int new_insn_uid_start;
161
162/* If LOC is nonnull, strip any outer subreg from it. */
163static inline rtx *
164strip_subreg (rtx *loc)
165{
166 return loc && GET_CODE (*loc)((enum rtx_code) (*loc)->code) == SUBREG ? &SUBREG_REG (*loc)(((*loc)->u.fld[0]).rt_rtx) : loc;
167}
168
169/* Return hard regno of REGNO or if it is was not assigned to a hard
170 register, use a hard register from its allocno class. */
171static int
172get_try_hard_regno (int regno)
173{
174 int hard_regno;
175 enum reg_class rclass;
176
177 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER76)
178 hard_regno = lra_get_regno_hard_regno (regno);
179 if (hard_regno >= 0)
180 return hard_regno;
181 rclass = lra_get_allocno_class (regno);
182 if (rclass == NO_REGS)
183 return -1;
184 return ira_class_hard_regs(this_target_ira->x_ira_class_hard_regs)[rclass][0];
185}
186
187/* Return the hard regno of X after removing its subreg. If X is not
188 a register or a subreg of a register, return -1. If X is a pseudo,
189 use its assignment. If FINAL_P return the final hard regno which will
190 be after elimination. */
191static int
192get_hard_regno (rtx x, bool final_p)
193{
194 rtx reg;
195 int hard_regno;
196
197 reg = x;
198 if (SUBREG_P (x)(((enum rtx_code) (x)->code) == SUBREG))
199 reg = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
200 if (! REG_P (reg)(((enum rtx_code) (reg)->code) == REG))
201 return -1;
202 if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg))((hard_regno = (rhs_regno(reg))) < 76))
203 hard_regno = lra_get_regno_hard_regno (hard_regno);
204 if (hard_regno < 0)
205 return -1;
206 if (final_p)
207 hard_regno = lra_get_elimination_hard_regno (hard_regno);
208 if (SUBREG_P (x)(((enum rtx_code) (x)->code) == SUBREG))
209 hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg)((machine_mode) (reg)->mode),
210 SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg), GET_MODE (x)((machine_mode) (x)->mode));
211 return hard_regno;
212}
213
214/* If REGNO is a hard register or has been allocated a hard register,
215 return the class of that register. If REGNO is a reload pseudo
216 created by the current constraints pass, return its allocno class.
217 Return NO_REGS otherwise. */
218static enum reg_class
219get_reg_class (int regno)
220{
221 int hard_regno;
222
223 if (! HARD_REGISTER_NUM_P (hard_regno = regno)((hard_regno = regno) < 76))
224 hard_regno = lra_get_regno_hard_regno (regno);
225 if (hard_regno >= 0)
226 {
227 hard_regno = lra_get_elimination_hard_regno (hard_regno);
228 return REGNO_REG_CLASS (hard_regno)(regclass_map[(hard_regno)]);
229 }
230 if (regno >= new_regno_start)
231 return lra_get_allocno_class (regno);
232 return NO_REGS;
233}
234
235/* Return true if REG satisfies (or will satisfy) reg class constraint
236 CL. Use elimination first if REG is a hard register. If REG is a
237 reload pseudo created by this constraints pass, assume that it will
238 be allocated a hard register from its allocno class, but allow that
239 class to be narrowed to CL if it is currently a superset of CL and
240 if either:
241
242 - ALLOW_ALL_RELOAD_CLASS_CHANGES_P is true or
243 - the instruction we're processing is not a reload move.
244
245 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
246 REGNO (reg), or NO_REGS if no change in its class was needed. */
247static bool
248in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class,
249 bool allow_all_reload_class_changes_p = false)
250{
251 enum reg_class rclass, common_class;
252 machine_mode reg_mode;
253 rtx src;
254 int class_size, hard_regno, nregs, i, j;
255 int regno = REGNO (reg)(rhs_regno(reg));
256
257 if (new_class != NULLnullptr)
258 *new_class = NO_REGS;
259 if (regno < FIRST_PSEUDO_REGISTER76)
260 {
261 rtx final_reg = reg;
262 rtx *final_loc = &final_reg;
263
264 lra_eliminate_reg_if_possible (final_loc);
265 return TEST_HARD_REG_BIT (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[cl], REGNO (*final_loc)(rhs_regno(*final_loc)));
266 }
267 reg_mode = GET_MODE (reg)((machine_mode) (reg)->mode);
268 rclass = get_reg_class (regno);
269 src = curr_insn_set != NULLnullptr ? SET_SRC (curr_insn_set)(((curr_insn_set)->u.fld[1]).rt_rtx) : NULLnullptr;
270 if (regno < new_regno_start
271 /* Do not allow the constraints for reload instructions to
272 influence the classes of new pseudos. These reloads are
273 typically moves that have many alternatives, and restricting
274 reload pseudos for one alternative may lead to situations
275 where other reload pseudos are no longer allocatable. */
276 || (!allow_all_reload_class_changes_p
277 && INSN_UID (curr_insn) >= new_insn_uid_start
278 && src != NULLnullptr
279 && ((REG_P (src)(((enum rtx_code) (src)->code) == REG) || MEM_P (src)(((enum rtx_code) (src)->code) == MEM))
280 || (GET_CODE (src)((enum rtx_code) (src)->code) == SUBREG
281 && (REG_P (SUBREG_REG (src))(((enum rtx_code) ((((src)->u.fld[0]).rt_rtx))->code) ==
REG)
|| MEM_P (SUBREG_REG (src))(((enum rtx_code) ((((src)->u.fld[0]).rt_rtx))->code) ==
MEM)
)))))
282 /* When we don't know what class will be used finally for reload
283 pseudos, we use ALL_REGS. */
284 return ((regno >= new_regno_start && rclass == ALL_REGS)
285 || (rclass != NO_REGS && ira_class_subset_p(this_target_ira->x_ira_class_subset_p)[rclass][cl]
286 && ! hard_reg_set_subset_p (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[cl],
287 lra_no_alloc_regs)));
288 else
289 {
290 common_class = ira_reg_class_subset(this_target_ira->x_ira_reg_class_subset)[rclass][cl];
291 if (new_class != NULLnullptr)
292 *new_class = common_class;
293 if (hard_reg_set_subset_p (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[common_class],
294 lra_no_alloc_regs))
295 return false;
296 /* Check that there are enough allocatable regs. */
297 class_size = ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[common_class];
298 for (i = 0; i < class_size; i++)
299 {
300 hard_regno = ira_class_hard_regs(this_target_ira->x_ira_class_hard_regs)[common_class][i];
301 nregs = hard_regno_nregs (hard_regno, reg_mode);
302 if (nregs == 1)
303 return true;
304 for (j = 0; j < nregs; j++)
305 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j)
306 || ! TEST_HARD_REG_BIT (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[common_class],
307 hard_regno + j))
308 break;
309 if (j >= nregs)
310 return true;
311 }
312 return false;
313 }
314}
315
316/* Return true if REGNO satisfies a memory constraint. */
317static bool
318in_mem_p (int regno)
319{
320 return get_reg_class (regno) == NO_REGS;
321}
322
323/* Return 1 if ADDR is a valid memory address for mode MODE in address
324 space AS, and check that each pseudo has the proper kind of hard
325 reg. */
326static int
327valid_address_p (machine_mode mode ATTRIBUTE_UNUSED__attribute__ ((__unused__)),
328 rtx addr, addr_space_t as)
329{
330#ifdef GO_IF_LEGITIMATE_ADDRESS
331 lra_assert (ADDR_SPACE_GENERIC_P (as))((void)(!(((as) == 0)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 331, __FUNCTION__), 0 : 0))
;
332 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
333 return 0;
334
335 win:
336 return 1;
337#else
338 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as);
339#endif
340}
341
342namespace {
343 /* Temporarily eliminates registers in an address (for the lifetime of
344 the object). */
345 class address_eliminator {
346 public:
347 address_eliminator (struct address_info *ad);
348 ~address_eliminator ();
349
350 private:
351 struct address_info *m_ad;
352 rtx *m_base_loc;
353 rtx m_base_reg;
354 rtx *m_index_loc;
355 rtx m_index_reg;
356 };
357}
358
359address_eliminator::address_eliminator (struct address_info *ad)
360 : m_ad (ad),
361 m_base_loc (strip_subreg (ad->base_term)),
362 m_base_reg (NULL_RTX(rtx) 0),
363 m_index_loc (strip_subreg (ad->index_term)),
364 m_index_reg (NULL_RTX(rtx) 0)
365{
366 if (m_base_loc != NULLnullptr)
367 {
368 m_base_reg = *m_base_loc;
369 /* If we have non-legitimate address which is decomposed not in
370 the way we expected, don't do elimination here. In such case
371 the address will be reloaded and elimination will be done in
372 reload insn finally. */
373 if (REG_P (m_base_reg)(((enum rtx_code) (m_base_reg)->code) == REG))
374 lra_eliminate_reg_if_possible (m_base_loc);
375 if (m_ad->base_term2 != NULLnullptr)
376 *m_ad->base_term2 = *m_ad->base_term;
377 }
378 if (m_index_loc != NULLnullptr)
379 {
380 m_index_reg = *m_index_loc;
381 if (REG_P (m_index_reg)(((enum rtx_code) (m_index_reg)->code) == REG))
382 lra_eliminate_reg_if_possible (m_index_loc);
383 }
384}
385
386address_eliminator::~address_eliminator ()
387{
388 if (m_base_loc && *m_base_loc != m_base_reg)
389 {
390 *m_base_loc = m_base_reg;
391 if (m_ad->base_term2 != NULLnullptr)
392 *m_ad->base_term2 = *m_ad->base_term;
393 }
394 if (m_index_loc && *m_index_loc != m_index_reg)
395 *m_index_loc = m_index_reg;
396}
397
398/* Return true if the eliminated form of AD is a legitimate target address.
399 If OP is a MEM, AD is the address within OP, otherwise OP should be
400 ignored. CONSTRAINT is one constraint that the operand may need
401 to meet. */
402static bool
403valid_address_p (rtx op, struct address_info *ad,
404 enum constraint_num constraint)
405{
406 address_eliminator eliminator (ad);
407
408 /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more
409 forgiving than "m".
410 Need to extract memory from op for special memory constraint,
411 i.e. bcst_mem_operand in i386 backend. */
412 if (MEM_P (extract_mem_from_operand (op))(((enum rtx_code) (extract_mem_from_operand (op))->code) ==
MEM)
413 && insn_extra_relaxed_memory_constraint (constraint)
414 && constraint_satisfied_p (op, constraint))
415 return true;
416
417 return valid_address_p (ad->mode, *ad->outer, ad->as);
418}
419
420/* For special_memory_operand, it could be false for MEM_P (op),
421 i.e. bcst_mem_operand in i386 backend.
422 Extract and return real memory operand or op. */
423rtx
424extract_mem_from_operand (rtx op)
425{
426 for (rtx x = op;; x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
427 {
428 if (MEM_P (x)(((enum rtx_code) (x)->code) == MEM))
429 return x;
430 if (GET_RTX_LENGTH (GET_CODE (x))(rtx_length[(int) (((enum rtx_code) (x)->code))]) != 1
431 || GET_RTX_FORMAT (GET_CODE (x))(rtx_format[(int) (((enum rtx_code) (x)->code))])[0] != 'e')
432 break;
433 }
434 return op;
435}
436
437/* Return true if the eliminated form of memory reference OP satisfies
438 extra (special) memory constraint CONSTRAINT. */
439static bool
440satisfies_memory_constraint_p (rtx op, enum constraint_num constraint)
441{
442 struct address_info ad;
443 rtx mem = extract_mem_from_operand (op);
444 if (!MEM_P (mem)(((enum rtx_code) (mem)->code) == MEM))
445 return false;
446
447 decompose_mem_address (&ad, mem);
448 address_eliminator eliminator (&ad);
449 return constraint_satisfied_p (op, constraint);
450}
451
452/* Return true if the eliminated form of address AD satisfies extra
453 address constraint CONSTRAINT. */
454static bool
455satisfies_address_constraint_p (struct address_info *ad,
456 enum constraint_num constraint)
457{
458 address_eliminator eliminator (ad);
459 return constraint_satisfied_p (*ad->outer, constraint);
460}
461
462/* Return true if the eliminated form of address OP satisfies extra
463 address constraint CONSTRAINT. */
464static bool
465satisfies_address_constraint_p (rtx op, enum constraint_num constraint)
466{
467 struct address_info ad;
468
469 decompose_lea_address (&ad, &op);
470 return satisfies_address_constraint_p (&ad, constraint);
471}
472
473/* Initiate equivalences for LRA. As we keep original equivalences
474 before any elimination, we need to make copies otherwise any change
475 in insns might change the equivalences. */
476void
477lra_init_equiv (void)
478{
479 ira_expand_reg_equiv ();
480 for (int i = FIRST_PSEUDO_REGISTER76; i < max_reg_num (); i++)
481 {
482 rtx res;
483
484 if ((res = ira_reg_equiv[i].memory) != NULL_RTX(rtx) 0)
485 ira_reg_equiv[i].memory = copy_rtx (res);
486 if ((res = ira_reg_equiv[i].invariant) != NULL_RTX(rtx) 0)
487 ira_reg_equiv[i].invariant = copy_rtx (res);
488 }
489}
490
491static rtx loc_equivalence_callback (rtx, const_rtx, void *);
492
493/* Update equivalence for REGNO. We need to this as the equivalence
494 might contain other pseudos which are changed by their
495 equivalences. */
496static void
497update_equiv (int regno)
498{
499 rtx x;
500
501 if ((x = ira_reg_equiv[regno].memory) != NULL_RTX(rtx) 0)
502 ira_reg_equiv[regno].memory
503 = simplify_replace_fn_rtx (x, NULL_RTX(rtx) 0, loc_equivalence_callback,
504 NULL_RTX(rtx) 0);
505 if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX(rtx) 0)
506 ira_reg_equiv[regno].invariant
507 = simplify_replace_fn_rtx (x, NULL_RTX(rtx) 0, loc_equivalence_callback,
508 NULL_RTX(rtx) 0);
509}
510
511/* If we have decided to substitute X with another value, return that
512 value, otherwise return X. */
513static rtx
514get_equiv (rtx x)
515{
516 int regno;
517 rtx res;
518
519 if (! REG_P (x)(((enum rtx_code) (x)->code) == REG) || (regno = REGNO (x)(rhs_regno(x))) < FIRST_PSEUDO_REGISTER76
520 || ! ira_reg_equiv[regno].defined_p
521 || ! ira_reg_equiv[regno].profitable_p
522 || lra_get_regno_hard_regno (regno) >= 0)
523 return x;
524 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX(rtx) 0)
525 {
526 if (targetm.cannot_substitute_mem_equiv_p (res))
527 return x;
528 return res;
529 }
530 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX(rtx) 0)
531 return res;
532 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX(rtx) 0)
533 return res;
534 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 534, __FUNCTION__))
;
535}
536
537/* If we have decided to substitute X with the equivalent value,
538 return that value after elimination for INSN, otherwise return
539 X. */
540static rtx
541get_equiv_with_elimination (rtx x, rtx_insn *insn)
542{
543 rtx res = get_equiv (x);
544
545 if (x == res || CONSTANT_P (res)((rtx_class[(int) (((enum rtx_code) (res)->code))]) == RTX_CONST_OBJ
)
)
546 return res;
547 return lra_eliminate_regs_1 (insn, res, GET_MODE (res)((machine_mode) (res)->mode),
548 false, false, 0, true);
549}
550
551/* Set up curr_operand_mode. */
552static void
553init_curr_operand_mode (void)
554{
555 int nop = curr_static_id->n_operands;
556 for (int i = 0; i < nop; i++)
557 {
558 machine_mode mode = GET_MODE (*curr_id->operand_loc[i])((machine_mode) (*curr_id->operand_loc[i])->mode);
559 if (mode == VOIDmode((void) 0, E_VOIDmode))
560 {
561 /* The .md mode for address operands is the mode of the
562 addressed value rather than the mode of the address itself. */
563 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address)
564 mode = Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
;
565 else
566 mode = curr_static_id->operand[i].mode;
567 }
568 curr_operand_mode[i] = mode;
569 }
570}
571
572
573
574/* The page contains code to reuse input reloads. */
575
576/* Structure describes input reload of the current insns. */
577struct input_reload
578{
579 /* True for input reload of matched operands. */
580 bool match_p;
581 /* Reloaded value. */
582 rtx input;
583 /* Reload pseudo used. */
584 rtx reg;
585};
586
587/* The number of elements in the following array. */
588static int curr_insn_input_reloads_num;
589/* Array containing info about input reloads. It is used to find the
590 same input reload and reuse the reload pseudo in this case. */
591static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS(30 * 3)];
592
593/* Initiate data concerning reuse of input reloads for the current
594 insn. */
595static void
596init_curr_insn_input_reloads (void)
597{
598 curr_insn_input_reloads_num = 0;
599}
600
601/* The canonical form of an rtx inside a MEM is not necessarily the same as the
602 canonical form of the rtx outside the MEM. Fix this up in the case that
603 we're reloading an address (and therefore pulling it outside a MEM). */
604static rtx
605canonicalize_reload_addr (rtx addr)
606{
607 subrtx_var_iterator::array_type array;
608 FOR_EACH_SUBRTX_VAR (iter, array, addr, NONCONST)for (subrtx_var_iterator iter (array, addr, rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
609 {
610 rtx x = *iter;
611 if (GET_CODE (x)((enum rtx_code) (x)->code) == MULT && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
)
612 {
613 const HOST_WIDE_INTlong ci = INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]);
614 const int pwr2 = exact_log2 (ci);
615 if (pwr2 > 0)
616 {
617 /* Rewrite this to use a shift instead, which is canonical when
618 outside of a MEM. */
619 PUT_CODE (x, ASHIFT)((x)->code = (ASHIFT));
620 XEXP (x, 1)(((x)->u.fld[1]).rt_rtx) = GEN_INT (pwr2)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (pwr2));
621 }
622 }
623 }
624
625 return addr;
626}
627
628/* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse an existing
629 reload pseudo. Don't reuse an existing reload pseudo if IN_SUBREG_P
630 is true and the reused pseudo should be wrapped up in a SUBREG.
631 The result pseudo is returned through RESULT_REG. Return TRUE if we
632 created a new pseudo, FALSE if we reused an existing reload pseudo.
633 Use TITLE to describe new registers for debug purposes. */
634static bool
635get_reload_reg (enum op_type type, machine_mode mode, rtx original,
636 enum reg_class rclass, bool in_subreg_p,
637 const char *title, rtx *result_reg)
638{
639 int i, regno;
640 enum reg_class new_class;
641 bool unique_p = false;
642
643 if (type == OP_OUT)
644 {
645 /* Output reload registers tend to start out with a conservative
646 choice of register class. Usually this is ALL_REGS, although
647 a target might narrow it (for performance reasons) through
648 targetm.preferred_reload_class. It's therefore quite common
649 for a reload instruction to require a more restrictive class
650 than the class that was originally assigned to the reload register.
651
652 In these situations, it's more efficient to refine the choice
653 of register class rather than create a second reload register.
654 This also helps to avoid cycling for registers that are only
655 used by reload instructions. */
656 if (REG_P (original)(((enum rtx_code) (original)->code) == REG)
657 && (int) REGNO (original)(rhs_regno(original)) >= new_regno_start
658 && INSN_UID (curr_insn) >= new_insn_uid_start
659 && in_class_p (original, rclass, &new_class, true))
660 {
661 unsigned int regno = REGNO (original)(rhs_regno(original));
662 if (lra_dump_file != NULLnullptr)
663 {
664 fprintf (lra_dump_file, " Reuse r%d for output ", regno);
665 dump_value_slim (lra_dump_file, original, 1);
666 }
667 if (new_class != lra_get_allocno_class (regno))
668 lra_change_class (regno, new_class, ", change to", false);
669 if (lra_dump_file != NULLnullptr)
670 fprintf (lra_dump_file, "\n");
671 *result_reg = original;
672 return false;
673 }
674 *result_reg
675 = lra_create_new_reg_with_unique_value (mode, original, rclass, title);
676 return true;
677 }
678 /* Prevent reuse value of expression with side effects,
679 e.g. volatile memory. */
680 if (! side_effects_p (original))
681 for (i = 0; i < curr_insn_input_reloads_num; i++)
682 {
683 if (! curr_insn_input_reloads[i].match_p
684 && rtx_equal_p (curr_insn_input_reloads[i].input, original)
685 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class))
686 {
687 rtx reg = curr_insn_input_reloads[i].reg;
688 regno = REGNO (reg)(rhs_regno(reg));
689 /* If input is equal to original and both are VOIDmode,
690 GET_MODE (reg) might be still different from mode.
691 Ensure we don't return *result_reg with wrong mode. */
692 if (GET_MODE (reg)((machine_mode) (reg)->mode) != mode)
693 {
694 if (in_subreg_p)
695 continue;
696 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)((machine_mode) (reg)->mode)),
697 GET_MODE_SIZE (mode)))
698 continue;
699 reg = lowpart_subreg (mode, reg, GET_MODE (reg)((machine_mode) (reg)->mode));
700 if (reg == NULL_RTX(rtx) 0 || GET_CODE (reg)((enum rtx_code) (reg)->code) != SUBREG)
701 continue;
702 }
703 *result_reg = reg;
704 if (lra_dump_file != NULLnullptr)
705 {
706 fprintf (lra_dump_file, " Reuse r%d for reload ", regno);
707 dump_value_slim (lra_dump_file, original, 1);
708 }
709 if (new_class != lra_get_allocno_class (regno))
710 lra_change_class (regno, new_class, ", change to", false);
711 if (lra_dump_file != NULLnullptr)
712 fprintf (lra_dump_file, "\n");
713 return false;
714 }
715 /* If we have an input reload with a different mode, make sure it
716 will get a different hard reg. */
717 else if (REG_P (original)(((enum rtx_code) (original)->code) == REG)
718 && REG_P (curr_insn_input_reloads[i].input)(((enum rtx_code) (curr_insn_input_reloads[i].input)->code
) == REG)
719 && REGNO (original)(rhs_regno(original)) == REGNO (curr_insn_input_reloads[i].input)(rhs_regno(curr_insn_input_reloads[i].input))
720 && (GET_MODE (original)((machine_mode) (original)->mode)
721 != GET_MODE (curr_insn_input_reloads[i].input)((machine_mode) (curr_insn_input_reloads[i].input)->mode)))
722 unique_p = true;
723 }
724 *result_reg = (unique_p
725 ? lra_create_new_reg_with_unique_value
726 : lra_create_new_reg) (mode, original, rclass, title);
727 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS)((void)(!(curr_insn_input_reloads_num < (30 * 3)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 727, __FUNCTION__), 0 : 0))
;
728 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original;
729 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false;
730 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg;
731 return true;
732}
733
734
735/* The page contains major code to choose the current insn alternative
736 and generate reloads for it. */
737
738/* Return the offset from REGNO of the least significant register
739 in (reg:MODE REGNO).
740
741 This function is used to tell whether two registers satisfy
742 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
743
744 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
745 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
746int
747lra_constraint_offset (int regno, machine_mode mode)
748{
749 lra_assert (regno < FIRST_PSEUDO_REGISTER)((void)(!(regno < 76) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 749, __FUNCTION__), 0 : 0))
;
750
751 scalar_int_mode int_mode;
752 if (WORDS_BIG_ENDIAN0
753 && is_a <scalar_int_mode> (mode, &int_mode)
754 && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
0) ? 8 : 4)
)
755 return hard_regno_nregs (regno, mode) - 1;
756 return 0;
757}
758
759/* Like rtx_equal_p except that it allows a REG and a SUBREG to match
760 if they are the same hard reg, and has special hacks for
761 auto-increment and auto-decrement. This is specifically intended for
762 process_alt_operands to use in determining whether two operands
763 match. X is the operand whose number is the lower of the two.
764
765 It is supposed that X is the output operand and Y is the input
766 operand. Y_HARD_REGNO is the final hard regno of register Y or
767 register in subreg Y as we know it now. Otherwise, it is a
768 negative value. */
769static bool
770operands_match_p (rtx x, rtx y, int y_hard_regno)
771{
772 int i;
773 RTX_CODEenum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
774 const char *fmt;
775
776 if (x == y)
777 return true;
778 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
))
779 && (REG_P (y)(((enum rtx_code) (y)->code) == REG) || (GET_CODE (y)((enum rtx_code) (y)->code) == SUBREG && REG_P (SUBREG_REG (y))(((enum rtx_code) ((((y)->u.fld[0]).rt_rtx))->code) == REG
)
)))
780 {
781 int j;
782
783 i = get_hard_regno (x, false);
784 if (i < 0)
785 goto slow;
786
787 if ((j = y_hard_regno) < 0)
788 goto slow;
789
790 i += lra_constraint_offset (i, GET_MODE (x)((machine_mode) (x)->mode));
791 j += lra_constraint_offset (j, GET_MODE (y)((machine_mode) (y)->mode));
792
793 return i == j;
794 }
795
796 /* If two operands must match, because they are really a single
797 operand of an assembler insn, then two post-increments are invalid
798 because the assembler insn would increment only once. On the
799 other hand, a post-increment matches ordinary indexing if the
800 post-increment is the output operand. */
801 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
802 return operands_match_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), y, y_hard_regno);
803
804 /* Two pre-increments are invalid because the assembler insn would
805 increment only once. On the other hand, a pre-increment matches
806 ordinary indexing if the pre-increment is the input operand. */
807 if (GET_CODE (y)((enum rtx_code) (y)->code) == PRE_DEC || GET_CODE (y)((enum rtx_code) (y)->code) == PRE_INC
808 || GET_CODE (y)((enum rtx_code) (y)->code) == PRE_MODIFY)
809 return operands_match_p (x, XEXP (y, 0)(((y)->u.fld[0]).rt_rtx), -1);
810
811 slow:
812
813 if (code == REG && REG_P (y)(((enum rtx_code) (y)->code) == REG))
814 return REGNO (x)(rhs_regno(x)) == REGNO (y)(rhs_regno(y));
815
816 if (code == REG && GET_CODE (y)((enum rtx_code) (y)->code) == SUBREG && REG_P (SUBREG_REG (y))(((enum rtx_code) ((((y)->u.fld[0]).rt_rtx))->code) == REG
)
817 && x == SUBREG_REG (y)(((y)->u.fld[0]).rt_rtx))
818 return true;
819 if (GET_CODE (y)((enum rtx_code) (y)->code) == REG && code == SUBREG && REG_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
820 && SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx) == y)
821 return true;
822
823 /* Now we have disposed of all the cases in which different rtx
824 codes can match. */
825 if (code != GET_CODE (y)((enum rtx_code) (y)->code))
826 return false;
827
828 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
829 if (GET_MODE (x)((machine_mode) (x)->mode) != GET_MODE (y)((machine_mode) (y)->mode))
830 return false;
831
832 switch (code)
833 {
834 CASE_CONST_UNIQUEcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED
:
835 return false;
836
837 case CONST_VECTOR:
838 if (!same_vector_encodings_p (x, y))
839 return false;
840 break;
841
842 case LABEL_REF:
843 return label_ref_label (x) == label_ref_label (y);
844 case SYMBOL_REF:
845 return XSTR (x, 0)(((x)->u.fld[0]).rt_str) == XSTR (y, 0)(((y)->u.fld[0]).rt_str);
846
847 default:
848 break;
849 }
850
851 /* Compare the elements. If any pair of corresponding elements fail
852 to match, return false for the whole things. */
853
854 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
855 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
856 {
857 int val, j;
858 switch (fmt[i])
859 {
860 case 'w':
861 if (XWINT (x, i)((x)->u.hwint[i]) != XWINT (y, i)((y)->u.hwint[i]))
862 return false;
863 break;
864
865 case 'i':
866 if (XINT (x, i)(((x)->u.fld[i]).rt_int) != XINT (y, i)(((y)->u.fld[i]).rt_int))
867 return false;
868 break;
869
870 case 'p':
871 if (maybe_ne (SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg), SUBREG_BYTE (y)(((y)->u.fld[1]).rt_subreg)))
872 return false;
873 break;
874
875 case 'e':
876 val = operands_match_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), XEXP (y, i)(((y)->u.fld[i]).rt_rtx), -1);
877 if (val == 0)
878 return false;
879 break;
880
881 case '0':
882 break;
883
884 case 'E':
885 if (XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) != XVECLEN (y, i)(((((y)->u.fld[i]).rt_rtvec))->num_elem))
886 return false;
887 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; --j)
888 {
889 val = operands_match_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), XVECEXP (y, i, j)(((((y)->u.fld[i]).rt_rtvec))->elem[j]), -1);
890 if (val == 0)
891 return false;
892 }
893 break;
894
895 /* It is believed that rtx's at this level will never
896 contain anything but integers and other rtx's, except for
897 within LABEL_REFs and SYMBOL_REFs. */
898 default:
899 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 899, __FUNCTION__))
;
900 }
901 }
902 return true;
903}
904
905/* True if X is a constant that can be forced into the constant pool.
906 MODE is the mode of the operand, or VOIDmode if not known. */
907#define CONST_POOL_OK_P(MODE, X)((MODE) != ((void) 0, E_VOIDmode) && ((rtx_class[(int
) (((enum rtx_code) (X)->code))]) == RTX_CONST_OBJ) &&
((enum rtx_code) (X)->code) != HIGH && GET_MODE_SIZE
(MODE).is_constant () && !targetm.cannot_force_const_mem
(MODE, X))
\
908 ((MODE) != VOIDmode((void) 0, E_VOIDmode) \
909 && CONSTANT_P (X)((rtx_class[(int) (((enum rtx_code) (X)->code))]) == RTX_CONST_OBJ
)
\
910 && GET_CODE (X)((enum rtx_code) (X)->code) != HIGH \
911 && GET_MODE_SIZE (MODE).is_constant () \
912 && !targetm.cannot_force_const_mem (MODE, X))
913
914/* True if C is a non-empty register class that has too few registers
915 to be safely used as a reload target class. */
916#define SMALL_REGISTER_CLASS_P(C)((this_target_ira->x_ira_class_hard_regs_num) [(C)] == 1 ||
((this_target_ira->x_ira_class_hard_regs_num) [(C)] >=
1 && targetm.class_likely_spilled_p (C)))
\
917 (ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num) [(C)] == 1 \
918 || (ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num) [(C)] >= 1 \
919 && targetm.class_likely_spilled_p (C)))
920
921/* If REG is a reload pseudo, try to make its class satisfying CL. */
922static void
923narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
924{
925 enum reg_class rclass;
926
927 /* Do not make more accurate class from reloads generated. They are
928 mostly moves with a lot of constraints. Making more accurate
929 class may results in very narrow class and impossibility of find
930 registers for several reloads of one insn. */
931 if (INSN_UID (curr_insn) >= new_insn_uid_start)
932 return;
933 if (GET_CODE (reg)((enum rtx_code) (reg)->code) == SUBREG)
934 reg = SUBREG_REG (reg)(((reg)->u.fld[0]).rt_rtx);
935 if (! REG_P (reg)(((enum rtx_code) (reg)->code) == REG) || (int) REGNO (reg)(rhs_regno(reg)) < new_regno_start)
936 return;
937 if (in_class_p (reg, cl, &rclass) && rclass != cl)
938 lra_change_class (REGNO (reg)(rhs_regno(reg)), rclass, " Change to", true);
939}
940
941/* Searches X for any reference to a reg with the same value as REGNO,
942 returning the rtx of the reference found if any. Otherwise,
943 returns NULL_RTX. */
944static rtx
945regno_val_use_in (unsigned int regno, rtx x)
946{
947 const char *fmt;
948 int i, j;
949 rtx tem;
950
951 if (REG_P (x)(((enum rtx_code) (x)->code) == REG) && lra_reg_info[REGNO (x)(rhs_regno(x))].val == lra_reg_info[regno].val)
952 return x;
953
954 fmt = GET_RTX_FORMAT (GET_CODE (x))(rtx_format[(int) (((enum rtx_code) (x)->code))]);
955 for (i = GET_RTX_LENGTH (GET_CODE (x))(rtx_length[(int) (((enum rtx_code) (x)->code))]) - 1; i >= 0; i--)
956 {
957 if (fmt[i] == 'e')
958 {
959 if ((tem = regno_val_use_in (regno, XEXP (x, i)(((x)->u.fld[i]).rt_rtx))))
960 return tem;
961 }
962 else if (fmt[i] == 'E')
963 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
964 if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]))))
965 return tem;
966 }
967
968 return NULL_RTX(rtx) 0;
969}
970
971/* Return true if all current insn non-output operands except INS (it
972 has a negaitve end marker) do not use pseudos with the same value
973 as REGNO. */
974static bool
975check_conflict_input_operands (int regno, signed char *ins)
976{
977 int in;
978 int n_operands = curr_static_id->n_operands;
979
980 for (int nop = 0; nop < n_operands; nop++)
981 if (! curr_static_id->operand[nop].is_operator
982 && curr_static_id->operand[nop].type != OP_OUT)
983 {
984 for (int i = 0; (in = ins[i]) >= 0; i++)
985 if (in == nop)
986 break;
987 if (in < 0
988 && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX(rtx) 0)
989 return false;
990 }
991 return true;
992}
993
994/* Generate reloads for matching OUT and INS (array of input operand
995 numbers with end marker -1) with reg class GOAL_CLASS, considering
996 output operands OUTS (similar array to INS) needing to be in different
997 registers. Add input and output reloads correspondingly to the lists
998 *BEFORE and *AFTER. OUT might be negative. In this case we generate
999 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
1000 that the output operand is early clobbered for chosen alternative. */
1001static void
1002match_reload (signed char out, signed char *ins, signed char *outs,
1003 enum reg_class goal_class, rtx_insn **before,
1004 rtx_insn **after, bool early_clobber_p)
1005{
1006 bool out_conflict;
1007 int i, in;
1008 rtx new_in_reg, new_out_reg, reg;
1009 machine_mode inmode, outmode;
1010 rtx in_rtx = *curr_id->operand_loc[ins[0]];
1011 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out];
1012
1013 inmode = curr_operand_mode[ins[0]];
1014 outmode = out < 0 ? inmode : curr_operand_mode[out];
1015 push_to_sequence (*before);
1016 if (inmode != outmode)
1017 {
1018 /* process_alt_operands has already checked that the mode sizes
1019 are ordered. */
1020 if (partial_subreg_p (outmode, inmode))
1021 {
1022 reg = new_in_reg
1023 = lra_create_new_reg_with_unique_value (inmode, in_rtx,
1024 goal_class, "");
1025 new_out_reg = gen_lowpart_SUBREG (outmode, reg);
1026 LRA_SUBREG_P (new_out_reg)(__extension__ ({ __typeof ((new_out_reg)) const _rtx = ((new_out_reg
)); if (((enum rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag
("LRA_SUBREG_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1026, __FUNCTION__); _rtx; })->jump)
= 1;
1027 /* If the input reg is dying here, we can use the same hard
1028 register for REG and IN_RTX. We do it only for original
1029 pseudos as reload pseudos can die although original
1030 pseudos still live where reload pseudos dies. */
1031 if (REG_P (in_rtx)(((enum rtx_code) (in_rtx)->code) == REG) && (int) REGNO (in_rtx)(rhs_regno(in_rtx)) < lra_new_regno_start
1032 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)(rhs_regno(in_rtx)))
1033 && (!early_clobber_p
1034 || check_conflict_input_operands(REGNO (in_rtx)(rhs_regno(in_rtx)), ins)))
1035 lra_assign_reg_val (REGNO (in_rtx)(rhs_regno(in_rtx)), REGNO (reg)(rhs_regno(reg)));
1036 }
1037 else
1038 {
1039 reg = new_out_reg
1040 = lra_create_new_reg_with_unique_value (outmode, out_rtx,
1041 goal_class, "");
1042 new_in_reg = gen_lowpart_SUBREG (inmode, reg);
1043 /* NEW_IN_REG is non-paradoxical subreg. We don't want
1044 NEW_OUT_REG living above. We add clobber clause for
1045 this. This is just a temporary clobber. We can remove
1046 it at the end of LRA work. */
1047 rtx_insn *clobber = emit_clobber (new_out_reg);
1048 LRA_TEMP_CLOBBER_P (PATTERN (clobber))(__extension__ ({ __typeof ((PATTERN (clobber))) const _rtx =
((PATTERN (clobber))); if (((enum rtx_code) (_rtx)->code)
!= CLOBBER) rtl_check_failed_flag ("TEMP_CLOBBER_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1048, __FUNCTION__); _rtx; })->unchanging)
= 1;
1049 LRA_SUBREG_P (new_in_reg)(__extension__ ({ __typeof ((new_in_reg)) const _rtx = ((new_in_reg
)); if (((enum rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag
("LRA_SUBREG_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1049, __FUNCTION__); _rtx; })->jump)
= 1;
1050 if (GET_CODE (in_rtx)((enum rtx_code) (in_rtx)->code) == SUBREG)
1051 {
1052 rtx subreg_reg = SUBREG_REG (in_rtx)(((in_rtx)->u.fld[0]).rt_rtx);
1053
1054 /* If SUBREG_REG is dying here and sub-registers IN_RTX
1055 and NEW_IN_REG are similar, we can use the same hard
1056 register for REG and SUBREG_REG. */
1057 if (REG_P (subreg_reg)(((enum rtx_code) (subreg_reg)->code) == REG)
1058 && (int) REGNO (subreg_reg)(rhs_regno(subreg_reg)) < lra_new_regno_start
1059 && GET_MODE (subreg_reg)((machine_mode) (subreg_reg)->mode) == outmode
1060 && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg))(!maybe_ne ((((in_rtx)->u.fld[1]).rt_subreg), (((new_in_reg
)->u.fld[1]).rt_subreg)))
1061 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)(rhs_regno(subreg_reg)))
1062 && (! early_clobber_p
1063 || check_conflict_input_operands (REGNO (subreg_reg)(rhs_regno(subreg_reg)),
1064 ins)))
1065 lra_assign_reg_val (REGNO (subreg_reg)(rhs_regno(subreg_reg)), REGNO (reg)(rhs_regno(reg)));
1066 }
1067 }
1068 }
1069 else
1070 {
1071 /* Pseudos have values -- see comments for lra_reg_info.
1072 Different pseudos with the same value do not conflict even if
1073 they live in the same place. When we create a pseudo we
1074 assign value of original pseudo (if any) from which we
1075 created the new pseudo. If we create the pseudo from the
1076 input pseudo, the new pseudo will have no conflict with the
1077 input pseudo which is wrong when the input pseudo lives after
1078 the insn and as the new pseudo value is changed by the insn
1079 output. Therefore we create the new pseudo from the output
1080 except the case when we have single matched dying input
1081 pseudo.
1082
1083 We cannot reuse the current output register because we might
1084 have a situation like "a <- a op b", where the constraints
1085 force the second input operand ("b") to match the output
1086 operand ("a"). "b" must then be copied into a new register
1087 so that it doesn't clobber the current value of "a".
1088
1089 We cannot use the same value if the output pseudo is
1090 early clobbered or the input pseudo is mentioned in the
1091 output, e.g. as an address part in memory, because
1092 output reload will actually extend the pseudo liveness.
1093 We don't care about eliminable hard regs here as we are
1094 interesting only in pseudos. */
1095
1096 /* Matching input's register value is the same as one of the other
1097 output operand. Output operands in a parallel insn must be in
1098 different registers. */
1099 out_conflict = false;
1100 if (REG_P (in_rtx)(((enum rtx_code) (in_rtx)->code) == REG))
1101 {
1102 for (i = 0; outs[i] >= 0; i++)
1103 {
1104 rtx other_out_rtx = *curr_id->operand_loc[outs[i]];
1105 if (outs[i] != out && REG_P (other_out_rtx)(((enum rtx_code) (other_out_rtx)->code) == REG)
1106 && (regno_val_use_in (REGNO (in_rtx)(rhs_regno(in_rtx)), other_out_rtx)
1107 != NULL_RTX(rtx) 0))
1108 {
1109 out_conflict = true;
1110 break;
1111 }
1112 }
1113 }
1114
1115 new_in_reg = new_out_reg
1116 = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx)(((enum rtx_code) (in_rtx)->code) == REG)
1117 && (int) REGNO (in_rtx)(rhs_regno(in_rtx)) < lra_new_regno_start
1118 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)(rhs_regno(in_rtx)))
1119 && (! early_clobber_p
1120 || check_conflict_input_operands (REGNO (in_rtx)(rhs_regno(in_rtx)), ins))
1121 && (out < 0
1122 || regno_val_use_in (REGNO (in_rtx)(rhs_regno(in_rtx)), out_rtx) == NULL_RTX(rtx) 0)
1123 && !out_conflict
1124 ? lra_create_new_reg (inmode, in_rtx, goal_class, "")
1125 : lra_create_new_reg_with_unique_value (outmode, out_rtx,
1126 goal_class, ""));
1127 }
1128 /* In operand can be got from transformations before processing insn
1129 constraints. One example of such transformations is subreg
1130 reloading (see function simplify_operand_subreg). The new
1131 pseudos created by the transformations might have inaccurate
1132 class (ALL_REGS) and we should make their classes more
1133 accurate. */
1134 narrow_reload_pseudo_class (in_rtx, goal_class);
1135 lra_emit_move (copy_rtx (new_in_reg), in_rtx);
1136 *before = get_insns ();
1137 end_sequence ();
1138 /* Add the new pseudo to consider values of subsequent input reload
1139 pseudos. */
1140 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS)((void)(!(curr_insn_input_reloads_num < (30 * 3)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1140, __FUNCTION__), 0 : 0))
;
1141 curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx;
1142 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true;
1143 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg;
1144 for (i = 0; (in = ins[i]) >= 0; i++)
1145 if (GET_MODE (*curr_id->operand_loc[in])((machine_mode) (*curr_id->operand_loc[in])->mode) == VOIDmode((void) 0, E_VOIDmode)
1146 || GET_MODE (new_in_reg)((machine_mode) (new_in_reg)->mode) == GET_MODE (*curr_id->operand_loc[in])((machine_mode) (*curr_id->operand_loc[in])->mode))
1147 *curr_id->operand_loc[in] = new_in_reg;
1148 else
1149 {
1150 lra_assert((void)(!(((machine_mode) (new_out_reg)->mode) == ((machine_mode
) (*curr_id->operand_loc[in])->mode)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1151, __FUNCTION__), 0 : 0))
1151 (GET_MODE (new_out_reg) == GET_MODE (*curr_id->operand_loc[in]))((void)(!(((machine_mode) (new_out_reg)->mode) == ((machine_mode
) (*curr_id->operand_loc[in])->mode)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1151, __FUNCTION__), 0 : 0))
;
1152 *curr_id->operand_loc[in] = new_out_reg;
1153 }
1154 lra_update_dups (curr_id, ins);
1155 if (out < 0)
1156 return;
1157 /* See a comment for the input operand above. */
1158 narrow_reload_pseudo_class (out_rtx, goal_class);
1159 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX(rtx) 0)
1160 {
1161 reg = SUBREG_P (out_rtx)(((enum rtx_code) (out_rtx)->code) == SUBREG) ? SUBREG_REG (out_rtx)(((out_rtx)->u.fld[0]).rt_rtx) : out_rtx;
1162 start_sequence ();
1163 /* If we had strict_low_part, use it also in reload to keep other
1164 parts unchanged but do it only for regs as strict_low_part
1165 has no sense for memory and probably there is no insn pattern
1166 to match the reload insn in memory case. */
1167 if (out >= 0 && curr_static_id->operand[out].strict_low && REG_P (reg)(((enum rtx_code) (reg)->code) == REG))
1168 out_rtx = gen_rtx_STRICT_LOW_PART (VOIDmode, out_rtx)gen_rtx_fmt_e_stat ((STRICT_LOW_PART), ((((void) 0, E_VOIDmode
))), ((out_rtx)) )
;
1169 lra_emit_move (out_rtx, copy_rtx (new_out_reg));
1170 emit_insn (*after);
1171 *after = get_insns ();
1172 end_sequence ();
1173 }
1174 *curr_id->operand_loc[out] = new_out_reg;
1175 lra_update_dup (curr_id, out);
1176}
1177
1178/* Return register class which is union of all reg classes in insn
1179 constraint alternative string starting with P. */
1180static enum reg_class
1181reg_class_from_constraints (const char *p)
1182{
1183 int c, len;
1184 enum reg_class op_class = NO_REGS;
1185
1186 do
1187 switch ((c = *p, len = CONSTRAINT_LEN (c, p)insn_constraint_len (c,p)), c)
1188 {
1189 case '#':
1190 case ',':
1191 return op_class;
1192
1193 case 'g':
1194 op_class = reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[op_class][GENERAL_REGS];
1195 break;
1196
1197 default:
1198 enum constraint_num cn = lookup_constraint (p);
1199 enum reg_class cl = reg_class_for_constraint (cn);
1200 if (cl == NO_REGS)
1201 {
1202 if (insn_extra_address_constraint (cn))
1203 op_class
1204 = (reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)
1205 [op_class][base_reg_class (VOIDmode((void) 0, E_VOIDmode), ADDR_SPACE_GENERIC0,
1206 ADDRESS, SCRATCH)]);
1207 break;
1208 }
1209
1210 op_class = reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[op_class][cl];
1211 break;
1212 }
1213 while ((p += len), c);
1214 return op_class;
1215}
1216
1217/* If OP is a register, return the class of the register as per
1218 get_reg_class, otherwise return NO_REGS. */
1219static inline enum reg_class
1220get_op_class (rtx op)
1221{
1222 return REG_P (op)(((enum rtx_code) (op)->code) == REG) ? get_reg_class (REGNO (op)(rhs_regno(op))) : NO_REGS;
1223}
1224
1225/* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1226 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1227 SUBREG for VAL to make them equal. */
1228static rtx_insn *
1229emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
1230{
1231 if (GET_MODE (mem_pseudo)((machine_mode) (mem_pseudo)->mode) != GET_MODE (val)((machine_mode) (val)->mode))
1232 {
1233 /* Usually size of mem_pseudo is greater than val size but in
1234 rare cases it can be less as it can be defined by target
1235 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1236 if (! MEM_P (val)(((enum rtx_code) (val)->code) == MEM))
1237 {
1238 val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo)((machine_mode) (mem_pseudo)->mode),
1239 GET_CODE (val)((enum rtx_code) (val)->code) == SUBREG
1240 ? SUBREG_REG (val)(((val)->u.fld[0]).rt_rtx) : val);
1241 LRA_SUBREG_P (val)(__extension__ ({ __typeof ((val)) const _rtx = ((val)); if (
((enum rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag
("LRA_SUBREG_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1241, __FUNCTION__); _rtx; })->jump)
= 1;
1242 }
1243 else
1244 {
1245 mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val)((machine_mode) (val)->mode), mem_pseudo);
1246 LRA_SUBREG_P (mem_pseudo)(__extension__ ({ __typeof ((mem_pseudo)) const _rtx = ((mem_pseudo
)); if (((enum rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag
("LRA_SUBREG_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1246, __FUNCTION__); _rtx; })->jump)
= 1;
1247 }
1248 }
1249 return to_p ? gen_move_insn (mem_pseudo, val)
1250 : gen_move_insn (val, mem_pseudo);
1251}
1252
1253/* Process a special case insn (register move), return true if we
1254 don't need to process it anymore. INSN should be a single set
1255 insn. Set up that RTL was changed through CHANGE_P and that hook
1256 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1257 SEC_MEM_P. */
1258static bool
1259check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED__attribute__ ((__unused__)))
1260{
1261 int sregno, dregno;
1262 rtx dest, src, dreg, sreg, new_reg, scratch_reg;
1263 rtx_insn *before;
1264 enum reg_class dclass, sclass, secondary_class;
1265 secondary_reload_info sri;
1266
1267 lra_assert (curr_insn_set != NULL_RTX)((void)(!(curr_insn_set != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1267, __FUNCTION__), 0 : 0))
;
1268 dreg = dest = SET_DEST (curr_insn_set)(((curr_insn_set)->u.fld[0]).rt_rtx);
1269 sreg = src = SET_SRC (curr_insn_set)(((curr_insn_set)->u.fld[1]).rt_rtx);
1270 if (GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG)
1271 dreg = SUBREG_REG (dest)(((dest)->u.fld[0]).rt_rtx);
1272 if (GET_CODE (src)((enum rtx_code) (src)->code) == SUBREG)
1273 sreg = SUBREG_REG (src)(((src)->u.fld[0]).rt_rtx);
1274 if (! (REG_P (dreg)(((enum rtx_code) (dreg)->code) == REG) || MEM_P (dreg)(((enum rtx_code) (dreg)->code) == MEM)) || ! (REG_P (sreg)(((enum rtx_code) (sreg)->code) == REG) || MEM_P (sreg)(((enum rtx_code) (sreg)->code) == MEM)))
1275 return false;
1276 sclass = dclass = NO_REGS;
1277 if (REG_P (dreg)(((enum rtx_code) (dreg)->code) == REG))
1278 dclass = get_reg_class (REGNO (dreg)(rhs_regno(dreg)));
1279 gcc_assert (dclass < LIM_REG_CLASSES && dclass >= NO_REGS)((void)(!(dclass < LIM_REG_CLASSES && dclass >=
NO_REGS) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1279, __FUNCTION__), 0 : 0))
;
1280 if (dclass == ALL_REGS)
1281 /* ALL_REGS is used for new pseudos created by transformations
1282 like reload of SUBREG_REG (see function
1283 simplify_operand_subreg). We don't know their class yet. We
1284 should figure out the class from processing the insn
1285 constraints not in this fast path function. Even if ALL_REGS
1286 were a right class for the pseudo, secondary_... hooks usually
1287 are not define for ALL_REGS. */
1288 return false;
1289 if (REG_P (sreg)(((enum rtx_code) (sreg)->code) == REG))
1290 sclass = get_reg_class (REGNO (sreg)(rhs_regno(sreg)));
1291 gcc_assert (sclass < LIM_REG_CLASSES && sclass >= NO_REGS)((void)(!(sclass < LIM_REG_CLASSES && sclass >=
NO_REGS) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1291, __FUNCTION__), 0 : 0))
;
1292 if (sclass == ALL_REGS)
1293 /* See comments above. */
1294 return false;
1295 if (sclass == NO_REGS && dclass == NO_REGS)
1296 return false;
1297 if (targetm.secondary_memory_needed (GET_MODE (src)((machine_mode) (src)->mode), sclass, dclass)
1298 && ((sclass != NO_REGS && dclass != NO_REGS)
1299 || (GET_MODE (src)((machine_mode) (src)->mode)
1300 != targetm.secondary_memory_needed_mode (GET_MODE (src)((machine_mode) (src)->mode)))))
1301 {
1302 *sec_mem_p = true;
1303 return false;
1304 }
1305 if (! REG_P (dreg)(((enum rtx_code) (dreg)->code) == REG) || ! REG_P (sreg)(((enum rtx_code) (sreg)->code) == REG))
1306 return false;
1307 sri.prev_sri = NULLnullptr;
1308 sri.icode = CODE_FOR_nothing;
1309 sri.extra_cost = 0;
1310 secondary_class = NO_REGS;
1311 /* Set up hard register for a reload pseudo for hook
1312 secondary_reload because some targets just ignore unassigned
1313 pseudos in the hook. */
1314 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)(rhs_regno(dreg))) < 0)
1315 {
1316 dregno = REGNO (dreg)(rhs_regno(dreg));
1317 reg_renumber[dregno] = ira_class_hard_regs(this_target_ira->x_ira_class_hard_regs)[dclass][0];
1318 }
1319 else
1320 dregno = -1;
1321 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)(rhs_regno(sreg))) < 0)
1322 {
1323 sregno = REGNO (sreg)(rhs_regno(sreg));
1324 reg_renumber[sregno] = ira_class_hard_regs(this_target_ira->x_ira_class_hard_regs)[sclass][0];
1325 }
1326 else
1327 sregno = -1;
1328 if (sclass != NO_REGS)
1329 secondary_class
1330 = (enum reg_class) targetm.secondary_reload (false, dest,
1331 (reg_class_t) sclass,
1332 GET_MODE (src)((machine_mode) (src)->mode), &sri);
1333 if (sclass == NO_REGS
1334 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing)
1335 && dclass != NO_REGS))
1336 {
1337 enum reg_class old_sclass = secondary_class;
1338 secondary_reload_info old_sri = sri;
1339
1340 sri.prev_sri = NULLnullptr;
1341 sri.icode = CODE_FOR_nothing;
1342 sri.extra_cost = 0;
1343 secondary_class
1344 = (enum reg_class) targetm.secondary_reload (true, src,
1345 (reg_class_t) dclass,
1346 GET_MODE (src)((machine_mode) (src)->mode), &sri);
1347 /* Check the target hook consistency. */
1348 lra_assert((void)(!((secondary_class == NO_REGS && sri.icode ==
CODE_FOR_nothing) || (old_sclass == NO_REGS && old_sri
.icode == CODE_FOR_nothing) || (secondary_class == old_sclass
&& sri.icode == old_sri.icode)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1351, __FUNCTION__), 0 : 0))
1349 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)((void)(!((secondary_class == NO_REGS && sri.icode ==
CODE_FOR_nothing) || (old_sclass == NO_REGS && old_sri
.icode == CODE_FOR_nothing) || (secondary_class == old_sclass
&& sri.icode == old_sri.icode)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1351, __FUNCTION__), 0 : 0))
1350 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing)((void)(!((secondary_class == NO_REGS && sri.icode ==
CODE_FOR_nothing) || (old_sclass == NO_REGS && old_sri
.icode == CODE_FOR_nothing) || (secondary_class == old_sclass
&& sri.icode == old_sri.icode)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1351, __FUNCTION__), 0 : 0))
1351 || (secondary_class == old_sclass && sri.icode == old_sri.icode))((void)(!((secondary_class == NO_REGS && sri.icode ==
CODE_FOR_nothing) || (old_sclass == NO_REGS && old_sri
.icode == CODE_FOR_nothing) || (secondary_class == old_sclass
&& sri.icode == old_sri.icode)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1351, __FUNCTION__), 0 : 0))
;
1352 }
1353 if (sregno >= 0)
1354 reg_renumber [sregno] = -1;
1355 if (dregno >= 0)
1356 reg_renumber [dregno] = -1;
1357 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1358 return false;
1359 *change_p = true;
1360 new_reg = NULL_RTX(rtx) 0;
1361 if (secondary_class != NO_REGS)
1362 new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src)((machine_mode) (src)->mode), NULL_RTX(rtx) 0,
1363 secondary_class,
1364 "secondary");
1365 start_sequence ();
1366 if (sri.icode == CODE_FOR_nothing)
1367 lra_emit_move (new_reg, src);
1368 else
1369 {
1370 enum reg_class scratch_class;
1371
1372 scratch_class = (reg_class_from_constraints
1373 (insn_data[sri.icode].operand[2].constraint));
1374 scratch_reg = (lra_create_new_reg_with_unique_value
1375 (insn_data[sri.icode].operand[2].mode, NULL_RTX(rtx) 0,
1376 scratch_class, "scratch"));
1377 emit_insn (GEN_FCN (sri.icode)(insn_data[sri.icode].genfun) (new_reg != NULL_RTX(rtx) 0 ? new_reg : dest,
1378 src, scratch_reg));
1379 }
1380 before = get_insns ();
1381 end_sequence ();
1382 lra_process_new_insns (curr_insn, before, NULLnullptr, "Inserting the move");
1383 if (new_reg != NULL_RTX(rtx) 0)
1384 SET_SRC (curr_insn_set)(((curr_insn_set)->u.fld[1]).rt_rtx) = new_reg;
1385 else
1386 {
1387 if (lra_dump_file != NULLnullptr)
1388 {
1389 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn));
1390 dump_insn_slim (lra_dump_file, curr_insn);
1391 }
1392 lra_set_insn_deleted (curr_insn);
1393 return true;
1394 }
1395 return false;
1396}
1397
1398/* The following data describe the result of process_alt_operands.
1399 The data are used in curr_insn_transform to generate reloads. */
1400
1401/* The chosen reg classes which should be used for the corresponding
1402 operands. */
1403static enum reg_class goal_alt[MAX_RECOG_OPERANDS30];
1404/* True if the operand should be the same as another operand and that
1405 other operand does not need a reload. */
1406static bool goal_alt_match_win[MAX_RECOG_OPERANDS30];
1407/* True if the operand does not need a reload. */
1408static bool goal_alt_win[MAX_RECOG_OPERANDS30];
1409/* True if the operand can be offsetable memory. */
1410static bool goal_alt_offmemok[MAX_RECOG_OPERANDS30];
1411/* The number of an operand to which given operand can be matched to. */
1412static int goal_alt_matches[MAX_RECOG_OPERANDS30];
1413/* The number of elements in the following array. */
1414static int goal_alt_dont_inherit_ops_num;
1415/* Numbers of operands whose reload pseudos should not be inherited. */
1416static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS30];
1417/* True if the insn commutative operands should be swapped. */
1418static bool goal_alt_swapped;
1419/* The chosen insn alternative. */
1420static int goal_alt_number;
1421
1422/* True if the corresponding operand is the result of an equivalence
1423 substitution. */
1424static bool equiv_substition_p[MAX_RECOG_OPERANDS30];
1425
1426/* The following five variables are used to choose the best insn
1427 alternative. They reflect final characteristics of the best
1428 alternative. */
1429
1430/* Number of necessary reloads and overall cost reflecting the
1431 previous value and other unpleasantness of the best alternative. */
1432static int best_losers, best_overall;
1433/* Overall number hard registers used for reloads. For example, on
1434 some targets we need 2 general registers to reload DFmode and only
1435 one floating point register. */
1436static int best_reload_nregs;
1437/* Overall number reflecting distances of previous reloading the same
1438 value. The distances are counted from the current BB start. It is
1439 used to improve inheritance chances. */
1440static int best_reload_sum;
1441
1442/* True if the current insn should have no correspondingly input or
1443 output reloads. */
1444static bool no_input_reloads_p, no_output_reloads_p;
1445
1446/* True if we swapped the commutative operands in the current
1447 insn. */
1448static int curr_swapped;
1449
1450/* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1451 register of class CL. Add any input reloads to list BEFORE. AFTER
1452 is nonnull if *LOC is an automodified value; handle that case by
1453 adding the required output reloads to list AFTER. Return true if
1454 the RTL was changed.
1455
1456 if CHECK_ONLY_P is true, check that the *LOC is a correct address
1457 register. Return false if the address register is correct. */
1458static bool
1459process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after,
1460 enum reg_class cl)
1461{
1462 int regno;
1463 enum reg_class rclass, new_class;
1464 rtx reg;
1465 rtx new_reg;
1466 machine_mode mode;
1467 bool subreg_p, before_p = false;
1468
1469 subreg_p = GET_CODE (*loc)((enum rtx_code) (*loc)->code) == SUBREG;
1470 if (subreg_p)
1471 {
1472 reg = SUBREG_REG (*loc)(((*loc)->u.fld[0]).rt_rtx);
1473 mode = GET_MODE (reg)((machine_mode) (reg)->mode);
1474
1475 /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1476 between two registers with different classes, but there normally will
1477 be "mov" which transfers element of vector register into the general
1478 register, and this normally will be a subreg which should be reloaded
1479 as a whole. This is particularly likely to be triggered when
1480 -fno-split-wide-types specified. */
1481 if (!REG_P (reg)(((enum rtx_code) (reg)->code) == REG)
1482 || in_class_p (reg, cl, &new_class)
1483 || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode))(!maybe_lt (GET_MODE_SIZE (ptr_mode), GET_MODE_SIZE (mode))))
1484 loc = &SUBREG_REG (*loc)(((*loc)->u.fld[0]).rt_rtx);
1485 }
1486
1487 reg = *loc;
1488 mode = GET_MODE (reg)((machine_mode) (reg)->mode);
1489 if (! REG_P (reg)(((enum rtx_code) (reg)->code) == REG))
1490 {
1491 if (check_only_p)
1492 return true;
1493 /* Always reload memory in an address even if the target supports
1494 such addresses. */
1495 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address");
1496 before_p = true;
1497 }
1498 else
1499 {
1500 regno = REGNO (reg)(rhs_regno(reg));
1501 rclass = get_reg_class (regno);
1502 if (! check_only_p
1503 && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg)
1504 {
1505 if (lra_dump_file != NULLnullptr)
1506 {
1507 fprintf (lra_dump_file,
1508 "Changing pseudo %d in address of insn %u on equiv ",
1509 REGNO (reg)(rhs_regno(reg)), INSN_UID (curr_insn));
1510 dump_value_slim (lra_dump_file, *loc, 1);
1511 fprintf (lra_dump_file, "\n");
1512 }
1513 *loc = copy_rtx (*loc);
1514 }
1515 if (*loc != reg || ! in_class_p (reg, cl, &new_class))
1516 {
1517 if (check_only_p)
1518 return true;
1519 reg = *loc;
1520 if (get_reload_reg (after == NULLnullptr ? OP_IN : OP_INOUT,
1521 mode, reg, cl, subreg_p, "address", &new_reg))
1522 before_p = true;
1523 }
1524 else if (new_class != NO_REGS && rclass != new_class)
1525 {
1526 if (check_only_p)
1527 return true;
1528 lra_change_class (regno, new_class, " Change to", true);
1529 return false;
1530 }
1531 else
1532 return false;
1533 }
1534 if (before_p)
1535 {
1536 push_to_sequence (*before);
1537 lra_emit_move (new_reg, reg);
1538 *before = get_insns ();
1539 end_sequence ();
1540 }
1541 *loc = new_reg;
1542 if (after != NULLnullptr)
1543 {
1544 start_sequence ();
1545 lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg);
1546 emit_insn (*after);
1547 *after = get_insns ();
1548 end_sequence ();
1549 }
1550 return true;
1551}
1552
1553/* Insert move insn in simplify_operand_subreg. BEFORE returns
1554 the insn to be inserted before curr insn. AFTER returns the
1555 the insn to be inserted after curr insn. ORIGREG and NEWREG
1556 are the original reg and new reg for reload. */
1557static void
1558insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg,
1559 rtx newreg)
1560{
1561 if (before)
1562 {
1563 push_to_sequence (*before);
1564 lra_emit_move (newreg, origreg);
1565 *before = get_insns ();
1566 end_sequence ();
1567 }
1568 if (after)
1569 {
1570 start_sequence ();
1571 lra_emit_move (origreg, newreg);
1572 emit_insn (*after);
1573 *after = get_insns ();
1574 end_sequence ();
1575 }
1576}
1577
1578static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as);
1579static bool process_address (int, bool, rtx_insn **, rtx_insn **);
1580
1581/* Make reloads for subreg in operand NOP with internal subreg mode
1582 REG_MODE, add new reloads for further processing. Return true if
1583 any change was done. */
1584static bool
1585simplify_operand_subreg (int nop, machine_mode reg_mode)
1586{
1587 int hard_regno, inner_hard_regno;
1588 rtx_insn *before, *after;
1589 machine_mode mode, innermode;
1590 rtx reg, new_reg;
1591 rtx operand = *curr_id->operand_loc[nop];
1592 enum reg_class regclass;
1593 enum op_type type;
1594
1595 before = after = NULLnullptr;
1596
1597 if (GET_CODE (operand)((enum rtx_code) (operand)->code) != SUBREG)
1598 return false;
1599
1600 mode = GET_MODE (operand)((machine_mode) (operand)->mode);
1601 reg = SUBREG_REG (operand)(((operand)->u.fld[0]).rt_rtx);
1602 innermode = GET_MODE (reg)((machine_mode) (reg)->mode);
1603 type = curr_static_id->operand[nop].type;
1604 if (MEM_P (reg)(((enum rtx_code) (reg)->code) == MEM))
1605 {
1606 const bool addr_was_valid
1607 = valid_address_p (innermode, XEXP (reg, 0)(((reg)->u.fld[0]).rt_rtx), MEM_ADDR_SPACE (reg)(get_mem_attrs (reg)->addrspace));
1608 alter_subreg (curr_id->operand_loc[nop], false);
1609 rtx subst = *curr_id->operand_loc[nop];
1610 lra_assert (MEM_P (subst))((void)(!((((enum rtx_code) (subst)->code) == MEM)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1610, __FUNCTION__), 0 : 0))
;
1611 const bool addr_is_valid = valid_address_p (GET_MODE (subst)((machine_mode) (subst)->mode),
1612 XEXP (subst, 0)(((subst)->u.fld[0]).rt_rtx),
1613 MEM_ADDR_SPACE (subst)(get_mem_attrs (subst)->addrspace));
1614 if (!addr_was_valid
1615 || addr_is_valid
1616 || ((get_constraint_type (lookup_constraint
1617 (curr_static_id->operand[nop].constraint))
1618 != CT_SPECIAL_MEMORY)
1619 /* We still can reload address and if the address is
1620 valid, we can remove subreg without reloading its
1621 inner memory. */
1622 && valid_address_p (GET_MODE (subst)((machine_mode) (subst)->mode),
1623 regno_reg_rtx
1624 [ira_class_hard_regs(this_target_ira->x_ira_class_hard_regs)
1625 [base_reg_class (GET_MODE (subst)((machine_mode) (subst)->mode),
1626 MEM_ADDR_SPACE (subst)(get_mem_attrs (subst)->addrspace),
1627 ADDRESS, SCRATCH)][0]],
1628 MEM_ADDR_SPACE (subst)(get_mem_attrs (subst)->addrspace))))
1629 {
1630 /* If we change the address for a paradoxical subreg of memory, the
1631 new address might violate the necessary alignment or the access
1632 might be slow; take this into consideration. We need not worry
1633 about accesses beyond allocated memory for paradoxical memory
1634 subregs as we don't substitute such equiv memory (see processing
1635 equivalences in function lra_constraints) and because for spilled
1636 pseudos we allocate stack memory enough for the biggest
1637 corresponding paradoxical subreg.
1638
1639 However, do not blindly simplify a (subreg (mem ...)) for
1640 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1641 data into a register when the inner is narrower than outer or
1642 missing important data from memory when the inner is wider than
1643 outer. This rule only applies to modes that are no wider than
1644 a word.
1645
1646 If valid memory becomes invalid after subreg elimination
1647 and address might be different we still have to reload
1648 memory.
1649 */
1650 if ((! addr_was_valid
1651 || addr_is_valid
1652 || known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode))(!maybe_ne (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode))))
1653 && !(maybe_ne (GET_MODE_PRECISION (mode),
1654 GET_MODE_PRECISION (innermode))
1655 && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD)(!maybe_lt ((((global_options.x_ix86_isa_flags & (1UL <<
1)) != 0) ? 8 : 4), GET_MODE_SIZE (mode)))
1656 && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD)(!maybe_lt ((((global_options.x_ix86_isa_flags & (1UL <<
1)) != 0) ? 8 : 4), GET_MODE_SIZE (innermode)))
1657 && WORD_REGISTER_OPERATIONS0)
1658 && (!(MEM_ALIGN (subst)(get_mem_attrs (subst)->align) < GET_MODE_ALIGNMENT (mode)get_mode_alignment (mode)
1659 && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst)(get_mem_attrs (subst)->align)))
1660 || (MEM_ALIGN (reg)(get_mem_attrs (reg)->align) < GET_MODE_ALIGNMENT (innermode)get_mode_alignment (innermode)
1661 && targetm.slow_unaligned_access (innermode,
1662 MEM_ALIGN (reg)(get_mem_attrs (reg)->align)))))
1663 return true;
1664
1665 *curr_id->operand_loc[nop] = operand;
1666
1667 /* But if the address was not valid, we cannot reload the MEM without
1668 reloading the address first. */
1669 if (!addr_was_valid)
1670 process_address (nop, false, &before, &after);
1671
1672 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1673 enum reg_class rclass
1674 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1675 if (get_reload_reg (curr_static_id->operand[nop].type, innermode,
1676 reg, rclass, TRUEtrue, "slow/invalid mem", &new_reg))
1677 {
1678 bool insert_before, insert_after;
1679 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)(rhs_regno(new_reg)));
1680
1681 insert_before = (type != OP_OUT
1682 || partial_subreg_p (mode, innermode));
1683 insert_after = type != OP_IN;
1684 insert_move_for_subreg (insert_before ? &before : NULLnullptr,
1685 insert_after ? &after : NULLnullptr,
1686 reg, new_reg);
1687 }
1688 SUBREG_REG (operand)(((operand)->u.fld[0]).rt_rtx) = new_reg;
1689
1690 /* Convert to MODE. */
1691 reg = operand;
1692 rclass
1693 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1694 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1695 rclass, TRUEtrue, "slow/invalid mem", &new_reg))
1696 {
1697 bool insert_before, insert_after;
1698 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)(rhs_regno(new_reg)));
1699
1700 insert_before = type != OP_OUT;
1701 insert_after = type != OP_IN;
1702 insert_move_for_subreg (insert_before ? &before : NULLnullptr,
1703 insert_after ? &after : NULLnullptr,
1704 reg, new_reg);
1705 }
1706 *curr_id->operand_loc[nop] = new_reg;
1707 lra_process_new_insns (curr_insn, before, after,
1708 "Inserting slow/invalid mem reload");
1709 return true;
1710 }
1711
1712 /* If the address was valid and became invalid, prefer to reload
1713 the memory. Typical case is when the index scale should
1714 correspond the memory. */
1715 *curr_id->operand_loc[nop] = operand;
1716 /* Do not return false here as the MEM_P (reg) will be processed
1717 later in this function. */
1718 }
1719 else if (REG_P (reg)(((enum rtx_code) (reg)->code) == REG) && REGNO (reg)(rhs_regno(reg)) < FIRST_PSEUDO_REGISTER76)
1720 {
1721 alter_subreg (curr_id->operand_loc[nop], false);
1722 return true;
1723 }
1724 else if (CONSTANT_P (reg)((rtx_class[(int) (((enum rtx_code) (reg)->code))]) == RTX_CONST_OBJ
)
)
1725 {
1726 /* Try to simplify subreg of constant. It is usually result of
1727 equivalence substitution. */
1728 if (innermode == VOIDmode((void) 0, E_VOIDmode)
1729 && (innermode = original_subreg_reg_mode[nop]) == VOIDmode((void) 0, E_VOIDmode))
1730 innermode = curr_static_id->operand[nop].mode;
1731 if ((new_reg = simplify_subreg (mode, reg, innermode,
1732 SUBREG_BYTE (operand)(((operand)->u.fld[1]).rt_subreg))) != NULL_RTX(rtx) 0)
1733 {
1734 *curr_id->operand_loc[nop] = new_reg;
1735 return true;
1736 }
1737 }
1738 /* Put constant into memory when we have mixed modes. It generates
1739 a better code in most cases as it does not need a secondary
1740 reload memory. It also prevents LRA looping when LRA is using
1741 secondary reload memory again and again. */
1742 if (CONSTANT_P (reg)((rtx_class[(int) (((enum rtx_code) (reg)->code))]) == RTX_CONST_OBJ
)
&& CONST_POOL_OK_P (reg_mode, reg)((reg_mode) != ((void) 0, E_VOIDmode) && ((rtx_class[
(int) (((enum rtx_code) (reg)->code))]) == RTX_CONST_OBJ) &&
((enum rtx_code) (reg)->code) != HIGH && GET_MODE_SIZE
(reg_mode).is_constant () && !targetm.cannot_force_const_mem
(reg_mode, reg))
1743 && SCALAR_INT_MODE_P (reg_mode)(((enum mode_class) mode_class[reg_mode]) == MODE_INT || ((enum
mode_class) mode_class[reg_mode]) == MODE_PARTIAL_INT)
!= SCALAR_INT_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_INT || ((enum mode_class
) mode_class[mode]) == MODE_PARTIAL_INT)
)
1744 {
1745 SUBREG_REG (operand)(((operand)->u.fld[0]).rt_rtx) = force_const_mem (reg_mode, reg);
1746 alter_subreg (curr_id->operand_loc[nop], false);
1747 return true;
1748 }
1749 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1750 if there may be a problem accessing OPERAND in the outer
1751 mode. */
1752 if ((REG_P (reg)(((enum rtx_code) (reg)->code) == REG)
1753 && REGNO (reg)(rhs_regno(reg)) >= FIRST_PSEUDO_REGISTER76
1754 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg)(rhs_regno(reg)))) >= 0
1755 /* Don't reload paradoxical subregs because we could be looping
1756 having repeatedly final regno out of hard regs range. */
1757 && (hard_regno_nregs (hard_regno, innermode)
1758 >= hard_regno_nregs (hard_regno, mode))
1759 && simplify_subreg_regno (hard_regno, innermode,
1760 SUBREG_BYTE (operand)(((operand)->u.fld[1]).rt_subreg), mode) < 0
1761 /* Don't reload subreg for matching reload. It is actually
1762 valid subreg in LRA. */
1763 && ! LRA_SUBREG_P (operand)(__extension__ ({ __typeof ((operand)) const _rtx = ((operand
)); if (((enum rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag
("LRA_SUBREG_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1763, __FUNCTION__); _rtx; })->jump)
)
1764 || CONSTANT_P (reg)((rtx_class[(int) (((enum rtx_code) (reg)->code))]) == RTX_CONST_OBJ
)
|| GET_CODE (reg)((enum rtx_code) (reg)->code) == PLUS || MEM_P (reg)(((enum rtx_code) (reg)->code) == MEM))
1765 {
1766 enum reg_class rclass;
1767
1768 if (REG_P (reg)(((enum rtx_code) (reg)->code) == REG))
1769 /* There is a big probability that we will get the same class
1770 for the new pseudo and we will get the same insn which
1771 means infinite looping. So spill the new pseudo. */
1772 rclass = NO_REGS;
1773 else
1774 /* The class will be defined later in curr_insn_transform. */
1775 rclass
1776 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1777
1778 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg,
1779 rclass, TRUEtrue, "subreg reg", &new_reg))
1780 {
1781 bool insert_before, insert_after;
1782 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)(rhs_regno(new_reg)));
1783
1784 insert_before = (type != OP_OUT
1785 || read_modify_subreg_p (operand));
1786 insert_after = (type != OP_IN);
1787 insert_move_for_subreg (insert_before ? &before : NULLnullptr,
1788 insert_after ? &after : NULLnullptr,
1789 reg, new_reg);
1790 }
1791 SUBREG_REG (operand)(((operand)->u.fld[0]).rt_rtx) = new_reg;
1792 lra_process_new_insns (curr_insn, before, after,
1793 "Inserting subreg reload");
1794 return true;
1795 }
1796 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1797 IRA allocates hardreg to the inner pseudo reg according to its mode
1798 instead of the outermode, so the size of the hardreg may not be enough
1799 to contain the outermode operand, in that case we may need to insert
1800 reload for the reg. For the following two types of paradoxical subreg,
1801 we need to insert reload:
1802 1. If the op_type is OP_IN, and the hardreg could not be paired with
1803 other hardreg to contain the outermode operand
1804 (checked by in_hard_reg_set_p), we need to insert the reload.
1805 2. If the op_type is OP_OUT or OP_INOUT.
1806
1807 Here is a paradoxical subreg example showing how the reload is generated:
1808
1809 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1810 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1811
1812 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1813 here, if reg107 is assigned to hardreg R15, because R15 is the last
1814 hardreg, compiler cannot find another hardreg to pair with R15 to
1815 contain TImode data. So we insert a TImode reload reg180 for it.
1816 After reload is inserted:
1817
1818 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1819 (reg:DI 107 [ __comp ])) -1
1820 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1821 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1822
1823 Two reload hard registers will be allocated to reg180 to save TImode data
1824 in LRA_assign.
1825
1826 For LRA pseudos this should normally be handled by the biggest_mode
1827 mechanism. However, it's possible for new uses of an LRA pseudo
1828 to be introduced after we've allocated it, such as when undoing
1829 inheritance, and the allocated register might not then be appropriate
1830 for the new uses. */
1831 else if (REG_P (reg)(((enum rtx_code) (reg)->code) == REG)
1832 && REGNO (reg)(rhs_regno(reg)) >= FIRST_PSEUDO_REGISTER76
1833 && paradoxical_subreg_p (operand)
1834 && (inner_hard_regno = lra_get_regno_hard_regno (REGNO (reg)(rhs_regno(reg)))) >= 0
1835 && ((hard_regno
1836 = simplify_subreg_regno (inner_hard_regno, innermode,
1837 SUBREG_BYTE (operand)(((operand)->u.fld[1]).rt_subreg), mode)) < 0
1838 || ((hard_regno_nregs (inner_hard_regno, innermode)
1839 < hard_regno_nregs (hard_regno, mode))
1840 && (regclass = lra_get_allocno_class (REGNO (reg)(rhs_regno(reg))))
1841 && (type != OP_IN
1842 || !in_hard_reg_set_p (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[regclass],
1843 mode, hard_regno)
1844 || overlaps_hard_reg_set_p (lra_no_alloc_regs,
1845 mode, hard_regno)))))
1846 {
1847 /* The class will be defined later in curr_insn_transform. */
1848 enum reg_class rclass
1849 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1850
1851 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1852 rclass, TRUEtrue, "paradoxical subreg", &new_reg))
1853 {
1854 rtx subreg;
1855 bool insert_before, insert_after;
1856
1857 PUT_MODE (new_reg, mode);
1858 subreg = gen_lowpart_SUBREG (innermode, new_reg);
1859 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)(rhs_regno(new_reg)));
1860
1861 insert_before = (type != OP_OUT);
1862 insert_after = (type != OP_IN);
1863 insert_move_for_subreg (insert_before ? &before : NULLnullptr,
1864 insert_after ? &after : NULLnullptr,
1865 reg, subreg);
1866 }
1867 SUBREG_REG (operand)(((operand)->u.fld[0]).rt_rtx) = new_reg;
1868 lra_process_new_insns (curr_insn, before, after,
1869 "Inserting paradoxical subreg reload");
1870 return true;
1871 }
1872 return false;
1873}
1874
1875/* Return TRUE if X refers for a hard register from SET. */
1876static bool
1877uses_hard_regs_p (rtx x, HARD_REG_SET set)
1878{
1879 int i, j, x_hard_regno;
1880 machine_mode mode;
1881 const char *fmt;
1882 enum rtx_code code;
1883
1884 if (x == NULL_RTX(rtx) 0)
1885 return false;
1886 code = GET_CODE (x)((enum rtx_code) (x)->code);
1887 mode = GET_MODE (x)((machine_mode) (x)->mode);
1888
1889 if (code == SUBREG)
1890 {
1891 /* For all SUBREGs we want to check whether the full multi-register
1892 overlaps the set. For normal SUBREGs this means 'get_hard_regno' of
1893 the inner register, for paradoxical SUBREGs this means the
1894 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is
1895 fine. Use the wider mode for all cases. */
1896 rtx subreg = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
1897 mode = wider_subreg_mode (x);
1898 if (mode == GET_MODE (subreg)((machine_mode) (subreg)->mode))
1899 {
1900 x = subreg;
1901 code = GET_CODE (x)((enum rtx_code) (x)->code);
1902 }
1903 }
1904
1905 if (REG_P (x)(((enum rtx_code) (x)->code) == REG) || SUBREG_P (x)(((enum rtx_code) (x)->code) == SUBREG))
1906 {
1907 x_hard_regno = get_hard_regno (x, true);
1908 return (x_hard_regno >= 0
1909 && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
1910 }
1911 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
1912 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
1913 {
1914 if (fmt[i] == 'e')
1915 {
1916 if (uses_hard_regs_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), set))
1917 return true;
1918 }
1919 else if (fmt[i] == 'E')
1920 {
1921 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
1922 if (uses_hard_regs_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), set))
1923 return true;
1924 }
1925 }
1926 return false;
1927}
1928
1929/* Return true if OP is a spilled pseudo. */
1930static inline bool
1931spilled_pseudo_p (rtx op)
1932{
1933 return (REG_P (op)(((enum rtx_code) (op)->code) == REG)
1934 && REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76 && in_mem_p (REGNO (op)(rhs_regno(op))));
1935}
1936
1937/* Return true if X is a general constant. */
1938static inline bool
1939general_constant_p (rtx x)
1940{
1941 return CONSTANT_P (x)((rtx_class[(int) (((enum rtx_code) (x)->code))]) == RTX_CONST_OBJ
)
&& (! flag_picglobal_options.x_flag_pic || LEGITIMATE_PIC_OPERAND_P (x)legitimate_pic_operand_p (x));
1942}
1943
1944static bool
1945reg_in_class_p (rtx reg, enum reg_class cl)
1946{
1947 if (cl == NO_REGS)
1948 return get_reg_class (REGNO (reg)(rhs_regno(reg))) == NO_REGS;
1949 return in_class_p (reg, cl, NULLnullptr);
1950}
1951
1952/* Return true if SET of RCLASS contains no hard regs which can be
1953 used in MODE. */
1954static bool
1955prohibited_class_reg_set_mode_p (enum reg_class rclass,
1956 HARD_REG_SET &set,
1957 machine_mode mode)
1958{
1959 HARD_REG_SET temp;
1960
1961 lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set))((void)(!(hard_reg_set_subset_p ((this_target_hard_regs->x_reg_class_contents
)[rclass], set)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 1961, __FUNCTION__), 0 : 0))
;
1962 temp = set & ~lra_no_alloc_regs;
1963 return (hard_reg_set_subset_p
1964 (temp, ira_prohibited_class_mode_regs(this_target_ira->x_ira_prohibited_class_mode_regs)[rclass][mode]));
1965}
1966
1967
1968/* Used to check validity info about small class input operands. It
1969 should be incremented at start of processing an insn
1970 alternative. */
1971static unsigned int curr_small_class_check = 0;
1972
1973/* Update number of used inputs of class OP_CLASS for operand NOP
1974 of alternative NALT. Return true if we have more such class operands
1975 than the number of available regs. */
1976static bool
1977update_and_check_small_class_inputs (int nop, int nalt,
1978 enum reg_class op_class)
1979{
1980 static unsigned int small_class_check[LIM_REG_CLASSES];
1981 static int small_class_input_nums[LIM_REG_CLASSES];
1982
1983 if (SMALL_REGISTER_CLASS_P (op_class)((this_target_ira->x_ira_class_hard_regs_num) [(op_class)]
== 1 || ((this_target_ira->x_ira_class_hard_regs_num) [(op_class
)] >= 1 && targetm.class_likely_spilled_p (op_class
)))
1984 /* We are interesting in classes became small because of fixing
1985 some hard regs, e.g. by an user through GCC options. */
1986 && hard_reg_set_intersect_p (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[op_class],
1987 ira_no_alloc_regs(this_target_ira->x_ira_no_alloc_regs))
1988 && (curr_static_id->operand[nop].type != OP_OUT
1989 || TEST_BIT (curr_static_id->operand[nop].early_clobber_alts, nalt)(((curr_static_id->operand[nop].early_clobber_alts) >>
(nalt)) & 1)
))
1990 {
1991 if (small_class_check[op_class] == curr_small_class_check)
1992 small_class_input_nums[op_class]++;
1993 else
1994 {
1995 small_class_check[op_class] = curr_small_class_check;
1996 small_class_input_nums[op_class] = 1;
1997 }
1998 if (small_class_input_nums[op_class] > ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[op_class])
1999 return true;
2000 }
2001 return false;
2002}
2003
2004/* Major function to choose the current insn alternative and what
2005 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
2006 negative we should consider only this alternative. Return false if
2007 we cannot choose the alternative or find how to reload the
2008 operands. */
2009static bool
2010process_alt_operands (int only_alternative)
2011{
2012 bool ok_p = false;
2013 int nop, overall, nalt;
2014 int n_alternatives = curr_static_id->n_alternatives;
2015 int n_operands = curr_static_id->n_operands;
2016 /* LOSERS counts the operands that don't fit this alternative and
2017 would require loading. */
2018 int losers;
2019 int addr_losers;
2020 /* REJECT is a count of how undesirable this alternative says it is
2021 if any reloading is required. If the alternative matches exactly
2022 then REJECT is ignored, but otherwise it gets this much counted
2023 against it in addition to the reloading needed. */
2024 int reject;
2025 /* This is defined by '!' or '?' alternative constraint and added to
2026 reject. But in some cases it can be ignored. */
2027 int static_reject;
2028 int op_reject;
2029 /* The number of elements in the following array. */
2030 int early_clobbered_regs_num;
2031 /* Numbers of operands which are early clobber registers. */
2032 int early_clobbered_nops[MAX_RECOG_OPERANDS30];
2033 enum reg_class curr_alt[MAX_RECOG_OPERANDS30];
2034 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS30];
2035 bool curr_alt_match_win[MAX_RECOG_OPERANDS30];
2036 bool curr_alt_win[MAX_RECOG_OPERANDS30];
2037 bool curr_alt_offmemok[MAX_RECOG_OPERANDS30];
2038 int curr_alt_matches[MAX_RECOG_OPERANDS30];
2039 /* The number of elements in the following array. */
2040 int curr_alt_dont_inherit_ops_num;
2041 /* Numbers of operands whose reload pseudos should not be inherited. */
2042 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS30];
2043 rtx op;
2044 /* The register when the operand is a subreg of register, otherwise the
2045 operand itself. */
2046 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS30];
2047 /* The register if the operand is a register or subreg of register,
2048 otherwise NULL. */
2049 rtx operand_reg[MAX_RECOG_OPERANDS30];
2050 int hard_regno[MAX_RECOG_OPERANDS30];
2051 machine_mode biggest_mode[MAX_RECOG_OPERANDS30];
2052 int reload_nregs, reload_sum;
2053 bool costly_p;
2054 enum reg_class cl;
2055
2056 /* Calculate some data common for all alternatives to speed up the
2057 function. */
2058 for (nop = 0; nop < n_operands; nop++)
2059 {
2060 rtx reg;
2061
2062 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop];
2063 /* The real hard regno of the operand after the allocation. */
2064 hard_regno[nop] = get_hard_regno (op, true);
2065
2066 operand_reg[nop] = reg = op;
2067 biggest_mode[nop] = GET_MODE (op)((machine_mode) (op)->mode);
2068 if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG)
2069 {
2070 biggest_mode[nop] = wider_subreg_mode (op);
2071 operand_reg[nop] = reg = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);
2072 }
2073 if (! REG_P (reg)(((enum rtx_code) (reg)->code) == REG))
2074 operand_reg[nop] = NULL_RTX(rtx) 0;
2075 else if (REGNO (reg)(rhs_regno(reg)) >= FIRST_PSEUDO_REGISTER76
2076 || ((int) REGNO (reg)(rhs_regno(reg))
2077 == lra_get_elimination_hard_regno (REGNO (reg)(rhs_regno(reg)))))
2078 no_subreg_reg_operand[nop] = reg;
2079 else
2080 operand_reg[nop] = no_subreg_reg_operand[nop]
2081 /* Just use natural mode for elimination result. It should
2082 be enough for extra constraints hooks. */
2083 = regno_reg_rtx[hard_regno[nop]];
2084 }
2085
2086 /* The constraints are made of several alternatives. Each operand's
2087 constraint looks like foo,bar,... with commas separating the
2088 alternatives. The first alternatives for all operands go
2089 together, the second alternatives go together, etc.
2090
2091 First loop over alternatives. */
2092 alternative_mask preferred = curr_id->preferred_alternatives;
2093 if (only_alternative >= 0)
2094 preferred &= ALTERNATIVE_BIT (only_alternative)((alternative_mask) 1 << (only_alternative));
2095
2096 for (nalt = 0; nalt < n_alternatives; nalt++)
2097 {
2098 /* Loop over operands for one constraint alternative. */
2099 if (!TEST_BIT (preferred, nalt)(((preferred) >> (nalt)) & 1))
2100 continue;
2101
2102 bool matching_early_clobber[MAX_RECOG_OPERANDS30];
2103 curr_small_class_check++;
2104 overall = losers = addr_losers = 0;
2105 static_reject = reject = reload_nregs = reload_sum = 0;
2106 for (nop = 0; nop < n_operands; nop++)
2107 {
2108 int inc = (curr_static_id
2109 ->operand_alternative[nalt * n_operands + nop].reject);
2110 if (lra_dump_file != NULLnullptr && inc != 0)
2111 fprintf (lra_dump_file,
2112 " Staticly defined alt reject+=%d\n", inc);
2113 static_reject += inc;
2114 matching_early_clobber[nop] = 0;
2115 }
2116 reject += static_reject;
2117 early_clobbered_regs_num = 0;
2118
2119 for (nop = 0; nop < n_operands; nop++)
2120 {
2121 const char *p;
2122 char *end;
2123 int len, c, m, i, opalt_num, this_alternative_matches;
2124 bool win, did_match, offmemok, early_clobber_p;
2125 /* false => this operand can be reloaded somehow for this
2126 alternative. */
2127 bool badop;
2128 /* true => this operand can be reloaded if the alternative
2129 allows regs. */
2130 bool winreg;
2131 /* True if a constant forced into memory would be OK for
2132 this operand. */
2133 bool constmemok;
2134 enum reg_class this_alternative, this_costly_alternative;
2135 HARD_REG_SET this_alternative_set, this_costly_alternative_set;
2136 bool this_alternative_match_win, this_alternative_win;
2137 bool this_alternative_offmemok;
2138 bool scratch_p;
2139 machine_mode mode;
2140 enum constraint_num cn;
2141
2142 opalt_num = nalt * n_operands + nop;
2143 if (curr_static_id->operand_alternative[opalt_num].anything_ok)
2144 {
2145 /* Fast track for no constraints at all. */
2146 curr_alt[nop] = NO_REGS;
2147 CLEAR_HARD_REG_SET (curr_alt_set[nop]);
2148 curr_alt_win[nop] = true;
2149 curr_alt_match_win[nop] = false;
2150 curr_alt_offmemok[nop] = false;
2151 curr_alt_matches[nop] = -1;
2152 continue;
2153 }
2154
2155 op = no_subreg_reg_operand[nop];
2156 mode = curr_operand_mode[nop];
2157
2158 win = did_match = winreg = offmemok = constmemok = false;
2159 badop = true;
2160
2161 early_clobber_p = false;
2162 p = curr_static_id->operand_alternative[opalt_num].constraint;
2163
2164 this_costly_alternative = this_alternative = NO_REGS;
2165 /* We update set of possible hard regs besides its class
2166 because reg class might be inaccurate. For example,
2167 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2168 is translated in HI_REGS because classes are merged by
2169 pairs and there is no accurate intermediate class. */
2170 CLEAR_HARD_REG_SET (this_alternative_set);
2171 CLEAR_HARD_REG_SET (this_costly_alternative_set);
2172 this_alternative_win = false;
2173 this_alternative_match_win = false;
2174 this_alternative_offmemok = false;
2175 this_alternative_matches = -1;
2176
2177 /* An empty constraint should be excluded by the fast
2178 track. */
2179 lra_assert (*p != 0 && *p != ',')((void)(!(*p != 0 && *p != ',') ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 2179, __FUNCTION__), 0 : 0))
;
2180
2181 op_reject = 0;
2182 /* Scan this alternative's specs for this operand; set WIN
2183 if the operand fits any letter in this alternative.
2184 Otherwise, clear BADOP if this operand could fit some
2185 letter after reloads, or set WINREG if this operand could
2186 fit after reloads provided the constraint allows some
2187 registers. */
2188 costly_p = false;
2189 do
2190 {
2191 switch ((c = *p, len = CONSTRAINT_LEN (c, p)insn_constraint_len (c,p)), c)
2192 {
2193 case '\0':
2194 len = 0;
2195 break;
2196 case ',':
2197 c = '\0';
2198 break;
2199
2200 case '&':
2201 early_clobber_p = true;
2202 break;
2203
2204 case '$':
2205 op_reject += LRA_MAX_REJECT600;
2206 break;
2207 case '^':
2208 op_reject += LRA_LOSER_COST_FACTOR6;
2209 break;
2210
2211 case '#':
2212 /* Ignore rest of this alternative. */
2213 c = '\0';
2214 break;
2215
2216 case '0': case '1': case '2': case '3': case '4':
2217 case '5': case '6': case '7': case '8': case '9':
2218 {
2219 int m_hregno;
2220 bool match_p;
2221
2222 m = strtoul (p, &end, 10);
2223 p = end;
2224 len = 0;
2225 lra_assert (nop > m)((void)(!(nop > m) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 2225, __FUNCTION__), 0 : 0))
;
2226
2227 /* Reject matches if we don't know which operand is
2228 bigger. This situation would arguably be a bug in
2229 an .md pattern, but could also occur in a user asm. */
2230 if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]),
2231 GET_MODE_SIZE (biggest_mode[nop])))
2232 break;
2233
2234 /* Don't match wrong asm insn operands for proper
2235 diagnostic later. */
2236 if (INSN_CODE (curr_insn)(((curr_insn)->u.fld[5]).rt_int) < 0
2237 && (curr_operand_mode[m] == BLKmode((void) 0, E_BLKmode)
2238 || curr_operand_mode[nop] == BLKmode((void) 0, E_BLKmode))
2239 && curr_operand_mode[m] != curr_operand_mode[nop])
2240 break;
2241
2242 m_hregno = get_hard_regno (*curr_id->operand_loc[m], false);
2243 /* We are supposed to match a previous operand.
2244 If we do, we win if that one did. If we do
2245 not, count both of the operands as losers.
2246 (This is too conservative, since most of the
2247 time only a single reload insn will be needed
2248 to make the two operands win. As a result,
2249 this alternative may be rejected when it is
2250 actually desirable.) */
2251 match_p = false;
2252 if (operands_match_p (*curr_id->operand_loc[nop],
2253 *curr_id->operand_loc[m], m_hregno))
2254 {
2255 /* We should reject matching of an early
2256 clobber operand if the matching operand is
2257 not dying in the insn. */
2258 if (!TEST_BIT (curr_static_id->operand[m](((curr_static_id->operand[m] .early_clobber_alts) >>
(nalt)) & 1)
2259 .early_clobber_alts, nalt)(((curr_static_id->operand[m] .early_clobber_alts) >>
(nalt)) & 1)
2260 || operand_reg[nop] == NULL_RTX(rtx) 0
2261 || (find_regno_note (curr_insn, REG_DEAD,
2262 REGNO (op)(rhs_regno(op)))
2263 || REGNO (op)(rhs_regno(op)) == REGNO (operand_reg[m])(rhs_regno(operand_reg[m]))))
2264 match_p = true;
2265 }
2266 if (match_p)
2267 {
2268 /* If we are matching a non-offsettable
2269 address where an offsettable address was
2270 expected, then we must reject this
2271 combination, because we can't reload
2272 it. */
2273 if (curr_alt_offmemok[m]
2274 && MEM_P (*curr_id->operand_loc[m])(((enum rtx_code) (*curr_id->operand_loc[m])->code) == MEM
)
2275 && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
2276 continue;
2277 }
2278 else
2279 {
2280 /* If the operands do not match and one
2281 operand is INOUT, we can not match them.
2282 Try other possibilities, e.g. other
2283 alternatives or commutative operand
2284 exchange. */
2285 if (curr_static_id->operand[nop].type == OP_INOUT
2286 || curr_static_id->operand[m].type == OP_INOUT)
2287 break;
2288 /* Operands don't match. If the operands are
2289 different user defined explicit hard
2290 registers, then we cannot make them match
2291 when one is early clobber operand. */
2292 if ((REG_P (*curr_id->operand_loc[nop])(((enum rtx_code) (*curr_id->operand_loc[nop])->code) ==
REG)
2293 || SUBREG_P (*curr_id->operand_loc[nop])(((enum rtx_code) (*curr_id->operand_loc[nop])->code) ==
SUBREG)
)
2294 && (REG_P (*curr_id->operand_loc[m])(((enum rtx_code) (*curr_id->operand_loc[m])->code) == REG
)
2295 || SUBREG_P (*curr_id->operand_loc[m])(((enum rtx_code) (*curr_id->operand_loc[m])->code) == SUBREG
)
))
2296 {
2297 rtx nop_reg = *curr_id->operand_loc[nop];
2298 if (SUBREG_P (nop_reg)(((enum rtx_code) (nop_reg)->code) == SUBREG))
2299 nop_reg = SUBREG_REG (nop_reg)(((nop_reg)->u.fld[0]).rt_rtx);
2300 rtx m_reg = *curr_id->operand_loc[m];
2301 if (SUBREG_P (m_reg)(((enum rtx_code) (m_reg)->code) == SUBREG))
2302 m_reg = SUBREG_REG (m_reg)(((m_reg)->u.fld[0]).rt_rtx);
2303
2304 if (REG_P (nop_reg)(((enum rtx_code) (nop_reg)->code) == REG)
2305 && HARD_REGISTER_P (nop_reg)((((rhs_regno(nop_reg))) < 76))
2306 && REG_USERVAR_P (nop_reg)(__extension__ ({ __typeof ((nop_reg)) const _rtx = ((nop_reg
)); if (((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
("REG_USERVAR_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 2306, __FUNCTION__); _rtx; })->volatil)
2307 && REG_P (m_reg)(((enum rtx_code) (m_reg)->code) == REG)
2308 && HARD_REGISTER_P (m_reg)((((rhs_regno(m_reg))) < 76))
2309 && REG_USERVAR_P (m_reg)(__extension__ ({ __typeof ((m_reg)) const _rtx = ((m_reg)); if
(((enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
("REG_USERVAR_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 2309, __FUNCTION__); _rtx; })->volatil)
)
2310 {
2311 int i;
2312
2313 for (i = 0; i < early_clobbered_regs_num; i++)
2314 if (m == early_clobbered_nops[i])
2315 break;
2316 if (i < early_clobbered_regs_num
2317 || early_clobber_p)
2318 break;
2319 }
2320 }
2321 /* Both operands must allow a reload register,
2322 otherwise we cannot make them match. */
2323 if (curr_alt[m] == NO_REGS)
2324 break;
2325 /* Retroactively mark the operand we had to
2326 match as a loser, if it wasn't already and
2327 it wasn't matched to a register constraint
2328 (e.g it might be matched by memory). */
2329 if (curr_alt_win[m]
2330 && (operand_reg[m] == NULL_RTX(rtx) 0
2331 || hard_regno[m] < 0))
2332 {
2333 losers++;
2334 reload_nregs
2335 += (ira_reg_class_max_nregs(this_target_ira->x_ira_reg_class_max_nregs)[curr_alt[m]]
2336 [GET_MODE (*curr_id->operand_loc[m])((machine_mode) (*curr_id->operand_loc[m])->mode)]);
2337 }
2338
2339 /* Prefer matching earlyclobber alternative as
2340 it results in less hard regs required for
2341 the insn than a non-matching earlyclobber
2342 alternative. */
2343 if (TEST_BIT (curr_static_id->operand[m](((curr_static_id->operand[m] .early_clobber_alts) >>
(nalt)) & 1)
2344 .early_clobber_alts, nalt)(((curr_static_id->operand[m] .early_clobber_alts) >>
(nalt)) & 1)
)
2345 {
2346 if (lra_dump_file != NULLnullptr)
2347 fprintf
2348 (lra_dump_file,
2349 " %d Matching earlyclobber alt:"
2350 " reject--\n",
2351 nop);
2352 if (!matching_early_clobber[m])
2353 {
2354 reject--;
2355 matching_early_clobber[m] = 1;
2356 }
2357 }
2358 /* Otherwise we prefer no matching
2359 alternatives because it gives more freedom
2360 in RA. */
2361 else if (operand_reg[nop] == NULL_RTX(rtx) 0
2362 || (find_regno_note (curr_insn, REG_DEAD,
2363 REGNO (operand_reg[nop])(rhs_regno(operand_reg[nop])))
2364 == NULL_RTX(rtx) 0))
2365 {
2366 if (lra_dump_file != NULLnullptr)
2367 fprintf
2368 (lra_dump_file,
2369 " %d Matching alt: reject+=2\n",
2370 nop);
2371 reject += 2;
2372 }
2373 }
2374 /* If we have to reload this operand and some
2375 previous operand also had to match the same
2376 thing as this operand, we don't know how to do
2377 that. */
2378 if (!match_p || !curr_alt_win[m])
2379 {
2380 for (i = 0; i < nop; i++)
2381 if (curr_alt_matches[i] == m)
2382 break;
2383 if (i < nop)
2384 break;
2385 }
2386 else
2387 did_match = true;
2388
2389 this_alternative_matches = m;
2390 /* This can be fixed with reloads if the operand
2391 we are supposed to match can be fixed with
2392 reloads. */
2393 badop = false;
2394 this_alternative = curr_alt[m];
2395 this_alternative_set = curr_alt_set[m];
2396 winreg = this_alternative != NO_REGS;
2397 break;
2398 }
2399
2400 case 'g':
2401 if (MEM_P (op)(((enum rtx_code) (op)->code) == MEM)
2402 || general_constant_p (op)
2403 || spilled_pseudo_p (op))
2404 win = true;
2405 cl = GENERAL_REGS;
2406 goto reg;
2407
2408 default:
2409 cn = lookup_constraint (p);
2410 switch (get_constraint_type (cn))
2411 {
2412 case CT_REGISTER:
2413 cl = reg_class_for_constraint (cn);
2414 if (cl != NO_REGS)
2415 goto reg;
2416 break;
2417
2418 case CT_CONST_INT:
2419 if (CONST_INT_P (op)(((enum rtx_code) (op)->code) == CONST_INT)
2420 && insn_const_int_ok_for_constraint (INTVAL (op)((op)->u.hwint[0]), cn))
2421 win = true;
2422 break;
2423
2424 case CT_MEMORY:
2425 case CT_RELAXED_MEMORY:
2426 if (MEM_P (op)(((enum rtx_code) (op)->code) == MEM)
2427 && satisfies_memory_constraint_p (op, cn))
2428 win = true;
2429 else if (spilled_pseudo_p (op))
2430 win = true;
2431
2432 /* If we didn't already win, we can reload constants
2433 via force_const_mem or put the pseudo value into
2434 memory, or make other memory by reloading the
2435 address like for 'o'. */
2436 if (CONST_POOL_OK_P (mode, op)((mode) != ((void) 0, E_VOIDmode) && ((rtx_class[(int
) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ) &&
((enum rtx_code) (op)->code) != HIGH && GET_MODE_SIZE
(mode).is_constant () && !targetm.cannot_force_const_mem
(mode, op))
2437 || MEM_P (op)(((enum rtx_code) (op)->code) == MEM) || REG_P (op)(((enum rtx_code) (op)->code) == REG)
2438 /* We can restore the equiv insn by a
2439 reload. */
2440 || equiv_substition_p[nop])
2441 badop = false;
2442 constmemok = true;
2443 offmemok = true;
2444 break;
2445
2446 case CT_ADDRESS:
2447 /* An asm operand with an address constraint
2448 that doesn't satisfy address_operand has
2449 is_address cleared, so that we don't try to
2450 make a non-address fit. */
2451 if (!curr_static_id->operand[nop].is_address)
2452 break;
2453 /* If we didn't already win, we can reload the address
2454 into a base register. */
2455 if (satisfies_address_constraint_p (op, cn))
2456 win = true;
2457 cl = base_reg_class (VOIDmode((void) 0, E_VOIDmode), ADDR_SPACE_GENERIC0,
2458 ADDRESS, SCRATCH);
2459 badop = false;
2460 goto reg;
2461
2462 case CT_FIXED_FORM:
2463 if (constraint_satisfied_p (op, cn))
2464 win = true;
2465 break;
2466
2467 case CT_SPECIAL_MEMORY:
2468 if (satisfies_memory_constraint_p (op, cn))
2469 win = true;
2470 else if (spilled_pseudo_p (op))
2471 win = true;
2472 break;
2473 }
2474 break;
2475
2476 reg:
2477 if (mode == BLKmode((void) 0, E_BLKmode))
2478 break;
2479 this_alternative = reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[this_alternative][cl];
2480 this_alternative_set |= reg_class_contents(this_target_hard_regs->x_reg_class_contents)[cl];
2481 if (costly_p)
2482 {
2483 this_costly_alternative
2484 = reg_class_subunion(this_target_hard_regs->x_reg_class_subunion)[this_costly_alternative][cl];
2485 this_costly_alternative_set |= reg_class_contents(this_target_hard_regs->x_reg_class_contents)[cl];
2486 }
2487 winreg = true;
2488 if (REG_P (op)(((enum rtx_code) (op)->code) == REG))
2489 {
2490 if (hard_regno[nop] >= 0
2491 && in_hard_reg_set_p (this_alternative_set,
2492 mode, hard_regno[nop]))
2493 win = true;
2494 else if (hard_regno[nop] < 0
2495 && in_class_p (op, this_alternative, NULLnullptr))
2496 win = true;
2497 }
2498 break;
2499 }
2500 if (c != ' ' && c != '\t')
2501 costly_p = c == '*';
2502 }
2503 while ((p += len), c);
2504
2505 scratch_p = (operand_reg[nop] != NULL_RTX(rtx) 0
2506 && ira_former_scratch_p (REGNO (operand_reg[nop])(rhs_regno(operand_reg[nop]))));
2507 /* Record which operands fit this alternative. */
2508 if (win)
2509 {
2510 this_alternative_win = true;
2511 if (operand_reg[nop] != NULL_RTX(rtx) 0)
2512 {
2513 if (hard_regno[nop] >= 0)
2514 {
2515 if (in_hard_reg_set_p (this_costly_alternative_set,
2516 mode, hard_regno[nop]))
2517 {
2518 if (lra_dump_file != NULLnullptr)
2519 fprintf (lra_dump_file,
2520 " %d Costly set: reject++\n",
2521 nop);
2522 reject++;
2523 }
2524 }
2525 else
2526 {
2527 /* Prefer won reg to spilled pseudo under other
2528 equal conditions for possibe inheritance. */
2529 if (! scratch_p)
2530 {
2531 if (lra_dump_file != NULLnullptr)
2532 fprintf
2533 (lra_dump_file,
2534 " %d Non pseudo reload: reject++\n",
2535 nop);
2536 reject++;
2537 }
2538 if (in_class_p (operand_reg[nop],
2539 this_costly_alternative, NULLnullptr))
2540 {
2541 if (lra_dump_file != NULLnullptr)
2542 fprintf
2543 (lra_dump_file,
2544 " %d Non pseudo costly reload:"
2545 " reject++\n",
2546 nop);
2547 reject++;
2548 }
2549 }
2550 /* We simulate the behavior of old reload here.
2551 Although scratches need hard registers and it
2552 might result in spilling other pseudos, no reload
2553 insns are generated for the scratches. So it
2554 might cost something but probably less than old
2555 reload pass believes. */
2556 if (scratch_p)
2557 {
2558 if (lra_dump_file != NULLnullptr)
2559 fprintf (lra_dump_file,
2560 " %d Scratch win: reject+=2\n",
2561 nop);
2562 reject += 2;
2563 }
2564 }
2565 }
2566 else if (did_match)
2567 this_alternative_match_win = true;
2568 else
2569 {
2570 int const_to_mem = 0;
2571 bool no_regs_p;
2572
2573 reject += op_reject;
2574 /* Never do output reload of stack pointer. It makes
2575 impossible to do elimination when SP is changed in
2576 RTL. */
2577 if (op == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]) && ! frame_pointer_needed((&x_rtl)->frame_pointer_needed)
2578 && curr_static_id->operand[nop].type != OP_IN)
2579 goto fail;
2580
2581 /* If this alternative asks for a specific reg class, see if there
2582 is at least one allocatable register in that class. */
2583 no_regs_p
2584 = (this_alternative == NO_REGS
2585 || (hard_reg_set_subset_p
2586 (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[this_alternative],
2587 lra_no_alloc_regs)));
2588
2589 /* For asms, verify that the class for this alternative is possible
2590 for the mode that is specified. */
2591 if (!no_regs_p && INSN_CODE (curr_insn)(((curr_insn)->u.fld[5]).rt_int) < 0)
2592 {
2593 int i;
2594 for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
2595 if (targetm.hard_regno_mode_ok (i, mode)
2596 && in_hard_reg_set_p (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[this_alternative],
2597 mode, i))
2598 break;
2599 if (i == FIRST_PSEUDO_REGISTER76)
2600 winreg = false;
2601 }
2602
2603 /* If this operand accepts a register, and if the
2604 register class has at least one allocatable register,
2605 then this operand can be reloaded. */
2606 if (winreg && !no_regs_p)
2607 badop = false;
2608
2609 if (badop)
2610 {
2611 if (lra_dump_file != NULLnullptr)
2612 fprintf (lra_dump_file,
2613 " alt=%d: Bad operand -- refuse\n",
2614 nalt);
2615 goto fail;
2616 }
2617
2618 if (this_alternative != NO_REGS)
2619 {
2620 HARD_REG_SET available_regs
2621 = (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[this_alternative]
2622 & ~((ira_prohibited_class_mode_regs(this_target_ira->x_ira_prohibited_class_mode_regs)
2623 [this_alternative][mode])
2624 | lra_no_alloc_regs));
2625 if (hard_reg_set_empty_p (available_regs))
2626 {
2627 /* There are no hard regs holding a value of given
2628 mode. */
2629 if (offmemok)
2630 {
2631 this_alternative = NO_REGS;
2632 if (lra_dump_file != NULLnullptr)
2633 fprintf (lra_dump_file,
2634 " %d Using memory because of"
2635 " a bad mode: reject+=2\n",
2636 nop);
2637 reject += 2;
2638 }
2639 else
2640 {
2641 if (lra_dump_file != NULLnullptr)
2642 fprintf (lra_dump_file,
2643 " alt=%d: Wrong mode -- refuse\n",
2644 nalt);
2645 goto fail;
2646 }
2647 }
2648 }
2649
2650 /* If not assigned pseudo has a class which a subset of
2651 required reg class, it is a less costly alternative
2652 as the pseudo still can get a hard reg of necessary
2653 class. */
2654 if (! no_regs_p && REG_P (op)(((enum rtx_code) (op)->code) == REG) && hard_regno[nop] < 0
2655 && (cl = get_reg_class (REGNO (op)(rhs_regno(op)))) != NO_REGS
2656 && ira_class_subset_p(this_target_ira->x_ira_class_subset_p)[this_alternative][cl])
2657 {
2658 if (lra_dump_file != NULLnullptr)
2659 fprintf
2660 (lra_dump_file,
2661 " %d Super set class reg: reject-=3\n", nop);
2662 reject -= 3;
2663 }
2664
2665 this_alternative_offmemok = offmemok;
2666 if (this_costly_alternative != NO_REGS)
2667 {
2668 if (lra_dump_file != NULLnullptr)
2669 fprintf (lra_dump_file,
2670 " %d Costly loser: reject++\n", nop);
2671 reject++;
2672 }
2673 /* If the operand is dying, has a matching constraint,
2674 and satisfies constraints of the matched operand
2675 which failed to satisfy the own constraints, most probably
2676 the reload for this operand will be gone. */
2677 if (this_alternative_matches >= 0
2678 && !curr_alt_win[this_alternative_matches]
2679 && REG_P (op)(((enum rtx_code) (op)->code) == REG)
2680 && find_regno_note (curr_insn, REG_DEAD, REGNO (op)(rhs_regno(op)))
2681 && (hard_regno[nop] >= 0
2682 ? in_hard_reg_set_p (this_alternative_set,
2683 mode, hard_regno[nop])
2684 : in_class_p (op, this_alternative, NULLnullptr)))
2685 {
2686 if (lra_dump_file != NULLnullptr)
2687 fprintf
2688 (lra_dump_file,
2689 " %d Dying matched operand reload: reject++\n",
2690 nop);
2691 reject++;
2692 }
2693 else
2694 {
2695 /* Strict_low_part requires to reload the register
2696 not the sub-register. In this case we should
2697 check that a final reload hard reg can hold the
2698 value mode. */
2699 if (curr_static_id->operand[nop].strict_low
2700 && REG_P (op)(((enum rtx_code) (op)->code) == REG)
2701 && hard_regno[nop] < 0
2702 && GET_CODE (*curr_id->operand_loc[nop])((enum rtx_code) (*curr_id->operand_loc[nop])->code) == SUBREG
2703 && ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[this_alternative] > 0
2704 && (!targetm.hard_regno_mode_ok
2705 (ira_class_hard_regs(this_target_ira->x_ira_class_hard_regs)[this_alternative][0],
2706 GET_MODE (*curr_id->operand_loc[nop])((machine_mode) (*curr_id->operand_loc[nop])->mode))))
2707 {
2708 if (lra_dump_file != NULLnullptr)
2709 fprintf
2710 (lra_dump_file,
2711 " alt=%d: Strict low subreg reload -- refuse\n",
2712 nalt);
2713 goto fail;
2714 }
2715 losers++;
2716 }
2717 if (operand_reg[nop] != NULL_RTX(rtx) 0
2718 /* Output operands and matched input operands are
2719 not inherited. The following conditions do not
2720 exactly describe the previous statement but they
2721 are pretty close. */
2722 && curr_static_id->operand[nop].type != OP_OUT
2723 && (this_alternative_matches < 0
2724 || curr_static_id->operand[nop].type != OP_IN))
2725 {
2726 int last_reload = (lra_reg_info[ORIGINAL_REGNO(__extension__ ({ __typeof ((operand_reg[nop])) const _rtx = (
(operand_reg[nop])); if (((enum rtx_code) (_rtx)->code) !=
REG) rtl_check_failed_flag ("ORIGINAL_REGNO", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 2727, __FUNCTION__); _rtx; })->u2.original_regno)
2727 (operand_reg[nop])(__extension__ ({ __typeof ((operand_reg[nop])) const _rtx = (
(operand_reg[nop])); if (((enum rtx_code) (_rtx)->code) !=
REG) rtl_check_failed_flag ("ORIGINAL_REGNO", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 2727, __FUNCTION__); _rtx; })->u2.original_regno)
]
2728 .last_reload);
2729
2730 /* The value of reload_sum has sense only if we
2731 process insns in their order. It happens only on
2732 the first constraints sub-pass when we do most of
2733 reload work. */
2734 if (lra_constraint_iter == 1 && last_reload > bb_reload_num)
2735 reload_sum += last_reload - bb_reload_num;
2736 }
2737 /* If this is a constant that is reloaded into the
2738 desired class by copying it to memory first, count
2739 that as another reload. This is consistent with
2740 other code and is required to avoid choosing another
2741 alternative when the constant is moved into memory.
2742 Note that the test here is precisely the same as in
2743 the code below that calls force_const_mem. */
2744 if (CONST_POOL_OK_P (mode, op)((mode) != ((void) 0, E_VOIDmode) && ((rtx_class[(int
) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ) &&
((enum rtx_code) (op)->code) != HIGH && GET_MODE_SIZE
(mode).is_constant () && !targetm.cannot_force_const_mem
(mode, op))
2745 && ((targetm.preferred_reload_class
2746 (op, this_alternative) == NO_REGS)
2747 || no_input_reloads_p))
2748 {
2749 const_to_mem = 1;
2750 if (! no_regs_p)
2751 losers++;
2752 }
2753
2754 /* Alternative loses if it requires a type of reload not
2755 permitted for this insn. We can always reload
2756 objects with a REG_UNUSED note. */
2757 if ((curr_static_id->operand[nop].type != OP_IN
2758 && no_output_reloads_p
2759 && ! find_reg_note (curr_insn, REG_UNUSED, op))
2760 || (curr_static_id->operand[nop].type != OP_OUT
2761 && no_input_reloads_p && ! const_to_mem)
2762 || (this_alternative_matches >= 0
2763 && (no_input_reloads_p
2764 || (no_output_reloads_p
2765 && (curr_static_id->operand
2766 [this_alternative_matches].type != OP_IN)
2767 && ! find_reg_note (curr_insn, REG_UNUSED,
2768 no_subreg_reg_operand
2769 [this_alternative_matches])))))
2770 {
2771 if (lra_dump_file != NULLnullptr)
2772 fprintf
2773 (lra_dump_file,
2774 " alt=%d: No input/output reload -- refuse\n",
2775 nalt);
2776 goto fail;
2777 }
2778
2779 /* Alternative loses if it required class pseudo cannot
2780 hold value of required mode. Such insns can be
2781 described by insn definitions with mode iterators. */
2782 if (GET_MODE (*curr_id->operand_loc[nop])((machine_mode) (*curr_id->operand_loc[nop])->mode) != VOIDmode((void) 0, E_VOIDmode)
2783 && ! hard_reg_set_empty_p (this_alternative_set)
2784 /* It is common practice for constraints to use a
2785 class which does not have actually enough regs to
2786 hold the value (e.g. x86 AREG for mode requiring
2787 more one general reg). Therefore we have 2
2788 conditions to check that the reload pseudo cannot
2789 hold the mode value. */
2790 && (!targetm.hard_regno_mode_ok
2791 (ira_class_hard_regs(this_target_ira->x_ira_class_hard_regs)[this_alternative][0],
2792 GET_MODE (*curr_id->operand_loc[nop])((machine_mode) (*curr_id->operand_loc[nop])->mode)))
2793 /* The above condition is not enough as the first
2794 reg in ira_class_hard_regs can be not aligned for
2795 multi-words mode values. */
2796 && (prohibited_class_reg_set_mode_p
2797 (this_alternative, this_alternative_set,
2798 GET_MODE (*curr_id->operand_loc[nop])((machine_mode) (*curr_id->operand_loc[nop])->mode))))
2799 {
2800 if (lra_dump_file != NULLnullptr)
2801 fprintf (lra_dump_file,
2802 " alt=%d: reload pseudo for op %d "
2803 "cannot hold the mode value -- refuse\n",
2804 nalt, nop);
2805 goto fail;
2806 }
2807
2808 /* Check strong discouragement of reload of non-constant
2809 into class THIS_ALTERNATIVE. */
2810 if (! CONSTANT_P (op)((rtx_class[(int) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ
)
&& ! no_regs_p
2811 && (targetm.preferred_reload_class
2812 (op, this_alternative) == NO_REGS
2813 || (curr_static_id->operand[nop].type == OP_OUT
2814 && (targetm.preferred_output_reload_class
2815 (op, this_alternative) == NO_REGS))))
2816 {
2817 if (offmemok && REG_P (op)(((enum rtx_code) (op)->code) == REG))
2818 {
2819 if (lra_dump_file != NULLnullptr)
2820 fprintf
2821 (lra_dump_file,
2822 " %d Spill pseudo into memory: reject+=3\n",
2823 nop);
2824 reject += 3;
2825 }
2826 else
2827 {
2828 if (lra_dump_file != NULLnullptr)
2829 fprintf
2830 (lra_dump_file,
2831 " %d Non-prefered reload: reject+=%d\n",
2832 nop, LRA_MAX_REJECT600);
2833 reject += LRA_MAX_REJECT600;
2834 }
2835 }
2836
2837 if (! (MEM_P (op)(((enum rtx_code) (op)->code) == MEM) && offmemok)
2838 && ! (const_to_mem && constmemok))
2839 {
2840 /* We prefer to reload pseudos over reloading other
2841 things, since such reloads may be able to be
2842 eliminated later. So bump REJECT in other cases.
2843 Don't do this in the case where we are forcing a
2844 constant into memory and it will then win since
2845 we don't want to have a different alternative
2846 match then. */
2847 if (! (REG_P (op)(((enum rtx_code) (op)->code) == REG) && REGNO (op)(rhs_regno(op)) >= FIRST_PSEUDO_REGISTER76))
2848 {
2849 if (lra_dump_file != NULLnullptr)
2850 fprintf
2851 (lra_dump_file,
2852 " %d Non-pseudo reload: reject+=2\n",
2853 nop);
2854 reject += 2;
2855 }
2856
2857 if (! no_regs_p)
2858 reload_nregs
2859 += ira_reg_class_max_nregs(this_target_ira->x_ira_reg_class_max_nregs)[this_alternative][mode];
2860
2861 if (SMALL_REGISTER_CLASS_P (this_alternative)((this_target_ira->x_ira_class_hard_regs_num) [(this_alternative
)] == 1 || ((this_target_ira->x_ira_class_hard_regs_num) [
(this_alternative)] >= 1 && targetm.class_likely_spilled_p
(this_alternative)))
)
2862 {
2863 if (lra_dump_file != NULLnullptr)
2864 fprintf
2865 (lra_dump_file,
2866 " %d Small class reload: reject+=%d\n",
2867 nop, LRA_LOSER_COST_FACTOR6 / 2);
2868 reject += LRA_LOSER_COST_FACTOR6 / 2;
2869 }
2870 }
2871
2872 /* We are trying to spill pseudo into memory. It is
2873 usually more costly than moving to a hard register
2874 although it might takes the same number of
2875 reloads.
2876
2877 Non-pseudo spill may happen also. Suppose a target allows both
2878 register and memory in the operand constraint alternatives,
2879 then it's typical that an eliminable register has a substition
2880 of "base + offset" which can either be reloaded by a simple
2881 "new_reg <= base + offset" which will match the register
2882 constraint, or a similar reg addition followed by further spill
2883 to and reload from memory which will match the memory
2884 constraint, but this memory spill will be much more costly
2885 usually.
2886
2887 Code below increases the reject for both pseudo and non-pseudo
2888 spill. */
2889 if (no_regs_p
2890 && !(MEM_P (op)(((enum rtx_code) (op)->code) == MEM) && offmemok)
2891 && !(REG_P (op)(((enum rtx_code) (op)->code) == REG) && hard_regno[nop] < 0))
2892 {
2893 if (lra_dump_file != NULLnullptr)
2894 fprintf
2895 (lra_dump_file,
2896 " %d Spill %spseudo into memory: reject+=3\n",
2897 nop, REG_P (op)(((enum rtx_code) (op)->code) == REG) ? "" : "Non-");
2898 reject += 3;
2899 if (VECTOR_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_VECTOR_BOOL || (
(enum mode_class) mode_class[mode]) == MODE_VECTOR_INT || ((enum
mode_class) mode_class[mode]) == MODE_VECTOR_FLOAT || ((enum
mode_class) mode_class[mode]) == MODE_VECTOR_FRACT || ((enum
mode_class) mode_class[mode]) == MODE_VECTOR_UFRACT || ((enum
mode_class) mode_class[mode]) == MODE_VECTOR_ACCUM || ((enum
mode_class) mode_class[mode]) == MODE_VECTOR_UACCUM)
)
2900 {
2901 /* Spilling vectors into memory is usually more
2902 costly as they contain big values. */
2903 if (lra_dump_file != NULLnullptr)
2904 fprintf
2905 (lra_dump_file,
2906 " %d Spill vector pseudo: reject+=2\n",
2907 nop);
2908 reject += 2;
2909 }
2910 }
2911
2912 /* When we use an operand requiring memory in given
2913 alternative, the insn should write *and* read the
2914 value to/from memory it is costly in comparison with
2915 an insn alternative which does not use memory
2916 (e.g. register or immediate operand). We exclude
2917 memory operand for such case as we can satisfy the
2918 memory constraints by reloading address. */
2919 if (no_regs_p && offmemok && !MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
2920 {
2921 if (lra_dump_file != NULLnullptr)
2922 fprintf
2923 (lra_dump_file,
2924 " Using memory insn operand %d: reject+=3\n",
2925 nop);
2926 reject += 3;
2927 }
2928
2929 /* If reload requires moving value through secondary
2930 memory, it will need one more insn at least. */
2931 if (this_alternative != NO_REGS
2932 && REG_P (op)(((enum rtx_code) (op)->code) == REG) && (cl = get_reg_class (REGNO (op)(rhs_regno(op)))) != NO_REGS
2933 && ((curr_static_id->operand[nop].type != OP_OUT
2934 && targetm.secondary_memory_needed (GET_MODE (op)((machine_mode) (op)->mode), cl,
2935 this_alternative))
2936 || (curr_static_id->operand[nop].type != OP_IN
2937 && (targetm.secondary_memory_needed
2938 (GET_MODE (op)((machine_mode) (op)->mode), this_alternative, cl)))))
2939 losers++;
2940
2941 if (MEM_P (op)(((enum rtx_code) (op)->code) == MEM) && offmemok)
2942 addr_losers++;
2943 else
2944 {
2945 /* Input reloads can be inherited more often than
2946 output reloads can be removed, so penalize output
2947 reloads. */
2948 if (!REG_P (op)(((enum rtx_code) (op)->code) == REG) || curr_static_id->operand[nop].type != OP_IN)
2949 {
2950 if (lra_dump_file != NULLnullptr)
2951 fprintf
2952 (lra_dump_file,
2953 " %d Non input pseudo reload: reject++\n",
2954 nop);
2955 reject++;
2956 }
2957
2958 if (curr_static_id->operand[nop].type == OP_INOUT)
2959 {
2960 if (lra_dump_file != NULLnullptr)
2961 fprintf
2962 (lra_dump_file,
2963 " %d Input/Output reload: reject+=%d\n",
2964 nop, LRA_LOSER_COST_FACTOR6);
2965 reject += LRA_LOSER_COST_FACTOR6;
2966 }
2967 }
2968 }
2969
2970 if (early_clobber_p && ! scratch_p)
2971 {
2972 if (lra_dump_file != NULLnullptr)
2973 fprintf (lra_dump_file,
2974 " %d Early clobber: reject++\n", nop);
2975 reject++;
2976 }
2977 /* ??? We check early clobbers after processing all operands
2978 (see loop below) and there we update the costs more.
2979 Should we update the cost (may be approximately) here
2980 because of early clobber register reloads or it is a rare
2981 or non-important thing to be worth to do it. */
2982 overall = (losers * LRA_LOSER_COST_FACTOR6 + reject
2983 - (addr_losers == losers ? static_reject : 0));
2984 if ((best_losers == 0 || losers != 0) && best_overall < overall)
2985 {
2986 if (lra_dump_file != NULLnullptr)
2987 fprintf (lra_dump_file,
2988 " alt=%d,overall=%d,losers=%d -- refuse\n",
2989 nalt, overall, losers);
2990 goto fail;
2991 }
2992
2993 if (update_and_check_small_class_inputs (nop, nalt,
2994 this_alternative))
2995 {
2996 if (lra_dump_file != NULLnullptr)
2997 fprintf (lra_dump_file,
2998 " alt=%d, not enough small class regs -- refuse\n",
2999 nalt);
3000 goto fail;
3001 }
3002 curr_alt[nop] = this_alternative;
3003 curr_alt_set[nop] = this_alternative_set;
3004 curr_alt_win[nop] = this_alternative_win;
3005 curr_alt_match_win[nop] = this_alternative_match_win;
3006 curr_alt_offmemok[nop] = this_alternative_offmemok;
3007 curr_alt_matches[nop] = this_alternative_matches;
3008
3009 if (this_alternative_matches >= 0
3010 && !did_match && !this_alternative_win)
3011 curr_alt_win[this_alternative_matches] = false;
3012
3013 if (early_clobber_p && operand_reg[nop] != NULL_RTX(rtx) 0)
3014 early_clobbered_nops[early_clobbered_regs_num++] = nop;
3015 }
3016
3017 if (curr_insn_set != NULL_RTX(rtx) 0 && n_operands == 2
3018 /* Prevent processing non-move insns. */
3019 && (GET_CODE (SET_SRC (curr_insn_set))((enum rtx_code) ((((curr_insn_set)->u.fld[1]).rt_rtx))->
code)
== SUBREG
3020 || SET_SRC (curr_insn_set)(((curr_insn_set)->u.fld[1]).rt_rtx) == no_subreg_reg_operand[1])
3021 && ((! curr_alt_win[0] && ! curr_alt_win[1]
3022 && REG_P (no_subreg_reg_operand[0])(((enum rtx_code) (no_subreg_reg_operand[0])->code) == REG
)
3023 && REG_P (no_subreg_reg_operand[1])(((enum rtx_code) (no_subreg_reg_operand[1])->code) == REG
)
3024 && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
3025 || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
3026 || (! curr_alt_win[0] && curr_alt_win[1]
3027 && REG_P (no_subreg_reg_operand[1])(((enum rtx_code) (no_subreg_reg_operand[1])->code) == REG
)
3028 /* Check that we reload memory not the memory
3029 address. */
3030 && ! (curr_alt_offmemok[0]
3031 && MEM_P (no_subreg_reg_operand[0])(((enum rtx_code) (no_subreg_reg_operand[0])->code) == MEM
)
)
3032 && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
3033 || (curr_alt_win[0] && ! curr_alt_win[1]
3034 && REG_P (no_subreg_reg_operand[0])(((enum rtx_code) (no_subreg_reg_operand[0])->code) == REG
)
3035 /* Check that we reload memory not the memory
3036 address. */
3037 && ! (curr_alt_offmemok[1]
3038 && MEM_P (no_subreg_reg_operand[1])(((enum rtx_code) (no_subreg_reg_operand[1])->code) == MEM
)
)
3039 && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
3040 && (! CONST_POOL_OK_P (curr_operand_mode[1],((curr_operand_mode[1]) != ((void) 0, E_VOIDmode) && (
(rtx_class[(int) (((enum rtx_code) (no_subreg_reg_operand[1])
->code))]) == RTX_CONST_OBJ) && ((enum rtx_code) (
no_subreg_reg_operand[1])->code) != HIGH && GET_MODE_SIZE
(curr_operand_mode[1]).is_constant () && !targetm.cannot_force_const_mem
(curr_operand_mode[1], no_subreg_reg_operand[1]))
3041 no_subreg_reg_operand[1])((curr_operand_mode[1]) != ((void) 0, E_VOIDmode) && (
(rtx_class[(int) (((enum rtx_code) (no_subreg_reg_operand[1])
->code))]) == RTX_CONST_OBJ) && ((enum rtx_code) (
no_subreg_reg_operand[1])->code) != HIGH && GET_MODE_SIZE
(curr_operand_mode[1]).is_constant () && !targetm.cannot_force_const_mem
(curr_operand_mode[1], no_subreg_reg_operand[1]))
3042 || (targetm.preferred_reload_class
3043 (no_subreg_reg_operand[1],
3044 (enum reg_class) curr_alt[1]) != NO_REGS))
3045 /* If it is a result of recent elimination in move
3046 insn we can transform it into an add still by
3047 using this alternative. */
3048 && GET_CODE (no_subreg_reg_operand[1])((enum rtx_code) (no_subreg_reg_operand[1])->code) != PLUS
3049 /* Likewise if the source has been replaced with an
3050 equivalent value. This only happens once -- the reload
3051 will use the equivalent value instead of the register it
3052 replaces -- so there should be no danger of cycling. */
3053 && !equiv_substition_p[1])))
3054 {
3055 /* We have a move insn and a new reload insn will be similar
3056 to the current insn. We should avoid such situation as
3057 it results in LRA cycling. */
3058 if (lra_dump_file != NULLnullptr)
3059 fprintf (lra_dump_file,
3060 " Cycle danger: overall += LRA_MAX_REJECT\n");
3061 overall += LRA_MAX_REJECT600;
3062 }
3063 ok_p = true;
3064 curr_alt_dont_inherit_ops_num = 0;
3065 for (nop = 0; nop < early_clobbered_regs_num; nop++)
3066 {
3067 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j;
3068 HARD_REG_SET temp_set;
3069
3070 i = early_clobbered_nops[nop];
3071 if ((! curr_alt_win[i] && ! curr_alt_match_win[i])
3072 || hard_regno[i] < 0)
3073 continue;
3074 lra_assert (operand_reg[i] != NULL_RTX)((void)(!(operand_reg[i] != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3074, __FUNCTION__), 0 : 0))
;
3075 clobbered_hard_regno = hard_regno[i];
3076 CLEAR_HARD_REG_SET (temp_set);
3077 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno);
3078 first_conflict_j = last_conflict_j = -1;
3079 for (j = 0; j < n_operands; j++)
3080 if (j == i
3081 /* We don't want process insides of match_operator and
3082 match_parallel because otherwise we would process
3083 their operands once again generating a wrong
3084 code. */
3085 || curr_static_id->operand[j].is_operator)
3086 continue;
3087 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j])
3088 || (curr_alt_matches[i] == j && curr_alt_match_win[i]))
3089 continue;
3090 /* If we don't reload j-th operand, check conflicts. */
3091 else if ((curr_alt_win[j] || curr_alt_match_win[j])
3092 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
3093 {
3094 if (first_conflict_j < 0)
3095 first_conflict_j = j;
3096 last_conflict_j = j;
3097 /* Both the earlyclobber operand and conflicting operand
3098 cannot both be user defined hard registers. */
3099 if (HARD_REGISTER_P (operand_reg[i])((((rhs_regno(operand_reg[i]))) < 76))
3100 && REG_USERVAR_P (operand_reg[i])(__extension__ ({ __typeof ((operand_reg[i])) const _rtx = ((
operand_reg[i])); if (((enum rtx_code) (_rtx)->code) != REG
) rtl_check_failed_flag ("REG_USERVAR_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3100, __FUNCTION__); _rtx; })->volatil)
3101 && operand_reg[j] != NULL_RTX(rtx) 0
3102 && HARD_REGISTER_P (operand_reg[j])((((rhs_regno(operand_reg[j]))) < 76))
3103 && REG_USERVAR_P (operand_reg[j])(__extension__ ({ __typeof ((operand_reg[j])) const _rtx = ((
operand_reg[j])); if (((enum rtx_code) (_rtx)->code) != REG
) rtl_check_failed_flag ("REG_USERVAR_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3103, __FUNCTION__); _rtx; })->volatil)
)
3104 {
3105 /* For asm, let curr_insn_transform diagnose it. */
3106 if (INSN_CODE (curr_insn)(((curr_insn)->u.fld[5]).rt_int) < 0)
3107 return false;
3108 fatal_insn ("unable to generate reloads for "_fatal_insn ("unable to generate reloads for " "impossible constraints:"
, curr_insn, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3109, __FUNCTION__)
3109 "impossible constraints:", curr_insn)_fatal_insn ("unable to generate reloads for " "impossible constraints:"
, curr_insn, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3109, __FUNCTION__)
;
3110 }
3111 }
3112 if (last_conflict_j < 0)
3113 continue;
3114
3115 /* If an earlyclobber operand conflicts with another non-matching
3116 operand (ie, they have been assigned the same hard register),
3117 then it is better to reload the other operand, as there may
3118 exist yet another operand with a matching constraint associated
3119 with the earlyclobber operand. However, if one of the operands
3120 is an explicit use of a hard register, then we must reload the
3121 other non-hard register operand. */
3122 if (HARD_REGISTER_P (operand_reg[i])((((rhs_regno(operand_reg[i]))) < 76))
3123 || (first_conflict_j == last_conflict_j
3124 && operand_reg[last_conflict_j] != NULL_RTX(rtx) 0
3125 && !curr_alt_match_win[last_conflict_j]
3126 && !HARD_REGISTER_P (operand_reg[last_conflict_j])((((rhs_regno(operand_reg[last_conflict_j]))) < 76))))
3127 {
3128 curr_alt_win[last_conflict_j] = false;
3129 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
3130 = last_conflict_j;
3131 losers++;
3132 if (lra_dump_file != NULLnullptr)
3133 fprintf
3134 (lra_dump_file,
3135 " %d Conflict early clobber reload: reject--\n",
3136 i);
3137 }
3138 else
3139 {
3140 /* We need to reload early clobbered register and the
3141 matched registers. */
3142 for (j = 0; j < n_operands; j++)
3143 if (curr_alt_matches[j] == i)
3144 {
3145 curr_alt_match_win[j] = false;
3146 losers++;
3147 overall += LRA_LOSER_COST_FACTOR6;
3148 }
3149 if (! curr_alt_match_win[i])
3150 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i;
3151 else
3152 {
3153 /* Remember pseudos used for match reloads are never
3154 inherited. */
3155 lra_assert (curr_alt_matches[i] >= 0)((void)(!(curr_alt_matches[i] >= 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3155, __FUNCTION__), 0 : 0))
;
3156 curr_alt_win[curr_alt_matches[i]] = false;
3157 }
3158 curr_alt_win[i] = curr_alt_match_win[i] = false;
3159 losers++;
3160 if (lra_dump_file != NULLnullptr)
3161 fprintf
3162 (lra_dump_file,
3163 " %d Matched conflict early clobber reloads: "
3164 "reject--\n",
3165 i);
3166 }
3167 /* Early clobber was already reflected in REJECT. */
3168 if (!matching_early_clobber[i])
3169 {
3170 lra_assert (reject > 0)((void)(!(reject > 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3170, __FUNCTION__), 0 : 0))
;
3171 reject--;
3172 matching_early_clobber[i] = 1;
3173 }
3174 overall += LRA_LOSER_COST_FACTOR6 - 1;
3175 }
3176 if (lra_dump_file != NULLnullptr)
3177 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
3178 nalt, overall, losers, reload_nregs);
3179
3180 /* If this alternative can be made to work by reloading, and it
3181 needs less reloading than the others checked so far, record
3182 it as the chosen goal for reloading. */
3183 if ((best_losers != 0 && losers == 0)
3184 || (((best_losers == 0 && losers == 0)
3185 || (best_losers != 0 && losers != 0))
3186 && (best_overall > overall
3187 || (best_overall == overall
3188 /* If the cost of the reloads is the same,
3189 prefer alternative which requires minimal
3190 number of reload regs. */
3191 && (reload_nregs < best_reload_nregs
3192 || (reload_nregs == best_reload_nregs
3193 && (best_reload_sum < reload_sum
3194 || (best_reload_sum == reload_sum
3195 && nalt < goal_alt_number))))))))
3196 {
3197 for (nop = 0; nop < n_operands; nop++)
3198 {
3199 goal_alt_win[nop] = curr_alt_win[nop];
3200 goal_alt_match_win[nop] = curr_alt_match_win[nop];
3201 goal_alt_matches[nop] = curr_alt_matches[nop];
3202 goal_alt[nop] = curr_alt[nop];
3203 goal_alt_offmemok[nop] = curr_alt_offmemok[nop];
3204 }
3205 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num;
3206 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++)
3207 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop];
3208 goal_alt_swapped = curr_swapped;
3209 best_overall = overall;
3210 best_losers = losers;
3211 best_reload_nregs = reload_nregs;
3212 best_reload_sum = reload_sum;
3213 goal_alt_number = nalt;
3214 }
3215 if (losers == 0)
3216 /* Everything is satisfied. Do not process alternatives
3217 anymore. */
3218 break;
3219 fail:
3220 ;
3221 }
3222 return ok_p;
3223}
3224
3225/* Make reload base reg from address AD. */
3226static rtx
3227base_to_reg (struct address_info *ad)
3228{
3229 enum reg_class cl;
3230 int code = -1;
3231 rtx new_inner = NULL_RTX(rtx) 0;
3232 rtx new_reg = NULL_RTX(rtx) 0;
3233 rtx_insn *insn;
3234 rtx_insn *last_insn = get_last_insn();
3235
3236 lra_assert (ad->disp == ad->disp_term)((void)(!(ad->disp == ad->disp_term) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3236, __FUNCTION__), 0 : 0))
;
3237 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3238 get_index_code (ad));
3239 new_reg = lra_create_new_reg (GET_MODE (*ad->base)((machine_mode) (*ad->base)->mode), NULL_RTX(rtx) 0,
3240 cl, "base");
3241 new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg)((machine_mode) (new_reg)->mode), new_reg,
3242 ad->disp_term == NULLnullptr
3243 ? const0_rtx(const_int_rtx[64])
3244 : *ad->disp_term);
3245 if (!valid_address_p (ad->mode, new_inner, ad->as))
3246 return NULL_RTX(rtx) 0;
3247 insn = emit_insn (gen_rtx_SET (new_reg, *ad->base)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((new_reg
)), ((*ad->base)) )
);
3248 code = recog_memoized (insn);
3249 if (code < 0)
3250 {
3251 delete_insns_since (last_insn);
3252 return NULL_RTX(rtx) 0;
3253 }
3254
3255 return new_inner;
3256}
3257
3258/* Make reload base reg + DISP from address AD. Return the new pseudo. */
3259static rtx
3260base_plus_disp_to_reg (struct address_info *ad, rtx disp)
3261{
3262 enum reg_class cl;
3263 rtx new_reg;
3264
3265 lra_assert (ad->base == ad->base_term)((void)(!(ad->base == ad->base_term) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3265, __FUNCTION__), 0 : 0))
;
3266 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3267 get_index_code (ad));
3268 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term)((machine_mode) (*ad->base_term)->mode), NULL_RTX(rtx) 0,
3269 cl, "base + disp");
3270 lra_emit_add (new_reg, *ad->base_term, disp);
3271 return new_reg;
3272}
3273
3274/* Make reload of index part of address AD. Return the new
3275 pseudo. */
3276static rtx
3277index_part_to_reg (struct address_info *ad)
3278{
3279 rtx new_reg;
3280
3281 new_reg = lra_create_new_reg (GET_MODE (*ad->index)((machine_mode) (*ad->index)->mode), NULL_RTX(rtx) 0,
3282 INDEX_REG_CLASSINDEX_REGS, "index term");
3283 expand_mult (GET_MODE (*ad->index)((machine_mode) (*ad->index)->mode), *ad->index_term,
3284 GEN_INT (get_index_scale (ad))gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (get_index_scale (
ad)))
, new_reg, 1);
3285 return new_reg;
3286}
3287
3288/* Return true if we can add a displacement to address AD, even if that
3289 makes the address invalid. The fix-up code requires any new address
3290 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3291static bool
3292can_add_disp_p (struct address_info *ad)
3293{
3294 return (!ad->autoinc_p
3295 && ad->segment == NULLnullptr
3296 && ad->base == ad->base_term
3297 && ad->disp == ad->disp_term);
3298}
3299
3300/* Make equiv substitution in address AD. Return true if a substitution
3301 was made. */
3302static bool
3303equiv_address_substitution (struct address_info *ad)
3304{
3305 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term;
3306 poly_int64 disp;
3307 HOST_WIDE_INTlong scale;
3308 bool change_p;
3309
3310 base_term = strip_subreg (ad->base_term);
3311 if (base_term == NULLnullptr)
3312 base_reg = new_base_reg = NULL_RTX(rtx) 0;
3313 else
3314 {
3315 base_reg = *base_term;
3316 new_base_reg = get_equiv_with_elimination (base_reg, curr_insn);
3317 }
3318 index_term = strip_subreg (ad->index_term);
3319 if (index_term == NULLnullptr)
3320 index_reg = new_index_reg = NULL_RTX(rtx) 0;
3321 else
3322 {
3323 index_reg = *index_term;
3324 new_index_reg = get_equiv_with_elimination (index_reg, curr_insn);
3325 }
3326 if (base_reg == new_base_reg && index_reg == new_index_reg)
3327 return false;
3328 disp = 0;
3329 change_p = false;
3330 if (lra_dump_file != NULLnullptr)
3331 {
3332 fprintf (lra_dump_file, "Changing address in insn %d ",
3333 INSN_UID (curr_insn));
3334 dump_value_slim (lra_dump_file, *ad->outer, 1);
3335 }
3336 if (base_reg != new_base_reg)
3337 {
3338 poly_int64 offset;
3339 if (REG_P (new_base_reg)(((enum rtx_code) (new_base_reg)->code) == REG))
3340 {
3341 *base_term = new_base_reg;
3342 change_p = true;
3343 }
3344 else if (GET_CODE (new_base_reg)((enum rtx_code) (new_base_reg)->code) == PLUS
3345 && REG_P (XEXP (new_base_reg, 0))(((enum rtx_code) ((((new_base_reg)->u.fld[0]).rt_rtx))->
code) == REG)
3346 && poly_int_rtx_p (XEXP (new_base_reg, 1)(((new_base_reg)->u.fld[1]).rt_rtx), &offset)
3347 && can_add_disp_p (ad))
3348 {
3349 disp += offset;
3350 *base_term = XEXP (new_base_reg, 0)(((new_base_reg)->u.fld[0]).rt_rtx);
3351 change_p = true;
3352 }
3353 if (ad->base_term2 != NULLnullptr)
3354 *ad->base_term2 = *ad->base_term;
3355 }
3356 if (index_reg != new_index_reg)
3357 {
3358 poly_int64 offset;
3359 if (REG_P (new_index_reg)(((enum rtx_code) (new_index_reg)->code) == REG))
3360 {
3361 *index_term = new_index_reg;
3362 change_p = true;
3363 }
3364 else if (GET_CODE (new_index_reg)((enum rtx_code) (new_index_reg)->code) == PLUS
3365 && REG_P (XEXP (new_index_reg, 0))(((enum rtx_code) ((((new_index_reg)->u.fld[0]).rt_rtx))->
code) == REG)
3366 && poly_int_rtx_p (XEXP (new_index_reg, 1)(((new_index_reg)->u.fld[1]).rt_rtx), &offset)
3367 && can_add_disp_p (ad)
3368 && (scale = get_index_scale (ad)))
3369 {
3370 disp += offset * scale;
3371 *index_term = XEXP (new_index_reg, 0)(((new_index_reg)->u.fld[0]).rt_rtx);
3372 change_p = true;
3373 }
3374 }
3375 if (maybe_ne (disp, 0))
3376 {
3377 if (ad->disp != NULLnullptr)
3378 *ad->disp = plus_constant (GET_MODE (*ad->inner)((machine_mode) (*ad->inner)->mode), *ad->disp, disp);
3379 else
3380 {
3381 *ad->inner = plus_constant (GET_MODE (*ad->inner)((machine_mode) (*ad->inner)->mode), *ad->inner, disp);
3382 update_address (ad);
3383 }
3384 change_p = true;
3385 }
3386 if (lra_dump_file != NULLnullptr)
3387 {
3388 if (! change_p)
3389 fprintf (lra_dump_file, " -- no change\n");
3390 else
3391 {
3392 fprintf (lra_dump_file, " on equiv ");
3393 dump_value_slim (lra_dump_file, *ad->outer, 1);
3394 fprintf (lra_dump_file, "\n");
3395 }
3396 }
3397 return change_p;
3398}
3399
3400/* Skip all modifiers and whitespaces in constraint STR and return the
3401 result. */
3402static const char *
3403skip_constraint_modifiers (const char *str)
3404{
3405 for (;;str++)
3406 switch (*str)
3407 {
3408 case '+': case '&' : case '=': case '*': case ' ': case '\t':
3409 case '$': case '^' : case '%': case '?': case '!':
3410 break;
3411 default: return str;
3412 }
3413}
3414
3415/* Major function to make reloads for an address in operand NOP or
3416 check its correctness (If CHECK_ONLY_P is true). The supported
3417 cases are:
3418
3419 1) an address that existed before LRA started, at which point it
3420 must have been valid. These addresses are subject to elimination
3421 and may have become invalid due to the elimination offset being out
3422 of range.
3423
3424 2) an address created by forcing a constant to memory
3425 (force_const_to_mem). The initial form of these addresses might
3426 not be valid, and it is this function's job to make them valid.
3427
3428 3) a frame address formed from a register and a (possibly zero)
3429 constant offset. As above, these addresses might not be valid and
3430 this function must make them so.
3431
3432 Add reloads to the lists *BEFORE and *AFTER. We might need to add
3433 reloads to *AFTER because of inc/dec, {pre, post} modify in the
3434 address. Return true for any RTL change.
3435
3436 The function is a helper function which does not produce all
3437 transformations (when CHECK_ONLY_P is false) which can be
3438 necessary. It does just basic steps. To do all necessary
3439 transformations use function process_address. */
3440static bool
3441process_address_1 (int nop, bool check_only_p,
3442 rtx_insn **before, rtx_insn **after)
3443{
3444 struct address_info ad;
3445 rtx new_reg;
3446 HOST_WIDE_INTlong scale;
3447 rtx op = *curr_id->operand_loc[nop];
3448 rtx mem = extract_mem_from_operand (op);
3449 const char *constraint;
3450 enum constraint_num cn;
3451 bool change_p = false;
3452
3453 if (MEM_P (mem)(((enum rtx_code) (mem)->code) == MEM)
3454 && GET_MODE (mem)((machine_mode) (mem)->mode) == BLKmode((void) 0, E_BLKmode)
3455 && GET_CODE (XEXP (mem, 0))((enum rtx_code) ((((mem)->u.fld[0]).rt_rtx))->code) == SCRATCH)
3456 return false;
3457
3458 constraint
3459 = skip_constraint_modifiers (curr_static_id->operand[nop].constraint);
3460 if (IN_RANGE (constraint[0], '0', '9')((unsigned long) (constraint[0]) - (unsigned long) ('0') <=
(unsigned long) ('9') - (unsigned long) ('0'))
)
3461 {
3462 char *end;
3463 unsigned long dup = strtoul (constraint, &end, 10);
3464 constraint
3465 = skip_constraint_modifiers (curr_static_id->operand[dup].constraint);
3466 }
3467 cn = lookup_constraint (*constraint == '\0' ? "X" : constraint);
3468 /* If we have several alternatives or/and several constraints in an
3469 alternative and we can not say at this stage what constraint will be used,
3470 use unknown constraint. The exception is an address constraint. If
3471 operand has one address constraint, probably all others constraints are
3472 address ones. */
3473 if (constraint[0] != '\0' && get_constraint_type (cn) != CT_ADDRESS
3474 && *skip_constraint_modifiers (constraint
3475 + CONSTRAINT_LEN (constraint[0],insn_constraint_len (constraint[0],constraint)
3476 constraint)insn_constraint_len (constraint[0],constraint)) != '\0')
3477 cn = CONSTRAINT__UNKNOWN;
3478 if (insn_extra_address_constraint (cn)
3479 /* When we find an asm operand with an address constraint that
3480 doesn't satisfy address_operand to begin with, we clear
3481 is_address, so that we don't try to make a non-address fit.
3482 If the asm statement got this far, it's because other
3483 constraints are available, and we'll use them, disregarding
3484 the unsatisfiable address ones. */
3485 && curr_static_id->operand[nop].is_address)
3486 decompose_lea_address (&ad, curr_id->operand_loc[nop]);
3487 /* Do not attempt to decompose arbitrary addresses generated by combine
3488 for asm operands with loose constraints, e.g 'X'.
3489 Need to extract memory from op for special memory constraint,
3490 i.e. bcst_mem_operand in i386 backend. */
3491 else if (MEM_P (mem)(((enum rtx_code) (mem)->code) == MEM)
3492 && !(INSN_CODE (curr_insn)(((curr_insn)->u.fld[5]).rt_int) < 0
3493 && get_constraint_type (cn) == CT_FIXED_FORM
3494 && constraint_satisfied_p (op, cn)))
3495 decompose_mem_address (&ad, mem);
3496 else if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG
3497 && MEM_P (SUBREG_REG (op))(((enum rtx_code) ((((op)->u.fld[0]).rt_rtx))->code) ==
MEM)
)
3498 decompose_mem_address (&ad, SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx));
3499 else
3500 return false;
3501 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3502 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3503 when INDEX_REG_CLASS is a single register class. */
3504 if (ad.base_term != NULLnullptr
3505 && ad.index_term != NULLnullptr
3506 && ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[INDEX_REG_CLASSINDEX_REGS] == 1
3507 && REG_P (*ad.base_term)(((enum rtx_code) (*ad.base_term)->code) == REG)
3508 && REG_P (*ad.index_term)(((enum rtx_code) (*ad.index_term)->code) == REG)
3509 && in_class_p (*ad.base_term, INDEX_REG_CLASSINDEX_REGS, NULLnullptr)
3510 && ! in_class_p (*ad.index_term, INDEX_REG_CLASSINDEX_REGS, NULLnullptr))
3511 {
3512 std::swap (ad.base, ad.index);
3513 std::swap (ad.base_term, ad.index_term);
3514 }
3515 if (! check_only_p)
3516 change_p = equiv_address_substitution (&ad);
3517 if (ad.base_term != NULLnullptr
3518 && (process_addr_reg
3519 (ad.base_term, check_only_p, before,
3520 (ad.autoinc_p
3521 && !(REG_P (*ad.base_term)(((enum rtx_code) (*ad.base_term)->code) == REG)
3522 && find_regno_note (curr_insn, REG_DEAD,
3523 REGNO (*ad.base_term)(rhs_regno(*ad.base_term))) != NULL_RTX(rtx) 0)
3524 ? after : NULLnullptr),
3525 base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3526 get_index_code (&ad)))))
3527 {
3528 change_p = true;
3529 if (ad.base_term2 != NULLnullptr)
3530 *ad.base_term2 = *ad.base_term;
3531 }
3532 if (ad.index_term != NULLnullptr
3533 && process_addr_reg (ad.index_term, check_only_p,
3534 before, NULLnullptr, INDEX_REG_CLASSINDEX_REGS))
3535 change_p = true;
3536
3537 /* Target hooks sometimes don't treat extra-constraint addresses as
3538 legitimate address_operands, so handle them specially. */
3539 if (insn_extra_address_constraint (cn)
3540 && satisfies_address_constraint_p (&ad, cn))
3541 return change_p;
3542
3543 if (check_only_p)
3544 return change_p;
3545
3546 /* There are three cases where the shape of *AD.INNER may now be invalid:
3547
3548 1) the original address was valid, but either elimination or
3549 equiv_address_substitution was applied and that made
3550 the address invalid.
3551
3552 2) the address is an invalid symbolic address created by
3553 force_const_to_mem.
3554
3555 3) the address is a frame address with an invalid offset.
3556
3557 4) the address is a frame address with an invalid base.
3558
3559 All these cases involve a non-autoinc address, so there is no
3560 point revalidating other types. */
3561 if (ad.autoinc_p || valid_address_p (op, &ad, cn))
3562 return change_p;
3563
3564 /* Any index existed before LRA started, so we can assume that the
3565 presence and shape of the index is valid. */
3566 push_to_sequence (*before);
3567 lra_assert (ad.disp == ad.disp_term)((void)(!(ad.disp == ad.disp_term) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3567, __FUNCTION__), 0 : 0))
;
3568 if (ad.base == NULLnullptr)
3569 {
3570 if (ad.index == NULLnullptr)
3571 {
3572 rtx_insn *insn;
3573 rtx_insn *last = get_last_insn ();
3574 int code = -1;
3575 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3576 SCRATCH, SCRATCH);
3577 rtx addr = *ad.inner;
3578
3579 new_reg = lra_create_new_reg (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
, NULL_RTX(rtx) 0, cl, "addr");
3580 if (HAVE_lo_sum0)
3581 {
3582 /* addr => lo_sum (new_base, addr), case (2) above. */
3583 insn = emit_insn (gen_rtx_SETgen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((new_reg
)), ((gen_rtx_fmt_e_stat ((HIGH), (((global_options.x_ix86_pmode
== PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((copy_rtx (addr))) ))) )
3584 (new_reg,gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((new_reg
)), ((gen_rtx_fmt_e_stat ((HIGH), (((global_options.x_ix86_pmode
== PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((copy_rtx (addr))) ))) )
3585 gen_rtx_HIGH (Pmode, copy_rtx (addr)))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((new_reg
)), ((gen_rtx_fmt_e_stat ((HIGH), (((global_options.x_ix86_pmode
== PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((copy_rtx (addr))) ))) )
);
3586 code = recog_memoized (insn);
3587 if (code >= 0)
3588 {
3589 *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr)gen_rtx_fmt_ee_stat ((LO_SUM), (((global_options.x_ix86_pmode
== PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((new_reg)), ((addr)) )
;
3590 if (!valid_address_p (op, &ad, cn))
3591 {
3592 /* Try to put lo_sum into register. */
3593 insn = emit_insn (gen_rtx_SETgen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((new_reg
)), ((gen_rtx_fmt_ee_stat ((LO_SUM), (((global_options.x_ix86_pmode
== PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((new_reg)), ((addr)) ))) )
3594 (new_reg,gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((new_reg
)), ((gen_rtx_fmt_ee_stat ((LO_SUM), (((global_options.x_ix86_pmode
== PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((new_reg)), ((addr)) ))) )
3595 gen_rtx_LO_SUM (Pmode, new_reg, addr))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((new_reg
)), ((gen_rtx_fmt_ee_stat ((LO_SUM), (((global_options.x_ix86_pmode
== PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((new_reg)), ((addr)) ))) )
);
3596 code = recog_memoized (insn);
3597 if (code >= 0)
3598 {
3599 *ad.inner = new_reg;
3600 if (!valid_address_p (op, &ad, cn))
3601 {
3602 *ad.inner = addr;
3603 code = -1;
3604 }
3605 }
3606
3607 }
3608 }
3609 if (code < 0)
3610 delete_insns_since (last);
3611 }
3612
3613 if (code < 0)
3614 {
3615 /* addr => new_base, case (2) above. */
3616 lra_emit_move (new_reg, addr);
3617
3618 for (insn = last == NULL_RTX(rtx) 0 ? get_insns () : NEXT_INSN (last);
3619 insn != NULL_RTX(rtx) 0;
3620 insn = NEXT_INSN (insn))
3621 if (recog_memoized (insn) < 0)
3622 break;
3623 if (insn != NULL_RTX(rtx) 0)
3624 {
3625 /* Do nothing if we cannot generate right insns.
3626 This is analogous to reload pass behavior. */
3627 delete_insns_since (last);
3628 end_sequence ();
3629 return false;
3630 }
3631 *ad.inner = new_reg;
3632 }
3633 }
3634 else
3635 {
3636 /* index * scale + disp => new base + index * scale,
3637 case (1) above. */
3638 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS,
3639 GET_CODE (*ad.index)((enum rtx_code) (*ad.index)->code));
3640
3641 lra_assert (INDEX_REG_CLASS != NO_REGS)((void)(!(INDEX_REGS != NO_REGS) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3641, __FUNCTION__), 0 : 0))
;
3642 new_reg = lra_create_new_reg (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
, NULL_RTX(rtx) 0, cl, "disp");
3643 lra_emit_move (new_reg, *ad.disp);
3644 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg)((machine_mode) (new_reg)->mode),
3645 new_reg, *ad.index);
3646 }
3647 }
3648 else if (ad.index == NULLnullptr)
3649 {
3650 int regno;
3651 enum reg_class cl;
3652 rtx set;
3653 rtx_insn *insns, *last_insn;
3654 /* Try to reload base into register only if the base is invalid
3655 for the address but with valid offset, case (4) above. */
3656 start_sequence ();
3657 new_reg = base_to_reg (&ad);
3658
3659 /* base + disp => new base, cases (1) and (3) above. */
3660 /* Another option would be to reload the displacement into an
3661 index register. However, postreload has code to optimize
3662 address reloads that have the same base and different
3663 displacements, so reloading into an index register would
3664 not necessarily be a win. */
3665 if (new_reg == NULL_RTX(rtx) 0)
3666 {
3667 /* See if the target can split the displacement into a
3668 legitimate new displacement from a local anchor. */
3669 gcc_assert (ad.disp == ad.disp_term)((void)(!(ad.disp == ad.disp_term) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3669, __FUNCTION__), 0 : 0))
;
3670 poly_int64 orig_offset;
3671 rtx offset1, offset2;
3672 if (poly_int_rtx_p (*ad.disp, &orig_offset)
3673 && targetm.legitimize_address_displacement (&offset1, &offset2,
3674 orig_offset,
3675 ad.mode))
3676 {
3677 new_reg = base_plus_disp_to_reg (&ad, offset1);
3678 new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2)gen_rtx_fmt_ee_stat ((PLUS), ((((machine_mode) (new_reg)->
mode))), ((new_reg)), ((offset2)) )
;
3679 }
3680 else
3681 new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3682 }
3683 insns = get_insns ();
3684 last_insn = get_last_insn ();
3685 /* If we generated at least two insns, try last insn source as
3686 an address. If we succeed, we generate one less insn. */
3687 if (REG_P (new_reg)(((enum rtx_code) (new_reg)->code) == REG)
3688 && last_insn != insns
3689 && (set = single_set (last_insn)) != NULL_RTX(rtx) 0
3690 && GET_CODE (SET_SRC (set))((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) == PLUS
3691 && REG_P (XEXP (SET_SRC (set), 0))(((enum rtx_code) (((((((set)->u.fld[1]).rt_rtx))->u.fld
[0]).rt_rtx))->code) == REG)
3692 && CONSTANT_P (XEXP (SET_SRC (set), 1))((rtx_class[(int) (((enum rtx_code) (((((((set)->u.fld[1])
.rt_rtx))->u.fld[1]).rt_rtx))->code))]) == RTX_CONST_OBJ
)
)
3693 {
3694 *ad.inner = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
3695 if (valid_address_p (op, &ad, cn))
3696 {
3697 *ad.base_term = XEXP (SET_SRC (set), 0)((((((set)->u.fld[1]).rt_rtx))->u.fld[0]).rt_rtx);
3698 *ad.disp_term = XEXP (SET_SRC (set), 1)((((((set)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx);
3699 cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3700 get_index_code (&ad));
3701 regno = REGNO (*ad.base_term)(rhs_regno(*ad.base_term));
3702 if (regno >= FIRST_PSEUDO_REGISTER76
3703 && cl != lra_get_allocno_class (regno))
3704 lra_change_class (regno, cl, " Change to", true);
3705 new_reg = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
3706 delete_insns_since (PREV_INSN (last_insn));
3707 }
3708 }
3709 end_sequence ();
3710 emit_insn (insns);
3711 *ad.inner = new_reg;
3712 }
3713 else if (ad.disp_term != NULLnullptr)
3714 {
3715 /* base + scale * index + disp => new base + scale * index,
3716 case (1) above. */
3717 gcc_assert (ad.disp == ad.disp_term)((void)(!(ad.disp == ad.disp_term) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3717, __FUNCTION__), 0 : 0))
;
3718 new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3719 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg)((machine_mode) (new_reg)->mode),
3720 new_reg, *ad.index);
3721 }
3722 else if ((scale = get_index_scale (&ad)) == 1)
3723 {
3724 /* The last transformation to one reg will be made in
3725 curr_insn_transform function. */
3726 end_sequence ();
3727 return false;
3728 }
3729 else if (scale != 0)
3730 {
3731 /* base + scale * index => base + new_reg,
3732 case (1) above.
3733 Index part of address may become invalid. For example, we
3734 changed pseudo on the equivalent memory and a subreg of the
3735 pseudo onto the memory of different mode for which the scale is
3736 prohibitted. */
3737 new_reg = index_part_to_reg (&ad);
3738 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg)((machine_mode) (new_reg)->mode),
3739 *ad.base_term, new_reg);
3740 }
3741 else
3742 {
3743 enum reg_class cl = base_reg_class (ad.mode, ad.as,
3744 SCRATCH, SCRATCH);
3745 rtx addr = *ad.inner;
3746
3747 new_reg = lra_create_new_reg (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
, NULL_RTX(rtx) 0, cl, "addr");
3748 /* addr => new_base. */
3749 lra_emit_move (new_reg, addr);
3750 *ad.inner = new_reg;
3751 }
3752 *before = get_insns ();
3753 end_sequence ();
3754 return true;
3755}
3756
3757/* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3758 Use process_address_1 as a helper function. Return true for any
3759 RTL changes.
3760
3761 If CHECK_ONLY_P is true, just check address correctness. Return
3762 false if the address correct. */
3763static bool
3764process_address (int nop, bool check_only_p,
3765 rtx_insn **before, rtx_insn **after)
3766{
3767 bool res = false;
3768
3769 while (process_address_1 (nop, check_only_p, before, after))
3770 {
3771 if (check_only_p)
3772 return true;
3773 res = true;
3774 }
3775 return res;
3776}
3777
3778/* Emit insns to reload VALUE into a new register. VALUE is an
3779 auto-increment or auto-decrement RTX whose operand is a register or
3780 memory location; so reloading involves incrementing that location.
3781 IN is either identical to VALUE, or some cheaper place to reload
3782 value being incremented/decremented from.
3783
3784 INC_AMOUNT is the number to increment or decrement by (always
3785 positive and ignored for POST_MODIFY/PRE_MODIFY).
3786
3787 Return pseudo containing the result. */
3788static rtx
3789emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount)
3790{
3791 /* REG or MEM to be copied and incremented. */
3792 rtx incloc = XEXP (value, 0)(((value)->u.fld[0]).rt_rtx);
3793 /* Nonzero if increment after copying. */
3794 int post = (GET_CODE (value)((enum rtx_code) (value)->code) == POST_DEC || GET_CODE (value)((enum rtx_code) (value)->code) == POST_INC
3795 || GET_CODE (value)((enum rtx_code) (value)->code) == POST_MODIFY);
3796 rtx_insn *last;
3797 rtx inc;
3798 rtx_insn *add_insn;
3799 int code;
3800 rtx real_in = in == value ? incloc : in;
3801 rtx result;
3802 bool plus_p = true;
3803
3804 if (GET_CODE (value)((enum rtx_code) (value)->code) == PRE_MODIFY || GET_CODE (value)((enum rtx_code) (value)->code) == POST_MODIFY)
3805 {
3806 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS((void)(!(((enum rtx_code) ((((value)->u.fld[1]).rt_rtx))->
code) == PLUS || ((enum rtx_code) ((((value)->u.fld[1]).rt_rtx
))->code) == MINUS) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3807, __FUNCTION__), 0 : 0))
3807 || GET_CODE (XEXP (value, 1)) == MINUS)((void)(!(((enum rtx_code) ((((value)->u.fld[1]).rt_rtx))->
code) == PLUS || ((enum rtx_code) ((((value)->u.fld[1]).rt_rtx
))->code) == MINUS) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3807, __FUNCTION__), 0 : 0))
;
3808 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0)))((void)(!(rtx_equal_p (((((((value)->u.fld[1]).rt_rtx))->
u.fld[0]).rt_rtx), (((value)->u.fld[0]).rt_rtx))) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3808, __FUNCTION__), 0 : 0))
;
3809 plus_p = GET_CODE (XEXP (value, 1))((enum rtx_code) ((((value)->u.fld[1]).rt_rtx))->code) == PLUS;
3810 inc = XEXP (XEXP (value, 1), 1)((((((value)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx);
3811 }
3812 else
3813 {
3814 if (GET_CODE (value)((enum rtx_code) (value)->code) == PRE_DEC || GET_CODE (value)((enum rtx_code) (value)->code) == POST_DEC)
3815 inc_amount = -inc_amount;
3816
3817 inc = gen_int_mode (inc_amount, GET_MODE (value)((machine_mode) (value)->mode));
3818 }
3819
3820 if (! post && REG_P (incloc)(((enum rtx_code) (incloc)->code) == REG))
3821 result = incloc;
3822 else
3823 result = lra_create_new_reg (GET_MODE (value)((machine_mode) (value)->mode), value, new_rclass,
3824 "INC/DEC result");
3825
3826 if (real_in != result)
3827 {
3828 /* First copy the location to the result register. */
3829 lra_assert (REG_P (result))((void)(!((((enum rtx_code) (result)->code) == REG)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3829, __FUNCTION__), 0 : 0))
;
3830 emit_insn (gen_move_insn (result, real_in));
3831 }
3832
3833 /* We suppose that there are insns to add/sub with the constant
3834 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
3835 old reload worked with this assumption. If the assumption
3836 becomes wrong, we should use approach in function
3837 base_plus_disp_to_reg. */
3838 if (in == value)
3839 {
3840 /* See if we can directly increment INCLOC. */
3841 last = get_last_insn ();
3842 add_insn = emit_insn (plus_p
3843 ? gen_add2_insn (incloc, inc)
3844 : gen_sub2_insn (incloc, inc));
3845
3846 code = recog_memoized (add_insn);
3847 if (code >= 0)
3848 {
3849 if (! post && result != incloc)
3850 emit_insn (gen_move_insn (result, incloc));
3851 return result;
3852 }
3853 delete_insns_since (last);
3854 }
3855
3856 /* If couldn't do the increment directly, must increment in RESULT.
3857 The way we do this depends on whether this is pre- or
3858 post-increment. For pre-increment, copy INCLOC to the reload
3859 register, increment it there, then save back. */
3860 if (! post)
3861 {
3862 if (real_in != result)
3863 emit_insn (gen_move_insn (result, real_in));
3864 if (plus_p)
3865 emit_insn (gen_add2_insn (result, inc));
3866 else
3867 emit_insn (gen_sub2_insn (result, inc));
3868 if (result != incloc)
3869 emit_insn (gen_move_insn (incloc, result));
3870 }
3871 else
3872 {
3873 /* Post-increment.
3874
3875 Because this might be a jump insn or a compare, and because
3876 RESULT may not be available after the insn in an input
3877 reload, we must do the incrementing before the insn being
3878 reloaded for.
3879
3880 We have already copied IN to RESULT. Increment the copy in
3881 RESULT, save that back, then decrement RESULT so it has
3882 the original value. */
3883 if (plus_p)
3884 emit_insn (gen_add2_insn (result, inc));
3885 else
3886 emit_insn (gen_sub2_insn (result, inc));
3887 emit_insn (gen_move_insn (incloc, result));
3888 /* Restore non-modified value for the result. We prefer this
3889 way because it does not require an additional hard
3890 register. */
3891 if (plus_p)
3892 {
3893 poly_int64 offset;
3894 if (poly_int_rtx_p (inc, &offset))
3895 emit_insn (gen_add2_insn (result,
3896 gen_int_mode (-offset,
3897 GET_MODE (result)((machine_mode) (result)->mode))));
3898 else
3899 emit_insn (gen_sub2_insn (result, inc));
3900 }
3901 else
3902 emit_insn (gen_add2_insn (result, inc));
3903 }
3904 return result;
3905}
3906
3907/* Return true if the current move insn does not need processing as we
3908 already know that it satisfies its constraints. */
3909static bool
3910simple_move_p (void)
3911{
3912 rtx dest, src;
3913 enum reg_class dclass, sclass;
3914
3915 lra_assert (curr_insn_set != NULL_RTX)((void)(!(curr_insn_set != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 3915, __FUNCTION__), 0 : 0))
;
3916 dest = SET_DEST (curr_insn_set)(((curr_insn_set)->u.fld[0]).rt_rtx);
3917 src = SET_SRC (curr_insn_set)(((curr_insn_set)->u.fld[1]).rt_rtx);
3918
3919 /* If the instruction has multiple sets we need to process it even if it
3920 is single_set. This can happen if one or more of the SETs are dead.
3921 See PR73650. */
3922 if (multiple_sets (curr_insn))
3923 return false;
3924
3925 return ((dclass = get_op_class (dest)) != NO_REGS
3926 && (sclass = get_op_class (src)) != NO_REGS
3927 /* The backend guarantees that register moves of cost 2
3928 never need reloads. */
3929 && targetm.register_move_cost (GET_MODE (src)((machine_mode) (src)->mode), sclass, dclass) == 2);
3930 }
3931
3932/* Swap operands NOP and NOP + 1. */
3933static inline void
3934swap_operands (int nop)
3935{
3936 std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]);
3937 std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]);
3938 std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]);
3939 std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]);
3940 /* Swap the duplicates too. */
3941 lra_update_dup (curr_id, nop);
3942 lra_update_dup (curr_id, nop + 1);
3943}
3944
3945/* Main entry point of the constraint code: search the body of the
3946 current insn to choose the best alternative. It is mimicking insn
3947 alternative cost calculation model of former reload pass. That is
3948 because machine descriptions were written to use this model. This
3949 model can be changed in future. Make commutative operand exchange
3950 if it is chosen.
3951
3952 if CHECK_ONLY_P is false, do RTL changes to satisfy the
3953 constraints. Return true if any change happened during function
3954 call.
3955
3956 If CHECK_ONLY_P is true then don't do any transformation. Just
3957 check that the insn satisfies all constraints. If the insn does
3958 not satisfy any constraint, return true. */
3959static bool
3960curr_insn_transform (bool check_only_p)
3961{
3962 int i, j, k;
3963 int n_operands;
3964 int n_alternatives;
3965 int n_outputs;
3966 int commutative;
3967 signed char goal_alt_matched[MAX_RECOG_OPERANDS30][MAX_RECOG_OPERANDS30];
3968 signed char match_inputs[MAX_RECOG_OPERANDS30 + 1];
3969 signed char outputs[MAX_RECOG_OPERANDS30 + 1];
3970 rtx_insn *before, *after;
3971 bool alt_p = false;
3972 /* Flag that the insn has been changed through a transformation. */
3973 bool change_p;
3974 bool sec_mem_p;
3975 bool use_sec_mem_p;
3976 int max_regno_before;
3977 int reused_alternative_num;
3978
3979 curr_insn_set = single_set (curr_insn);
3980 if (curr_insn_set != NULL_RTX(rtx) 0 && simple_move_p ())
3981 {
3982 /* We assume that the corresponding insn alternative has no
3983 earlier clobbers. If it is not the case, don't define move
3984 cost equal to 2 for the corresponding register classes. */
3985 lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT-2);
3986 return false;
3987 }
3988
3989 no_input_reloads_p = no_output_reloads_p = false;
3990 goal_alt_number = -1;
3991 change_p = sec_mem_p = false;
3992
3993 /* CALL_INSNs are not allowed to have any output reloads. */
3994 if (CALL_P (curr_insn)(((enum rtx_code) (curr_insn)->code) == CALL_INSN))
3995 no_output_reloads_p = true;
3996
3997 n_operands = curr_static_id->n_operands;
3998 n_alternatives = curr_static_id->n_alternatives;
3999
4000 /* Just return "no reloads" if insn has no operands with
4001 constraints. */
4002 if (n_operands == 0 || n_alternatives == 0)
4003 return false;
4004
4005 max_regno_before = max_reg_num ();
4006
4007 for (i = 0; i < n_operands; i++)
4008 {
4009 goal_alt_matched[i][0] = -1;
4010 goal_alt_matches[i] = -1;
4011 }
4012
4013 commutative = curr_static_id->commutative;
4014
4015 /* Now see what we need for pseudos that didn't get hard regs or got
4016 the wrong kind of hard reg. For this, we must consider all the
4017 operands together against the register constraints. */
4018
4019 best_losers = best_overall = INT_MAX2147483647;
4020 best_reload_sum = 0;
4021
4022 curr_swapped = false;
4023 goal_alt_swapped = false;
4024
4025 if (! check_only_p)
4026 /* Make equivalence substitution and memory subreg elimination
4027 before address processing because an address legitimacy can
4028 depend on memory mode. */
4029 for (i = 0; i < n_operands; i++)
4030 {
4031 rtx op, subst, old;
4032 bool op_change_p = false;
4033
4034 if (curr_static_id->operand[i].is_operator)
4035 continue;
4036
4037 old = op = *curr_id->operand_loc[i];
4038 if (GET_CODE (old)((enum rtx_code) (old)->code) == SUBREG)
4039 old = SUBREG_REG (old)(((old)->u.fld[0]).rt_rtx);
4040 subst = get_equiv_with_elimination (old, curr_insn);
4041 original_subreg_reg_mode[i] = VOIDmode((void) 0, E_VOIDmode);
4042 equiv_substition_p[i] = false;
4043 if (subst != old)
4044 {
4045 equiv_substition_p[i] = true;
4046 subst = copy_rtx (subst);
4047 lra_assert (REG_P (old))((void)(!((((enum rtx_code) (old)->code) == REG)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4047, __FUNCTION__), 0 : 0))
;
4048 if (GET_CODE (op)((enum rtx_code) (op)->code) != SUBREG)
4049 *curr_id->operand_loc[i] = subst;
4050 else
4051 {
4052 SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx) = subst;
4053 if (GET_MODE (subst)((machine_mode) (subst)->mode) == VOIDmode((void) 0, E_VOIDmode))
4054 original_subreg_reg_mode[i] = GET_MODE (old)((machine_mode) (old)->mode);
4055 }
4056 if (lra_dump_file != NULLnullptr)
4057 {
4058 fprintf (lra_dump_file,
4059 "Changing pseudo %d in operand %i of insn %u on equiv ",
4060 REGNO (old)(rhs_regno(old)), i, INSN_UID (curr_insn));
4061 dump_value_slim (lra_dump_file, subst, 1);
4062 fprintf (lra_dump_file, "\n");
4063 }
4064 op_change_p = change_p = true;
4065 }
4066 if (simplify_operand_subreg (i, GET_MODE (old)((machine_mode) (old)->mode)) || op_change_p)
4067 {
4068 change_p = true;
4069 lra_update_dup (curr_id, i);
4070 }
4071 }
4072
4073 /* Reload address registers and displacements. We do it before
4074 finding an alternative because of memory constraints. */
4075 before = after = NULLnullptr;
4076 for (i = 0; i < n_operands; i++)
4077 if (! curr_static_id->operand[i].is_operator
4078 && process_address (i, check_only_p, &before, &after))
4079 {
4080 if (check_only_p)
4081 return true;
4082 change_p = true;
4083 lra_update_dup (curr_id, i);
4084 }
4085
4086 if (change_p)
4087 /* If we've changed the instruction then any alternative that
4088 we chose previously may no longer be valid. */
4089 lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT-1);
4090
4091 if (! check_only_p && curr_insn_set != NULL_RTX(rtx) 0
4092 && check_and_process_move (&change_p, &sec_mem_p))
4093 return change_p;
4094
4095 try_swapped:
4096
4097 reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT-1 : curr_id->used_insn_alternative;
4098 if (lra_dump_file != NULLnullptr && reused_alternative_num >= 0)
4099 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n",
4100 reused_alternative_num, INSN_UID (curr_insn));
4101
4102 if (process_alt_operands (reused_alternative_num))
4103 alt_p = true;
4104
4105 if (check_only_p)
4106 return ! alt_p || best_losers != 0;
4107
4108 /* If insn is commutative (it's safe to exchange a certain pair of
4109 operands) then we need to try each alternative twice, the second
4110 time matching those two operands as if we had exchanged them. To
4111 do this, really exchange them in operands.
4112
4113 If we have just tried the alternatives the second time, return
4114 operands to normal and drop through. */
4115
4116 if (reused_alternative_num < 0 && commutative >= 0)
4117 {
4118 curr_swapped = !curr_swapped;
4119 if (curr_swapped)
4120 {
4121 swap_operands (commutative);
4122 goto try_swapped;
4123 }
4124 else
4125 swap_operands (commutative);
4126 }
4127
4128 if (! alt_p && ! sec_mem_p)
4129 {
4130 /* No alternative works with reloads?? */
4131 if (INSN_CODE (curr_insn)(((curr_insn)->u.fld[5]).rt_int) >= 0)
4132 fatal_insn ("unable to generate reloads for:", curr_insn)_fatal_insn ("unable to generate reloads for:", curr_insn, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4132, __FUNCTION__)
;
4133 error_for_asm (curr_insn,
4134 "inconsistent operand constraints in an %<asm%>");
4135 lra_asm_error_p = true;
4136 if (! JUMP_P (curr_insn)(((enum rtx_code) (curr_insn)->code) == JUMP_INSN))
4137 {
4138 /* Avoid further trouble with this insn. Don't generate use
4139 pattern here as we could use the insn SP offset. */
4140 lra_set_insn_deleted (curr_insn);
4141 }
4142 else
4143 {
4144 lra_invalidate_insn_data (curr_insn);
4145 ira_nullify_asm_goto (curr_insn);
4146 lra_update_insn_regno_info (curr_insn);
4147 }
4148 return true;
4149 }
4150
4151 /* If the best alternative is with operands 1 and 2 swapped, swap
4152 them. Update the operand numbers of any reloads already
4153 pushed. */
4154
4155 if (goal_alt_swapped)
4156 {
4157 if (lra_dump_file != NULLnullptr)
4158 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n",
4159 INSN_UID (curr_insn));
4160
4161 /* Swap the duplicates too. */
4162 swap_operands (commutative);
4163 change_p = true;
4164 }
4165
4166 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
4167 too conservatively. So we use the secondary memory only if there
4168 is no any alternative without reloads. */
4169 use_sec_mem_p = false;
4170 if (! alt_p)
4171 use_sec_mem_p = true;
4172 else if (sec_mem_p)
4173 {
4174 for (i = 0; i < n_operands; i++)
4175 if (! goal_alt_win[i] && ! goal_alt_match_win[i])
4176 break;
4177 use_sec_mem_p = i < n_operands;
4178 }
4179
4180 if (use_sec_mem_p)
4181 {
4182 int in = -1, out = -1;
4183 rtx new_reg, src, dest, rld;
4184 machine_mode sec_mode, rld_mode;
4185
4186 lra_assert (curr_insn_set != NULL_RTX && sec_mem_p)((void)(!(curr_insn_set != (rtx) 0 && sec_mem_p) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4186, __FUNCTION__), 0 : 0))
;
4187 dest = SET_DEST (curr_insn_set)(((curr_insn_set)->u.fld[0]).rt_rtx);
4188 src = SET_SRC (curr_insn_set)(((curr_insn_set)->u.fld[1]).rt_rtx);
4189 for (i = 0; i < n_operands; i++)
4190 if (*curr_id->operand_loc[i] == dest)
4191 out = i;
4192 else if (*curr_id->operand_loc[i] == src)
4193 in = i;
4194 for (i = 0; i < curr_static_id->n_dups; i++)
4195 if (out < 0 && *curr_id->dup_loc[i] == dest)
4196 out = curr_static_id->dup_num[i];
4197 else if (in < 0 && *curr_id->dup_loc[i] == src)
4198 in = curr_static_id->dup_num[i];
4199 lra_assert (out >= 0 && in >= 0((void)(!(out >= 0 && in >= 0 && curr_static_id
->operand[out].type == OP_OUT && curr_static_id->
operand[in].type == OP_IN) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4201, __FUNCTION__), 0 : 0))
4200 && curr_static_id->operand[out].type == OP_OUT((void)(!(out >= 0 && in >= 0 && curr_static_id
->operand[out].type == OP_OUT && curr_static_id->
operand[in].type == OP_IN) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4201, __FUNCTION__), 0 : 0))
4201 && curr_static_id->operand[in].type == OP_IN)((void)(!(out >= 0 && in >= 0 && curr_static_id
->operand[out].type == OP_OUT && curr_static_id->
operand[in].type == OP_IN) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4201, __FUNCTION__), 0 : 0))
;
4202 rld = partial_subreg_p (GET_MODE (src)((machine_mode) (src)->mode), GET_MODE (dest)((machine_mode) (dest)->mode)) ? src : dest;
4203 rld_mode = GET_MODE (rld)((machine_mode) (rld)->mode);
4204 sec_mode = targetm.secondary_memory_needed_mode (rld_mode);
4205 new_reg = lra_create_new_reg (sec_mode, NULL_RTX(rtx) 0,
4206 NO_REGS, "secondary");
4207 /* If the mode is changed, it should be wider. */
4208 lra_assert (!partial_subreg_p (sec_mode, rld_mode))((void)(!(!partial_subreg_p (sec_mode, rld_mode)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4208, __FUNCTION__), 0 : 0))
;
4209 if (sec_mode != rld_mode)
4210 {
4211 /* If the target says specifically to use another mode for
4212 secondary memory moves we cannot reuse the original
4213 insn. */
4214 after = emit_spill_move (false, new_reg, dest);
4215 lra_process_new_insns (curr_insn, NULLnullptr, after,
4216 "Inserting the sec. move");
4217 /* We may have non null BEFORE here (e.g. after address
4218 processing. */
4219 push_to_sequence (before);
4220 before = emit_spill_move (true, new_reg, src);
4221 emit_insn (before);
4222 before = get_insns ();
4223 end_sequence ();
4224 lra_process_new_insns (curr_insn, before, NULLnullptr, "Changing on");
4225 lra_set_insn_deleted (curr_insn);
4226 }
4227 else if (dest == rld)
4228 {
4229 *curr_id->operand_loc[out] = new_reg;
4230 lra_update_dup (curr_id, out);
4231 after = emit_spill_move (false, new_reg, dest);
4232 lra_process_new_insns (curr_insn, NULLnullptr, after,
4233 "Inserting the sec. move");
4234 }
4235 else
4236 {
4237 *curr_id->operand_loc[in] = new_reg;
4238 lra_update_dup (curr_id, in);
4239 /* See comments above. */
4240 push_to_sequence (before);
4241 before = emit_spill_move (true, new_reg, src);
4242 emit_insn (before);
4243 before = get_insns ();
4244 end_sequence ();
4245 lra_process_new_insns (curr_insn, before, NULLnullptr,
4246 "Inserting the sec. move");
4247 }
4248 lra_update_insn_regno_info (curr_insn);
4249 return true;
4250 }
4251
4252 lra_assert (goal_alt_number >= 0)((void)(!(goal_alt_number >= 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4252, __FUNCTION__), 0 : 0))
;
4253 lra_set_used_insn_alternative (curr_insn, goal_alt_number);
4254
4255 if (lra_dump_file != NULLnullptr)
4256 {
4257 const char *p;
4258
4259 fprintf (lra_dump_file, " Choosing alt %d in insn %u:",
4260 goal_alt_number, INSN_UID (curr_insn));
4261 for (i = 0; i < n_operands; i++)
4262 {
4263 p = (curr_static_id->operand_alternative
4264 [goal_alt_number * n_operands + i].constraint);
4265 if (*p == '\0')
4266 continue;
4267 fprintf (lra_dump_file, " (%d) ", i);
4268 for (; *p != '\0' && *p != ',' && *p != '#'; p++)
4269 fputc (*p, lra_dump_file);
4270 }
4271 if (INSN_CODE (curr_insn)(((curr_insn)->u.fld[5]).rt_int) >= 0
4272 && (p = get_insn_name (INSN_CODE (curr_insn)(((curr_insn)->u.fld[5]).rt_int))) != NULLnullptr)
4273 fprintf (lra_dump_file, " {%s}", p);
4274 if (maybe_ne (curr_id->sp_offset, 0))
4275 {
4276 fprintf (lra_dump_file, " (sp_off=");
4277 print_dec (curr_id->sp_offset, lra_dump_file);
4278 fprintf (lra_dump_file, ")");
4279 }
4280 fprintf (lra_dump_file, "\n");
4281 }
4282
4283 /* Right now, for any pair of operands I and J that are required to
4284 match, with J < I, goal_alt_matches[I] is J. Add I to
4285 goal_alt_matched[J]. */
4286
4287 for (i = 0; i < n_operands; i++)
4288 if ((j = goal_alt_matches[i]) >= 0)
4289 {
4290 for (k = 0; goal_alt_matched[j][k] >= 0; k++)
4291 ;
4292 /* We allow matching one output operand and several input
4293 operands. */
4294 lra_assert (k == 0((void)(!(k == 0 || (curr_static_id->operand[j].type == OP_OUT
&& curr_static_id->operand[i].type == OP_IN &&
(curr_static_id->operand [goal_alt_matched[j][0]].type ==
OP_IN))) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4298, __FUNCTION__), 0 : 0))
4295 || (curr_static_id->operand[j].type == OP_OUT((void)(!(k == 0 || (curr_static_id->operand[j].type == OP_OUT
&& curr_static_id->operand[i].type == OP_IN &&
(curr_static_id->operand [goal_alt_matched[j][0]].type ==
OP_IN))) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4298, __FUNCTION__), 0 : 0))
4296 && curr_static_id->operand[i].type == OP_IN((void)(!(k == 0 || (curr_static_id->operand[j].type == OP_OUT
&& curr_static_id->operand[i].type == OP_IN &&
(curr_static_id->operand [goal_alt_matched[j][0]].type ==
OP_IN))) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4298, __FUNCTION__), 0 : 0))
4297 && (curr_static_id->operand((void)(!(k == 0 || (curr_static_id->operand[j].type == OP_OUT
&& curr_static_id->operand[i].type == OP_IN &&
(curr_static_id->operand [goal_alt_matched[j][0]].type ==
OP_IN))) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4298, __FUNCTION__), 0 : 0))
4298 [goal_alt_matched[j][0]].type == OP_IN)))((void)(!(k == 0 || (curr_static_id->operand[j].type == OP_OUT
&& curr_static_id->operand[i].type == OP_IN &&
(curr_static_id->operand [goal_alt_matched[j][0]].type ==
OP_IN))) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4298, __FUNCTION__), 0 : 0))
;
4299 goal_alt_matched[j][k] = i;
4300 goal_alt_matched[j][k + 1] = -1;
4301 }
4302
4303 for (i = 0; i < n_operands; i++)
4304 goal_alt_win[i] |= goal_alt_match_win[i];
4305
4306 /* Any constants that aren't allowed and can't be reloaded into
4307 registers are here changed into memory references. */
4308 for (i = 0; i < n_operands; i++)
4309 if (goal_alt_win[i])
4310 {
4311 int regno;
4312 enum reg_class new_class;
4313 rtx reg = *curr_id->operand_loc[i];
4314
4315 if (GET_CODE (reg)((enum rtx_code) (reg)->code) == SUBREG)
4316 reg = SUBREG_REG (reg)(((reg)->u.fld[0]).rt_rtx);
4317
4318 if (REG_P (reg)(((enum rtx_code) (reg)->code) == REG) && (regno = REGNO (reg)(rhs_regno(reg))) >= FIRST_PSEUDO_REGISTER76)
4319 {
4320 bool ok_p = in_class_p (reg, goal_alt[i], &new_class);
4321
4322 if (new_class != NO_REGS && get_reg_class (regno) != new_class)
4323 {
4324 lra_assert (ok_p)((void)(!(ok_p) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4324, __FUNCTION__), 0 : 0))
;
4325 lra_change_class (regno, new_class, " Change to", true);
4326 }
4327 }
4328 }
4329 else
4330 {
4331 const char *constraint;
4332 char c;
4333 rtx op = *curr_id->operand_loc[i];
4334 rtx subreg = NULL_RTX(rtx) 0;
4335 machine_mode mode = curr_operand_mode[i];
4336
4337 if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG)
4338 {
4339 subreg = op;
4340 op = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);
4341 mode = GET_MODE (op)((machine_mode) (op)->mode);
4342 }
4343
4344 if (CONST_POOL_OK_P (mode, op)((mode) != ((void) 0, E_VOIDmode) && ((rtx_class[(int
) (((enum rtx_code) (op)->code))]) == RTX_CONST_OBJ) &&
((enum rtx_code) (op)->code) != HIGH && GET_MODE_SIZE
(mode).is_constant () && !targetm.cannot_force_const_mem
(mode, op))
4345 && ((targetm.preferred_reload_class
4346 (op, (enum reg_class) goal_alt[i]) == NO_REGS)
4347 || no_input_reloads_p))
4348 {
4349 rtx tem = force_const_mem (mode, op);
4350
4351 change_p = true;
4352 if (subreg != NULL_RTX(rtx) 0)
4353 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)(((subreg)->u.fld[1]).rt_subreg));
4354
4355 *curr_id->operand_loc[i] = tem;
4356 lra_update_dup (curr_id, i);
4357 process_address (i, false, &before, &after);
4358
4359 /* If the alternative accepts constant pool refs directly
4360 there will be no reload needed at all. */
4361 if (subreg != NULL_RTX(rtx) 0)
4362 continue;
4363 /* Skip alternatives before the one requested. */
4364 constraint = (curr_static_id->operand_alternative
4365 [goal_alt_number * n_operands + i].constraint);
4366 for (;
4367 (c = *constraint) && c != ',' && c != '#';
4368 constraint += CONSTRAINT_LEN (c, constraint)insn_constraint_len (c,constraint))
4369 {
4370 enum constraint_num cn = lookup_constraint (constraint);
4371 if ((insn_extra_memory_constraint (cn)
4372 || insn_extra_special_memory_constraint (cn)
4373 || insn_extra_relaxed_memory_constraint (cn))
4374 && satisfies_memory_constraint_p (tem, cn))
4375 break;
4376 }
4377 if (c == '\0' || c == ',' || c == '#')
4378 continue;
4379
4380 goal_alt_win[i] = true;
4381 }
4382 }
4383
4384 n_outputs = 0;
4385 for (i = 0; i < n_operands; i++)
4386 if (curr_static_id->operand[i].type == OP_OUT)
4387 outputs[n_outputs++] = i;
4388 outputs[n_outputs] = -1;
4389 for (i = 0; i < n_operands; i++)
4390 {
4391 int regno;
4392 bool optional_p = false;
4393 rtx old, new_reg;
4394 rtx op = *curr_id->operand_loc[i];
4395
4396 if (goal_alt_win[i])
4397 {
4398 if (goal_alt[i] == NO_REGS
4399 && REG_P (op)(((enum rtx_code) (op)->code) == REG)
4400 /* When we assign NO_REGS it means that we will not
4401 assign a hard register to the scratch pseudo by
4402 assigment pass and the scratch pseudo will be
4403 spilled. Spilled scratch pseudos are transformed
4404 back to scratches at the LRA end. */
4405 && ira_former_scratch_operand_p (curr_insn, i)
4406 && ira_former_scratch_p (REGNO (op)(rhs_regno(op))))
4407 {
4408 int regno = REGNO (op)(rhs_regno(op));
4409 lra_change_class (regno, NO_REGS, " Change to", true);
4410 if (lra_get_regno_hard_regno (regno) >= 0)
4411 /* We don't have to mark all insn affected by the
4412 spilled pseudo as there is only one such insn, the
4413 current one. */
4414 reg_renumber[regno] = -1;
4415 lra_assert (bitmap_single_bit_set_p((void)(!(bitmap_single_bit_set_p (&lra_reg_info[(rhs_regno
(op))].insn_bitmap)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4416, __FUNCTION__), 0 : 0))
4416 (&lra_reg_info[REGNO (op)].insn_bitmap))((void)(!(bitmap_single_bit_set_p (&lra_reg_info[(rhs_regno
(op))].insn_bitmap)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4416, __FUNCTION__), 0 : 0))
;
4417 }
4418 /* We can do an optional reload. If the pseudo got a hard
4419 reg, we might improve the code through inheritance. If
4420 it does not get a hard register we coalesce memory/memory
4421 moves later. Ignore move insns to avoid cycling. */
4422 if (! lra_simple_p
4423 && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES2
4424 && goal_alt[i] != NO_REGS && REG_P (op)(((enum rtx_code) (op)->code) == REG)
4425 && (regno = REGNO (op)(rhs_regno(op))) >= FIRST_PSEUDO_REGISTER76
4426 && regno < new_regno_start
4427 && ! ira_former_scratch_p (regno)
4428 && reg_renumber[regno] < 0
4429 /* Check that the optional reload pseudo will be able to
4430 hold given mode value. */
4431 && ! (prohibited_class_reg_set_mode_p
4432 (goal_alt[i], reg_class_contents(this_target_hard_regs->x_reg_class_contents)[goal_alt[i]],
4433 PSEUDO_REGNO_MODE (regno)((machine_mode) (regno_reg_rtx[regno])->mode)))
4434 && (curr_insn_set == NULL_RTX(rtx) 0
4435 || !((REG_P (SET_SRC (curr_insn_set))(((enum rtx_code) ((((curr_insn_set)->u.fld[1]).rt_rtx))->
code) == REG)
4436 || MEM_P (SET_SRC (curr_insn_set))(((enum rtx_code) ((((curr_insn_set)->u.fld[1]).rt_rtx))->
code) == MEM)
4437 || GET_CODE (SET_SRC (curr_insn_set))((enum rtx_code) ((((curr_insn_set)->u.fld[1]).rt_rtx))->
code)
== SUBREG)
4438 && (REG_P (SET_DEST (curr_insn_set))(((enum rtx_code) ((((curr_insn_set)->u.fld[0]).rt_rtx))->
code) == REG)
4439 || MEM_P (SET_DEST (curr_insn_set))(((enum rtx_code) ((((curr_insn_set)->u.fld[0]).rt_rtx))->
code) == MEM)
4440 || GET_CODE (SET_DEST (curr_insn_set))((enum rtx_code) ((((curr_insn_set)->u.fld[0]).rt_rtx))->
code)
== SUBREG))))
4441 optional_p = true;
4442 else if (goal_alt_matched[i][0] != -1
4443 && curr_static_id->operand[i].type == OP_OUT
4444 && (curr_static_id->operand_alternative
4445 [goal_alt_number * n_operands + i].earlyclobber)
4446 && REG_P (op)(((enum rtx_code) (op)->code) == REG))
4447 {
4448 for (j = 0; goal_alt_matched[i][j] != -1; j++)
4449 {
4450 rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]];
4451
4452 if (REG_P (op2)(((enum rtx_code) (op2)->code) == REG) && REGNO (op)(rhs_regno(op)) != REGNO (op2)(rhs_regno(op2)))
4453 break;
4454 }
4455 if (goal_alt_matched[i][j] != -1)
4456 {
4457 /* Generate reloads for different output and matched
4458 input registers. This is the easiest way to avoid
4459 creation of non-existing register conflicts in
4460 lra-lives.c. */
4461 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
4462 &after, TRUEtrue);
4463 }
4464 continue;
4465 }
4466 else
4467 continue;
4468 }
4469
4470 /* Operands that match previous ones have already been handled. */
4471 if (goal_alt_matches[i] >= 0)
4472 continue;
4473
4474 /* We should not have an operand with a non-offsettable address
4475 appearing where an offsettable address will do. It also may
4476 be a case when the address should be special in other words
4477 not a general one (e.g. it needs no index reg). */
4478 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
4479 {
4480 enum reg_class rclass;
4481 rtx *loc = &XEXP (op, 0)(((op)->u.fld[0]).rt_rtx);
4482 enum rtx_code code = GET_CODE (*loc)((enum rtx_code) (*loc)->code);
4483
4484 push_to_sequence (before);
4485 rclass = base_reg_class (GET_MODE (op)((machine_mode) (op)->mode), MEM_ADDR_SPACE (op)(get_mem_attrs (op)->addrspace),
4486 MEM, SCRATCH);
4487 if (GET_RTX_CLASS (code)(rtx_class[(int) (code)]) == RTX_AUTOINC)
4488 new_reg = emit_inc (rclass, *loc, *loc,
4489 /* This value does not matter for MODIFY. */
4490 GET_MODE_SIZE (GET_MODE (op)((machine_mode) (op)->mode)));
4491 else if (get_reload_reg (OP_IN, Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
, *loc, rclass, FALSEfalse,
4492 "offsetable address", &new_reg))
4493 {
4494 rtx addr = *loc;
4495 enum rtx_code code = GET_CODE (addr)((enum rtx_code) (addr)->code);
4496 bool align_p = false;
4497
4498 if (code == AND && CONST_INT_P (XEXP (addr, 1))(((enum rtx_code) ((((addr)->u.fld[1]).rt_rtx))->code) ==
CONST_INT)
)
4499 {
4500 /* (and ... (const_int -X)) is used to align to X bytes. */
4501 align_p = true;
4502 addr = XEXP (*loc, 0)(((*loc)->u.fld[0]).rt_rtx);
4503 }
4504 else
4505 addr = canonicalize_reload_addr (addr);
4506
4507 lra_emit_move (new_reg, addr);
4508 if (align_p)
4509 emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1))gen_rtx_fmt_ee_stat ((AND), ((((machine_mode) (new_reg)->mode
))), ((new_reg)), (((((*loc)->u.fld[1]).rt_rtx))) )
);
4510 }
4511 before = get_insns ();
4512 end_sequence ();
4513 *loc = new_reg;
4514 lra_update_dup (curr_id, i);
4515 }
4516 else if (goal_alt_matched[i][0] == -1)
4517 {
4518 machine_mode mode;
4519 rtx reg, *loc;
4520 int hard_regno;
4521 enum op_type type = curr_static_id->operand[i].type;
4522
4523 loc = curr_id->operand_loc[i];
4524 mode = curr_operand_mode[i];
4525 if (GET_CODE (*loc)((enum rtx_code) (*loc)->code) == SUBREG)
4526 {
4527 reg = SUBREG_REG (*loc)(((*loc)->u.fld[0]).rt_rtx);
4528 poly_int64 byte = SUBREG_BYTE (*loc)(((*loc)->u.fld[1]).rt_subreg);
4529 if (REG_P (reg)(((enum rtx_code) (reg)->code) == REG)
4530 /* Strict_low_part requires reloading the register and not
4531 just the subreg. Likewise for a strict subreg no wider
4532 than a word for WORD_REGISTER_OPERATIONS targets. */
4533 && (curr_static_id->operand[i].strict_low
4534 || (!paradoxical_subreg_p (mode, GET_MODE (reg)((machine_mode) (reg)->mode))
4535 && (hard_regno
4536 = get_try_hard_regno (REGNO (reg)(rhs_regno(reg)))) >= 0
4537 && (simplify_subreg_regno
4538 (hard_regno,
4539 GET_MODE (reg)((machine_mode) (reg)->mode), byte, mode) < 0)
4540 && (goal_alt[i] == NO_REGS
4541 || (simplify_subreg_regno
4542 (ira_class_hard_regs(this_target_ira->x_ira_class_hard_regs)[goal_alt[i]][0],
4543 GET_MODE (reg)((machine_mode) (reg)->mode), byte, mode) >= 0)))
4544 || (partial_subreg_p (mode, GET_MODE (reg)((machine_mode) (reg)->mode))
4545 && known_le (GET_MODE_SIZE (GET_MODE (reg)),(!maybe_lt ((((global_options.x_ix86_isa_flags & (1UL <<
1)) != 0) ? 8 : 4), GET_MODE_SIZE (((machine_mode) (reg)->
mode))))
4546 UNITS_PER_WORD)(!maybe_lt ((((global_options.x_ix86_isa_flags & (1UL <<
1)) != 0) ? 8 : 4), GET_MODE_SIZE (((machine_mode) (reg)->
mode))))
4547 && WORD_REGISTER_OPERATIONS0)))
4548 {
4549 /* An OP_INOUT is required when reloading a subreg of a
4550 mode wider than a word to ensure that data beyond the
4551 word being reloaded is preserved. Also automatically
4552 ensure that strict_low_part reloads are made into
4553 OP_INOUT which should already be true from the backend
4554 constraints. */
4555 if (type == OP_OUT
4556 && (curr_static_id->operand[i].strict_low
4557 || read_modify_subreg_p (*loc)))
4558 type = OP_INOUT;
4559 loc = &SUBREG_REG (*loc)(((*loc)->u.fld[0]).rt_rtx);
4560 mode = GET_MODE (*loc)((machine_mode) (*loc)->mode);
4561 }
4562 }
4563 old = *loc;
4564 if (get_reload_reg (type, mode, old, goal_alt[i],
4565 loc != curr_id->operand_loc[i], "", &new_reg)
4566 && type != OP_OUT)
4567 {
4568 push_to_sequence (before);
4569 lra_emit_move (new_reg, old);
4570 before = get_insns ();
4571 end_sequence ();
4572 }
4573 *loc = new_reg;
4574 if (type != OP_IN
4575 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX(rtx) 0)
4576 {
4577 start_sequence ();
4578 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg);
4579 emit_insn (after);
4580 after = get_insns ();
4581 end_sequence ();
4582 *loc = new_reg;
4583 }
4584 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++)
4585 if (goal_alt_dont_inherit_ops[j] == i)
4586 {
4587 lra_set_regno_unique_value (REGNO (new_reg)(rhs_regno(new_reg)));
4588 break;
4589 }
4590 lra_update_dup (curr_id, i);
4591 }
4592 else if (curr_static_id->operand[i].type == OP_IN
4593 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4594 == OP_OUT
4595 || (curr_static_id->operand[goal_alt_matched[i][0]].type
4596 == OP_INOUT
4597 && (operands_match_p
4598 (*curr_id->operand_loc[i],
4599 *curr_id->operand_loc[goal_alt_matched[i][0]],
4600 -1)))))
4601 {
4602 /* generate reloads for input and matched outputs. */
4603 match_inputs[0] = i;
4604 match_inputs[1] = -1;
4605 match_reload (goal_alt_matched[i][0], match_inputs, outputs,
4606 goal_alt[i], &before, &after,
4607 curr_static_id->operand_alternative
4608 [goal_alt_number * n_operands + goal_alt_matched[i][0]]
4609 .earlyclobber);
4610 }
4611 else if ((curr_static_id->operand[i].type == OP_OUT
4612 || (curr_static_id->operand[i].type == OP_INOUT
4613 && (operands_match_p
4614 (*curr_id->operand_loc[i],
4615 *curr_id->operand_loc[goal_alt_matched[i][0]],
4616 -1))))
4617 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4618 == OP_IN))
4619 /* Generate reloads for output and matched inputs. */
4620 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before,
4621 &after, curr_static_id->operand_alternative
4622 [goal_alt_number * n_operands + i].earlyclobber);
4623 else if (curr_static_id->operand[i].type == OP_IN
4624 && (curr_static_id->operand[goal_alt_matched[i][0]].type
4625 == OP_IN))
4626 {
4627 /* Generate reloads for matched inputs. */
4628 match_inputs[0] = i;
4629 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++)
4630 match_inputs[j + 1] = k;
4631 match_inputs[j + 1] = -1;
4632 match_reload (-1, match_inputs, outputs, goal_alt[i], &before,
4633 &after, false);
4634 }
4635 else
4636 /* We must generate code in any case when function
4637 process_alt_operands decides that it is possible. */
4638 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4638, __FUNCTION__))
;
4639
4640 if (optional_p)
4641 {
4642 rtx reg = op;
4643
4644 lra_assert (REG_P (reg))((void)(!((((enum rtx_code) (reg)->code) == REG)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4644, __FUNCTION__), 0 : 0))
;
4645 regno = REGNO (reg)(rhs_regno(reg));
4646 op = *curr_id->operand_loc[i]; /* Substitution. */
4647 if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG)
4648 op = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);
4649 gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start)((void)(!((((enum rtx_code) (op)->code) == REG) &&
(int) (rhs_regno(op)) >= new_regno_start) ? fancy_abort (
"/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4649, __FUNCTION__), 0 : 0))
;
4650 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)(rhs_regno(op)));
4651 lra_reg_info[REGNO (op)(rhs_regno(op))].restore_rtx = reg;
4652 if (lra_dump_file != NULLnullptr)
4653 fprintf (lra_dump_file,
4654 " Making reload reg %d for reg %d optional\n",
4655 REGNO (op)(rhs_regno(op)), regno);
4656 }
4657 }
4658 if (before != NULL_RTX(rtx) 0 || after != NULL_RTX(rtx) 0
4659 || max_regno_before != max_reg_num ())
4660 change_p = true;
4661 if (change_p)
4662 {
4663 lra_update_operator_dups (curr_id);
4664 /* Something changes -- process the insn. */
4665 lra_update_insn_regno_info (curr_insn);
4666 }
4667 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload");
4668 return change_p;
4669}
4670
4671/* Return true if INSN satisfies all constraints. In other words, no
4672 reload insns are needed. */
4673bool
4674lra_constrain_insn (rtx_insn *insn)
4675{
4676 int saved_new_regno_start = new_regno_start;
4677 int saved_new_insn_uid_start = new_insn_uid_start;
4678 bool change_p;
4679
4680 curr_insn = insn;
4681 curr_id = lra_get_insn_recog_data (curr_insn);
4682 curr_static_id = curr_id->insn_static_data;
4683 new_insn_uid_start = get_max_uid ();
4684 new_regno_start = max_reg_num ();
4685 change_p = curr_insn_transform (true);
4686 new_regno_start = saved_new_regno_start;
4687 new_insn_uid_start = saved_new_insn_uid_start;
4688 return ! change_p;
4689}
4690
4691/* Return true if X is in LIST. */
4692static bool
4693in_list_p (rtx x, rtx list)
4694{
4695 for (; list != NULL_RTX(rtx) 0; list = XEXP (list, 1)(((list)->u.fld[1]).rt_rtx))
4696 if (XEXP (list, 0)(((list)->u.fld[0]).rt_rtx) == x)
4697 return true;
4698 return false;
4699}
4700
4701/* Return true if X contains an allocatable hard register (if
4702 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4703static bool
4704contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p)
4705{
4706 int i, j;
4707 const char *fmt;
4708 enum rtx_code code;
4709
4710 code = GET_CODE (x)((enum rtx_code) (x)->code);
4711 if (REG_P (x)(((enum rtx_code) (x)->code) == REG))
4712 {
4713 int regno = REGNO (x)(rhs_regno(x));
4714 HARD_REG_SET alloc_regs;
4715
4716 if (hard_reg_p)
4717 {
4718 if (regno >= FIRST_PSEUDO_REGISTER76)
4719 regno = lra_get_regno_hard_regno (regno);
4720 if (regno < 0)
4721 return false;
4722 alloc_regs = ~lra_no_alloc_regs;
4723 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x)((machine_mode) (x)->mode), regno);
4724 }
4725 else
4726 {
4727 if (regno < FIRST_PSEUDO_REGISTER76)
4728 return false;
4729 if (! spilled_p)
4730 return true;
4731 return lra_get_regno_hard_regno (regno) < 0;
4732 }
4733 }
4734 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
4735 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
4736 {
4737 if (fmt[i] == 'e')
4738 {
4739 if (contains_reg_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), hard_reg_p, spilled_p))
4740 return true;
4741 }
4742 else if (fmt[i] == 'E')
4743 {
4744 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
4745 if (contains_reg_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), hard_reg_p, spilled_p))
4746 return true;
4747 }
4748 }
4749 return false;
4750}
4751
4752/* Process all regs in location *LOC and change them on equivalent
4753 substitution. Return true if any change was done. */
4754static bool
4755loc_equivalence_change_p (rtx *loc)
4756{
4757 rtx subst, reg, x = *loc;
4758 bool result = false;
4759 enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
4760 const char *fmt;
4761 int i, j;
4762
4763 if (code == SUBREG)
4764 {
4765 reg = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
4766 if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg
4767 && GET_MODE (subst)((machine_mode) (subst)->mode) == VOIDmode((void) 0, E_VOIDmode))
4768 {
4769 /* We cannot reload debug location. Simplify subreg here
4770 while we know the inner mode. */
4771 *loc = simplify_gen_subreg (GET_MODE (x)((machine_mode) (x)->mode), subst,
4772 GET_MODE (reg)((machine_mode) (reg)->mode), SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg));
4773 return true;
4774 }
4775 }
4776 if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x)
4777 {
4778 *loc = subst;
4779 return true;
4780 }
4781
4782 /* Scan all the operand sub-expressions. */
4783 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
4784 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
4785 {
4786 if (fmt[i] == 'e')
4787 result = loc_equivalence_change_p (&XEXP (x, i)(((x)->u.fld[i]).rt_rtx)) || result;
4788 else if (fmt[i] == 'E')
4789 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
4790 result
4791 = loc_equivalence_change_p (&XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])) || result;
4792 }
4793 return result;
4794}
4795
4796/* Similar to loc_equivalence_change_p, but for use as
4797 simplify_replace_fn_rtx callback. DATA is insn for which the
4798 elimination is done. If it null we don't do the elimination. */
4799static rtx
4800loc_equivalence_callback (rtx loc, const_rtx, void *data)
4801{
4802 if (!REG_P (loc)(((enum rtx_code) (loc)->code) == REG))
4803 return NULL_RTX(rtx) 0;
4804
4805 rtx subst = (data == NULLnullptr
4806 ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data));
4807 if (subst != loc)
4808 return subst;
4809
4810 return NULL_RTX(rtx) 0;
4811}
4812
4813/* Maximum number of generated reload insns per an insn. It is for
4814 preventing this pass cycling in a bug case. */
4815#define MAX_RELOAD_INSNS_NUMBER(30 * 3) LRA_MAX_INSN_RELOADS(30 * 3)
4816
4817/* The current iteration number of this LRA pass. */
4818int lra_constraint_iter;
4819
4820/* True if we should during assignment sub-pass check assignment
4821 correctness for all pseudos and spill some of them to correct
4822 conflicts. It can be necessary when we substitute equiv which
4823 needs checking register allocation correctness because the
4824 equivalent value contains allocatable hard registers, or when we
4825 restore multi-register pseudo, or when we change the insn code and
4826 its operand became INOUT operand when it was IN one before. */
4827bool check_and_force_assignment_correctness_p;
4828
4829/* Return true if REGNO is referenced in more than one block. */
4830static bool
4831multi_block_pseudo_p (int regno)
4832{
4833 basic_block bb = NULLnullptr;
4834 unsigned int uid;
4835 bitmap_iterator bi;
4836
4837 if (regno < FIRST_PSEUDO_REGISTER76)
4838 return false;
4839
4840 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)for (bmp_iter_set_init (&(bi), (&lra_reg_info[regno].
insn_bitmap), (0), &(uid)); bmp_iter_set (&(bi), &
(uid)); bmp_iter_next (&(bi), &(uid)))
4841 if (bb == NULLnullptr)
4842 bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn);
4843 else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb)
4844 return true;
4845 return false;
4846}
4847
4848/* Return true if LIST contains a deleted insn. */
4849static bool
4850contains_deleted_insn_p (rtx_insn_list *list)
4851{
4852 for (; list != NULL_RTX(rtx) 0; list = list->next ())
4853 if (NOTE_P (list->insn ())(((enum rtx_code) (list->insn ())->code) == NOTE)
4854 && NOTE_KIND (list->insn ())(((list->insn ())->u.fld[4]).rt_int) == NOTE_INSN_DELETED)
4855 return true;
4856 return false;
4857}
4858
4859/* Return true if X contains a pseudo dying in INSN. */
4860static bool
4861dead_pseudo_p (rtx x, rtx_insn *insn)
4862{
4863 int i, j;
4864 const char *fmt;
4865 enum rtx_code code;
4866
4867 if (REG_P (x)(((enum rtx_code) (x)->code) == REG))
4868 return (insn != NULL_RTX(rtx) 0
4869 && find_regno_note (insn, REG_DEAD, REGNO (x)(rhs_regno(x))) != NULL_RTX(rtx) 0);
4870 code = GET_CODE (x)((enum rtx_code) (x)->code);
4871 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
4872 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
4873 {
4874 if (fmt[i] == 'e')
4875 {
4876 if (dead_pseudo_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), insn))
4877 return true;
4878 }
4879 else if (fmt[i] == 'E')
4880 {
4881 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
4882 if (dead_pseudo_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), insn))
4883 return true;
4884 }
4885 }
4886 return false;
4887}
4888
4889/* Return true if INSN contains a dying pseudo in INSN right hand
4890 side. */
4891static bool
4892insn_rhs_dead_pseudo_p (rtx_insn *insn)
4893{
4894 rtx set = single_set (insn);
4895
4896 gcc_assert (set != NULL)((void)(!(set != nullptr) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 4896, __FUNCTION__), 0 : 0))
;
4897 return dead_pseudo_p (SET_SRC (set)(((set)->u.fld[1]).rt_rtx), insn);
4898}
4899
4900/* Return true if any init insn of REGNO contains a dying pseudo in
4901 insn right hand side. */
4902static bool
4903init_insn_rhs_dead_pseudo_p (int regno)
4904{
4905 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4906
4907 if (insns == NULLnullptr)
4908 return false;
4909 for (; insns != NULL_RTX(rtx) 0; insns = insns->next ())
4910 if (insn_rhs_dead_pseudo_p (insns->insn ()))
4911 return true;
4912 return false;
4913}
4914
4915/* Return TRUE if REGNO has a reverse equivalence. The equivalence is
4916 reverse only if we have one init insn with given REGNO as a
4917 source. */
4918static bool
4919reverse_equiv_p (int regno)
4920{
4921 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
4922 rtx set;
4923
4924 if (insns == NULLnullptr)
4925 return false;
4926 if (! INSN_P (insns->insn ())(((((enum rtx_code) (insns->insn ())->code) == INSN) ||
(((enum rtx_code) (insns->insn ())->code) == JUMP_INSN
) || (((enum rtx_code) (insns->insn ())->code) == CALL_INSN
)) || (((enum rtx_code) (insns->insn ())->code) == DEBUG_INSN
))
4927 || insns->next () != NULLnullptr)
4928 return false;
4929 if ((set = single_set (insns->insn ())) == NULL_RTX(rtx) 0)
4930 return false;
4931 return REG_P (SET_SRC (set))(((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) ==
REG)
&& (int) REGNO (SET_SRC (set))(rhs_regno((((set)->u.fld[1]).rt_rtx))) == regno;
4932}
4933
4934/* Return TRUE if REGNO was reloaded in an equivalence init insn. We
4935 call this function only for non-reverse equivalence. */
4936static bool
4937contains_reloaded_insn_p (int regno)
4938{
4939 rtx set;
4940 rtx_insn_list *list = ira_reg_equiv[regno].init_insns;
4941
4942 for (; list != NULLnullptr; list = list->next ())
4943 if ((set = single_set (list->insn ())) == NULL_RTX(rtx) 0
4944 || ! REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
REG)
4945 || (int) REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx))) != regno)
4946 return true;
4947 return false;
4948}
4949
4950/* Entry function of LRA constraint pass. Return true if the
4951 constraint pass did change the code. */
4952bool
4953lra_constraints (bool first_p)
4954{
4955 bool changed_p;
4956 int i, hard_regno, new_insns_num;
4957 unsigned int min_len, new_min_len, uid;
4958 rtx set, x, reg, dest_reg;
4959 basic_block last_bb;
4960 bitmap_iterator bi;
4961
4962 lra_constraint_iter++;
4963 if (lra_dump_file != NULLnullptr)
4964 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n",
4965 lra_constraint_iter);
4966 changed_p = false;
Value stored to 'changed_p' is never read
4967 if (pic_offset_table_rtx(this_target_rtl->x_pic_offset_table_rtx)
4968 && REGNO (pic_offset_table_rtx)(rhs_regno((this_target_rtl->x_pic_offset_table_rtx))) >= FIRST_PSEUDO_REGISTER76)
4969 check_and_force_assignment_correctness_p = true;
4970 else if (first_p)
4971 /* On the first iteration we should check IRA assignment
4972 correctness. In rare cases, the assignments can be wrong as
4973 early clobbers operands are ignored in IRA or usages of
4974 paradoxical sub-registers are not taken into account by
4975 IRA. */
4976 check_and_force_assignment_correctness_p = true;
4977 new_insn_uid_start = get_max_uid ();
4978 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num ();
4979 /* Mark used hard regs for target stack size calulations. */
4980 for (i = FIRST_PSEUDO_REGISTER76; i < new_regno_start; i++)
4981 if (lra_reg_info[i].nrefs != 0
4982 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
4983 {
4984 int j, nregs;
4985
4986 nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode);
4987 for (j = 0; j < nregs; j++)
4988 df_set_regs_ever_live (hard_regno + j, true);
4989 }
4990 /* Do elimination before the equivalence processing as we can spill
4991 some pseudos during elimination. */
4992 lra_eliminate (false, first_p);
4993 auto_bitmap equiv_insn_bitmap (&reg_obstack);
4994 for (i = FIRST_PSEUDO_REGISTER76; i < new_regno_start; i++)
4995 if (lra_reg_info[i].nrefs != 0)
4996 {
4997 ira_reg_equiv[i].profitable_p = true;
4998 reg = regno_reg_rtx[i];
4999 if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg)
5000 {
5001 bool pseudo_p = contains_reg_p (x, false, false);
5002
5003 /* After RTL transformation, we cannot guarantee that
5004 pseudo in the substitution was not reloaded which might
5005 make equivalence invalid. For example, in reverse
5006 equiv of p0
5007
5008 p0 <- ...
5009 ...
5010 equiv_mem <- p0
5011
5012 the memory address register was reloaded before the 2nd
5013 insn. */
5014 if ((! first_p && pseudo_p)
5015 /* We don't use DF for compilation speed sake. So it
5016 is problematic to update live info when we use an
5017 equivalence containing pseudos in more than one
5018 BB. */
5019 || (pseudo_p && multi_block_pseudo_p (i))
5020 /* If an init insn was deleted for some reason, cancel
5021 the equiv. We could update the equiv insns after
5022 transformations including an equiv insn deletion
5023 but it is not worthy as such cases are extremely
5024 rare. */
5025 || contains_deleted_insn_p (ira_reg_equiv[i].init_insns)
5026 /* If it is not a reverse equivalence, we check that a
5027 pseudo in rhs of the init insn is not dying in the
5028 insn. Otherwise, the live info at the beginning of
5029 the corresponding BB might be wrong after we
5030 removed the insn. When the equiv can be a
5031 constant, the right hand side of the init insn can
5032 be a pseudo. */
5033 || (! reverse_equiv_p (i)
5034 && (init_insn_rhs_dead_pseudo_p (i)
5035 /* If we reloaded the pseudo in an equivalence
5036 init insn, we cannot remove the equiv init
5037 insns and the init insns might write into
5038 const memory in this case. */
5039 || contains_reloaded_insn_p (i)))
5040 /* Prevent access beyond equivalent memory for
5041 paradoxical subregs. */
5042 || (MEM_P (x)(((enum rtx_code) (x)->code) == MEM)
5043 && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode),maybe_lt (GET_MODE_SIZE (((machine_mode) (x)->mode)), GET_MODE_SIZE
(lra_reg_info[i].biggest_mode))
5044 GET_MODE_SIZE (GET_MODE (x)))maybe_lt (GET_MODE_SIZE (((machine_mode) (x)->mode)), GET_MODE_SIZE
(lra_reg_info[i].biggest_mode))
)
5045 || (pic_offset_table_rtx(this_target_rtl->x_pic_offset_table_rtx)
5046 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x)((((machine_mode) (regno_reg_rtx[i])->mode)) != ((void) 0,
E_VOIDmode) && ((rtx_class[(int) (((enum rtx_code) (
x)->code))]) == RTX_CONST_OBJ) && ((enum rtx_code)
(x)->code) != HIGH && GET_MODE_SIZE (((machine_mode
) (regno_reg_rtx[i])->mode)).is_constant () && !targetm
.cannot_force_const_mem (((machine_mode) (regno_reg_rtx[i])->
mode), x))
5047 && (targetm.preferred_reload_class
5048 (x, lra_get_allocno_class (i)) == NO_REGS))
5049 || contains_symbol_ref_p (x))))
5050 ira_reg_equiv[i].defined_p = false;
5051 if (contains_reg_p (x, false, true))
5052 ira_reg_equiv[i].profitable_p = false;
5053 if (get_equiv (reg) != reg)
5054 bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap);
5055 }
5056 }
5057 for (i = FIRST_PSEUDO_REGISTER76; i < new_regno_start; i++)
5058 update_equiv (i);
5059 /* We should add all insns containing pseudos which should be
5060 substituted by their equivalences. */
5061 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi)for (bmp_iter_set_init (&(bi), (equiv_insn_bitmap), (0), &
(uid)); bmp_iter_set (&(bi), &(uid)); bmp_iter_next (
&(bi), &(uid)))
5062 lra_push_insn_by_uid (uid);
5063 min_len = lra_insn_stack_length ();
5064 new_insns_num = 0;
5065 last_bb = NULLnullptr;
5066 changed_p = false;
5067 while ((new_min_len = lra_insn_stack_length ()) != 0)
5068 {
5069 curr_insn = lra_pop_insn ();
5070 --new_min_len;
5071 curr_bb = BLOCK_FOR_INSN (curr_insn);
5072 if (curr_bb != last_bb)
5073 {
5074 last_bb = curr_bb;
5075 bb_reload_num = lra_curr_reload_num;
5076 }
5077 if (min_len > new_min_len)
5078 {
5079 min_len = new_min_len;
5080 new_insns_num = 0;
5081 }
5082 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER(30 * 3))
5083 internal_error
5084 ("maximum number of generated reload insns per insn achieved (%d)",
5085 MAX_RELOAD_INSNS_NUMBER(30 * 3));
5086 new_insns_num++;
5087 if (DEBUG_INSN_P (curr_insn)(((enum rtx_code) (curr_insn)->code) == DEBUG_INSN))
5088 {
5089 /* We need to check equivalence in debug insn and change
5090 pseudo to the equivalent value if necessary. */
5091 curr_id = lra_get_insn_recog_data (curr_insn);
5092 if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)))
5093 {
5094 rtx old = *curr_id->operand_loc[0];
5095 *curr_id->operand_loc[0]
5096 = simplify_replace_fn_rtx (old, NULL_RTX(rtx) 0,
5097 loc_equivalence_callback, curr_insn);
5098 if (old != *curr_id->operand_loc[0])
5099 {
5100 lra_update_insn_regno_info (curr_insn);
5101 changed_p = true;
5102 }
5103 }
5104 }
5105 else if (INSN_P (curr_insn)(((((enum rtx_code) (curr_insn)->code) == INSN) || (((enum
rtx_code) (curr_insn)->code) == JUMP_INSN) || (((enum rtx_code
) (curr_insn)->code) == CALL_INSN)) || (((enum rtx_code) (
curr_insn)->code) == DEBUG_INSN))
)
5106 {
5107 if ((set = single_set (curr_insn)) != NULL_RTX(rtx) 0)
5108 {
5109 dest_reg = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);
5110 /* The equivalence pseudo could be set up as SUBREG in a
5111 case when it is a call restore insn in a mode
5112 different from the pseudo mode. */
5113 if (GET_CODE (dest_reg)((enum rtx_code) (dest_reg)->code) == SUBREG)
5114 dest_reg = SUBREG_REG (dest_reg)(((dest_reg)->u.fld[0]).rt_rtx);
5115 if ((REG_P (dest_reg)(((enum rtx_code) (dest_reg)->code) == REG)
5116 && (x = get_equiv (dest_reg)) != dest_reg
5117 /* Remove insns which set up a pseudo whose value
5118 cannot be changed. Such insns might be not in
5119 init_insns because we don't update equiv data
5120 during insn transformations.
5121
5122 As an example, let suppose that a pseudo got
5123 hard register and on the 1st pass was not
5124 changed to equivalent constant. We generate an
5125 additional insn setting up the pseudo because of
5126 secondary memory movement. Then the pseudo is
5127 spilled and we use the equiv constant. In this
5128 case we should remove the additional insn and
5129 this insn is not init_insns list. */
5130 && (! MEM_P (x)(((enum rtx_code) (x)->code) == MEM) || MEM_READONLY_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5130, __FUNCTION__); _rtx; })->unchanging)
5131 /* Check that this is actually an insn setting
5132 up the equivalence. */
5133 || in_list_p (curr_insn,
5134 ira_reg_equiv
5135 [REGNO (dest_reg)(rhs_regno(dest_reg))].init_insns)))
5136 || (((x = get_equiv (SET_SRC (set)(((set)->u.fld[1]).rt_rtx))) != SET_SRC (set)(((set)->u.fld[1]).rt_rtx))
5137 && in_list_p (curr_insn,
5138 ira_reg_equiv
5139 [REGNO (SET_SRC (set))(rhs_regno((((set)->u.fld[1]).rt_rtx)))].init_insns)))
5140 {
5141 /* This is equiv init insn of pseudo which did not get a
5142 hard register -- remove the insn. */
5143 if (lra_dump_file != NULLnullptr)
5144 {
5145 fprintf (lra_dump_file,
5146 " Removing equiv init insn %i (freq=%d)\n",
5147 INSN_UID (curr_insn),
5148 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn))((optimize_function_for_size_p ((cfun + 0)) || !(cfun + 0)->
cfg->count_max.initialized_p ()) ? 1000 : ((BLOCK_FOR_INSN
(curr_insn))->count.to_frequency ((cfun + 0)) * 1000 / 10000
) ? ((BLOCK_FOR_INSN (curr_insn))->count.to_frequency ((cfun
+ 0)) * 1000 / 10000) : 1)
);
5149 dump_insn_slim (lra_dump_file, curr_insn);
5150 }
5151 if (contains_reg_p (x, true, false))
5152 check_and_force_assignment_correctness_p = true;
5153 lra_set_insn_deleted (curr_insn);
5154 continue;
5155 }
5156 }
5157 curr_id = lra_get_insn_recog_data (curr_insn);
5158 curr_static_id = curr_id->insn_static_data;
5159 init_curr_insn_input_reloads ();
5160 init_curr_operand_mode ();
5161 if (curr_insn_transform (false))
5162 changed_p = true;
5163 /* Check non-transformed insns too for equiv change as USE
5164 or CLOBBER don't need reloads but can contain pseudos
5165 being changed on their equivalences. */
5166 else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))
5167 && loc_equivalence_change_p (&PATTERN (curr_insn)))
5168 {
5169 lra_update_insn_regno_info (curr_insn);
5170 changed_p = true;
5171 }
5172 }
5173 }
5174
5175 /* If we used a new hard regno, changed_p should be true because the
5176 hard reg is assigned to a new pseudo. */
5177 if (flag_checkingglobal_options.x_flag_checking && !changed_p)
5178 {
5179 for (i = FIRST_PSEUDO_REGISTER76; i < new_regno_start; i++)
5180 if (lra_reg_info[i].nrefs != 0
5181 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
5182 {
5183 int j, nregs = hard_regno_nregs (hard_regno,
5184 PSEUDO_REGNO_MODE (i)((machine_mode) (regno_reg_rtx[i])->mode));
5185
5186 for (j = 0; j < nregs; j++)
5187 lra_assert (df_regs_ever_live_p (hard_regno + j))((void)(!(df_regs_ever_live_p (hard_regno + j)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5187, __FUNCTION__), 0 : 0))
;
5188 }
5189 }
5190 return changed_p;
5191}
5192
5193static void initiate_invariants (void);
5194static void finish_invariants (void);
5195
5196/* Initiate the LRA constraint pass. It is done once per
5197 function. */
5198void
5199lra_constraints_init (void)
5200{
5201 initiate_invariants ();
5202}
5203
5204/* Finalize the LRA constraint pass. It is done once per
5205 function. */
5206void
5207lra_constraints_finish (void)
5208{
5209 finish_invariants ();
5210}
5211
5212
5213
5214/* Structure describes invariants for ineheritance. */
5215struct lra_invariant
5216{
5217 /* The order number of the invariant. */
5218 int num;
5219 /* The invariant RTX. */
5220 rtx invariant_rtx;
5221 /* The origin insn of the invariant. */
5222 rtx_insn *insn;
5223};
5224
5225typedef lra_invariant invariant_t;
5226typedef invariant_t *invariant_ptr_t;
5227typedef const invariant_t *const_invariant_ptr_t;
5228
5229/* Pointer to the inheritance invariants. */
5230static vec<invariant_ptr_t> invariants;
5231
5232/* Allocation pool for the invariants. */
5233static object_allocator<lra_invariant> *invariants_pool;
5234
5235/* Hash table for the invariants. */
5236static htab_t invariant_table;
5237
5238/* Hash function for INVARIANT. */
5239static hashval_t
5240invariant_hash (const void *invariant)
5241{
5242 rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx;
5243 return lra_rtx_hash (inv);
5244}
5245
5246/* Equal function for invariants INVARIANT1 and INVARIANT2. */
5247static int
5248invariant_eq_p (const void *invariant1, const void *invariant2)
5249{
5250 rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx;
5251 rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx;
5252
5253 return rtx_equal_p (inv1, inv2);
5254}
5255
5256/* Insert INVARIANT_RTX into the table if it is not there yet. Return
5257 invariant which is in the table. */
5258static invariant_ptr_t
5259insert_invariant (rtx invariant_rtx)
5260{
5261 void **entry_ptr;
5262 invariant_t invariant;
5263 invariant_ptr_t invariant_ptr;
5264
5265 invariant.invariant_rtx = invariant_rtx;
5266 entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT);
5267 if (*entry_ptr == NULLnullptr)
5268 {
5269 invariant_ptr = invariants_pool->allocate ();
5270 invariant_ptr->invariant_rtx = invariant_rtx;
5271 invariant_ptr->insn = NULLnullptr;
5272 invariants.safe_push (invariant_ptr);
5273 *entry_ptr = (void *) invariant_ptr;
5274 }
5275 return (invariant_ptr_t) *entry_ptr;
5276}
5277
5278/* Initiate the invariant table. */
5279static void
5280initiate_invariants (void)
5281{
5282 invariants.create (100);
5283 invariants_pool
5284 = new object_allocator<lra_invariant> ("Inheritance invariants");
5285 invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULLnullptr);
5286}
5287
5288/* Finish the invariant table. */
5289static void
5290finish_invariants (void)
5291{
5292 htab_delete (invariant_table);
5293 delete invariants_pool;
5294 invariants.release ();
5295}
5296
5297/* Make the invariant table empty. */
5298static void
5299clear_invariants (void)
5300{
5301 htab_empty (invariant_table);
5302 invariants_pool->release ();
5303 invariants.truncate (0);
5304}
5305
5306
5307
5308/* This page contains code to do inheritance/split
5309 transformations. */
5310
5311/* Number of reloads passed so far in current EBB. */
5312static int reloads_num;
5313
5314/* Number of calls passed so far in current EBB. */
5315static int calls_num;
5316
5317/* Index ID is the CALLS_NUM associated the last call we saw with
5318 ABI identifier ID. */
5319static int last_call_for_abi[NUM_ABI_IDS];
5320
5321/* Which registers have been fully or partially clobbered by a call
5322 since they were last used. */
5323static HARD_REG_SET full_and_partial_call_clobbers;
5324
5325/* Current reload pseudo check for validity of elements in
5326 USAGE_INSNS. */
5327static int curr_usage_insns_check;
5328
5329/* Info about last usage of registers in EBB to do inheritance/split
5330 transformation. Inheritance transformation is done from a spilled
5331 pseudo and split transformations from a hard register or a pseudo
5332 assigned to a hard register. */
5333struct usage_insns
5334{
5335 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5336 value INSNS is valid. The insns is chain of optional debug insns
5337 and a finishing non-debug insn using the corresponding reg. The
5338 value is also used to mark the registers which are set up in the
5339 current insn. The negated insn uid is used for this. */
5340 int check;
5341 /* Value of global reloads_num at the last insn in INSNS. */
5342 int reloads_num;
5343 /* Value of global reloads_nums at the last insn in INSNS. */
5344 int calls_num;
5345 /* It can be true only for splitting. And it means that the restore
5346 insn should be put after insn given by the following member. */
5347 bool after_p;
5348 /* Next insns in the current EBB which use the original reg and the
5349 original reg value is not changed between the current insn and
5350 the next insns. In order words, e.g. for inheritance, if we need
5351 to use the original reg value again in the next insns we can try
5352 to use the value in a hard register from a reload insn of the
5353 current insn. */
5354 rtx insns;
5355};
5356
5357/* Map: regno -> corresponding pseudo usage insns. */
5358static struct usage_insns *usage_insns;
5359
5360static void
5361setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p)
5362{
5363 usage_insns[regno].check = curr_usage_insns_check;
5364 usage_insns[regno].insns = insn;
5365 usage_insns[regno].reloads_num = reloads_num;
5366 usage_insns[regno].calls_num = calls_num;
5367 usage_insns[regno].after_p = after_p;
5368 if (regno >= FIRST_PSEUDO_REGISTER76 && reg_renumber[regno] >= 0)
5369 remove_from_hard_reg_set (&full_and_partial_call_clobbers,
5370 PSEUDO_REGNO_MODE (regno)((machine_mode) (regno_reg_rtx[regno])->mode),
5371 reg_renumber[regno]);
5372}
5373
5374/* The function is used to form list REGNO usages which consists of
5375 optional debug insns finished by a non-debug insn using REGNO.
5376 RELOADS_NUM is current number of reload insns processed so far. */
5377static void
5378add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num)
5379{
5380 rtx next_usage_insns;
5381
5382 if (usage_insns[regno].check == curr_usage_insns_check
5383 && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX(rtx) 0
5384 && DEBUG_INSN_P (insn)(((enum rtx_code) (insn)->code) == DEBUG_INSN))
5385 {
5386 /* Check that we did not add the debug insn yet. */
5387 if (next_usage_insns != insn
5388 && (GET_CODE (next_usage_insns)((enum rtx_code) (next_usage_insns)->code) != INSN_LIST
5389 || XEXP (next_usage_insns, 0)(((next_usage_insns)->u.fld[0]).rt_rtx) != insn))
5390 usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode((void) 0, E_VOIDmode), insn,
5391 next_usage_insns);
5392 }
5393 else if (NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN))
)
5394 setup_next_usage_insn (regno, insn, reloads_num, false);
5395 else
5396 usage_insns[regno].check = 0;
5397}
5398
5399/* Return first non-debug insn in list USAGE_INSNS. */
5400static rtx_insn *
5401skip_usage_debug_insns (rtx usage_insns)
5402{
5403 rtx insn;
5404
5405 /* Skip debug insns. */
5406 for (insn = usage_insns;
5407 insn != NULL_RTX(rtx) 0 && GET_CODE (insn)((enum rtx_code) (insn)->code) == INSN_LIST;
5408 insn = XEXP (insn, 1)(((insn)->u.fld[1]).rt_rtx))
5409 ;
5410 return safe_as_a <rtx_insn *> (insn);
5411}
5412
5413/* Return true if we need secondary memory moves for insn in
5414 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5415 into the insn. */
5416static bool
5417check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED__attribute__ ((__unused__)),
5418 rtx usage_insns ATTRIBUTE_UNUSED__attribute__ ((__unused__)))
5419{
5420 rtx_insn *insn;
5421 rtx set, dest;
5422 enum reg_class cl;
5423
5424 if (inher_cl == ALL_REGS
5425 || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX(rtx) 0)
5426 return false;
5427 lra_assert (INSN_P (insn))((void)(!((((((enum rtx_code) (insn)->code) == INSN) || ((
(enum rtx_code) (insn)->code) == JUMP_INSN) || (((enum rtx_code
) (insn)->code) == CALL_INSN)) || (((enum rtx_code) (insn)
->code) == DEBUG_INSN))) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5427, __FUNCTION__), 0 : 0))
;
5428 if ((set = single_set (insn)) == NULL_RTX(rtx) 0 || ! REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
REG)
)
5429 return false;
5430 dest = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);
5431 if (! REG_P (dest)(((enum rtx_code) (dest)->code) == REG))
5432 return false;
5433 lra_assert (inher_cl != NO_REGS)((void)(!(inher_cl != NO_REGS) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5433, __FUNCTION__), 0 : 0))
;
5434 cl = get_reg_class (REGNO (dest)(rhs_regno(dest)));
5435 return (cl != NO_REGS && cl != ALL_REGS
5436 && targetm.secondary_memory_needed (GET_MODE (dest)((machine_mode) (dest)->mode), inher_cl, cl));
5437}
5438
5439/* Registers involved in inheritance/split in the current EBB
5440 (inheritance/split pseudos and original registers). */
5441static bitmap_head check_only_regs;
5442
5443/* Reload pseudos cannot be involded in invariant inheritance in the
5444 current EBB. */
5445static bitmap_head invalid_invariant_regs;
5446
5447/* Do inheritance transformations for insn INSN, which defines (if
5448 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5449 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5450 form as the "insns" field of usage_insns. Return true if we
5451 succeed in such transformation.
5452
5453 The transformations look like:
5454
5455 p <- ... i <- ...
5456 ... p <- i (new insn)
5457 ... =>
5458 <- ... p ... <- ... i ...
5459 or
5460 ... i <- p (new insn)
5461 <- ... p ... <- ... i ...
5462 ... =>
5463 <- ... p ... <- ... i ...
5464 where p is a spilled original pseudo and i is a new inheritance pseudo.
5465
5466
5467 The inheritance pseudo has the smallest class of two classes CL and
5468 class of ORIGINAL REGNO. */
5469static bool
5470inherit_reload_reg (bool def_p, int original_regno,
5471 enum reg_class cl, rtx_insn *insn, rtx next_usage_insns)
5472{
5473 if (optimize_function_for_size_p (cfun(cfun + 0)))
5474 return false;
5475
5476 enum reg_class rclass = lra_get_allocno_class (original_regno);
5477 rtx original_reg = regno_reg_rtx[original_regno];
5478 rtx new_reg, usage_insn;
5479 rtx_insn *new_insns;
5480
5481 lra_assert (! usage_insns[original_regno].after_p)((void)(!(! usage_insns[original_regno].after_p) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5481, __FUNCTION__), 0 : 0))
;
5482 if (lra_dump_file != NULLnullptr)
5483 fprintf (lra_dump_file,
5484 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5485 if (! ira_reg_classes_intersect_p(this_target_ira->x_ira_reg_classes_intersect_p)[cl][rclass])
5486 {
5487 if (lra_dump_file != NULLnullptr)
5488 {
5489 fprintf (lra_dump_file,
5490 " Rejecting inheritance for %d "
5491 "because of disjoint classes %s and %s\n",
5492 original_regno, reg_class_names[cl],
5493 reg_class_names[rclass]);
5494 fprintf (lra_dump_file,
5495 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5496 }
5497 return false;
5498 }
5499 if ((ira_class_subset_p(this_target_ira->x_ira_class_subset_p)[cl][rclass] && cl != rclass)
5500 /* We don't use a subset of two classes because it can be
5501 NO_REGS. This transformation is still profitable in most
5502 cases even if the classes are not intersected as register
5503 move is probably cheaper than a memory load. */
5504 || ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[cl] < ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[rclass])
5505 {
5506 if (lra_dump_file != NULLnullptr)
5507 fprintf (lra_dump_file, " Use smallest class of %s and %s\n",
5508 reg_class_names[cl], reg_class_names[rclass]);
5509
5510 rclass = cl;
5511 }
5512 if (check_secondary_memory_needed_p (rclass, next_usage_insns))
5513 {
5514 /* Reject inheritance resulting in secondary memory moves.
5515 Otherwise, there is a danger in LRA cycling. Also such
5516 transformation will be unprofitable. */
5517 if (lra_dump_file != NULLnullptr)
5518 {
5519 rtx_insn *insn = skip_usage_debug_insns (next_usage_insns);
5520 rtx set = single_set (insn);
5521
5522 lra_assert (set != NULL_RTX)((void)(!(set != (rtx) 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5522, __FUNCTION__), 0 : 0))
;
5523
5524 rtx dest = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);
5525
5526 lra_assert (REG_P (dest))((void)(!((((enum rtx_code) (dest)->code) == REG)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5526, __FUNCTION__), 0 : 0))
;
5527 fprintf (lra_dump_file,
5528 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5529 "as secondary mem is needed\n",
5530 REGNO (dest)(rhs_regno(dest)), reg_class_names[get_reg_class (REGNO (dest)(rhs_regno(dest)))],
5531 original_regno, reg_class_names[rclass]);
5532 fprintf (lra_dump_file,
5533 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5534 }
5535 return false;
5536 }
5537 new_reg = lra_create_new_reg (GET_MODE (original_reg)((machine_mode) (original_reg)->mode), original_reg,
5538 rclass, "inheritance");
5539 start_sequence ();
5540 if (def_p)
5541 lra_emit_move (original_reg, new_reg);
5542 else
5543 lra_emit_move (new_reg, original_reg);
5544 new_insns = get_insns ();
5545 end_sequence ();
5546 if (NEXT_INSN (new_insns) != NULL_RTX(rtx) 0)
5547 {
5548 if (lra_dump_file != NULLnullptr)
5549 {
5550 fprintf (lra_dump_file,
5551 " Rejecting inheritance %d->%d "
5552 "as it results in 2 or more insns:\n",
5553 original_regno, REGNO (new_reg)(rhs_regno(new_reg)));
5554 dump_rtl_slim (lra_dump_file, new_insns, NULLnullptr, -1, 0);
5555 fprintf (lra_dump_file,
5556 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5557 }
5558 return false;
5559 }
5560 lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false);
5561 lra_update_insn_regno_info (insn);
5562 if (! def_p)
5563 /* We now have a new usage insn for original regno. */
5564 setup_next_usage_insn (original_regno, new_insns, reloads_num, false);
5565 if (lra_dump_file != NULLnullptr)
5566 fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n",
5567 original_regno, REGNO (new_reg)(rhs_regno(new_reg)), BLOCK_FOR_INSN (insn)->index);
5568 lra_reg_info[REGNO (new_reg)(rhs_regno(new_reg))].restore_rtx = regno_reg_rtx[original_regno];
5569 bitmap_set_bit (&check_only_regs, REGNO (new_reg)(rhs_regno(new_reg)));
5570 bitmap_set_bit (&check_only_regs, original_regno);
5571 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)(rhs_regno(new_reg)));
5572 if (def_p)
5573 lra_process_new_insns (insn, NULLnullptr, new_insns,
5574 "Add original<-inheritance");
5575 else
5576 lra_process_new_insns (insn, new_insns, NULLnullptr,
5577 "Add inheritance<-original");
5578 while (next_usage_insns != NULL_RTX(rtx) 0)
5579 {
5580 if (GET_CODE (next_usage_insns)((enum rtx_code) (next_usage_insns)->code) != INSN_LIST)
5581 {
5582 usage_insn = next_usage_insns;
5583 lra_assert (NONDEBUG_INSN_P (usage_insn))((void)(!(((((enum rtx_code) (usage_insn)->code) == INSN) ||
(((enum rtx_code) (usage_insn)->code) == JUMP_INSN) || ((
(enum rtx_code) (usage_insn)->code) == CALL_INSN))) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5583, __FUNCTION__), 0 : 0))
;
5584 next_usage_insns = NULLnullptr;
5585 }
5586 else
5587 {
5588 usage_insn = XEXP (next_usage_insns, 0)(((next_usage_insns)->u.fld[0]).rt_rtx);
5589 lra_assert (DEBUG_INSN_P (usage_insn))((void)(!((((enum rtx_code) (usage_insn)->code) == DEBUG_INSN
)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5589, __FUNCTION__), 0 : 0))
;
5590 next_usage_insns = XEXP (next_usage_insns, 1)(((next_usage_insns)->u.fld[1]).rt_rtx);
5591 }
5592 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false,
5593 DEBUG_INSN_P (usage_insn)(((enum rtx_code) (usage_insn)->code) == DEBUG_INSN));
5594 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5595 if (lra_dump_file != NULLnullptr)
5596 {
5597 basic_block bb = BLOCK_FOR_INSN (usage_insn);
5598 fprintf (lra_dump_file,
5599 " Inheritance reuse change %d->%d (bb%d):\n",
5600 original_regno, REGNO (new_reg)(rhs_regno(new_reg)),
5601 bb ? bb->index : -1);
5602 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5603 }
5604 }
5605 if (lra_dump_file != NULLnullptr)
5606 fprintf (lra_dump_file,
5607 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5608 return true;
5609}
5610
5611/* Return true if we need a caller save/restore for pseudo REGNO which
5612 was assigned to a hard register. */
5613static inline bool
5614need_for_call_save_p (int regno)
5615{
5616 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0)((void)(!(regno >= 76 && reg_renumber[regno] >=
0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5616, __FUNCTION__), 0 : 0))
;
5617 if (usage_insns[regno].calls_num < calls_num)
5618 {
5619 unsigned int abis = 0;
5620 for (unsigned int i = 0; i < NUM_ABI_IDS; ++i)
5621 if (last_call_for_abi[i] > usage_insns[regno].calls_num)
5622 abis |= 1 << i;
5623 gcc_assert (abis)((void)(!(abis) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5623, __FUNCTION__), 0 : 0))
;
5624 if (call_clobbered_in_region_p (abis, full_and_partial_call_clobbers,
5625 PSEUDO_REGNO_MODE (regno)((machine_mode) (regno_reg_rtx[regno])->mode),
5626 reg_renumber[regno]))
5627 return true;
5628 }
5629 return false;
5630}
5631
5632/* Global registers occurring in the current EBB. */
5633static bitmap_head ebb_global_regs;
5634
5635/* Return true if we need a split for hard register REGNO or pseudo
5636 REGNO which was assigned to a hard register.
5637 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5638 used for reloads since the EBB end. It is an approximation of the
5639 used hard registers in the split range. The exact value would
5640 require expensive calculations. If we were aggressive with
5641 splitting because of the approximation, the split pseudo will save
5642 the same hard register assignment and will be removed in the undo
5643 pass. We still need the approximation because too aggressive
5644 splitting would result in too inaccurate cost calculation in the
5645 assignment pass because of too many generated moves which will be
5646 probably removed in the undo pass. */
5647static inline bool
5648need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno)
5649{
5650 int hard_regno = regno < FIRST_PSEUDO_REGISTER76 ? regno : reg_renumber[regno];
5651
5652 lra_assert (hard_regno >= 0)((void)(!(hard_regno >= 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/lra-constraints.c"
, 5652, __FUNCTION__), 0 : 0))
;
5653 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno)
5654 /* Don't split eliminable hard registers, otherwise we can
5655 split hard registers like hard frame pointer, which
5656 lives on BB start/end according to DF-infrastructure,
5657 when there is a pseudo assigned to the register and
5658 living in the same BB. */
5659 && (regno >= FIRST_PSEUDO_REGISTER76
5660 || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno))
5661 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno)
5662 /* Don't split call clobbered hard regs living through
5663 calls, otherwise we might have a check problem in the
5664 assign sub-pass as in the most cases (exception is a
5665 situation when check_and_force_assignment_correctness_p value is
5666 true) the assign pass assumes that all pseudos living
5667 through calls are assigned to call saved hard regs. */
5668 && (regno >= FIRST_PSEUDO_REGISTER76
5669 || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers, regno))
5670 /* We need at least 2 reloads to make pseudo splitting
5671 profitable. We should provide hard regno splitting in
5672 any case to solve 1st insn scheduling problem when
5673 moving hard register definition up might result in
5674 impossibility to find hard register for reload pseudo of
5675 small register class. */
5676 && (usage_insns[regno].reloads_num
5677 + (regno < FIRST_PSEUDO_REGISTER76 ? 0 : 3) < reloads_num)
5678 && (regno < FIRST_PSEUDO_REGISTER76
5679 /* For short living pseudos, spilling + inheritance can
5680 be considered a substitution for splitting.
5681 Therefore we do not splitting for local pseudos. It
5682 decreases also aggressiveness of splitting. The
5683 minimal number of references is chosen taking into
5684 account that for 2 references splitting has no sense
5685 as we can just spill the pseudo. */
5686 || (regno >= FIRST_PSEUDO_REGISTER76
5687 && lra_reg_info[regno].nrefs > 3
5688 && bitmap_bit_p (&ebb_global_regs, regno))))
5689 || (regno >= FIRST_PSEUDO_REGISTER76 && need_for_call_save_p (regno)));
5690}
5691
5692/* Return class for the split pseudo created from original pseudo with
5693 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5694 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5695 results in no secondary memory movements. */
5696static enum reg_class
5697choose_split_class (enum reg_class allocno_class,
5698 int hard_regno ATTRIBUTE_UNUSED__attribute__ ((__unused__)),
5699 machine_mode mode ATTRIBUTE_UNUSED__attribute__ ((__unused__)))
5700{
5701 int i;
5702 enum reg_class cl, best_cl = NO_REGS;
5703 enum reg_class hard_reg_class ATTRIBUTE_UNUSED__attribute__ ((__unused__))
5704 = REGNO_REG_CLASS (hard_regno)(regclass_map[(hard_regno)]);
5705
5706 if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class)
5707 && TEST_HARD_REG_BIT (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[allocno_class], hard_regno))
5708 return allocno_class;
5709 for (i = 0;
5710 (cl = reg_class_subclasses(this_target_hard_regs->x_reg_class_subclasses)[allocno_class][i]) != LIM_REG_CLASSES;
5711 i++)
5712 if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class)
5713 && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl)
5714 && TEST_HARD_REG_BIT (reg_class_contents(this_target_hard_regs->x_reg_class_contents)[cl], hard_regno)
5715 && (best_cl == NO_REGS
5716 || ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[best_cl] < ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[cl]))
5717 best_cl = cl;
5718 return best_cl;
5719}
5720
5721/* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
5722 It only makes sense to call this function if NEW_REGNO is always
5723 equal to ORIGINAL_REGNO. */
5724
5725static void
5726lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno)
5727{
5728 if (!ira_reg_equiv[original_regno].defined_p)
5729 return;
5730
5731 ira_expand_reg_equiv ();
5732 ira_reg_equiv[new_regno].defined_p = true;
5733 if (ira_reg_equiv[original_regno].memory)
5734 ira_reg_equiv[new_regno].memory
5735 = copy_rtx (ira_reg_equiv[original_regno].memory);
5736 if (ira_reg_equiv[original_regno].constant)
5737 ira_reg_equiv[new_regno].constant
5738 = copy_rtx (ira_reg_equiv[original_regno].constant);
5739 if (ira_reg_equiv[original_regno].invariant)
5740 ira_reg_equiv[new_regno].invariant
5741 = copy_rtx (ira_reg_equiv[original_regno].invariant);
5742}
5743
5744/* Do split transformations for insn INSN, which defines or uses
5745 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
5746 the EBB next uses ORIGINAL_REGNO; it has the same form as the
5747 "insns" field of usage_insns. If TO is not NULL, we don't use
5748 usage_insns, we put restore insns after TO insn. It is a case when
5749 we call it from lra_split_hard_reg_for, outside the inheritance
5750 pass.
5751
5752 The transformations look like:
5753
5754 p <- ... p <- ...
5755 ... s <- p (new insn -- save)
5756 ... =>
5757 ... p <- s (new insn -- restore)
5758 <- ... p ... <- ... p ...
5759 or
5760 <- ... p ... <- ... p ...
5761 ... s <- p (new insn -- save)
5762 ... =>
5763 ... p <- s (new insn -- restore)
5764 <- ... p ... <- ... p ...
5765
5766 where p is an original pseudo got a hard register or a hard
5767 register and s is a new split pseudo. The save is put before INSN
5768 if BEFORE_P is true. Return true if we succeed in such
5769 transformation. */
5770static bool
5771split_reg (bool before_p, int original_regno, rtx_insn *insn,
5772 rtx next_usage_insns, rtx_insn *to)
5773{
5774 enum reg_class rclass;
5775 rtx original_reg;
5776 int hard_regno, nregs;
5777 rtx new_reg, usage_insn;
5778 rtx_insn *restore, *save;
5779 bool after_p;
5780 bool call_save_p;
5781 machine_mode mode;
5782
5783 if (original_regno < FIRST_PSEUDO_REGISTER76)
5784 {
5785 rclass = ira_allocno_class_translate(this_target_ira->x_ira_allocno_class_translate)[REGNO_REG_CLASS (original_regno)(regclass_map[(original_regno)])];
5786 hard_regno = original_regno;
5787 call_save_p = false;
5788 nregs = 1;
5789 mode = lra_reg_info[hard_regno].biggest_mode;
5790 machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno])((machine_mode) (regno_reg_rtx[hard_regno])->mode);
5791 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen as
5792 part of a multi-word register. In that case, just use the reg_rtx
5793 mode. Do the same also if the biggest mode was larger than a register
5794 or we can not compare the modes. Otherwise, limit the size to that of
5795 the biggest access in the function or to the natural mode at least. */
5796 if (mode == VOIDmode((void) 0, E_VOIDmode)
5797 || !ordered_p (GET_MODE_PRECISION (mode),